74AUP2G38GD,125

74AUP2G38 Low-power dual 2-input NAND gate; open drain Rev. 10 — 3 December 2020 Product data sheet 1. General description The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • • • Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: • JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.9 V to 1.65 V) • JESD8-7 (1.2 V to 1.95 V) • JESD8-5 (1.8 V to 2.7 V) • JESD8-B (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114F Class 3A exceeds 5000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101E exceeds 1000 V Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78B Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G38DC -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 74AUP2G38GT -40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1 74AUP2G38GN -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.2 × 1.0 × 0.35 mm SOT1116 74AUP2G38GS -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1.0 × 0.35 mm SOT1203 4. Marking Table 2. Marking codes Type number Marking code[1] 74AUP2G38DC a38 74AUP2G38GT a38 74AUP2G38GN aB 74AUP2G38GS aB [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram & 1A Y 1Y 1B A 2A & 2Y 2B B 001aah753 Fig. 1. Logic symbol 74AUP2G38 Product data sheet GND 001aah754 Fig. 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 mnb131 Fig. 3. Logic diagram (one gate) © Nexperia B.V. 2020. All rights reserved 2 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain 6. Pinning information 6.1. Pinning 74AUP2G38 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 74AUP2G38 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 001aaf548 Transparent top view 001aaf547 Fig. 4. Pin configuration SOT765-1 (VSSOP8) Fig. 5. Pin configuration SOT833-1, SOT1116 and SOT1203 (XSON8) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1A, 2A 1, 5 data input 1B, 2B 2, 6 data input GND 4 ground (0 V) 1Y, 2Y 7, 3 data output VCC 8 supply voltage 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF state. Output Input nA nB nY L L Z L H Z H L Z H H L 74AUP2G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 3 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +4.6 V -50 - -0.5 +4.6 -50 - -0.5 +4.6 V - +20 mA +50 mA VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO < 0 V VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC ICC supply current - IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 250 mW Min Max Unit 0.8 3.6 V 0 3.6 V 0 3.6 V -40 +125 °C 0 200 ns/V [1] [2] VI < 0 V [1] Tamb = -40 °C to +125 °C [1] [2] mA V mA The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT765-1 (VSSOP8) package: Ptot derates linearly with 4.9 mW/K above 99 °C. For SOT833-1 (XSON8) package: Ptot derates linearly with 3.1 mW/K above 68 °C. For SOT1116 (XSON8) package: Ptot derates linearly with 4.2 mW/K above 90 °C. For SOT1203 (XSON8) package: Ptot derates linearly with 3.6 mW/K above 81 °C. 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate 74AUP2G38 Product data sheet Conditions Active mode and Power-down mode VCC = 0.8 V to 3.6 V All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 4 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 0.8 V 0.70VCC - - V VCC = 0.9 V to 1.95 V 0.65VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30VCC V VCC = 0.9 V to 1.95 V - - 0.35VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V Tamb = 25 °C VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage VI = VIH or VIL - - 0.44 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.1 μA IOZ OFF-state output current VI = VIH or VIL; VO = 0 V to 3.6 V; VCC = 0 V to 3.6 V - - ±0.1 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.2 μA ΔIOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.2 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 μA ΔICC additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V - - 40 μA CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 0.7 - pF CO output capacitance VO = GND; VCC = 0 V - 0.9 - pF 74AUP2G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 5 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain Symbol Parameter Conditions Min Typ Max Unit VCC = 0.8 V 0.70VCC - - V VCC = 0.9 V to 1.95 V 0.65VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30VCC V VCC = 0.9 V to 1.95 V - - 0.35VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V Tamb = -40 °C to +85 °C VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage VI = VIH or VIL - - 0.45 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.5 μA IOZ OFF-state output current VI = VIH or VIL; VO = 0 V to 3.6 V; VCC = 0 V to 3.6 V - - ±0.5 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.5 μA ΔIOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.6 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 μA ΔICC additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V - - 50 μA 74AUP2G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 6 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain Symbol Parameter Conditions Min Typ Max Unit VCC = 0.8 V 0.75VCC - - V VCC = 0.9 V to 1.95 V 0.70VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.25VCC V VCC = 0.9 V to 1.95 V - - 0.30VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - 0.33VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.41 V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V Tamb = -40 °C to +125 °C VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage VI = VIH or VIL - - 0.50 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.75 μA IOZ OFF-state output current VI = VIH or VIL; VO = 0 V to 3.6 V; VCC = 0 V to 3.6 V - - ±0.75 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.75 μA ΔIOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.75 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 μA ΔICC additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V - - 75 μA 74AUP2G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 7 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7. Symbol Parameter Conditions Tamb = 25 °C Tamb = Tamb = Unit -40 °C to +85 °C -40 °C to +125 °C Min Typ [1] Max Min Max Min Max - 13.5 - - - - - ns VCC = 1.1 V to 1.3 V 1.9 4.6 10.4 1.8 11.4 1.8 12.6 ns VCC = 1.4 V to 1.6 V 1.5 3.3 6.5 1.4 7.4 1.4 8.2 ns VCC = 1.65 V to 1.95 V 1.2 2.9 5.1 1.1 5.9 1.1 6.5 ns VCC = 2.3 V to 2.7 V 1.0 2.2 3.8 0.9 4.5 0.9 4.9 ns VCC = 3.0 V to 3.6 V 0.9 2.3 4.0 0.8 4.5 0.8 4.9 ns CL = 5 pF tpd propagation nA, nB to nY; see Fig. 6 delay VCC = 0.8 V [2] CL = 10 pF tpd propagation nA, nB to nY; see Fig. 6 delay VCC = 0.8 V [2] - 16.3 - - - - - ns VCC = 1.1 V to 1.3 V 2.3 5.6 12.3 2.1 13.7 2.1 15.1 ns VCC = 1.4 V to 1.6 V 1.8 4.1 7.6 1.7 8.8 1.7 9.7 ns VCC = 1.65 V to 1.95 V 1.6 3.8 6.1 1.4 7.1 1.4 7.8 ns VCC = 2.3 V to 2.7 V 1.4 2.9 4.6 1.2 5.4 1.2 5.9 ns VCC = 3.0 V to 3.6 V 1.3 3.2 5.7 1.1 6.4 1.1 7.0 ns - 19.0 - - - - - ns VCC = 1.1 V to 1.3 V 2.6 6.6 14.2 2.4 15.8 2.4 17.4 ns VCC = 1.4 V to 1.6 V 2.1 4.8 8.7 1.9 10.1 1.9 11.1 ns VCC = 1.65 V to 1.95 V 1.9 4.6 7.6 1.7 8.5 1.7 9.3 ns VCC = 2.3 V to 2.7 V 1.6 3.6 5.6 1.5 6.3 1.5 6.9 ns VCC = 3.0 V to 3.6 V 1.6 4.1 7.5 1.4 8.3 1.4 9.1 ns - 27.0 - - - - - ns VCC = 1.1 V to 1.3 V 3.6 9.5 19.5 3.2 21.8 3.2 24.0 ns VCC = 1.4 V to 1.6 V 2.9 7.0 11.5 2.6 13.6 2.6 15.0 ns VCC = 1.65 V to 1.95 V 2.6 7.0 12.1 2.3 13.3 2.3 14.6 ns VCC = 2.3 V to 2.7 V 2.4 5.4 8.9 2.1 9.9 2.1 10.9 ns VCC = 3.0 V to 3.6 V 2.3 6.5 12.7 2.1 13.9 2.1 15.3 ns CL = 15 pF tpd propagation nA, nB to nY; see Fig. 6 delay VCC = 0.8 V [2] CL = 30 pF tpd propagation nA, nB to nY; see Fig. 6 delay VCC = 0.8 V 74AUP2G38 Product data sheet [2] All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 8 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain Symbol Parameter Conditions Tamb = 25 °C Tamb = Tamb = Unit -40 °C to +85 °C -40 °C to +125 °C Min Typ [1] Max Min Max Min Max - 0.6 - - - - - pF - 0.7 - - - - - pF VCC = 1.4 V to 1.6 V - 0.8 - - - - - pF VCC = 1.65 V to 1.95 V - 0.9 - - - - - pF VCC = 2.3 V to 2.7 V - 1.1 - - - - - pF VCC = 3.0 V to 3.6 V - 1.4 - - - - - pF CL = 5 pF, 10 pF, 15 pF and 30 pF f = 1 MHz; VI = GND to VCC [3] power dissipation VCC = 0.8 V capacitance VCC = 1.1 V to 1.3 V CPD [1] [2] [3] All typical values are measured at nominal VCC. tpd is the same as tPZL and tPLZ. CPD is used to determine the dynamic power dissipation (PD in μW). 2 PD = CPD × VCC × fi × N where: fi = input frequency in MHz; VCC = supply voltage in V; N = number of inputs switching. 11.1. Waveforms and test circuit VI nA, nB input VM GND t PZL t PLZ VCC nY output VM VOL VX mnb132 Measurement points are given in Table 9. VOL is a typical output voltage level that occurs with the output load. Fig. 6. The data input (nA, nB) to output (nY) propagation delays Table 9. Measurement points Supply voltage Input Output VCC VM VI tr = tf VM VX 0.8 V to 1.6 V 0.5VCC VCC ≤ 3.0 ns 0.5VCC VOL + 0.1 V 1.65 V to 2.7 V 0.5VCC VCC ≤ 3.0 ns 0.5VCC VOL + 0.15 V 3.0 V to 3.6 V 0.5VCC VCC ≤ 3.0 ns 0.5VCC VOL + 0.3 V 74AUP2G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 9 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain VCC G VI DUT VEXT 5 kΩ VO RT CL RL 001aac521 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 7. Test circuit for measuring switching times Table 10. Test data Supply voltage Load VCC CL RL [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ open GND 2VCC [1] VEXT For measuring enable and disable times RL = 5 kΩ. For measuring propagation delays, set-up times, hold times and pulse width, RL = 1 MΩ. 74AUP2G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 10 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain 12. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D SOT765-1 E A X c y HE v A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 detail X 4 e L w bp 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A max. max nom min 1 A1 A2 0.15 0.85 0.00 0.60 A3 0.12 D(1) E(2) 0.27 0.23 2.1 2.4 0.17 0.08 1.9 2.2 bp c e HE 0.5 3.2 3.0 L 0.4 Lp Q 0.40 0.21 0.15 0.19 v w y 0.2 0.08 0.1 Z(1) θ 0.4 8° 0.1 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. Outline version SOT765-1 Fig. 8. References IEC JEDEC JEITA sot765-1_po European projection Issue date 07-06-02 16-05-31 MO-187 Package outline SOT765-1 (VSSOP8) 74AUP2G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 11 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Fig. 9. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Package outline SOT833-1 (XSON8) 74AUP2G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 12 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm 1 2 SOT1116 b 4 3 (4×)(2) L L1 e 8 7 6 e1 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e max 0.35 0.04 0.20 1.25 1.05 nom 0.15 1.20 1.00 0.55 min 0.12 1.15 0.95 e1 L L1 0.35 0.40 0.30 0.35 0.27 0.32 0.3 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1116_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1116 Fig. 10. Package outline SOT1116 (XSON8) 74AUP2G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 13 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203 b 1 2 3 (4×)(2) 4 L L1 e 8 7 6 e1 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1203_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1203 Fig. 11. Package outline SOT1203 (XSON8) 74AUP2G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 14 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP2G38 v.10 20201203 Product data sheet - Modifications: • • 74AUP2G38 v.9 20190326 Modifications: • • • • • 74AUP2G38 v.9 Section 8: Derating values for Ptot total power dissipation have been updated. Type numbers 74AUP2G38GF (SOT1089/XSON8) and 74AUP2G38GM (SOT902-2/ XQFN8) removed. Product data sheet - 74AUP2G38 v.8 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type numbers 74AUP2G38GD (SOT996-2) removed. Package outline drawing SOT765-1 (VSSOP8) updated. Package outline drawing SOT902-2 (XQFN8) updated. 74AUP2G38 v.8 20130211 Modifications: • 74AUP2G38 v.7 20120605 Product data sheet - 74AUP2G38 v.6 74AUP2G38 v.6 20111209 Product data sheet - 74AUP2G38 v.5 74AUP2G38 v.5 20100923 Product data sheet - 74AUP2G38 v.4 74AUP2G38 v.4 20091008 Product data sheet - 74AUP2G38 v.3 74AUP2G38 v.3 20090616 Product data sheet - 74AUP2G38 v.2 74AUP2G38 v.2 20080312 Product data sheet - 74AUP2G38 v.1 74AUP2G38 v.1 20061016 Product data sheet - - 74AUP2G38 Product data sheet Product data sheet - 74AUP2G38 v.7 For type number 74AUP2G38GD XSON8U has changed to XSON8. All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 15 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain 15. Legal information injury, death or severe property or environmental damage. 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Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74AUP2G38 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 16 / 17 74AUP2G38 Nexperia Low-power dual 2-input NAND gate; open drain Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................8 11.1. Waveforms and test circuit........................................ 9 12. Package outline........................................................ 11 13. Abbreviations............................................................ 15 14. Revision history........................................................15 15. Legal information......................................................16 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 3 December 2020 74AUP2G38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 3 December 2020 © Nexperia B.V. 2020. All rights reserved 17 / 17