74AUP2T1326GF,132

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia 74AUP2T1326 Low-power dual supply buffer/line driver; 3-state Rev. 2 — 3 July 2012 Product data sheet 1. General description The 74AUP2T1326 is a high-performance, dual supply, low-power, low-voltage, dual buffer/line driver with output enable circuitry. The 74AUP2T1326 is designed for logic-level translation and combines the functions of the 74AUP1G32 and 74AUP2G126. The buffer/line driver is controlled by two output enable inputs (1OE and 2OE). A logic LOW on input 1OE causes the output 2Y to assume a high-impedance OFF-state, a logic LOW on 2OE causes the output 3Y to assume a high-impedance OFF-state. The output 1Y is the result of a logic OR of the two output enable inputs. The output enable inputs (1OE and 2OE) are Schmitt trigger inputs, they switch at different voltages for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT is defined as the input hysteresis voltage VH. The output enable inputs accept standard input signals and are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals Both VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V) with compatible input levels. Pins 1OE, 2OE and 1Y are referenced to VCC(A) and pins A, 2Y and 3Y are referenced to VCC(B). The device ensures low static and dynamic power consumption and is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the outputs, preventing any damaging backflow current through the device when it is powered down. 2. Features and benefits  Wide supply voltage range:  VCC(A): 1.1 V to 3.6 V; VCC(B): 1.1 V to 3.6 V.  High noise immunity  Complies with JEDEC standards:  JESD8-7 (1.2 V to 1.95 V)  JESD8-5 (1.8 V to 2.7 V)  JESD8-B (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F Class 2A exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Low static power consumption; ICC = 0.9 A (maximum)  Latch-up performance exceeds 100 mA per JESD 78 Class II 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state      Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AUP2T1326GF 40 C to +85 C Name Description Version XSON10 plastic extremely thin small outline package; no leads; SOT1081-2 10 terminals; body 1 x 1.7 x 0.5 mm 4. Marking Table 2. Marking Type number Marking code[1] 74AUP2T1326GF pf [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1OE 6 8 Rpd 2OE 1Y 7 Rpd VCC(A) 9 A 3 2 2Y 3Y VCC(B) 001aaj301 Rpd = Internal pull-down resistor. Fig 1. Logic symbol 74AUP2T1326 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 © NXP B.V. 2012. All rights reserved. 2 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state 6. Pinning information 6.1 Pinning 74AUP2T1326 VCC(B) 1 10 n.c. 3Y 2 9 2Y A 3 8 1Y VCC(A) 4 7 2OE GND 5 6 1OE 001aaj302 Transparent top view Fig 2. Pin configuration SOT1081-2 (XSON10) 6.2 Pin description Table 3. Pin description Symbol Pin Description VCC(B) 1 supply voltage B 3Y 2 data output A 3 data input VCC(A) 4 supply voltage A GND 5 ground (0 V) 1OE 6 output enable input (Schmitt trigger input) 2OE 7 output enable input (Schmitt trigger input) 1Y 8 data output 2Y 9 data output n.c. 10 not connected 74AUP2T1326 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 © NXP B.V. 2012. All rights reserved. 3 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state 7. Functional description Table 4. Function table[1] Input Output 1OE 2OE A 1Y 2Y 3Y L L X L Z Z L H L H Z L L H H H Z H H L L H L Z H L H H H Z H H L H L L H H H H H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC(A) supply voltage A VCC(B) supply voltage B IIK input clamping current VI input voltage output clamping current IOK Conditions Min Max Unit 0.5 +4.6 V 0.5 +4.6 V -50 - mA [1] 0.5 +4.6 V VO < 0 V [2] 50 - mA 0.5 +4.6 V - 20 mA VI < 0 V VO output voltage Active mode and Power-down mode [1] IO output current VO = 0 V to VCCO [2] ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature Ptot total power dissipation Tamb = 40 C to +85 C [3] 65 +150 C - 250 mW [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] VCCO is the supply voltage associated with an output pin. [3] For XSON10 package: above 45 C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC(A) Min Max Unit supply voltage A 1.1 3.6 V VCC(B) supply voltage B 1.1 3.6 V VI input voltage 0 3.6 V VO output voltage 0 VCCO V 74AUP2T1326 Product data sheet Conditions [1] All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 © NXP B.V. 2012. All rights reserved. 4 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state Table 6. Recommended operating conditions …continued Symbol Parameter Tamb ambient temperature t/V Conditions input transition rise and fall rate Min Max Unit 40 +85 C input A; VCCI = 1.1 V to 3.6 V [2] - 200 ns/V input nOE; VCCI = 1.1 V to 3.6 V [2] - 30 ms/V [1] VCCO is the supply voltage associated with an output pin. [2] VCCI is the supply voltage associated with an input pin. 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH HIGH-level input voltage 25 C Conditions Min Typ Max Min Max 0.65VCCI - - 0.65VCCI - V 1.6 - - 1.6 - V VCCI = 1.65 V to 1.95 V - - 0.35VCCI - 0.35VCCI V VCCI = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCCO  0.1 - - VCCO  0.1 - V IO = 3 mA; VCCO = 1.65 V 1.2 - - 1.2 - V IO = 2.3 mA; VCCO = 2.3 V 1.97 - - 1.97 - V 2.0 - - 2.0 - V - - 0.10 - 0.10 V VCCI = 1.65 V to 1.95 V VCCI = 2.3 V to 2.7 V [1][3] LOW-level input voltage input A; HIGH-level output voltage VI = VIL or VI or VI = VT+ or VT LOW-level output voltage Unit [1][3] input A; IO = 20 A; VCCO = 1.65 V to 2.7 V [2] IO = 4.0 mA; VCCO = 2.3 V VOL 40 C to +85 C VI = VIL or VI or VI = VT+ or VT [2] IO = 20 A; VCCO = 1.65 V to 2.7 V IO = 3.0 mA; VCCO = 1.65 V - - 0.45 - 0.45 V IO = 2.3 mA; VCCO = 2.3 V - - 0.33 - 0.33 V - - 0.40 - 0.40 V - - 0.1 - 0.5 A IO = 4.0 mA; VCCO = 2.3 V [1] II input leakage current input A; VI = 0 V to 2.7 V; VCCI = 1.65 V to 2.7 V IOZ OFF-state output current output 2Y, 3Y; VI = VIH or VIL; VO = 0 V to 2.7 V; VCC(A) = 1.65 V to 2.7 V; VCC(B) = 1.65 V to 2.7 V - - 0.1 - 0.5 A IOFF power-off leakage current 1Y; VCC(A) = 0 V; VO = 0 V to 2.7 V; VCC(B) = 1.65 V to 2.7 V - - 0.2 - 0.5 A A, 2Y, 3Y; VCC(B) = 0 V; VI or VO = 0 V to 2.7 V; VCC(A) = 1.65 V to 2.7 V - - 0.2 - 0.5 A 74AUP2T1326 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 © NXP B.V. 2012. All rights reserved. 5 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IOFF ICC(A) ICC(B) ICC 25 C Conditions Min Typ Max Min Max Unit additional power-off leakage current 1Y; VCC(A) = 0 V to 0.2 V; VO = 0 V to 2.7 V; VCC(B) = 1.65 V to 2.7 V - - 0.2 - 0.6 A A, 2Y, 3Y; VCC(B) = 0 V to 0.2 V; VI or VO = 0 V to 2.7 V; VCC(A) = 1.65 V to 2.7 V - - 0.2 - 0.6 A supply current A VI = 0 V or VCC(A); IO = 0 A - - 0.5 - 0.9 A supply current B VI = 0 V or VCC(B); IO = 0 A - - 0.5 - 0.9 A VCC(A) = 1.71 V; VCC(B) = 2.6 V - - 500 - 750 A additional supply current nOE; VCC(A) = VCC(B) = 2.7 V; VI = VCC(A)  0.6 V - - 40 - 50 A A; VCC(A) = VCC(B) = 2.7 V; VI = VCC(B)  0.6 V; - - 80 - 100 A - - 2 - 2 A 145 200 255 140 260 k [1] - 0.9 - - - pF input nOE; VI = 0 V or VCCI; VCCI = 1.65 V to 2.7 V [1] - 0.8 - - - pF output 1Y; VO = GND; VCCO = 0 V capacitance 2Y, 3Y enabled; V = GND; O VCCO = 0 V [2] - 1.7 - - - pF [2] - 1.7 - - - pF [2] - 1.5 - - - pF [1] VCC(A) = 1.65 V to 2.7 V; VCC(B) = 0 V to 2.7 V [1] VCC(A) = VCC(B) = 1.65 V to 2.7 V; [4] A; VI = GND to 2.7 V; nOE = GND; VCC(A) = 1.65 V to 2.7 V; VCC(B) = 1.65 V to 2.7 V Rpd pull-down resistance CI input input A; VI = 0 V or VCCI; capacitance VCCI = 1.65 V to 2.7 V CO 40 C to +85 C 2Y, 3Y disabled; VCCO = 0 V to 2.7 V; VO = GND or VCCO [1] VCCI is the supply voltage associated with the input pin. [2] VCCO is the supply voltage associated with the output pin. [3] For VCCI values not specified in the data sheet: minimum VIH = 0.7  VCCI and maximum VIL = 0.3  VCCI. [4] To show ICC remains very low when the input-disable feature is enabled. 74AUP2T1326 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 © NXP B.V. 2012. All rights reserved. 6 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 5. Symbol Parameter 25 C Conditions 40 C to +85 C Unit Min Typ[1] Max Min Max VCC(B) = 1.65 V to 1.95 V 1.9 3.2 4.5 1.7 5.0 ns VCC(B) = 2.3 V to 2.7 V 1.5 2.6 3.4 1.3 3.8 ns VCC(A) = 1.65 V to 1.95 V 2.4 4.0 5.4 2.2 6.0 ns VCC(A) = 2.3 V to 2.7 V 2.2 3.2 3.9 2.0 4.3 ns VCC(B) = 1.65 V to 1.95 V 2.3 3.8 5.3 2.0 5.8 ns VCC(B) = 2.3 V to 2.7 V 1.8 3.2 4.1 1.5 4.5 ns VCC(A) = 1.65 V to 1.95 V 2.9 4.6 6.1 2.5 6.7 ns VCC(A) = 2.3 V to 2.7 V 2.5 3.7 4.6 2.2 5.0 ns CL = 5 pF tpd propagation delay A to 2Y, 3Y; see Figure 3 [2] nOE to 1Y; see Figure 3 CL = 10 pF tpd propagation delay A to 2Y, 3Y; see Figure 3 [2] nOE to 1Y; see Figure 3 CL = 5 pF; VCC(A) = 1.65 V to 1.95 V ten tdis enable time disable time nOE to 2Y, 3Y; see Figure 4 [3] VCC(B) = 1.65 V to 1.95 V 2.4 4.4 9.7 2.1 10.1 ns VCC(B) = 2.3 V to 2.7 V 2.2 3.9 8.2 1.9 8.8 ns VCC(B) = 1.65 V to 1.95 V 2.4 4.5 8.9 2.1 9.4 ns VCC(B) = 2.3 V to 2.7 V 2.2 3.8 7.8 1.9 8.4 ns 2.4 4.0 8.7 2.1 9.0 ns 2.2 3.4 7.2 1.9 7.7 ns VCC(B) = 1.65 V to 1.95 V 2.4 4.2 7.9 2.1 8.3 ns VCC(B) = 2.3 V to 2.7 V 2.2 3.5 6.8 1.9 7.3 ns 2.9 4.9 11.0 2.5 11.7 ns 2.5 4.4 9.7 2.2 10.5 ns VCC(B) = 1.65 V to 1.95 V 2.9 5.6 10.8 2.5 11.5 ns VCC(B) = 2.3 V to 2.7 V 2.5 4.6 9.5 2.2 10.1 ns nOE to 2Y, 3Y; see Figure 4 [4] CL = 5 pF; VCC(A) = 2.3 V to 2.7 V ten enable time nOE to 2Y, 3Y; see Figure 4 [3] VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V tdis disable time nOE to 2Y, 3Y; see Figure 4 [4] CL = 10 pF; VCC(A) = 1.65 V to 1.95 V ten enable time nOE to 2Y, 3Y; see Figure 4 [3] VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V tdis disable time 74AUP2T1326 Product data sheet nOE to 2Y, 3Y; see Figure 4 [4] All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 © NXP B.V. 2012. All rights reserved. 7 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 5. Symbol Parameter 25 C Conditions 40 C to +85 C Unit Min Typ[1] Max Min Max 2.9 4.5 10.0 2.5 10.5 ns 2.5 3.9 8.7 2.2 9.3 ns CL = 10 pF; VCC(A) = 2.3 V to 2.7 V enable time ten nOE to 2Y, 3Y; see Figure 4 [3] VCC(B) = 1.65 V to 1.95 V VCC(B) = 2.3 V to 2.7 V disable time tdis nOE to 2Y, 3Y; see Figure 4 [4] VCC(B) = 1.65 V to 1.95 V 2.9 5.3 9.8 2.5 10.3 ns VCC(B) = 2.3 V to 2.7 V 2.5 4.3 8.4 2.2 8.9 ns VCC(A) = VCC(B) = 1.8 V - 3.0 - - - pF VCC(A) = VCC(B) = 2.5 V - 3.6 - - - pF CL = 5 pF and 10 pF power dissipation capacitance CPD per active output; output 2Y, 3Y; fi = 1 MHz; VI = 0 V to VCC [1] All typical values are measured at nominal VCC(A) and VCC(B). [2] tpd is the same as tPLH and tPHL. [3] ten is the same as tPZH and tPZL. [4] tdis is the same as tPHZ and tPLZ. [5] [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of the outputs. 74AUP2T1326 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 © NXP B.V. 2012. All rights reserved. 8 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state 12. Waveforms VI nOE input VM VM tPLH tPHL GND VOH VM 1Y output VM VOL VI VM VM tPLH tPHL A input GND VOH VM 2Y, 3Y output VM VOL 001aaj303 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 3. Input nOE to output 1Y and A to output 2Y, 3Y propagation delay times VI VM nOE input GND tPLZ VCCO 2Y, 3Y output LOW-to-OFF OFF-to-LOW VOL tPZL VM VX tPHZ VOH tPZH VY 2Y, 3Y output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aaj304 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. VCCO is the supply voltage associated with the output pin. Fig 4. Enable and disable times 74AUP2T1326 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 © NXP B.V. 2012. All rights reserved. 9 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state Table 9. Measurement points Supply voltage Input[1] Output[2] VCC(A), VCC(B) VM VM VX VY 1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH  0.15 V [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. VCC VEXT 5 kΩ G VI VO DUT CL RT RL 001aac521 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 5. Table 10. Test circuit for measuring switching times Test data Load[2] Supply voltage Input VCC(A), VCC(B) VI[1] VEXT tr = tf CL RL 1.65 V to 2.7 V VCCI  3.0 ns 5 pF, 10 pF 5 k or 1 M open [3] tPLH, tPHL [1] VCCI is the supply voltage associated with the data input port. [2] For measuring enable and disable times, CL and RL are connected to pin 2Y and 3Y. [3] For measuring enable and disable times RL = 5 k, for measuring propagation delays RL = 1 M. [4] VCCO is the supply voltage associated with the output port. 74AUP2T1326 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 tPZH, tPHZ tPZL, tPLZ[4] GND 2VCCO © NXP B.V. 2012. All rights reserved. 10 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state 13. Transfer characteristics Table 11. Transfer characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 5. Symbol VT+ VT VH Parameter 25 C Conditions positive-going threshold voltage 40 C to +85 C Unit Min Typ Max Min Max VCC(A) = 1.65 V 0.91 - 1.29 0.91 1.29 V VCC(A) = 2.3 V 1.37 - 1.77 1.37 1.77 V VCC(A) = 1.65 V 0.47 - 0.84 0.47 0.84 V VCC(A) = 2.3 V 0.69 - 1.04 0.69 1.04 V VCC(A) = 1.65 V 0.27 - 0.66 0.27 0.66 V VCC(A) = 2.3 V 0.53 - 0.92 0.53 0.92 V nOE inputs; see Figure 6 and Figure 7 negative-going threshold voltage nOE inputs; see Figure 6 and Figure 7 hysteresis voltage nOE inputs; (VT+  VT); see Figure 6, Figure 7 and Figure 8 14. Waveforms transfer characteristics VT+ VO VI VH VT− VO VI VH VT− VT+ mna208 mna207 VT+ and VT limits at 70 % and 20 %. Fig 6. Transfer characteristic 74AUP2T1326 Product data sheet Fig 7. Definition of VT+, VT and VH All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 © NXP B.V. 2012. All rights reserved. 11 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state 001aad691 240 ICC (μA) 160 80 0 0 0.4 0.8 1.2 1.6 2.0 VI (V) Fig 8. Typical transfer characteristics; VCC(A) = 1.8 V 74AUP2T1326 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 © NXP B.V. 2012. All rights reserved. 12 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state 15. Package outline XSON10: plastic extremely thin small outline package; no leads; 10 terminals; body 1.0 x 1.7 x 0.5 mm SOT1081-2 X A B D E A A1 c terminal 1 index area detail X e1 terminal 1 index area e 1 5 C C A B C v w b y1 C y L1 k L 10 5 0 1 Dimensions Unit(1) max nom min mm 2 mm scale A 0.5 A1 b c D 0.05 0.20 1.8 0.15 0.127 1.7 0.00 0.10 1.6 E e e1 1.1 1.0 0.9 0.35 1.4 k L 0.2 L1 0.40 0.45 0.35 0.40 0.30 0.35 v 0.1 w y y1 0.05 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT1081-2 --- --- --- Fig 9. sot1081-2_po European projection Issue date 10-11-08 11-03-30 Package outline SOT1081-2 (XSON10) 74AUP2T1326 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 © NXP B.V. 2012. All rights reserved. 13 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state 16. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 17. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP2T1326 v.2 20120703 Product data sheet - 74AUP2T1326 v.1 Modifications: 74AUP2T1326 v.1 74AUP2T1326 Product data sheet • For type number 74AUP2T1326GF the sot code has changed to SOT1081-2. 20090701 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 - © NXP B.V. 2012. All rights reserved. 14 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74AUP2T1326 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 © NXP B.V. 2012. All rights reserved. 15 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AUP2T1326 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 July 2012 © NXP B.V. 2012. All rights reserved. 16 of 17 74AUP2T1326 NXP Semiconductors Low-power dual supply buffer/line driver; 3-state 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Transfer characteristics . . . . . . . . . . . . . . . . . 11 Waveforms transfer characteristics. . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 July 2012 Document identifier: 74AUP2T1326