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74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Rev. 13 — 7 February 2014
Product data sheet
1. General description
The 74LVC16244A; 74LVCH16244A are 16-bit non-inverting buffer/line drivers with
3-state bus compatible outputs. The device can be used as four 4-bit buffers, two 8-bit
buffers or one 16-bit buffer. It features four output enable inputs, (1OE to 4OE) each
controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a
high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 V and 5 V applications.
The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground
bounce
Direct interface with TTL levels
High-impedance when VCC = 0 V
All data inputs have bus hold. (74LVCH16244A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
74LVC16244ADL
Temperature range
Package
Name
Description
Version
40 C to +125 C
SSOP48
plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
40 C to +125 C
TSSOP48
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
40 C to +125 C
VFBGA56
plastic very thin fine-pitch ball grid array package; SOT702-1
56 balls; body 4.5 7 0.65 mm
40 C to +125 C
HXQFN60
plastic compatible thermal enhanced extremely
thin quad flat package; no leads; 60 terminals;
body 4 6 0.5 mm
74LVCH16244ADL
74LVC16244ADGG
74LVCH16244ADGG
74LVC16244AEV
74LVCH16244AEV
74LVC16244ABX
74LVCH16244ABX
SOT1134-2
4. Functional diagram
47
46
44
43
1A0
1Y0
1A1
1Y1
1A2
1Y2
1A3
1Y3
2
36
3
35
5
33
6
32
3A0
3Y0
3A1
3Y1
3A2
3Y2
3A3
3Y3
1
1OE
48
2OE
25
3OE
24
4OE
13
14
16
1A0
1A1
17
1A2
1A3
1
1OE
25
3OE
2A0
2A1
41
2A0
2Y0
8
30
4A0
4Y0
2A2
19
2A3
40
2A1
2Y1
9
29
4A1
4Y1
3A0
20
3A1
38
37
48
2A2
2A3
2Y2
2Y3
2OE
11
12
27
26
24
4A2
4A3
4Y2
4Y3
3A2
22
3A3
4A0
23
4A1
4A2
4OE
4A3
EN1
EN2
EN3
EN4
47
46
Fig 1. Logic symbol
74LVC_LVCH16244A
Product data sheet
1
2
3
44
5
43
6
41
40
1
2
8
9
38
11
37
12
36
35
1
3
13
14
33
16
32
17
30
29
1
4
19
20
27
22
26
23
001aae506
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
1
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
4Y3
001aae231
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Fig 2. IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
2 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
VCC
data input
to internal circuit
mna705
Fig 3.
Bus hold circuit
5. Pinning information
5.1 Pinning
1OE
1
48 2OE
1Y0
2
47 1A0
1Y1
3
46 1A1
GND
4
45 GND
1Y2
5
44 1A2
1Y3
6
43 1A3
VCC
7
42 VCC
2Y0
8
41 2A0
2Y1
9
40 2A1
GND 10
39 GND
2Y2 11
38 2A2
2Y3 12
3Y0 13
37 2A3
74LVC16244A
74LVCH16244A
36 3A0
3Y1 14
35 3A1
GND 15
34 GND
3Y2 16
33 3A2
3Y3 17
32 3A3
VCC 18
31 VCC
4Y0 19
30 4A0
4Y1 20
29 4A1
GND 21
28 GND
4Y2 22
27 4A2
4Y3 23
26 4A3
4OE 24
74LVC16244A
ball A1
74LVCH16244A
index area
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
25 3OE
001aaj053
Transparent top view
001aaj052
Fig 4.
Pin configuration SOT370-1 (SSOP48) and
SOT362-1 (TSSOP48)
74LVC_LVCH16244A
Product data sheet
Fig 5.
Pin configuration SOT702-1 (VFBGA56)
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
3 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
terminal 1
index area
D1
A32
A1
D5
A31
A30
B20
A29
B19
A28
B18
A27
D4
D8
A26
A2
A25
B1
B17
B2
B16
A3
A24
A4
A23
B15
B3
A5
A22
74LVC16244A
74LVCH16244A
B4
A6
B14
A21
B5
B13
B6
B12
A20
A7
A8
A19
B7
B11
GND(1)
A9
A10
D6
D2
A11
B8
A12
B9
A13
A18
B10
A14
A15
D7
A17
A16
D3
001aaj054
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 6.
Pin configuration SOT1134-2 (HXQFN60)
74LVC_LVCH16244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
4 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
5.2 Pin description
Table 2.
Symbol
Pin description
Pin
Description
SOT370-1 and
SOT362-1
SOT702-1
SOT1134-2
1, 48, 25, 24
A1, A6, K6, K1
A30, A29, A14, A13
output enable input (active LOW)
1Y0 to 1Y3 2, 3, 5, 6
B2, B1, C2, C1
B20, A31, D5, D1
data output
2Y0 to 2Y3 8, 9, 11, 12
D2, D1, E2, E1
A2, B2, B3, A5
data output
1OE, 2OE,
3OE, 4OE
3Y0 to 3Y3 13, 14, 16, 17
F1, F2, G1, G2
A6, B5, B6, A9
data output
4Y0 to 4Y3 19, 20, 22, 23
H1, H2, J1, J2
D2, D6, A12, B8
data output
GND
4, 10, 15, 21, 28,
34, 39, 45
B3, B4, D3, D4, G3, G4,
J3, J4
A32, A3, A8, A11, A16,
A19, A24, A27
ground (0 V)
VCC
7, 18, 31, 42
C3, C4, H3, H4
A1, A10, A17, A26
supply voltage
1A0 to 1A3 47, 46, 44, 43
B5, B6, C5, C6
B18, A28, D8, D4
data input
2A0 to 2A3 41, 40, 38, 37
D5, D6, E5, E6
A25, B16, B15, A22
data input
3A0 to 3A3 36, 35, 33, 32
F6, F5, G6, G5
A21, B13, B12, A18
data input
4A0 to 4A3 30, 29, 27, 26
H6, H5, J6, J5
D3, D7, A15, B10
data input
n.c.
A2, A3, A4, A5, K2, K3,
K4, K5
A4, A7, A20, A23, B1,
B4, B7, B9, B11, B14,
B17, B19
not connected
-
6. Functional description
Table 3.
Function table[1]
Control
Input
Output
nOE
nAn
nYn
L
L
L
L
H
H
H
X
Z
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74LVC_LVCH16244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
5 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
VI < 0 V
[1]
Max
Unit
0.5
+6.5
V
50
-
mA
0.5
+6.5
V
-
50
mA
output HIGH or LOW
[2]
0.5
VCC + 0.5
V
output 3-state
[2]
0.5
+6.5
V
-
50
mA
VO > VCC or VO < 0 V
output voltage
VO
Min
IO
output current
VO = 0 V to VCC
ICC
supply current
-
100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
Tamb = 40 C to +125 C;
(T)SSOP48 package
[3]
-
500
mW
VFBGA56 package
[4]
-
1000
mW
HXQFN60 package
[4]
-
1000
mW
[1]
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2]
The output voltage ratings may be exceeded if the output current ratings are observed.
[3]
Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
[4]
Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VO
output voltage
Conditions
Min
Typ
Max
Unit
1.65
-
3.6
V
1.2
-
3.6
V
0
-
5.5
V
output HIGH or LOW
0
-
VCC
V
output 3-state
0
-
5.5
V
functional
Tamb
ambient temperature
in free air
40
-
+125
C
t/V
input transition rise and fall rate
VCC = 1.2 V to 2.7 V
0
-
20
ns/V
VCC = 2.7 V to 3.6 V
0
-
10
ns/V
74LVC_LVCH16244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
6 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
Min
VIH
VIL
VOH
VOL
HIGH-level input VCC = 1.2 V
voltage
VCC = 1.65 V to 1.95 V
LOW-level input
voltage
HIGH-level
output voltage
LOW-level
output voltage
1.08
Typ[1]
40 C to +125 C
Max
Min
Unit
Max
-
-
1.08
-
V
0.65 VCC -
-
0.65 VCC -
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
-
0.12
V
VCC = 1.2 V
-
-
0.12
VCC = 1.65 V to 1.95 V
-
-
0.35 VCC -
0.35 VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC 0.2
-
-
VCC 0.3
-
V
IO = 4 mA; VCC = 1.65 V 1.2
-
-
1.05
-
V
IO = 8 mA; VCC = 2.3 V
VI = VIH or VIL
IO = 100 A;
VCC = 1.65 V to 3.6 V
1.8
-
-
1.65
-
V
IO = 12 mA; VCC = 2.7 V 2.2
-
-
2.05
-
V
IO = 18 mA; VCC = 3.0 V 2.4
-
-
2.25
-
V
IO = 24 mA; VCC = 3.0 V 2.2
-
-
2.0
-
V
VI = VIH or VIL
IO = 100 A;
VCC = 1.65 V to 3.6 V
-
-
0.2
-
0.3
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
-
0.65
V
IO = 8 mA; VCC = 2.3 V
-
-
0.6
-
0.8
V
IO = 12 mA; VCC = 2.7 V
-
-
0.4
-
0.6
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
-
0.8
V
II
input leakage
current
-
0.1
5
-
20
A
IOZ
OFF-state output VI = VIH or VIL; VCC = 3.6 V; current [2]
VO = 5.5 V or GND;
0.1
5
-
20
A
IOFF
power-off
leakage current
VCC = 0 V; VI or VO = 5.5 V
-
0.1
10
-
20
A
ICC
supply current
VCC = 3.6 V;
VI = VCC or GND; IO = 0 A
-
0.1
20
-
80
A
ICC
additional supply per input pin;
current
VCC = 2.7 V to 3.6 V;
VI = VCC 0.6 V; IO = 0 A
-
5
500
-
5000
A
CI
input
capacitance
VCC = 0 V to 3.6 V;
VI = GND to VCC
-
5.0
-
-
-
pF
IBHL
bus hold LOW
current [3][4]
VCC = 1.65; VI = 0.58 V
10
-
-
10
-
A
VCC = 2.3; VI = 0.7 V
30
-
-
25
-
A
VCC = 3.0; VI = 0.8 V
75
-
-
60
-
A
74LVC_LVCH16244A
Product data sheet
VCC = 3.6 V;
VI = 5.5 V or GND
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
7 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
IBHH
IBHLO
bus hold HIGH
current [3][4]
40 C to +85 C
Conditions
Unit
Min
Max
Min
Max
VCC = 1.65; VI = 1.07 V
10
-
-
10
-
A
VCC = 2.3; VI = 1.7 V
30
-
-
25
-
A
VCC = 3.0; VI = 2.0 V
75
-
-
60
-
A
200
-
-
200
-
A
300
-
-
300
-
A
bus hold LOW
VCC = 1.95 V
overdrive current V = 2.7 V
CC
[3][5]
500
-
-
500
-
A
200
-
-
200
-
A
300
-
-
300
-
A
500
-
-
500
-
A
VCC = 3.6 V
IBHHO
40 C to +125 C
Typ[1]
bus hold HIGH
VCC = 1.95 V
overdrive current V = 2.7 V
CC
[3][5]
VCC = 3.6 V
[1]
All typical values are measured at VCC = 3.3 V and Tamb = 25 C.
[2]
The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal.
[3]
Valid for data inputs only. Control inputs do not have a bus hold circuit.
[4]
The specified sustaining current at the data input holds the input below the specified VI level.
[5]
The specified overdrive current at the data input forces the data input to the opposite logic input state.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter
tpd
propagation
delay
40 C to +85 C
Conditions
nAn to nYn; see Figure 7
enable time
Typ[2]
Max
Min
Max
-
11.0
-
-
-
ns
[1]
VCC = 1.2 V
VCC = 1.65 V to 1.95 V
1.5
4.8
10.7
1.5
11.3
ns
VCC = 2.3 V to 2.7 V
1.0
2.6
5.3
1.0
5.9
ns
VCC = 2.7 V
1.0
2.6
4.7
1.0
6.0
ns
1.1
2.2
4.1
1.1
5.5
ns
-
15.0
-
-
-
ns
VCC = 1.65 V to 1.95 V
1.5
6.2
12.1
1.5
12.7
ns
VCC = 2.3 V to 2.7 V
1.0
3.5
6.4
1.0
7.1
ns
VCC = 2.7 V
1.0
3.3
5.8
1.0
7.5
ns
VCC = 3.0 V to 3.6 V
1.0
2.8
4.6
1.0
6.0
ns
-
10.0
-
-
-
ns
VCC = 1.65 V to 1.95 V
2.5
4.4
8.7
2.5
9.4
ns
VCC = 2.3 V to 2.7 V
1.0
2.4
4.9
1.0
5.3
ns
VCC = 2.7 V
1.0
3.2
6.2
1.0
8.0
ns
VCC = 3.0 V to 3.6 V
1.8
3.1
5.2
1.8
6.5
ns
VCC = 3.0 V to 3.6 V
ten
nOE to nYn; see Figure 8
[1]
VCC = 1.2 V
tdis
disable time
nOE to nYn; see Figure 8
[1]
VCC = 1.2 V
74LVC_LVCH16244A
Product data sheet
40 C to +125 C Unit
Min
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
8 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter
CPD
[1]
power
dissipation
capacitance
40 C to +85 C
Conditions
40 C to +125 C Unit
Min
Typ[2]
Max
Min
Max
[3]
per input; VI = GND to VCC
VCC = 1.65 V to 1.95 V
-
4.8
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
8.3
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
11.4
-
-
-
pF
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[2]
Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs.
11. Waveforms
VI
nAn input
VM
VM
GND
tPLH
tPHL
VOH
nYn output
VM
VOL
VM
mna171
Measurement points are given in Table 8.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
The input (nAn) to output (nYn) propagation delays
74LVC_LVCH16244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
9 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
VI
nOE input
VM
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
VOH
tPZH
VY
output
HIGH-to-OFF
OFF-to-HIGH
GND
VM
outputs
enabled
outputs
enabled
outputs
disabled
mna362
Measurement points are given in Table 8.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8.
3-state enable and disable times.
Table 8.
Measurement points
Supply voltage
VM
VCC
Input
VI
tr = tf
VX
VY
1.2 V
0.5 VCC
VCC
2.5 ns
VOL + 0.15 V
VOH 0.15 V
1.65 V to 1.95 V
0.5 VCC
VCC
2.5 ns
VOL + 0.15 V
VOH 0.15 V
2.3 V to 2.7 V
0.5 VCC
VCC
2.5 ns
VOL + 0.15 V
VOH 0.15 V
2.7 V
1.5 V
2.7 V
2.5 ns
VOL + 0.3 V
VOH 0.3 V
3.0 V to 3.6 V
1.5 V
2.7 V
2.5 ns
VOL + 0.3 V
VOH 0.3 V
74LVC_LVCH16244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
10 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VEXT
VCC
VI
RL
VO
G
DUT
RT
RL
CL
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9.
Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
Input
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
1.2 V
VCC
2 ns
30 pF
1 k
open
2 VCC
GND
1.65 V to 1.95 V
VCC
2 ns
30 pF
1 k
open
2 VCC
GND
2.3 V to 2.7 V
VCC
2 ns
30 pF
500
open
2 VCC
GND
2.7 V
2.7 V
2.5 ns
50 pF
500
open
2 VCC
GND
3.0 V to 3.6 V
2.7 V
2.5 ns
50 pF
500
open
2 VCC
GND
74LVC_LVCH16244A
Product data sheet
Load
VEXT
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
11 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
12. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
HE
v M A
Z
25
48
Q
A2
A1
A
(A 3)
θ
pin 1 index
Lp
L
24
1
detail X
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.8
0.4
0.2
2.35
2.20
0.25
0.3
0.2
0.22
0.13
16.00
15.75
7.6
7.4
0.635
10.4
10.1
1.4
1.0
0.6
1.2
1.0
0.25
0.18
0.1
0.85
0.40
8o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT370-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-118
Fig 10. Package outline SOT370-1 (SSOP48)
74LVC_LVCH16244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
12 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A
X
c
v
HE
y
A
Z
48
25
Q
A2
(A3)
A1
A
pin 1 index
θ
Lp
L
1
24
detail X
w
bp
e
0
5 mm
2.5
scale
Dimensions (mm are the original dimensions)
Unit
mm
max
nom
min
A
A1
A2
A3
0.15 1.05
1.2
bp
c
D(1)
E(2)
0.28
0.2
12.6
6.2
HE
0.17
0.1
12.4
L
8.3
0.5
0.25
0.05 0.85
e
6.0
Lp
Q
0.8
0.50
1
7.9
v
w
0.25 0.08
0.4
0.35
y
Z
θ
0.8
8°
0.4
0°
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
Outline
version
SOT362-1
References
IEC
JEDEC
JEITA
sot362-1_po
European
projection
Issue date
03-02-19
13-08-05
MO-153
Fig 11. Package outline SOT362-1 (TSSOP48)
74LVC_LVCH16244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
13 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm
B
D
SOT702-1
A
ball A1
index area
A2
A
E
A1
detail X
e1
1/2
C
∅v M
C A B
∅w M C
b
e
y1 C
e
y
K
J
H
e
G
F
e2
E
D
1/2
e
C
X
B
A
ball A1
index area
1
2
3
4
5
6
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1
0.3
0.2
0.7
0.6
0.45
0.35
4.6
4.4
7.1
6.9
0.65
3.25
5.85
0.15
0.08
0.08
0.1
OUTLINE
VERSION
SOT702-1
REFERENCES
IEC
JEDEC
JEITA
0
2.5
5 mm
scale
EUROPEAN
PROJECTION
ISSUE DATE
02-08-08
03-07-01
MO-225
Fig 12. Package outline SOT702-1 (VFBGA56)
74LVC_LVCH16244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
14 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads;
60 terminals; body 4 x 6 x 0.5 mm
A
B
D
SOT1134-2
terminal 1
index area
A
A2
E
A1
detail X
e2
b
e1
L1
L
A11
B10
A17
A10
eR
eT
y
y1 C
D3
D7
A16
B8
C
eT
1/2 e
D2
D6
C A B
C
eR
e
C A B
C
v
w
v
w
e
B11
B7
Eh
e3
e4
1/2 e
B17
B1
A1
terminal 1
index area
A26
D5
D1
A32
B20 B18
A27
Dh
D8
D4
eT
eR
X
K
eT
eR
0
5 mm
Dimensions
Unit
mm
A
A1
A2
b
max 0.50 0.08 0.42 0.28
nom
0.05 0.40 0.23
min
0.02 0.38 0.18
D
Dh
E
Eh
e
e1
e2
e3
e4
eR
4.1
4.0
3.9
1.95
1.85
1.75
6.1
6.0
5.9
3.95
3.85
3.75
0.5
1.0
2.5
3.0
4.5
0.5
eT
K
L
L1
v
w
0.25 0.28 0.195
0.49 0.20 0.23 0.145 0.1
0.15 0.18 0.095
y
0.05 0.08
y1
0.1
sot1134-2_po
References
Outline
version
IEC
JEDEC
JEITA
SOT1134-2
---
---
---
European
projection
Issue date
11-08-15
Fig 13. Package outline SOT1134-2 (HXQFN60)
74LVC_LVCH16244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
15 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC_LVCH16244A v.13
20140207
Product data sheet
-
74LVC_LVCH16244A v.12
•
Modifications:
Table 5: Minimum VCC changed from 2.3 V to 1.65 V (errata).
74LVC_LVCH16244A v.12
20120305
Product data sheet
-
74LVC_LVCH16244A v.11
74LVC_LVCH16244A v.11
20111027
Product data sheet
-
74LVC_LVCH16244A v.10
74LVC_LVCH16244A v.10
20110429
Product data sheet
-
74LVC_LVCH16244A v.9
74LVC_LVCH16244A v.9
20100318
Product data sheet
-
74LVC_LVCH16244A v.8
74LVC_LVCH16244A v.8
20081117
Product data sheet
-
74LVC_LVCH16244A v.7
74LVC_LVCH16244A v.7
20031208
Product specification
-
74LVC_LVCH16244A v.6
74LVC_LVCH16244A v.6
20030130
Product specification
-
74LVC_LVCH16244A v.5
74LVC_LVCH16244A v.5
20021030
Product specification
-
74LVC_H16244A v.4
74LVC_H16244A v.4
19971028
Product specification
-
74LVC16244A_
74LVCH16244A v.3
74LVC16244A_
74LVCH16244A v.3
19971028
Product specification
-
74LVC16244A v.2
74LVC16244A v.2
19970630
Product specification
-
74LVC16244A v.1
74LVC16244A v.1
-
-
-
-
74LVC_LVCH16244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
16 of 19
74LVC16244A; 74LVCH16244A
NXP Semiconductors
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC_LVCH16244A
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
17 of 19
NXP Semiconductors
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC_LVCH16244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 7 February 2014
© NXP B.V. 2014. All rights reserved.
18 of 19
NXP Semiconductors
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 February 2014
Document identifier: 74LVC_LVCH16244A
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