74HC03DB-Q100J

74HC03-Q100; 74HCT03-Q100 Quad 2-input NAND gate; open-drain output Rev. 3 — 10 August 2021 Product data sheet 1. General description The 74HC03-Q100; 74HCT03-Q100 is a quad 2-input NAND gate with open-drain outputs. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Input levels: • For 74HC03-Q100: CMOS level • For 74HCT03-Q100: TTL level Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) 3. Ordering information Table 1. Ordering information Type number Package 74HC03D-Q100 Temperature range Name Description Version -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HCT03D-Q100 74HC03PW-Q100 74HCT03PW-Q100 74HC03-Q100; 74HCT03-Q100 Nexperia Quad 2-input NAND gate; open-drain output 4. Functional diagram 1 1 1A 2 1B 1Y 3 4 2A 5 2B 2Y 6 9 3A 10 3B 3Y 8 2 4 12 4A 13 4B 5 9 10 12 4Y 11 13 mna212 Fig. 1. & 3 & 6 & 8 Y A & 11 B GND aaa-008083 Logic symbol Fig. 2. 001aab715 IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74HC03 74HCT03 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 74HC03 74HCT03 1A 1 14 VCC 1B 2 13 4B 3 12 4A 2A 4 11 4Y 1Y 2B 5 10 3B 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 2Y 6 9 3A GND 7 8 3Y GND 7 8 3A 3Y aaa-008084 Fig. 4. aaa-008085 Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 74HC_HCT03_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2021 © Nexperia B.V. 2021. All rights reserved 2 / 11 74HC03-Q100; 74HCT03-Q100 Nexperia Quad 2-input NAND gate; open-drain output 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. Output Input nA nB nY L L Z L H Z H L Z H H L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VO output voltage IIK input clamping current IOK Min Max -0.5 +7 V [1] -0.5 +7 V VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA output clamping current VO < -0.5 V [1] - -20 mA IO output current -0.5 V < VO - -25 mA ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] Conditions [2] Unit The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC03-Q100 Min Typ 74HCT03-Q100 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 74HC_HCT03_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2021 © Nexperia B.V. 2021. All rights reserved 3 / 11 74HC03-Q100; 74HCT03-Q100 Nexperia Quad 2-input NAND gate; open-drain output 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 VCC = 4.5 V 3.15 2.4 - 1.5 - 3.15 - 1.5 - V - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V 74HC03-Q100 VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - 0.1 - - ±1 - ±1 μA IOZ OFF-state output current VI = VIL; VCC = 6.0 V; VO = VCC or GND - - ±0.5 - ±5.0 - ±10 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - 2.0 - - 20 - 40 μA CI input capacitance - 3.5 - - - - - pF 74HCT03-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 μA - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1 - ±1 μA IOZ OFF-state output current VI = VIL; VCC = 5.5 V; VO = VCC or GND - - ±0.5 - ±5.0 - ±10 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 μA ΔICC additional supply current per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 100 360 - 450 - 490 μA CI input capacitance - 3.5 - - - - - pF 74HC_HCT03_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2021 © Nexperia B.V. 2021. All rights reserved 4 / 11 74HC03-Q100; 74HCT03-Q100 Nexperia Quad 2-input NAND gate; open-drain output 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for test circuit, see Fig. 7. Symbol Parameter Conditions -40 °C to -40 °C to Unit +85 °C +125 °C 25 °C Min Typ Max Max Max VCC = 2.0 V - 28 95 120 145 ns VCC = 4.5 V - 10 19 24 29 ns VCC = 5.0 V; CL = 15 pF - 8 - - - ns - 8 16 20 25 ns VCC = 2.0 V - 19 75 95 110 ns VCC = 4.5 V - 7 15 19 22 ns VCC = 6.0 V - 6 13 16 19 ns - 4 - - - pF VCC = 4.5 V - 12 24 30 36 ns VCC = 5.0 V; CL = 15 pF - 10 - - - ns [2] - 7 15 19 22 ns [3] - 4 - - - pF 74HC03-Q100 tpd propagation delay nA, nB to nY; see Fig. 6 [1] VCC = 6.0 V tt CPD transition time see Fig. 6 [2] power dissipation per package; VI = GND to VCC capacitance [3] 74HCT03-Q100 tpd propagation delay nA, nB to nY; see Fig. 6 tt transition time CPD power dissipation per package; VI = GND to VCC - 1.5 V capacitance [1] [2] [3] VCC = 4.5 V; see Fig. 6 [1] tpd is the same as tPLZ and tPZL. tt is the same as tTHL. CPD is used to determine the dynamic power dissipation (PD in μW): 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of outputs. 74HC_HCT03_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2021 © Nexperia B.V. 2021. All rights reserved 5 / 11 74HC03-Q100; 74HCT03-Q100 Nexperia Quad 2-input NAND gate; open-drain output 10.1. Waveforms and test circuit VI nA, nB input VM GND tPLZ tPZL VCC 90 % nY output VM 10 % VX VOL tTHL aaa-008086 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 6. Input to output propagation delays Table 8. Measurement points Input Type Output VM VM VX 74HC03-Q100 0.5VCC 0.5VCC 0.1VCC 74HCT03-Q100 1.3 V 1.3 V 0.1VCC VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VCC VO RT RL S1 open CL 001aad983 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig. 7. Test circuit for measuring switching times Table 9. Test data Type Input S1 position Load VI tr, tf CL RL tPZL, tPLZ 74HC03-Q100 VCC 6 ns 15 pF, 50 pF 1 kΩ VCC 74HCT03-Q100 3.0 V 6 ns 15 pF, 50 pF 1 kΩ VCC 74HC_HCT03_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2021 © Nexperia B.V. 2021. All rights reserved 6 / 11 74HC03-Q100; 74HCT03-Q100 Nexperia Quad 2-input NAND gate; open-drain output 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74HC_HCT03_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2021 © Nexperia B.V. 2021. All rights reserved 7 / 11 74HC03-Q100; 74HCT03-Q100 Nexperia Quad 2-input NAND gate; open-drain output TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 Fig. 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Package outline SOT402-1 (TSSOP14) 74HC_HCT03_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2021 © Nexperia B.V. 2021. All rights reserved 8 / 11 74HC03-Q100; 74HCT03-Q100 Nexperia Quad 2-input NAND gate; open-drain output 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT03_Q100 v.3 20210810 Product data sheet - 74HC_HCT03_Q100 v.2 Product data sheet - 74HC_HCT03_Q100 v.1 Modifications: • Section 2 updated. 74HC_HCT03_Q100 v.2 20210107 Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type numbers 74HC03DB-Q100, 74HCT03DB-Q100 (SOT337-1 / SSOP14) removed. Section 7: Derating values for Ptot total power dissipation have been updated. 74HC_HCT03_Q100 v.1 20130704 74HC_HCT03_Q100 Product data sheet Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2021 - © Nexperia B.V. 2021. All rights reserved 9 / 11 74HC03-Q100; 74HCT03-Q100 Nexperia Quad 2-input NAND gate; open-drain output equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 14. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74HC_HCT03_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2021 © Nexperia B.V. 2021. All rights reserved 10 / 11 74HC03-Q100; 74HCT03-Q100 Nexperia Quad 2-input NAND gate; open-drain output Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................2 5.1. Pinning.........................................................................2 5.2. Pin description............................................................. 2 6. Functional description................................................. 3 7. Limiting values............................................................. 3 8. Recommended operating conditions..........................3 9. Static characteristics....................................................4 10. Dynamic characteristics............................................ 5 10.1. Waveforms and test circuit........................................ 6 11. Package outline.......................................................... 7 12. Abbreviations.............................................................. 9 13. Revision history..........................................................9 14. Legal information......................................................10 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 10 August 2021 74HC_HCT03_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2021 © Nexperia B.V. 2021. All rights reserved 11 / 11