74ABT32DB,118

74ABT32 Quad 2-input OR gate Rev. 4 — 9 October 2020 Product data sheet 1. General description The 74ABT32 is a quad 2-input OR gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • Supply voltage range from 4.5 V to 5.5 V BiCMOS high speed and output drive Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT32D -40 °C to +85 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74ABT32PW -40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74ABT32 Nexperia Quad 2-input OR gate 4. Functional diagram 1 2 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 4 1Y 3 5 2Y 6 9 3Y 8 4Y 11 10 12 3 ≥1 6 ≥1 8 ≥1 11 A 13 Y B mna243 mna242 Fig. 1. ≥1 Logic symbol Fig. 2. IEC logic symbol mna241 Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74ABT32 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 2B 5 2Y GND 6 1A 1 1B 2 14 VCC 13 4B 11 4Y 1Y 3 12 4A 10 3B 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y 9 7 74ABT32 8 3A 3Y aaa-024199 aaa-024198 Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data input 1B, 2B, 3B, 4B 2, 5, 10, 13 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 74ABT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 October 2020 © Nexperia B.V. 2020. All rights reserved 2 / 10 74ABT32 Nexperia Quad 2-input OR gate 6. Functional description Table 3. Function selection H = HIGH voltage level; L = LOW voltage level; X = don’t care Output Input nA nB nY L L L X H H H X H H H H 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit -0.5 +7.0 V [1] -1.2 +7.0 V [1] -0.5 +5.5 V VI < 0 V -18 - mA output clamping current VO < 0 V -50 - mA output current output in LOW-state - 40 mA junction temperature - 150 °C storage temperature -65 +150 °C VCC supply voltage VI input voltage VO output voltage output in Off or High state IIK input clamping current IOK IO Tj Tstg [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 8. Recommended operating conditions Table 5. Operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit 4.5 - 5.5 V VCC supply voltage VI input voltage 0 - VCC V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IOH HIGH-level output current -15 - - mA IOL LOW-level output current - - 20 mA Δt/ΔV input transition rise and fall rate 0 - 10 ns/V Tamb ambient temperature -40 - +85 °C 74ABT32 Product data sheet in free air All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 October 2020 © Nexperia B.V. 2020. All rights reserved 3 / 10 74ABT32 Nexperia Quad 2-input OR gate 9. Static characteristics Table 6. Static characteristics Symbol Parameter Conditions 25 °C -40 °C to +85 °C Unit Min Typ Max Min Max VIK input clamping voltage VCC = 4.5 V; IIK = -18 mA -1.2 -0.9 - -1.2 - V VOH HIGH-level output voltage VCC = 4.5 V; IOH = -15 mA; VI = VIL or VIH 2.5 2.9 - 2.5 - V VOL LOW-level output voltage VCC = 4.5 V; IOL = 20 mA; VI = VIL or VIH - 0.35 0.5 - 0.5 V II input leakage current VCC = 5.5 V; VI = GND or 5.5 V - ±0.01 ±1.0 - ±1.0 μA IOFF power-off leakage current VCC = 0 V; VI or VO ≤ 4.5 V - ±5.0 ±100 - ±100 μA ICEX output high leakage current HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC - 5.0 50 - 50 μA IO output current VCC = 5.5 V; VO = 2.5 V -50 -75 -180 -50 -180 mA ICC supply current VCC = 5.5 V; VI = GND or VCC - 2 50 - 50 μA ΔICC additional supply current per input pin; VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND - 0.25 500 - 500 μA CI input capacitance VI = 0 V or VCC - 3 - - - pF [1] [2] [1] [2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input at 3.4 V. 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Fig. 7. Symbol Parameter Conditions 25 °C; VCC = 5.0 V -40 °C to +85 °C; VCC = 5.0 V ± 0.5 V Min Typ Max Min Max Unit tPLH LOW to HIGH propagation delay nA, nB to nY; see Fig. 6 1.0 2.3 3.4 1.0 3.8 ns tPHL HIGH to LOW propagation delay nA, nB to nY; see Fig. 6 1.0 1.9 2.9 1.0 3.2 ns tsk(o) output skew time - 0.4 0.5 - 0.5 ns [1] [1] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 74ABT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 October 2020 © Nexperia B.V. 2020. All rights reserved 4 / 10 74ABT32 Nexperia Quad 2-input OR gate 10.1. Waveform and test circuit VI VM nA, nB input GND t PHL t PLH VM nY output mna244 VM = 1.5 V VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. Propagation delay input (nA, nB) to output (nY) and output skew time VI negative pulse tW 90 % 90 % VM 0V VI positive pulse 0V VM 10 % 10 % tf tr tr tf 90 % VEXT VCC G 90 % VM VI VM 10 % DUT RT 10 % tW RL VO CL mna616 001aai298 a. Input pulse definition RL b. Test circuit Test data is given in Table 8. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 7. Test circuit for measuring switching times Table 8. Test data Input VEXT Load VI fi tW tr, tf CL RL tPHL, tPLH 3.0 V 1 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω open 74ABT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 October 2020 © Nexperia B.V. 2020. All rights reserved 5 / 10 74ABT32 Nexperia Quad 2-input OR gate 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74ABT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 October 2020 © Nexperia B.V. 2020. All rights reserved 6 / 10 74ABT32 Nexperia Quad 2-input OR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 Fig. 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Package outline SOT402-1 (TSSOP14) 74ABT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 October 2020 © Nexperia B.V. 2020. All rights reserved 7 / 10 74ABT32 Nexperia Quad 2-input OR gate 12. Abbreviations Table 9. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ABT32 v.4 20201009 Product data sheet - Modifications: • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74ABT32DB (SOT337-1 SSOP14) removed. 74ABT32 v.3 20160812 Modifications: • • 74ABT32 v.2 74ABT32 Product data sheet 74ABT32 v.3 Product data sheet - 74ABT32 v.2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. 19950918 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 October 2020 - © Nexperia B.V. 2020. All rights reserved 8 / 10 74ABT32 Nexperia Quad 2-input OR gate 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74ABT32 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 October 2020 © Nexperia B.V. 2020. All rights reserved 9 / 10 74ABT32 Nexperia Quad 2-input OR gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................2 5.1. Pinning.........................................................................2 5.2. Pin description............................................................. 2 6. Functional description................................................. 3 7. Limiting values............................................................. 3 8. Recommended operating conditions..........................3 9. Static characteristics....................................................4 10. Dynamic characteristics............................................ 4 10.1. Waveform and test circuit.......................................... 5 11. Package outline.......................................................... 6 12. Abbreviations.............................................................. 8 13. Revision history..........................................................8 14. Legal information........................................................9 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 9 October 2020 74ABT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 9 October 2020 © Nexperia B.V. 2020. All rights reserved 10 / 10