74ALVT162821DGG,11

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia INTEGRATED CIRCUITS 74ALVT162821 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30
termination resistors (3-State) Product specification Supersedes data of 1997 Feb 13 IC23 Data Handbook
     1998 Oct 02 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30
termination resistors (3-State) FEATURES 74ALVT162821 DESCRIPTION • Outputs include series resistance of 30
making external The 74ALVT162821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. It is designed for VCC operation at 2.5V or 3.3V with I/O compatibility to 5V. termination resistors unnecessary • 20-bit positive-edge triggered register • 5V I/O Compatible • Multiple VCC and GND pins minimize switching noise • Live insertion/extraction permitted • Power-up reset • Power-up 3-State • Output capability +12mA/-12mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 The 74ALVT162821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (nOE) controls all ten 3-State buffers independent of the register operation. When nOE is Low, the data in the register appears at the outputs. When nOE is High, the outputs are in high impedance “off” state, which means they will neither drive nor load the bus. and 200V per Machine Model • Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs The 74ALVT162821 is designed with 30
series resistance in both High and Low output stages. This design reduces the line noise in applications such as memory address drivers, clock drivers and bus receivers/transmitters. The series termination resistors reduce overshoot and undershoot and are ideal for driving memory arrays. QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C PARAMETER TYPICAL UNIT 2.5V 3.3V 4.4 3.8 3.2 3.2 ns tPLH tPHL Propagation delay nCP to nQ CL = 50pF CIN Input capacitance VI = 0V or VCC 3 3 pF COUT Output capacitance VO = 0 or VCC 9 9 pF ICCZ Total supply current Outputs disabled 40 70 µA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40°C to +85°C 74ALVT162821 DL AV162821 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVT162821 DGG AV162821 DGG SOT364-1 1998 Oct 02 2 853-2041 20127 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30
termination resistors (3-State) LOGIC SYMBOL 55 54 74ALVT162821 PIN CONFIGURATION 52 51 49 48 47 1D0 1D1 1D2 1D3 1D4 1D5 1D6 45 44 43 1D7 1D8 1D9 1OE 1 56 1CP 1Q0 2 55 1D0 56 1CP 1Q1 3 54 1D1 1 1OE GND 4 53 GND 1Q2 5 52 1D2 1Q3 6 51 1D3 VCC 7 50 VCC 1Q4 8 49 1D4 1Q5 9 48 1D5 1Q6 10 47 1D6 GND 11 46 GND 1Q7 12 45 1D7 1Q8 13 44 1D8 1Q9 14 43 1D9 2Q0 15 42 2D0 2Q1 16 41 2D1 2Q2 17 40 2D2 GND 18 39 GND 2Q3 19 38 2D3 2Q4 20 37 2D4 2Q5 21 36 2D5 VCC 22 35 VCC 2Q6 23 34 2D6 2Q7 24 33 2D7 GND 25 32 GND 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2 3 42 41 5 40 6 38 8 37 9 36 10 34 2D0 2D1 2D2 2D3 2D4 2D5 2D6 29 12 33 13 14 31 30 2D7 2D8 2D9 2CP 28 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 15 16 17 19 20 21 23 24 26 27 SH00002 LOGIC SYMBOL (IEEE/IEC) 1OE 1 1CP 56 2OE 28 2CP 29 1D0 55 1D1 EN2 C1 EN4 C3 2 1Q0 2Q8 26 31 2D8 54 3 1Q1 2Q9 27 30 2D9 1D2 52 5 1Q2 2OE 28 29 2CP 1D3 51 6 1Q3 1D4 49 8 1Q4 1D5 48 9 1Q5 1D6 47 10 1Q6 1D7 45 12 1Q7 1D8 44 13 1Q8 1D9 43 14 1Q9 2D0 42 15 2Q0 2D1 41 16 2Q1 2D2 40 17 2Q2 2D3 38 19 2Q3 2D4 37 20 2Q4 2D5 36 21 2Q5 2D6 34 23 2Q6 2D7 33 24 2Q7 2D8 31 26 2Q8 2D9 30 27 2Q9 1D 3D 2∇ 4∇ SH00001 SCHEMATIC OF EACH OUTPUT VCC VCC 27Ω OUTPUT 27Ω SH00003 1998 Oct 02 SW00007 3 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30
termination resistors (3-State) PIN DESCRIPTION PIN NUMBER FUNCTION TABLE SYMBOL 55, 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 74ALVT162821 INPUTS FUNCTION 1D0 - 1D9 2D0 - 2D9 1Q0 - 1Q9 2Q0 - 2Q9 Data outputs 1, 28 1OE, 2OE Output enable inputs (active-Low) 56, 29 1CP, 2CP Clock pulse inputs (active rising edge) 4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V) 7, 22, 35, 50 VCC Positive supply voltage nQ0 - nQ9 OPERATING MODE nOE nCP nDx L L ↑ ↑ l h L H L H Load and read register L ↑ X NC NC Hold Data inputs 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 OUTPUTS INTERNAL REGISTER H ↑ X NC Z Disable ↑ H Dn Dn Z outputs H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition NC= No change X = Don’t care Z = High impedance “off” state ↑ = Low to High clock transition ↑ = Not a Low-to-High clock transition LOGIC DIAGRAM nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nD9 D D D D D D D D D D CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q nCP nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9 SH00004 1998 Oct 02 4 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30
termination resistors (3-State) 74ALVT162821 ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER SYMBOL VCC CONDITIONS RATING UNIT –0.5 to +4.6 V –50 mA –1.2 to +7.0 V VO < 0 –50 mA Output in Off or High state –0.5 to +7.0 V Output in Low state 128 Output in High state –64 DC supply voltage IIK DC input diode current VI DC input voltage3 IOK DC output diode current VI < 0 VOUT DC output voltage3 IOUT O DC output current Tstg Storage temperature range mA °C –65 to 150 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC 2.5V RANGE LIMITS PARAMETER DC supply voltage 3.3V RANGE LIMITS UNIT MIN MAX MIN MAX 2.3 2.7 3.0 3.6 V 0 5.5 0 5.5 V VI Input voltage VIH High-level input voltage VIL Input voltage 0.7 0.8 V IOH High-level output current –8 –12 mA IOL 1.7 2.0 V Low-level output current 12 12 mA ∆t/∆v Input transition rise or fall rate; Outputs enabled 10 10 ns/V Tamb Operating free-air temperature range +85 °C 1998 Oct 02 –40 5 +85 –40 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30
termination resistors (3-State) 74ALVT162821 DC ELECTRICAL CHARACTERISTICS (3.3V
0.3V RANGE) LIMITS MIN VIK VOH Input clamp voltage High-level out output ut voltage VOL Low–level out output ut voltage VRST Power-up output low voltage6 VCC = 3.0V; IIK = –18mA VCC = 3.0 to 3.6V; IOH = –100µA Input In ut leakage current IHOLD Off current 2.0 2.3 0.2 VCC = 3.0V; IOL = 16mA 0.25 0.4 VCC = 3.0V; IOL = 32mA 0.3 0.5 VCC = 3.0V; IOL = 64mA 0.4 0.55 VCC = 3.6V; IO = 1mA; VI = VCC or GND Bus Hold current V 0.55 Control pins VCC = 0 or 3.6V; VI = 5.5V VCC = 3.6V; VI = VCC V V 0.07 Data pins ins4 VCC = 0V; VI or VO = 0 to 4.5V Data inputs7 –1.2 VCC VCC = 3.0V; IOL = 100µA VCC = 3.6V; VI = 0V IOFF MAX –0.85 VCC–0.2 VCC = 3.0V; IOH = –32mA VCC = 3.6V; VI = VCC or GND II TYP1 VCC = 3V; VI = 0.8V 0.1 ±1 0.1 10 0.5 1 0.1 -5 0.1 ±100 75 130 VCC = 3V; VI = 2.0V –75 –140 VCC = 0V to 3.6V; VCC = 3.6V ±500 V µA µA µA Current into an output in the High state when VO > VCC VO = 5.5V; VCC = 3.0V 10 125 µA Power up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC OE/OE = Don’t care 1 ±100 µA IOZH 3-State output High current VCC = 3.6V; VO = 3.0V; VI = VIL or VIH 0.5 5 µA IOZL 3-State output Low current VCC = 3.6V; VO = 0.5V; VI = VIL or VIH 0.5 –5 µA VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 0.07 0.1 5.1 7 0.07 0.1 0.04 0.4 IEX IPU/PD ICCH ICCL Quiescent supply current ICCZ ∆ICC VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = Additional supply current per input pin2 05 VCC = 3V to 3.6V; One input at VCC–0.6V, Other inputs at VCC or GND mA mA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.2V a transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 7. This is the bus hold overdrive current required to force the input to the opposite logic state. AC CHARACTERISTICS (3.3V
0.3V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER Tamb = –40 to +85oC VCC = +3.3V WAVEFORM MIN UNIT TYP MAX 1 1.0 1.0 3.2 3.2 5.0 4.7 ns Output enable time to High and Low level 3 4 1.0 0.5 3.4 2.3 5.6 3.7 ns tPHZ Output disable time tPLZ from High and Low level NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 3 4 1.5 1.5 3.7 3.0 5.4 4.3 ns fMAX Maximum clock frequency tPLH tPHL tPZH tPZL 1998 Oct 02 1 150 Propagation delay nCP to nQx 6 MHz Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30
termination resistors (3-State) 74ALVT162821 AC SETUP REQUIREMENTS (3.3V
0.3V RANGE) GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +3.3V ±0.3V WAVEFORM UNIT MIN TYP 1 1.5 1.5 0.1 0.1 ns Hold time, High or Low nDx to nCP 2 0.5 0.5 0.1 0.1 ns nCP pulse width High or Low 2 1.5 1.5 ts(H) ts(L) Setup time, High or Low nDx to nCP th(H) th(L) tw(H) tw(L) ns DC ELECTRICAL CHARACTERISTICS (2.5V
0.2V RANGE) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIK Input clamp voltage VOH High-level out output ut voltage VOL Low-level output voltage VCC = 2.3V; IIK = –18mA VCC = 2.3 to 3.6V; IOH = –100µA VCC = 2.3V; IOH = –8mA TYP1 MAX –0.85 –1.2 VCC–0.2 VCC 1.8 2.1 VRST Power-up output low voltage7 0.07 0.2 VCC = 2.3V; IOL = 24mA 0.3 0.5 Input In ut leakage current V 0.4 VCC = 2.7V; IO = 1mA; VI = VCC or GND VCC = 2.7V; VI = VCC or GND II V V VCC = 2.3V; IOL = 100µA VCC = 2.3V; IOL = 8mA UNIT 0.55 Control pins VCC = 0 or 2.7V; VI = 5.5V VCC = 2.7V; VI = VCC Data pins ins4 VCC = 2.7V; VI = 0 0.1 ±1 0.1 10 0.1 1 V µA 0.1 -5 Off current VCC = 0V; VI or VO = 0 to 4.5V 0.1
100 Bus Hold current VCC = 2.3V; VI = 0.7V 90 µA Data inputs6 VCC = 2.3V; VI = 1.7V –10 µA Current into an output in the High state when VO > VCC VO = 5.5V; VCC = 2.3V 10 125 µA Power up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC OE/OE = Don’t care 1
100 µA IOZH 3-State output High current VCC = 2.7V; VO = 2.3V; VI = VIL or VIH 0.5 5 µA IOZL 3-State output Low current VCC = 2.7V; VO = 0.5V; VI = VIL or VIH 0.5 –5 µA VCC = 2.7V; Outputs High, VI = GND or VCC, IO = 0 0.04 0.1 VCC = 2.7V; Outputs Low, VI = GND or VCC, IO = 0 2.3 4.5 VCC = 2.7V; Outputs Disabled; VI = GND or VCC, IO = 05 0.04 0.1 VCC = 2.3V to 2.7V; One input at VCC–0.6V, Other inputs at VCC or GND 0.04 0.4 IOFF IHOLD IEX IPU/PD ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 µA mA mA NOTES: 1. All typical values are at VCC = 2.5V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 2.5V ± 0.3V a transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. Not guaranteed. 7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 1998 Oct 02 7 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30
termination resistors (3-State) 74ALVT162821 AC CHARACTERISTICS (2.5V "0.2V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +2.5V ±0.2V WAVEFORM MIN UNIT TYP MAX 1 1.0 1.0 4.4 3.8 7.0 6.4 ns Output enable time to High and Low level 3 4 1.5 1.0 4.6 2.8 7.5 4.6 ns tPHZ Output disable time tPLZ from High and Low level NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 3 4 1.5 1.0 3.5 3.7 5.5 5.7 ns fMAX Maximum clock frequency 1 150 tPLH tPHL Propagation delay nCP to nQx tPZH tPZL MHz AC SETUP REQUIREMENTS (2.5V "0.2V RANGE) GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +2.5 ±0.2V WAVEFORM MIN TYP UNIT ts(H) ts(L) Setup time, High or Low nDx to nCP 1 1.5 2.0 0.1 0.5 ns th(H) th(L) Hold time, High or Low nDx to nCP 2 0.3 0.5 –0.5 –0.1 ns tw(H) tw(L) nCP pulse width High or Low 2 1.5 1.5 ns AC WAVEFORMS VM = 1.5V at VCC w 3.0V; VM = VCC/2 at VCC v 2.7V VX = VOL + 0.3V at VCC w 3.0V; VX = VOL + 0.15V at VCC v 2.7V VY = VOH – 0.3V at VCC w 3.0V; VY = VOH – 0.15V at VCC v 2.7V 1/fMAX nCP VM tw(H) VM tw(L) tPHL nQx 3.0V or VCC whichever is less VM nDx VM VM VM th(H) ts(L) th(L) 0V 0V tPLH CP VOH VM VM ts(H) 3.0V or VCC whichever is less VM VM 3.0V or VCC whichever is less 0V VM VOL SH00005 SH00006 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock frequency 1998 Oct 02 Waveform 2. Data Setup and Hold Times 8 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30
termination resistors (3-State) 3.0V or VCC whichever is less nOE VM VM 74ALVT162821 VM VM 0V 0V tPZH tPZL tPHZ VM tPLZ 3.0V or VCC nQx VOH VM VY nQx 3.0V or VCC whichever is less nOE VX VOL 0V 0V SH00008 SH00007 Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORM 6.0V or VCC x 2 VCC Open VIN VOUT PULSE GENERATOR tW 90% RL GND VM NEGATIVE PULSE 10% 0V tTHL (tF) CL VIN VM 10% D.U.T. RT 90% tTLH (tR) tTLH (tR) RL 90% POSITIVE PULSE Test Circuit for 3-State Outputs tTHL (tF) VIN 90% VM VM 10% 10% tW 0V SWITCH POSITION TEST SWITCH tPLZ/tPZL 6V or VCC x 2 tPLH/tPHL Open tPHZ/tPZH GND INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY Amplitude RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance: See AC CHARACTERISTICS for value. 74ALVT16 Rep. Rate 3.0V or VCC whichever v10MHz is less tW 500ns tR tF v2.5ns v2.5ns RT = Termination resistance should be equal to ZOUT of pulse generators. SW00025 1998 Oct 02 9 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30
termination resistors (3-State) SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 1998 Oct 02 10 74ALVT162821 SOT371-1 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30
termination resistors (3-State) TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 1998 Oct 02 11 74ALVT162821 SOT364-1 Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30
termination resistors (3-State) 74ALVT162821 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number:
     yyyy mmm dd 12 Date of release: 05-96 9397-750-04619