74LVT374PW,118

74LVT374 3.3 V octal D-type flip-flop; 3-state Rev. 4 — 22 November 2011 Product data sheet 1. General description The 74LVT374 is a high-performance product designed for VCC operation at 3.3 V. This device is an 8-bit, edge triggered register coupled to eight 3-state output buffers. The two sections of the device are controlled independently by the clock (pin CP) and output enable (pin OE) control gates. The state of each Dn input (one setup time before the LOW-to-HIGH clock transition) is transferred to the corresponding flip-flops Qn output. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active LOW output enable (pin OE) controls all eight 3-state buffers independent of the clock operation. When pin OE is LOW, the stored data appears at the outputs. When pin OE is HIGH, the outputs are in the high-impedance OFF-state, which means they will neither drive nor load the bus. 2. Features and benefits            Inputs and outputs arranged for easy interfacing to microprocessors 3-state outputs for bus interfacing Common output enable control TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up reset Power-up 3-state Latch-up protection  JESD78 class II exceeds 500 mA  ESD protection:  HBM JESD22-A114E exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Specified from 40 C to +85 C 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT374D 40 C to +85 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74LVT374DB 40 C to +85 C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 74LVT374PW 40 C to +85 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 4. Functional diagram 1 11 EN C1 11 3 CP 3 4 7 8 D0 Q0 D1 Q1 D2 Q2 D3 13 17 18 Q4 D5 Q5 D6 Q6 D7 Q7 5 6 7 6 9 8 9 12 13 12 14 15 17 16 18 19 15 16 19 OE 1 Fig 1. mna891 mna196 Logic symbol D0 Fig 2. D1 D CP D2 D Q CP 2 1D 4 5 Q3 D4 14 2 D3 D Q CP D4 D Q IEC logic symbol CP D5 D Q CP D6 D Q CP D7 D Q CP D Q CP Q CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae467 Fig 3. Logic diagram 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 5. Pinning information 5.1 Pinning 74LVT374 OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP aaa-000304 Fig 4. Pin configuration for SO20, and (T)SSOP20) 5.2 Pin description Table 2. Pin description Symbol Pin Description OE 1 output enable input (active LOW) D0 to D7 3, 4, 7, 8, 13, 14, 17, 18 data input GND 10 ground (0 V) CP 11 clock pulse input (active rising edge) Q0 to Q7 2, 5, 6, 9, 12, 15, 16, 19 data output VCC 20 supply voltage 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 6. Functional description 6.1 Function table Table 3. Function table [1] Operating mode Load and read register Control Input Internal register Output OE CP Dn Qn L  l L L h H H Hold L NC X NC NC Disable outputs H L or H X NC Z  Dn Dn Z [1] H = HIGH voltage level; L = LOW voltage level;  = LOW-to-HIGH clock transition; h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition; l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition; Z = high-impedance OFF-state; NC = no change; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +4.6 V 0.5 +7.0 V input voltage [1] VO output voltage output in OFF-state or HIGH-state [1] 0.5 +7.0 V IIK input clamping current VI < 0 V - 50 mA IOK output clamping current VO < 0 V - 50 mA IO output current output in LOW-state - 128 mA output in HIGH-state - 64 mA Tstg storage temperature 65 +150 C Tj junction temperature [2] - 150 C [3] - 500 mW VI total power dissipation Ptot Tamb = 40 C to +85 C [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. [3] For SO20 packages: above 70 C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K. 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Conditions Min Max Unit supply voltage 2.7 3.6 V VI input voltage 0 5.5 V VIH HIGH-level input voltage 2.0 - V VIL LOW-level input voltage - 0.8 V IOH HIGH-level output current - 32 mA IOL LOW-level output current - 32 mA current duty cycle  50 %; fi  1 kHz - 64 mA Tamb ambient temperature in free air 40 +85 C t/V input transition rise and fall rate outputs enabled - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC = 2.7 V; IIK = 18 mA VIK input clamping voltage VOH HIGH-level output voltage VCC = 2.7 V to 3.6 V; IOH = 100 A VOL LOW-level output voltage Tamb = 40 C to +85 C Conditions Unit Min Typ[1] Max 1.2 0.9 - V - V VCC  0.2 VCC  0.1 VCC = 2.7 V; IOH = 8 mA 2.4 2.5 - V VCC = 3.0 V; IOH = 32 mA 2.0 2.2 - V IOL = 100 A - 0.1 0.2 V IOL = 24 mA - 0.3 0.5 V IOL = 16 mA - 0.25 0.4 V IOL = 32 mA - 0.3 0.5 V - 0.4 0.55 V - 0.13 0.55 V - 1 10 A - 0.1 1 A VI = VCC - 0.1 1 A VI = 0 V 5 1 - A - 1 100 A VCC = 2.7 V VCC = 3.0 V IOL = 64 mA VOL(pu) power-up LOW-level output voltage VCC = 3.6 V; IO = 1 mA; VI = GND or VCC II input leakage current all input pins; VCC = 0 V or 3.6 V; VI = 5.5 V [2] control pins; VCC = 3.6 V; VI = VCC or GND data pins; VCC = 3.6 V IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V ILO output leakage current VO = 5.5 V and VCC = 3.0 V; output HIGH IBHL bus hold LOW current VCC = 3.0 V; VI = 0.8 V IBHH bus hold HIGH current VCC = 3.0 V; VI = 2.0 V VCC = 3.6; VI = 0 V to 3.6 V IBHHO [3] bus hold HIGH overdrive current 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 - 60 125 A 75 150 - A [4] - 150 75 A [4] - - 500 A [4] © NXP B.V. 2011. All rights reserved. 5 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 40 C to +85 C Conditions IBHLO bus hold LOW overdrive current VCC = 3.6; VI = 0 V to 3.6 V IO(pu/pd) power-up/power-down output current VCC  1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OE = don’t care IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL supply current ICC Unit Min Typ[1] Max 500 - - A - 1 100 A [5] output HIGH: VO = 3.0 V - 1 5 A output LOW: VO = 0.5 V 5 1 - A - 0.13 0.19 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled - 3 12 mA [6] - 0.13 0.19 mA [7] - 0.1 0.2 mA ICC additional supply current per input pin; VCC = 3 V to 3.6 V; one input at VCC  0.6 V and other inputs at VCC or GND CI input capacitance VI = 0 V or 3.0 V - 4 - pF CO output capacitance outputs disabled; VO = 0 V or 3.0 V - 7 - pF [1] Typical values are measured at VCC = 3.3 V and Tamb = 25 C. [2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. [3] Unused pins at VCC or GND. [4] This is the bus hold overdrive current required to force the input to the opposite logic state. [5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V  0.3 V a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only. [6] ICC is measured with outputs pulled to VCC or GND. [7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to ground (GND = 0 V); for test circuit see Figure 9. Symbol Parameter tPLH Conditions LOW to HIGH propagation delay VCC = 2.7 V HIGH to LOW propagation delay Typ[1] 1.7 3.2 5.1 ns - - 5.8 ns 2.2 3.5 5.2 ns - - 5.5 ns 1.5 3.2 5.3 ns - - 7.3 ns Max CP to Qn; see Table 6 VCC = 3.0 V to 3.6 V VCC = 2.7 V tPZH Min CP to Qn; see Table 6 VCC = 3.0 V to 3.6 V tPHL Tamb = 40 C to +85 C Unit OFF-state to HIGH propagation delay OE to Qn; see Figure 6 VCC = 3.0 V to 3.6 V VCC = 2.7 V 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to ground (GND = 0 V); for test circuit see Figure 9. Symbol Parameter tPZL Tamb = 40 C to +85 C Unit Conditions Min Typ[1] 2.0 3.4 5.2 ns - - 6.1 ns 1.9 4.3 6.7 ns - - 7.1 ns 2.0 3.4 5.1 ns - - 5.1 ns 2.0 0.7 - ns 2.0 - - ns 0.3 0.5 - ns 0 - - ns 1.5 0.8 - ns 1.5 - - ns VCC = 3.0 V to 3.6 V 2.5 1.7 - ns VCC = 2.7 V 3.0 - - ns VCC = 3.0 V to 3.6 V 125 200 - MHz VCC = 2.7 V 125 - - MHz OFF-state to LOW propagation delay OE to Qn; see Figure 7 VCC = 3.0 V to 3.6 V VCC = 2.7 V HIGH to OFF-state propagation delay OE to Qn; see Figure 6 tPHZ VCC = 3.0 V to 3.6 V VCC = 2.7 V LOW to OFF-state propagation delay OE to Qn; see Figure 7 tPLZ VCC = 3.0 V to 3.6 V VCC = 2.7 V set-up time tsu Dn to CP; see Figure 8 [2] VCC = 3.0 V to 3.6 V VCC = 2.7 V hold time th Dn to CP; see Figure 8 [3] VCC = 3.0 V to 3.6 V VCC = 2.7 V pulse width tW CP input HIGH; see Figure 5 [4] VCC = 3.0 V to 3.6 V VCC = 2.7 V CP input LOW; see Figure 5 maximum frequency fmax [1] Max [4] CP input; see Figure 5 Typical values are at VCC = 3.3 V and Tamb = 25 C. [2] tsu is the same as tsu(H) and tsu(L) [3] th is the same as th(H) and th(L) [4] tW is the same as tWH and tWL 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 11. Waveforms 1 / fmax VI CP input VM GND tWH tWL tPHL tPLH VOH VM Qn output VOL 001aac445 Measurement points are given in Table 8 VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay clock input (CP) to output (Qn), pulse width clock (CP) and maximum clock frequency VI OE input VI VM VM GND t PZH t PHZ tPZL VOH Qn output VM VM OE input GND tPLZ 3.0 V VY VM Qn output VM VX VOL GND 001aae468 Fig 6. 001aae469 Measurement points are given in Table 8 Measurement points are given in Table 8 VOL and VOH are typical voltage output levels that occur with the output load. VOL and VOH are typical voltage output levels that occur with the output load. Output enable time to HIGH-state and output disable time from HIGH-state Fig 7. Output enable time to LOW-state and output disable time from LOW-state Vl VM Dn input VM VM VM GND t su(H) t h(H) t su(L) t h(L) Vl VM CP input GND VM 001aac738 Measurement points are given in Table 8 Remark: The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 8. Data setup and hold times 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state Table 8. Measurement points Input Output VM VM VX VY 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 9. Table 9. Load circuitry for switching times Test data Input Load VEXT VI fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V  10 MHz 500 ns  2.5 ns 50 pF 500  GND 6V open 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT163-1 (SO20) 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8o o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT339-1 (SSOP20) 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT360-1 (TSSOP20) 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model MOS Metal Oxide Semiconductor TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT374 v.4 20111122 Product data sheet - 74LVT374 v.3 Modifications: • Legal pages updated. 74LVT374 v.3 20110914 Product data sheet - 74LVT374 v.2 74LVT374 v.2 19980219 product specification - 74LVT374 v.1 74LVT374 v.1 19960208 product specification - - 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Export might require a prior authorization from competent authorities. 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVT374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 15 of 16 74LVT374 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 November 2011 Document identifier: 74LVT374