74LVC1G08
Single 2-input AND gate
Rev. 11 — 28 November 2016
Product data sheet
1. General description
The 74LVC1G08 provides one 2-input AND function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
time.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
74LVC1G08
Nexperia
Single 2-input AND gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74LVC1G08GW
40 C to +125 C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74LVC1G08GV
40 C to +125 C
SC-74A
plastic surface-mounted package; 5 leads
SOT753
74LVC1G08GM
40 C to +125 C
XSON6
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 1.45 0.5 mm
SOT886
74LVC1G08GF
40 C to +125 C
XSON6
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 1 0.5 mm
SOT891
74LVC1G08GN
40 C to +125 C
XSON6
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
74LVC1G08GS
40 C to +125 C
XSON6
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
SOT1202
74LVC1G08GX
40 C to +125 C
X2SON5
X2SON5: plastic thermal enhanced extremely thin
small outline package; no leads; 5 terminals;
body 0.8 0.8 0.35 mm
SOT1226
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74LVC1G08GW
VE
74LVC1G08GV
V08
74LVC1G08GM
VE
74LVC1G08GF
VE
74LVC1G08GN
VE
74LVC1G08GS
VE
74LVC1G08GX
VE
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
$
%
$
<
<
%
PQD
PQD
Fig 1.
Logic symbol
74LVC1G08
Product data sheet
Fig 2.
IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 28 November 2016
PQD
Fig 3.
Logic diagram
©
Nexperia B.V. 2017. All rights reserved
2 of 19
74LVC1G08
Nexperia
Single 2-input AND gate
6. Pinning information
6.1 Pinning
/9&*
/9&*
%
$
*1'
9&&
<
%
9&&
$
QF
*1'
<
DDE
7UDQVSDUHQWWRSYLHZ
DDE
Fig 4.
Pin configuration SOT353-1 and SOT753
Fig 5.
Pin configuration SOT886
/9&*
/9&*
%
%
9&&
$
QF
*1'
<
9&&
<
*1'
$
DDH
DDD
7UDQVSDUHQWWRSYLHZ
7UDQVSDUHQWWRSYLHZ
Fig 6.
Pin configuration SOT891, SOT1115 and
SOT1202
Fig 7.
Pin configuration SOT1226 (X2SON5)
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
TSSOP5 and X2SON5
XSON6
B
1
1
data input
A
2
2
data input
GND
3
3
ground (0 V)
Y
4
4
data output
n.c.
-
5
not connected
VCC
5
6
supply voltage
74LVC1G08
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 28 November 2016
©
Nexperia B.V. 2017. All rights reserved
3 of 19
74LVC1G08
Nexperia
Single 2-input AND gate
7. Functional description
Table 4.
Function table[1]
Input
Output
A
B
Y
L
L
L
L
H
L
H
L
L
H
H
H
[1]
H = HIGH voltage level; L = LOW voltage level
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
output voltage
VO
IO
output current
ICC
supply current
IGND
ground current
Ptot
total power dissipation
Tstg
storage temperature
Conditions
VI < 0 V
[1]
Min
Max
0.5
+6.5
50
-
0.5
+6.5
V
mA
V
mA
-
50
Active mode
[1][2]
0.5
VCC + 0.5
V
Power-down mode
[1][2]
0.5
+6.5
V
-
50
mA
-
100
mA
100
-
mA
-
250
mW
65
+150
C
VO > VCC or VO < 0 V
VO = 0 V to VCC
Tamb = 40 C to +125 C
[3]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3]
Unit
For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 and X2SON5 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
74LVC1G08
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 28 November 2016
©
Nexperia B.V. 2017. All rights reserved
4 of 19
74LVC1G08
Nexperia
Single 2-input AND gate
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol
Parameter
Conditions
VCC
supply voltage
VI
input voltage
VO
output voltage
Tamb
ambient temperature
t/V
input transition rise and fall rate
Min
Typ
Max
Unit
1.65
-
5.5
V
0
-
5.5
V
Active mode
0
-
VCC
V
VCC = 0 V; Power-down mode
0
-
5.5
V
40
-
+125
C
VCC = 1.65 V to 2.7 V
-
-
20
ns/V
VCC = 2.7 V to 5.5 V
-
-
10
ns/V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
VIL
VOH
VOL
II
HIGH-level
input voltage
LOW-level
input voltage
40 C to +85 C
Conditions
Max
Min
Max
0.65VCC
-
-
0.65VCC
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 4.5 V to 5.5 V
0.7VCC
-
-
0.7VCC
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35VCC
-
0.35VCC
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3VCC
-
0.3VCC
V
VCC 0.1
-
-
VCC 0.1
-
V
IO = 4 mA; VCC = 1.65 V
1.2
-
-
0.95
-
V
IO = 8 mA; VCC = 2.3 V
1.9
-
-
1.7
-
V
IO = 12 mA; VCC = 2.7 V
2.2
-
-
1.9
-
V
IO = 24 mA; VCC = 3.0 V
2.3
-
-
2.0
-
V
IO = 32 mA; VCC = 4.5 V
3.8
-
-
3.4
-
V
-
-
0.10
-
0.10
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
-
0.70
V
IO = 8 mA; VCC = 2.3 V
-
-
0.30
-
0.45
V
IO = 12 mA; VCC = 2.7 V
-
-
0.40
-
0.60
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
-
0.80
V
IO = 32 mA; VCC = 4.5 V
-
-
0.55
-
0.80
V
-
0.1
1
-
1
A
LOW-level
VI = VIH or VIL
output voltage
IO = 100 A;
VCC = 1.65 V to 5.5 V
74LVC1G08
Product data sheet
Unit
Min
HIGH-level
VI = VIH or VIL
output voltage
IO = 100 A;
VCC = 1.65 V to 5.5 V
input leakage
current
40 C to +125 C
Typ[1]
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 28 November 2016
©
Nexperia B.V. 2017. All rights reserved
5 of 19
74LVC1G08
Nexperia
Single 2-input AND gate
Table 7.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
Unit
Min
Max
Min
Max
-
0.1
2
-
2
A
IOFF
power-off
leakage
current
ICC
supply current VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V
-
0.1
4
-
4
A
ICC
additional
per pin; VCC = 2.3 V to 5.5 V;
supply current VI = VCC 0.6 V; IO = 0 A
-
5
500
-
500
A
CI
input
capacitance
-
5
-
-
-
pF
[1]
VCC = 0 V; VI or VO = 5.5 V
40 C to +125 C
Typ[1]
VCC = 3.3 V; VI = GND to VCC
All typical values are measured at VCC = 3.3 V and Tamb = 25 C.
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 9.
Symbol Parameter
40 C to +85 C
Conditions
propagation delay A, B to Y; see Figure 8
tpd
Max
Min
Max
1.0
3.4
8.0
1.0
10.5
Unit
ns
VCC = 2.3 V to 2.7 V
0.5
2.2
5.5
0.5
7.0
ns
VCC = 2.7 V
0.5
2.5
5.5
0.5
7.0
ns
VCC = 3.0 V to 3.6 V
0.5
2.1
4.5
0.5
6.0
ns
0.5
1.7
4.0
0.5
5.5
ns
-
16
-
-
-
pF
VCC = 4.5 V to 5.5 V
power dissipation
capacitance
Typ[1]
[2]
VCC = 1.65 V to 1.95 V
CPD
40 C to +125 C
Min
VI = GND to VCC; VCC = 3.3 V
[3]
[1]
Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2]
tpd is the same as tPLZ and tPZL.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74LVC1G08
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 28 November 2016
©
Nexperia B.V. 2017. All rights reserved
6 of 19
74LVC1G08
Nexperia
Single 2-input AND gate
12. AC waveforms
9,
90
$%LQSXW
*1'
W 3+/
W 3/+
92+
90
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