74AHC374D,112

74AHC374; 74AHCT374 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 03 — 12 June 2008 Product data sheet 1. General description The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input (CP) and an output enable input (OE) are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the set-up and hold times requirements for the LOW-to-HIGH CP transition. When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. 2. Features n n n n n Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Common 3-state output enable input Input levels: u For 74AHC374: CMOS level u For 74AHCT374: TTL level n ESD protection: u HBM EIA/JESD22-A114E exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V u CDM EIA/JESD22-C101C exceeds 1000 V n Multiple package options n Specified from −40 °C to +85 °C and from −40 °C to +125 °C 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC374D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74AHC374PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm 74AHCT374D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm 74AHCT374PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm 74AHC374 74AHCT374 SOT163-1 4. Functional diagram 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 8 D3 Q3 9 13 D4 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 FF1 to FF8 3-STATE OUTPUTS Q4 12 11 CP 1 OE mna892 Fig 1. Functional diagram © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 2 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 1 EN 11 C1 11 3 CP 3 4 7 8 13 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 14 Q4 D5 17 18 Q5 D6 Q6 D7 Q7 2 4 5 7 6 9 8 9 12 13 12 14 15 17 16 18 19 5 6 15 16 19 OE 1 Fig 2. mna196 mna891 Logic symbol D0 Fig 3. D1 D Q D2 D CP Q D3 D CP FF1 2 1D Q FF2 D4 D CP Q D5 D CP FF3 IEC logic symbol Q D CP FF4 D6 Q D CP FF5 D7 Q D CP FF6 Q CP FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna893 Fig 4. Logic diagram © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 3 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 5. Pinning information 5.1 Pinning OE 1 Q0 2 20 VCC 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 Q2 6 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP 374 16 Q6 15 Q5 001aad040 Fig 5. Pin configuration SO20 and TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin Description OE 1 3-state output enable input (active LOW) Q0 2 3-state flip-flop output D0 3 data input D1 4 data input Q1 5 3-state flip-flop output Q2 6 3-state flip-flop output D2 7 data input D3 8 data input Q3 9 3-state flip-flop output GND 10 ground (0 V) CP 11 clock input (LOW-to-HIGH, edge triggered) Q4 12 3-state flip-flop output D4 13 data input D5 14 data input Q5 15 3-state flip-flop output Q6 16 3-state flip-flop output D6 17 data input D7 18 data input Q7 19 3-state flip-flop output VCC 20 supply voltage © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 4 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 6. Functional description Table 3. Function table[1] Operating mode OE CP Dn Internal flip-flop Load and read register L ↑ l L L L ↑ h H H Load register and disable outputs H ↑ l L Z H ↑ h H Z [1] Control Input Output Q0 to Q7 H = HIGH voltage level; h = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition; X = don’t care; ↑ = LOW-to-HIGH CP transition; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI Conditions Min Max Unit supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V −20 - mA −20 +20 mA input clamping current VI < −0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] VO = −0.5 V to (VCC + 0.5 V) IIK IO output current −25 +25 mA ICC supply current - +75 mA IGND ground current −75 - mA Tstg storage temperature −65 +150 °C - 500 mW total power dissipation Ptot Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 5 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit 2.0 5.0 5.5 V 74AHC374 VCC supply voltage VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V VCC = 4.5 V to 5.5 V - - 20 ns/V 74AHCT374 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate - - 20 ns/V VCC = 4.5 V to 5.5 V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74AHC374 VIH VIL VOH VOL HIGH-level input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V LOW-level input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = −8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 6 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 µA IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V - - ±0.25 - ±2.5 - ±10.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 µA CI input capacitance - 3 10 - 10 - 10 pF CO output capacitance - 4 - - - - - pF VI = VCC or GND 74AHCT374 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA IO = −8.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA 4.4 4.5 - 4.4 - 4.4 - V 3.94 - - 3.80 - 3.70 - V - 0 0.1 - 0.1 - 0.1 V - - 0.36 - 0.44 - 0.55 V II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 µA IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V - - ±0.25 - ±2.5 - ±10.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 µA ∆ICC additional per input pin; supply current VI = VCC − 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 3 10 - 10 - 10 pF CO output capacitance - 4 - - - - - pF VI = VCC or GND © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 7 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max CL = 15 pF - 6.4 12.7 1.0 15.0 1.0 16.0 ns CL = 50 pF - 8.4 16.2 1.0 18.5 1.0 20.5 ns - 4.4 8.1 1.0 9.5 1.0 10.0 ns - 5.7 10.1 1.0 11.5 1.0 12.5 ns CL = 15 pF - 5.5 11.0 1.0 13.0 1.0 14.0 ns CL = 50 pF - 7.3 14.5 1.0 16.5 1.0 18.0 ns - 3.9 7.6 1.0 9.0 1.0 9.5 ns - 5.2 9.6 1.0 11.0 1.0 12.0 ns CL = 15 pF - 5.6 10.5 1.0 12.5 1.0 13.0 ns CL = 50 pF - 9.4 14.0 1.0 16.0 1.0 17.5 ns CL = 15 pF - 4.2 6.8 1.0 8.0 1.0 8.5 ns CL = 50 pF - 6.4 8.8 1.0 10.0 1.0 11.0 ns CL = 15 pF 80 130 - 70 - 70 - MHz CL = 50 pF 55 85 - 50 - 50 - MHz CL = 15 pF 130 185 - 110 - 110 - MHz CL = 50 pF 85 120 - 75 - 75 - MHz VCC = 3.0 V to 3.6 V 5.0 - - 5.5 - 5.5 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 4.5 - - 4.0 - 4.0 - ns VCC = 4.5 V to 5.5 V 3.0 - - 3.0 - 3.0 - ns 74AHC374 tpd propagation CP to Qn; see Figure 6 and delay Figure 8 [2] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF ten enable time OE to Qn; see Figure 7 [3] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tdis disable time OE to Qn; see Figure 7 [4] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V fmax maximum frequency see Figure 6 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tW tsu pulse width set-up time CP HIGH or LOW; see Figure 6 Dn to CP; see Figure 8 © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 8 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter th CPD hold time 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max VCC = 3.0 V to 3.6 V 2.0 - - 2.0 - 2.0 - ns VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - ns - 10 - - - - - pF CL = 15 pF - 4.3 9.4 1.0 10.5 1.0 12.0 ns CL = 50 pF - 5.6 10.4 1.0 11.5 1.0 13.0 ns - 3.5 10.2 1.0 11.5 1.0 13.0 ns - 4.8 11.2 1.0 12.5 1.0 14.0 ns CL = 15 pF - 3.6 10.2 1.0 11.0 1.0 13.0 ns CL = 50 pF - 5.7 11.2 1.0 12.0 1.0 14.0 ns CL = 15 pF 90 140 - 80 - 80 - MHz CL = 50 pF 85 130 - 75 - 75 - MHz Dn to CP; see Figure 8 fi = 1 MHz; VI = GND to VCC power dissipation capacitance [5] 74AHCT374; VCC = 4.5 V to 5.5 V tpd ten propagation CP to Qn; see Figure 6 and delay Figure 8 [2] [3] enable time OE to Qn; see Figure 7 CL = 15 pF CL = 50 pF tdis fmax [4] disable time OE to Qn; see Figure 7 maximum frequency see Figure 6 tW pulse width CP HIGH or LOW; see Figure 6 6.5 - - 6.5 - 6.5 - ns tsu set-up time Dn to CP; see Figure 8 2.5 - - 2.5 - 2.5 - ns th hold time Dn to CP; see Figure 8 2.5 - - 2.5 - 2.5 - ns - 12 - - - - - pF CPD power fi = 1 MHz; VI = GND to VCC dissipation capacitance [5] [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. [3] ten is the same as tPZH and tPZL. [4] tdis is the same as tPHZ and tPLZ. [5] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 9 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 10.1 Waveforms 1/fmax VI CP input VM GND tW t PHL t PLH VOH VM Qn output 001aac426 VOL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Clock pulse width, maximum frequency and input to output propagation delays VI OE input VM GND t PLZ t PZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY Qn output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled mna813 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Enable and disable times © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 10 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state VI VM CP input GND tsu tsu th th VI VM Dn input GND VOH VM Qn output VOL mna202 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Data set-up and hold times Table 8. Measurement points Type Input Output VM VM VX VY 74AHC374 0.5 × VCC 0.5 × VCC VOL + 0.3 V VOH − 0.3 V 74AHCT374 1.5 V 0.5 × VCC VOL + 0.3 V VOH − 0.3 V © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 11 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. S1 = test selection switch. Fig 9. Test circuitry for measuring switching times Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74AHC374 VCC ≤ 3.0 ns 15 pF, 50 pF 1 kΩ open GND VCC 74AHCT374 3.0 V ≤ 3.0 ns 15 pF, 50 pF 1 kΩ open GND VCC © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 12 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 11. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT163-1 (SO20) © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 13 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 11. Package outline SOT360-1 (TSSOP20) © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 14 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT374_3 20080612 Product data sheet - 74AHC_AHCT374_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 6: the conditions for input leakage current have been changed. 74AHC_AHCT374_2 19990928 Product specification - 74AHC_AHCT374_1 74AHC_AHCT374_1 19981211 Product specification - - © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 15 of 17 74AHC374; 74AHCT374 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 14.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia accepts no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Nexperia. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com © 74AHC_AHCT374_3 Product data sheet Rev. 03 — 12 June 2008 Nexperia B.V. 2017. All rights reserved 16 of 17 Nexperia 74AHC374; 74AHCT374 Octal D-type flip-flop; positive edge-trigger; 3-state 16. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 10.1 11 12 13 14 14.1 14.2 14.3 14.4 15 16 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 12 June 2008