74HCT175DB,118

74HC175; 74HCT175 Quad D-type flip-flop with reset; positive-edge trigger Rev. 6 — 4 February 2021 Product data sheet 1. General description The 74HC175; 74HCT175 is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn) and complementary outputs (Qn and Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • • • • • • Input levels: • For 74HC175: CMOS level • For 74HCT175: TTL level Four edge-triggered D-type flip-flops Asynchronous master reset Complies with JEDEC standard no. 7A ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and -40 °C to +125 °C. 3. Ordering information Table 1. Ordering information Type number Package 74HC175D Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT175D 74HC175PW 74HCT175PW 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger 4. Functional diagram 9 1 9 4 5 12 13 D0 2 1D 3 7 5 6 Q1 6 10 Q2 11 Q2 10 12 11 15 Q3 14 MR Q3 1 Fig. 1. 7 Q1 D2 4 3 Q0 D1 D3 2 CP Q0 C1 R 15 13 14 aaa-008921 aaa-008922 Logic symbol Fig. 2. D0 D1 D Q CP D2 D FF1 IEC logic symbol Q CP D FF2 Q D3 Q CP FF3 Q RD D Q CP FF4 Q RD Q RD RD CP MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 aaa-008927 Fig. 3. Logic diagram 74HC_HCT175 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 2 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger 5. Pinning information 5.1. Pinning 74HC175 74HCT175 MR 1 16 VCC Q0 2 15 Q3 Q0 3 14 Q3 D0 4 13 D3 D1 5 12 D2 Q1 6 11 Q2 Q1 7 10 Q2 GND 8 9 74HC175 74HCT175 CP MR 1 Q0 2 16 VCC 15 Q3 Q0 3 14 Q3 D0 4 13 D3 D1 5 12 D2 Q1 6 11 Q2 Q1 7 10 Q2 GND 8 9 aaa-008929 Fig. 4. CP aaa-008930 Pin configuration SOT109-1 (SO16) Fig. 5. Pin configuration SOT403-1 (TSSOP16) 5.2. Pin description Table 2. Pin description Symbol Pin Description MR 1 asynchronous master reset input (active LOW) Q0 to Q3 2, 7, 10, 15 flip-flop output Q0 to Q3 3, 6, 11, 14 complementary flip-flop output D0 to D3 4, 5, 12, 13 data input GND 8 ground (0 V) CP 9 clock input (LOW-to-HIGH edge-triggered) VCC 16 positive supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care; ↑ = LOW-to-HIGH clock transition. Operating modes Inputs Outputs MR CP Dn Qn Qn reset (clear) L X X L H load "1" H ↑ h H L load "0" H ↑ l L H 74HC_HCT175 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 3 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger 4 5 12 13 D0 D1 D2 D3 D Q CP D FF1 Q CP D FF2 Q Q CP FF3 Q RD D Q CP FF4 Q RD Q RD RD 9 CP 1 MR Q0 3 Q0 Q1 2 6 Q1 Q2 Q2 Q3 Q3 7 11 10 14 15 aaa-008931 Fig. 6. Functional diagram 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage IIK input clamping current IOK Min Max -0.5 +7 V VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current -0.5 V < VO < VCC + 0.5 V - ±25 mA ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] Conditions Tamb = -40 °C to +125 °C [1] Unit For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC175 74HCT175 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 - +125 -40 - +125 °C Δt/ΔV input transition rise and fall rate VCC supply voltage VI 74HC_HCT175 Product data sheet VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 4 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 VCC = 4.5 V 3.15 2.4 - 1.5 - 3.15 - 1.5 - V - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V 74HC175 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1 - ±1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 μA CI input capacitance - 3.5 - - - - - pF 74HC_HCT175 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 5 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74HCT175 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA; VCC = 5.5 V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1 - ±1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80 - 160 μA ΔICC additional supply current per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V Dn input - 40 144 - 180 - 196 μA CP input - 60 216 - 270 - 294 μA MR input - 100 360 - 450 - 490 μA - 3.5 - - - - - pF VOL CI input capacitance 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Fig. 10 Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 55 175 - 220 - 265 ns VCC = 4.5 V - 20 35 - 44 - 53 ns VCC = 5 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 16 30 - 37 - 45 ns VCC = 2.0 V - 50 150 - 190 - 225 ns VCC = 4.5 V - 18 30 - 38 - 45 ns VCC = 5 V; CL = 15 pF - 15 - - - - - ns VCC = 6.0 V - 14 26 - 33 - 38 ns 74HC175 tpd tPHL propagation delay HIGH to LOW propagation delay 74HC_HCT175 Product data sheet CP to Qn, Qn; see Fig. 7 [1] MR to Qn, Qn; see Fig. 8 All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 6 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger Symbol Parameter tt tW transition time pulse width Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 80 19 - 100 - 120 - ns VCC = 4.5 V 16 7 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 5 -33 - 5 - 5 - ns VCC = 4.5 V 5 -12 - 5 - 5 - ns VCC = 6.0 V 5 -10 - 5 - 5 - ns VCC = 2.0 V 80 3 - 100 - 120 - ns VCC = 4.5 V 16 1 - 20 - 24 - ns VCC = 6.0 V 14 1 - 17 - 20 - ns VCC = 2.0 V 25 2 - 30 - 40 - ns VCC = 4.5 V 5 0 - 6 - 8 - ns VCC = 6.0 V 4 0 - 5 - 7 - ns VCC = 2.0 V 6 25 - 4.8 - 4 - MHz VCC = 4.5 V 30 75 - 24 - 20 - MHz - 83 - - - - - MHz 35 89 - 28 - 24 - MHz - 32 - - - - - pF Qn output; see Fig. 7 [2] CP input HIGH or LOW; see Fig. 7 MR input LOW; see Fig. 8 trec tsu th fmax recovery time set-up time hold time maximum frequency MR to CP; see Fig. 8 Dn to CP; see Fig. 9 Dn to CP; see Fig. 9 CP input; see Fig. 7 VCC = 5 V; CL = 15 pF VCC = 6.0 V CPD power per package; VI = GND to VCC [3] dissipation capacitance 74HC_HCT175 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 7 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 4.5 V - 19 33 - 41 - 50 ns VCC = 5 V; CL = 15 pF - 16 - - - - - ns VCC = 4.5 V - 22 38 - 48 - 57 ns VCC = 5 V; CL = 15 pF - 19 - - - - - ns VCC = 4.5 V - 19 35 - 44 - 53 ns VCC = 5 V; CL = 15 pF - 16 - - - - - ns - 7 15 - 19 - 22 ns 20 12 - 25 - 30 - ns 20 11 - 25 - 30 - ns 5 -10 - 5 - 5 - ns 16 5 - 20 - 24 - ns 5 0 - 5 - 5 - ns 25 49 - 20 - 17 - MHz - 54 - - - - - MHz - 34 - - - - - pF 74HCT175 tpd propagation delay tPHL HIGH to LOW propagation delay CP to Qn, Qn; see Fig. 7 [1] MR to Qn; see Fig. 8 MR to Qn; see Fig. 8 tt transition time Qn output; see Fig. 7 tW pulse width CP input HIGH or LOW; see Fig. 7 [2] VCC = 4.5 V VCC = 4.5 V MR input LOW; see Fig. 8 VCC = 4.5 V trec tsu recovery time MR to CP; see Fig. 8 set-up time Dn to CP; see Fig. 9 VCC = 4.5 V VCC = 4.5 V th hold time Dn to CP; see Fig. 9 VCC = 4.5 V fmax maximum frequency CP input; see Fig. 7 VCC = 4.5 V VCC = 5 V; CL = 15 pF CPD [1] [2] [3] power per package; dissipation VI = GND to VCC - 1.5 V capacitance [3] tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi + Σ (CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; 2 Σ (CL x VCC x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 74HC_HCT175 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 8 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger 10.1. Waveforms and test circuit 1/fmax VI VM CP input GND tW tPHL VOH tPLH VM Qn output VOL tTHL tPLH VOH Qn output tTLH tPHL VM VOL tTLH tTHL aaa-008932 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 7. Input to output propagation delay, output transition time, clock input pulse width and maximum frequency VI VM MR input GND tW trem VI VM CP input GND tPHL VOH VM Qn output VOL VOH tPLH VM Qn output VOL aaa-008934 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. Master reset to output propagation delays, master reset pulse width and master reset to clock recovery time 74HC_HCT175 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 9 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger VI CP input VM GND tsu VI Dn input tsu th th VM GND VOH VM Qn output VOL VOH VM Qn output VOL aaa-008933 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 9. Data set-up and hold times for data input Table 8. Measurement points Type Input Output VI VM VM 74HC175 VCC 0.5VCC 0.5VCC 74HCT175 3V 1.3 V 1.3 V 74HC_HCT175 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 10 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger VI negative pulse VM VI GND VM 10 % GND positive pulse tW 90 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VO RT CL 001aah768 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. Fig. 10. Test circuit for measuring switching times Table 9. Test data Type Input Load Test VI tr, tf CL RL 74HC175 VCC 6 ns 15 pF, 50 pF 1 kΩ tPLH, tPHL 74HCT175 3V 6 ns 15 pF, 50 pF 1 kΩ tPLH, tPHL 74HC_HCT175 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 11 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger 11. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 11. Package outline SOT109-1 (SO16) 74HC_HCT175 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 12 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 12. Package outline SOT403-1 (TSSOP16) 74HC_HCT175 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 13 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT175 v.6 20210204 Product data sheet - 74HC_HCT175 v.5 Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type numbers 74HC175DB and 74HCT175DB (SOT338-1 / SSOP16) removed. Section 7: Derating values for Ptot total power dissipation updated. 74HC_HCT175 v.5 20160129 Modifications: • 74HC_HCT175 v.4 20140408 Modifications: • 74HC_HCT175 v.3 20140331 Modifications: • • 74HC_HCT175_CNV_2 74HC_HCT175 Product data sheet Product data sheet - 74HC_HCT175 v.4 Type numbers 74HC175N and 74HCT175N (SOT38-4) removed. Product data sheet - 74HC_HCT175 v.3 - 74HC_HCT175_CNV_2 General description corrected (errata). Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. 19980708 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 - © Nexperia B.V. 2021. All rights reserved 14 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger 14. Legal information injury, death or severe property or environmental damage. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 15 / 16 74HC175; 74HCT175 Nexperia Quad D-type flip-flop with reset; positive-edge trigger Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 3 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................4 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 6 10.1. Waveforms and test circuit........................................ 9 11. Package outline........................................................ 12 12. Abbreviations............................................................ 14 13. Revision history........................................................14 14. Legal information......................................................15 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 4 February 2021 74HC_HCT175 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 4 February 2021 © Nexperia B.V. 2021. All rights reserved 16 / 16