74LVT162374DL,112

74LVT162374 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state Rev. 4 — 1 October 2018 Product data sheet 1. General description The 74LVT162374 is a high performance BiCMOS product designed for VCC operation at 3.3 V. The 74LVT162374 is designed with 30 Ω series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus receivers/transmitters. This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CP), the Q outputs of the flip-flop take on the logic levels set up at the D inputs. 2. Features and benefits • • • • • • • • • • • • • 16-bit edge-triggered flip-flop 3-state buffers Output capability: +12 mA and −12 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Outputs include series resistance of 30 Ω making external resistors unnecessary Power-up reset Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection: • JESD78B Class II exceeds 500 mA ESD protection: • HBM: JESD22-A114F exceeds 2000 V • MM: JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LVT162374DGG -40 °C to +85 °C Name Description Version TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 74LVT162374 Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state 4. Functional diagram 47 46 44 43 41 40 38 37 1 1OE 48 1CP 24 2OE 25 2CP 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 48 1CP 1 1OE 1D0 1D1 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2 36 3 5 35 33 6 32 8 30 9 11 29 27 1D2 1D3 12 1D4 1D5 26 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 25 2CP 24 2OE 2D0 2D1 2D2 2D3 2D4 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2D5 2D6 13 14 16 17 19 20 22 23 2D7 EN1 C3 EN2 C4 47 3D 46 5 43 6 41 8 40 9 38 11 37 12 36 4D 35 Fig. 2. nD1 D CP nD2 D Q CP nD3 D Q CP 13 2 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 001aaa254 Logic symbol nD0 3 44 001aac369 Fig. 1. 2 1 nD4 D Q IEC logic symbol CP nD5 D Q CP nD6 D Q CP nD7 D Q CP D Q CP Q nCP nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 001aac371 Fig. 3. Logic diagram 74LVT162374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 2 / 12 74LVT162374 Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state VCC VCC 27 Ω output 27 Ω 001aac372 Fig. 4. Schematic of each output 5. Pinning information 5.1. Pinning 74LVT162374 1OE 1 48 1CP 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 42 VCC 1Q4 8 41 1D4 1Q5 9 40 1D5 GND 10 39 GND 1Q6 11 38 1D6 1Q7 12 37 1D7 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 31 VCC 2Q4 19 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2CP aaa-029126 Fig. 5. Pin configuration SOT362-1 (TSSOP48) 74LVT162374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 3 / 12 74LVT162374 Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state 5.2. Pin description Table 2. Pin description Symbol Pin Description 1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7 47, 46, 44, 43, 41, 40, 38, 37 data inputs 2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7 36, 35, 33, 32, 30, 29, 27, 26 data inputs 1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7 2, 3, 5, 6, 8, 9, 11, 12 data outputs 2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7 13, 14, 16, 17, 19, 20, 22, 23 data outputs 1OE, 2OE 1, 24 output enable inputs (active LOW) 1CP, 2CP 48, 25 clock pulse inputs (active rising edge) GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V) VCC 7, 18, 31, 42 supply voltage 6. Functional description Table 3. Function table [1] Operating mode Output nOE nCP nDn Internal flip-flops L ↑ l L L L ↑ h H H Hold L NC X NC NC Disable outputs H NC X NC Z H ↑ nDn nDn Z Load and read register [1] Input nQn H = HIGH voltage level; L = LOW voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; NC = no change; X = don’t care; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage VI input voltage VO output voltage output in OFF-state or HIGH-state IIK input clamping current IOK IO Tstg Conditions Min Max Unit -0.5 +4.6 V [1] -0.5 +7.0 V [1] -0.5 +7.0 V VI < 0 V -50 - mA output clamping current VO < 0 V -50 - mA output current output in LOW-state - 128 mA output in HIGH-state -64 - mA -65 +150 °C storage temperature 74LVT162374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 4 / 12 74LVT162374 Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state Symbol Parameter Tj junction temperature [1] [2] Conditions Min [2] Max Unit +150 °C The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage Δt/ΔV input transition rise and fall rate Tamb ambient temperature Conditions outputs enabled Min Typ Max Unit 2.7 - 3.6 V 0 - 5.5 V - - 10 ns/V -40 - +85 °C Min Typ[1] Max Unit - -0.85 -1.2 V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VIK input clamping voltage VCC = 2.7 V; IIK = -18 mA VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V VOH HIGH-level output voltage VCC = 3.0 V; IOH = -12 mA 2.0 - - V VOL LOW-level output voltage VCC = 3.0 V; IOL = 12 mA - - 0.8 V IOH HIGH-level output current - - -12 mA IOL LOW-level output current - - 12 mA VOL(pu) power-up LOW-level output voltage VCC = 3.6 V; IO = 1 mA; VI = GND or VCC [2] - 0.1 0.55 V II input leakage current all input pins - 0.4 10 μA - 0.1 ±1 μA VI = VCC - 0.1 1 μA VI = 0 V - -0.4 -5 μA - 0.1 ±100 μA [3] VCC = 0 V or 3.6 V; VI = 5.5 V control pins [3] VCC = 3.6 V; VI = VCC or GND I/O data pins; VCC = 3.6 V [3] IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V IBHL bus hold LOW current nDn inputs; VCC = 3 V; VI = 0.8 V 75 135 - μA IBHH bus hold HIGH current nDn inputs; VCC = 3 V; VI = 2.0 V -75 -135 - μA IBHLO bus hold LOW overdrive current nDn inputs; VCC = 3.6 V; VI = 0 V to 3.6 V [4] 500 - - μA IBHHO bus hold HIGH overdrive current nDn inputs; VCC = 3.6 V; VI = 0 V to 3.6 V [4] - - -500 μA ICEX output high leakage current output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V - 50 125 μA IO(pu/pd) power-up/power-down output current - 1 ±100 μA 74LVT162374 Product data sheet VCC ≤ 1.2 V; VO = 5.0 V to VCC; VI = GND or VCC; nOE = don’t care All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 [5] © Nexperia B.V. 2018. All rights reserved 5 / 12 74LVT162374 Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state Symbol Parameter Conditions IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL ICC Min Typ[1] Max Unit VO = 3.0 V - 0.5 5 μA VO = 0.5 V - 0.5 -5 μA outputs HIGH - 0.07 0.12 mA outputs LOW - 4 6 mA [6] - 0.07 0.12 mA [7] - 0.1 0.2 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A supply current outputs disabled ΔICC additional supply current per input pin; VCC = 3 V to 3.6 V; one input at VCC - 0.6 V; other inputs at VCC or GND CI input capacitance VI = 0 V or 3.0 V - 3 - pF CO output capacitance outputs disabled; VO = 0 V or 3.0 V - 9 - pF [1] [2] [3] [4] [5] [6] [7] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. For valid test results, data must not be loaded into the flip-flops after applying power. Unused pins at VCC or GND. This is the bus-hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only. ICC is measured with outputs pulled to VCC or GND. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions; Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 9. Symbol Parameter Conditions Min Typ[1] Max Unit fmax maximum frequency nCP; VCC = 3.0 V to 3.6 V; see Fig. 6 150 - - MHz tPLH LOW to HIGH propagation delay nCP to nQn; see Fig. 6 - - 6.2 ns 1.5 3.0 5.3 ns HIGH to LOW propagation delay nCP to nQn; see Fig. 6 - - 5.1 ns 1.5 3.0 4.9 ns VCC = 2.7 V VCC = 3.0 V to 3.6 V tPHL VCC = 2.7 V VCC = 3.0 V to 3.6 V tPZH OFF-state to HIGH propagation delay nOE to nQn; see Fig. 8 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPZL OFF-state to LOW propagation delay HIGH to OFF-state propagation delay VCC = 2.7 V LOW to OFF-state propagation delay VCC = 2.7 V Product data sheet ns 5.6 ns - - 6.0 ns 1.5 3.2 4.9 ns - - 5.7 ns 1.5 3.5 5.4 ns - - 5.1 ns 1.5 3.2 5.0 ns nOE to nQn; see Fig. 8 VCC = 2.7 V VCC = 3.0 V to 3.6 V 74LVT162374 6.9 nOE to nQn; see Fig. 8 VCC = 3.0 V to 3.6 V tPLZ 3.5 nOE to nQn; see Fig. 8 VCC = 3.0 V to 3.6 V tPHZ 1.5 All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 6 / 12 74LVT162374 Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state Symbol Parameter Conditions tsu set-up time nDn to nCP; see Fig. 7 th [1] Max Unit VCC = 2.7 V 2.0 - - ns VCC = 3.0 V to 3.6 V 2.0 0.7 - ns VCC = 2.7 V 0.1 - - ns VCC = 3.0 V to 3.6 V 0.8 0 - ns nCP; see Fig. 6 pulse width HIGH tWL Typ[1] nDn to nCP; see Fig. 7 hold time tWH Min VCC = 2.7 V 1.5 - - ns VCC = 3.0 V to 3.6 V 1.5 0.6 - ns VCC = 2.7 V 3.0 - - ns VCC = 3.0 V to 3.6 V 3.0 1.6 - ns nCP pulse width LOW Typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 10.1. Waveforms and test circuit 1 / fmax VI nCP input GND VOH nQn output VOL VM VM tW tPHL VI nCP input GND VM tPLH VM VM tsu nDn input GND VM 001aal773 VM VM tsu th VI Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 6. VM VM VM th VM 001aal774 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Clock input (nCP) to output (nQn) propagation delay, clock pulse width and maximum clock frequency Fig. 7. Data set-up and hold times for input (nDn) to input (nCP) VI VM nOE input VM GND tPLZ nQn output LOW-to-OFF OFF-to-LOW tPZL 3.0 V VM VX VOL tPHZ nQn output HIGH-to-OFF OFF-to-HIGH VOH tPZH VY VM GND outputs enabled outputs disabled outputs enabled aaa-029125 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. 3-state output enable and disable times 74LVT162374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 7 / 12 74LVT162374 Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state Table 8. Measurement points Input Output VI VM VM VX VY 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig. 9. Test circuit for measuring switching times Table 9. Test data Input Load VEXT VI fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω GND 6V open 74LVT162374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 8 / 12 74LVT162374 Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state 11. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 A1 (A3) pin 1 index A θ Lp 1 L 24 bp e detail X w 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit mm max nom min A 1.2 A1 A2 0.15 1.05 0.05 0.85 A3 0.25 bp c D(1) E(2) 0.28 0.2 12.6 6.2 0.17 0.1 12.4 6.0 e HE 0.5 8.3 7.9 L 1 Lp Q 0.8 0.50 0.4 0.35 v w 0.25 0.08 y 0.1 Z θ 0.8 8° 0.4 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Fig. 10. Package outline SOT362-1 (TSSOP48) 74LVT162374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 9 / 12 74LVT162374 Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge MIL Military MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT162374 v.4 20181001 Product data sheet - 74LVT162374 v.3 Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74LVT162374DL (SOT370-1) removed Section "Quick reference data" removed 74LVT162374 v.3 20050117 Modifications: • • • • Product data sheet - 74LVT162374 v.2 The format of this data sheet is redesigned to comply with the current presentation and information standard of Philips Semiconductors. Section 2: Changed JEDEC Std 17 into JESD78 Table 1 "Quick reference data": Changed tPLH and tPHL propagation delays nCP to nQn to 3.0 ns Table 7: Changed the minimum values of th(H) and th(L) hold time nDn to nCP to 0.8 ns 74LVT162374 v.2 20040922 Product specification - 74LVT162374 v.1 74LVT162374 v.1 19990923 Product specification - - 74LVT162374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 10 / 12 74LVT162374 Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 11 / 12 74LVT162374 Nexperia 3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 4 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 6 10.1. Waveforms and test circuit........................................ 7 11. Package outline.......................................................... 9 12. Abbreviations............................................................ 10 13. Revision history........................................................10 14. Legal information......................................................11 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 1 October 2018 74LVT162374 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 12 / 12