74ALVT16823DL,518

74ALVT16823 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Rev. 6 — 20 October 2020 Product data sheet 1. General description The 74ALVT16823 is an 18-bit positive-edge triggered D-type flip-flop with 3-state outputs, reset and enable. The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. The device features clock (nCP), clock enable (nCE), master reset (nMR) and output enable (nOE, inputs each controlling 9-bits. When nCE is LOW, the flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. A LOW on nMR will reset the flip-flops LOW. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs 2. Features and benefits • • • • • • • • • • • • • • • • Wide supply voltage range from 2.3 V to 3.6 V Overvoltage tolerant inputs to 5.5 V BiCMOS high speed and output drive Direct interface with TTL levels Bus hold on data inputs Power-up 3-state IOFF circuitry provides partial Power-down mode operation Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors Live insertion and extraction permitted Power-up reset No bus current loading when output is tied to 5 V bus Output capability: +64 mA to -32 mA Latch-up performance exceeds 500 mA per JESD 78 Class II Level B ESD protection: • MIL STD 883, method 3015: exceeds 2000 V • MM: exceeds 200 V Specified from -40 °C to 85 °C 3. Ordering information Table 1. Ordering information Type number Package 74ALVT16823DGG Temperature range Name Description Version -40 °C to +85 °C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 4. Functional diagram 1OE 1MR 1CE 1CP 2OE 2MR 2CE 2CP 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2 1 55 56 27 28 30 29 54 52 EN1 R2 G3 3C4 EN5 R6 G7 7C8 4D 1,2 3 5 51 6 49 8 48 9 47 10 45 12 44 13 43 14 42 41 8D 5,6 15 16 40 17 38 19 37 20 36 21 34 23 33 24 31 26 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 VCC 2Q0 2Q1 2Q2 2Q3 data input 2Q4 2Q5 2Q6 2Q7 2Q8 001aad245 001aad242 Fig. 1. IEC logic symbol 74ALVT16823 Product data sheet to internal circuit Fig. 2. Bushold circuit (one data input) All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 © Nexperia B.V. 2020. All rights reserved 2 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state nCE nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nCP CP nD R CP nD Q R CP nD Q R CP nD Q R CP nD Q R CP nD Q R CP nD Q R CP nD Q R CP nD Q R Q nMR nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 001aad243 Fig. 3. Logic diagram 74ALVT16823 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 © Nexperia B.V. 2020. All rights reserved 3 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 5. Pinning information 5.1. Pinning 1MR 1 56 1CP 1OE 2 55 1CE 1Q0 3 54 1D0 GND 4 53 GND 1Q1 5 52 1D1 1Q2 6 51 1D2 VCC 7 50 VCC 1Q3 8 49 1D3 1Q4 9 48 1D4 1Q5 10 47 1D5 GND 11 46 GND 1Q6 12 45 1D6 1Q7 13 44 1D7 1Q8 14 43 1D8 74ALVT16823 2Q0 15 42 2D0 2Q1 16 41 2D1 2Q2 17 40 2D2 GND 18 39 GND 2Q3 19 38 2D3 2Q4 20 37 2D4 2Q5 21 36 2D5 VCC 22 35 VCC 2Q6 23 34 2D6 2Q7 24 33 2D7 GND 25 32 GND 2Q8 26 31 2D8 2OE 27 30 2CE 2MR 28 29 2CP 001aad403 Fig. 4. Pin configuration SOT364-1 (TSSOP56) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7, 1D8 54, 52, 51, 49, 48, 47, 45, 44, 43 data inputs 1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7, 1Q8 3, 5, 6, 8, 9, 10, 12, 13, 14 data outputs 2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7, 2D8 data inputs 42, 41, 40, 38, 37, 36, 34, 33, 31 2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7, 2Q8 15, 16, 17, 19, 20, 21, 23, 24, 26 data outputs 1MR, 2MR 1, 28 master reset input (active-LOW) 1OE, 2OE 2, 27 output enable inputs (active LOW) 1CP, 2CP 56, 29 clock pulse inputs (active rising edge) 1CE, 2CE 55, 30 clock enable input (active-LOW) GND 4, 11, 18, 25, 32, 39, 46, 53 ground (0 V) VCC 7, 22, 35, 50 supply voltage 74ALVT16823 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 © Nexperia B.V. 2020. All rights reserved 4 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 6. Functional description Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; NC = no change; X = don’t care; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition; ↑ = not a LOW-to-HIGH clock transition. Operating mode Output Input nOE nMR nCE nCP nDn nQn clear L L X X X L load and read data L H L ↑ h H l L hold L H H ↑ X NC high-impedance H X X X X Z 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage output in OFF-state or HIGH-state IIK input clamping current IOK IO Max Unit -0.5 +4.6 V [1] -0.5 +7.0 V [1] -0.5 +7.0 V VI < 0 V - -50 mA output clamping current VO < 0 V - -50 mA output current output in LOW-state - 128 mA output in HIGH-state -64 - mA -65 +150 °C - 150 °C Tstg storage temperature Tj junction temperature [1] [2] Min [2] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit 2.3 - 2.7 V VCC = 2.5 V VCC supply voltage VI input voltage 0 - 5.5 V IOH HIGH-level output current - - -8 mA IOL LOW-level output current none - - 8 mA current duty cycle ≤ 50 %; f ≥ 1 kHz - - 24 mA Δt/Δv input transition rise or fall rate outputs enabled - - 10 ns/V Tamb ambient temperature in free air -40 - +85 °C 74ALVT16823 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 © Nexperia B.V. 2020. All rights reserved 5 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Symbol Parameter Conditions Min Typ Max Unit 3.0 - 3.6 V VCC = 3.3 V VCC supply voltage VI input voltage 0 - 5.5 V IOH HIGH-level output current - - -32 mA IOL LOW-level output current none - - 32 mA current duty cycle ≤ 50 %; f ≥ 1 kHz - - 64 mA - - 10 ns/V -40 - +85 °C Δt/Δv input transition rise or fall rate outputs enabled Tamb ambient temperature in free air 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Tamb = −40 °C to +85 °C Unit Min Typ[1] Max - -0.85 -1.2 V VCC = 2.5 V ± 0.2 V VIK input clamping voltage VCC = 2.3 V; IIK = -18 mA VIH HIGH-level input voltage 1.7 - - V VIL LOW-level input voltage - - 0.7 V VOH HIGH-level output voltage VCC - 0.2 VCC - V VOL LOW-level output voltage VCC = 2.3 V to 2.7 V; IO = -100 μA VCC = 2.3 V; IO = -8 mA 1.8 2.5 - V VCC = 2.3 V; IO = 100 μA - 0.07 0.2 V VCC = 2.3 V; IO = 24 mA - 0.3 0.5 V VCC = 2.3 V; IO = 8 mA - - 0.4 V - - 0.55 V VCC = 2.7 V; VI = VCC or GND - 0.1 ±1 μA VCC = 0 V to 2.7 V; VI = 5.5 V - 0.1 10 μA VCC = 2.7 V; VI = VCC - 0.1 1 μA VCC = 2.7 V; VI = 0 V - +0.1 -5 μA - +0.1 ±100 μA - μA VOL(pu) power-up LOW-level output voltage VCC = 2.7 V; IO = 1 mA; VI = VCC or GND II input leakage current control pins I/O data pins [2] [3] IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V IBHL bus hold LOW current data inputs; VCC = 2.3 V; VI = 0.7 V [4] - 100 IBHH bus hold HIGH current data inputs; VCC = 2.3 V; VI = 1.7 V [4] - -70 - μA IEX external current output HIGH-state when VO > VCC; VO = 5.5 V; VCC = 2.3 V - 10 125 μA - 1 ±100 μA output HIGH state; VO = 2.3 V - 0.5 5 μA output LOW-state; VO = 0.5 V - +0.5 -5 μA IO(pu\pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC IOZ VCC = 2.7 V; VI = VIL or VIH OFF-state output current 74ALVT16823 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 [5] © Nexperia B.V. 2020. All rights reserved 6 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Symbol Parameter ICC supply current Conditions Tamb = −40 °C to +85 °C Unit Min Typ[1] Max outputs HIGH-state - 0.04 0.1 mA outputs LOW-state - 2.7 4.5 mA [6] - 0.04 0.1 mA [7] - 0.04 0.4 mA VCC = 2.7 V; VI = GND or VCC; IO = 0 A outputs disabled ΔICC additional supply current per input pin; VCC = 2.3 V to 2.7 V; one input at VCC - 0.6 V, other inputs at VCC or GND CI input capacitance VI = 0 V or VCC - 3 - pF CO output capacitance VI/O = 0 V or 3.0 V - 9 - pF VCC = 3.3 V ± 0.3 V VIK input clamping voltage - -0.85 -1.2 V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V VOH HIGH-level output voltage VCC - 0.2 VCC - V VCC = 3.0 V; IO = -32 mA 2.0 2.3 - V VCC = 3.0 V; IO = 100 μA - 0.07 0.2 V VCC = 3.0 V; IO = 16 mA - 0.25 0.4 V VCC = 3.0 V; IO = 32 mA - 0.3 0.5 V VCC = 3.0 V; IO = 64 mA - 0.4 0.55 V - - 0.55 V VCC = 3.6 V; VI = VCC or GND - 0.1 ±1 μA VCC = 0 V or 3.6 V; VI = 5.5 V - 0.1 10 μA VOL LOW-level output voltage VCC = 3.0 V; IIK = -18 mA VCC = 3.0 V to 3.6 V; IO = -100 μA VOL(pu) power-up LOW-level output voltage VCC = 3.6 V; IO = 1 mA; VI = VCC or GND II input leakage current control pins I/O data pins [2] [3] VCC = 3.6 V; VI = VCC - 0.5 1 μA VCC = 3.6 V; VI = 0 V - +0.1 -5 μA IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V - 0.1 ±100 μA IBHL bus hold LOW current data inputs; VCC = 3 V; VI = 0.8 V 75 130 - μA IBHH bus hold HIGH current data inputs; VCC = 3 V; VI = 2.0 V -75 -140 - μA IBHLO bus hold LOW overdrive current data inputs; VCC = 3.6 V; VI = 0 V to 3.6 V [8] 500 - - μA IBHHO bus hold HIGH overdrive current data inputs; VCC = 3.6 V; VI = 0 V to 3.6 V [8] −500 - - μA IEX external current output HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V - 10 125 μA - 1 ±100 μA output HIGH state; VO = 3.0 V - 0.5 5 μA output LOW-state; VO = 0.5 V - +0.5 -5 μA IO(pu\pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC IOZ VCC = 3.6 V; VI = VIL or VIH OFF-state output current 74ALVT16823 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 [9] © Nexperia B.V. 2020. All rights reserved 7 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Symbol Parameter ICC supply current Conditions Tamb = −40 °C to +85 °C Unit Min Typ[1] Max outputs HIGH-state - 0.06 0.1 mA outputs LOW-state - 3.9 5.5 mA [6] - 0.06 0.1 mA [7] - 0.04 0.4 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs disabled ΔICC additional supply current per input pin; VCC = 3 V to 3.6 V; one input at VCC - 0.6 V, other inputs at VCC or GND CI input capacitance VI = 0 V or VCC - 3 - pF CO output capacitance VI/O = 0 V or 3.0 V - 9 - pF [1] [2] [3] [4] [5] [6] [7] [8] [9] All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C. All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C. For valid test results, data must not be loaded into the flip-flops after applying power. Unused pins at VCC or GND. Not guaranteed. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 2.5 V ± 0.2 V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only. ICC is measured with outputs pulled up to VCC or pulled down to ground. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. This is the bus hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 9. Symbol Parameter Conditions Tamb = −40 °C to +85 °C Min Typ[1] Max Unit VCC = 2.5 V ± 0.2 V tPLH LOW to HIGH propagation delay nCP to nQn; see Fig. 5 1.5 2.9 4.5 ns tPHL HIGH-to-LOW propagation delay nCP to nQn; see Fig. 5 1.4 2.7 4.2 ns nMR to nQn; see Fig. 7 1.5 2.7 4.2 ns tPZH OFF-state to HIGH propagation delay nOE to nQn; see Fig. 8 2.1 3.4 5.0 ns tPZL OFF-state to LOW propagation delay nOE to nQn; see Fig. 8 1.8 3.0 4.7 ns tPHZ HIGH to OFF-state propagation delay nOE to nQn; see Fig. 8 1.7 3.0 4.3 ns tPLZ LOW to OFF-state propagation delay nOE to nQn; see Fig. 8 1.4 2.3 3.3 ns tsu(H) set-up time HIGH nDn to nCP; see Fig. 6 1.0 0.5 - ns nCE to nCP; see Fig. 6 1.0 0.2 - ns tsu(L) set-up time LOW nDn to nCP; see Fig. 6 1.8 1.3 - ns nCE to nCP; see Fig. 6 0.5 -0.1 - ns nDn to nCP; see Fig. 6 0.1 -1.4 - ns nCE to nCP; see Fig. 6 1.0 0.2 - ns nDn to nCP; see Fig. 6 0.1 -0.5 - ns nCE to nCP; see Fig. 6 1.0 -0.1 - ns th(H) th(L) hold time HIGH hold time LOW 74ALVT16823 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 © Nexperia B.V. 2020. All rights reserved 8 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Symbol Parameter Conditions Tamb = −40 °C to +85 °C Min Typ[1] Max Unit tWH pulse width HIGH nCP; see Fig. 5 2.0 0.8 - ns tWL pulse width LOW nCP 3.0 2.1 - ns nMR; see Fig. 7 2.0 0.8 - ns trec recovery time nMR to nCP; see Fig. 7 2.0 1.3 - ns fmax maximum frequency CP; see Fig. 5 150 - - MHz VCC = 3.3 V ± 0.3 V tPLH LOW to HIGH propagation delay nCP to nQn; see Fig. 5 1.0 2.3 3.1 ns tPHL HIGH-to-LOW propagation delay nCP to nQn; see Fig. 5 1.0 2.1 2.9 ns nMR to nQn; see Fig. 7 1.0 2.3 2.9 ns tPZH OFF-state to HIGH propagation delay nOE to nQn; see Fig. 8 1.7 2.7 4.0 ns tPZL OFF-state to LOW propagation delay nOE to nQn; see Fig. 8 1.4 2.3 3.5 ns tPHZ HIGH to OFF-state propagation delay nOE to nQn; see Fig. 8 2.2 3.1 4.0 ns tPLZ LOW to OFF-state propagation delay nOE to nQn; see Fig. 8 1.8 2.6 3.5 ns tsu(H) set-up time HIGH nDn to nCP; see Fig. 6 1.0 0.5 - ns nCE to nCP; see Fig. 6 1.0 0.1 - ns nDn to nCP; see Fig. 6 1.6 1.1 - ns nCE to nCP; see Fig. 6 0.5 -0.5 - ns nDn to nCP; see Fig. 6 0.1 -0.7 - ns nCE to nCP; see Fig. 6 1.0 0.5 - ns nDn to nCP; see Fig. 6 0.1 -0.5 - ns nCE to nCP; see Fig. 6 1.0 -0.1 - ns tsu(L) set-up time LOW th(H) hold time HIGH th(L) hold time LOW tWH pulse width HIGH nCP; see Fig. 5 1.5 0.7 - ns tWL pulse width LOW nCP 2.5 1.4 - ns nMR; see Fig. 7 2.0 1.5 - ns trec recovery time nMR to nCP; see Fig. 7 2.0 1.1 - ns fmax maximum frequency CP; see Fig. 5 250 - - MHz [1] All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C. All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C. 74ALVT16823 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 © Nexperia B.V. 2020. All rights reserved 9 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 10.1. Waveforms and test circuit 1/fmax VI nCP input VM VM GND tW t PHL t PLH VOH VM nQn output VOL 001aaa256 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 5. Propagation delay clock input (nCP) to output (nQn), clock pulse (nCP) width HIGH and maximum clock frequency VI input nDn, nCE VM GND VM t su(H) VM t h(H) VM t su(L) t h(L) VI input nCP VM VM GND 001aad401 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 6. Data set-up and hold times VI input nMR VM VM GND t WL t rec VI input nCP VM GND t PHL VOH output nQn VM VOL 001aad400 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 7. Master reset pulse width, master reset to output delay and master reset to clock recovery time 74ALVT16823 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 © Nexperia B.V. 2020. All rights reserved 10 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state VI nOE input VM VM GND tPLZ nQn output LOW-to-OFF OFF-to-LOW tPZL VCC VM VX VOL tPZH tPHZ nQn output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND outputs enabled outputs disabled outputs enabled 001aal795 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. OFF-state to HIGH and LOW propagation delays and LOW and HIGH to OFF-state propagation delays Table 8. Measurement points Input VCC Output VM VM VX VY ≤ 2.7 V 0.5 x VCC 0.5 x VCC VOL + 0.15 V VOH - 0.15 V ≥ 3.0 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig. 9. Test circuit for measuring switching times 74ALVT16823 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 © Nexperia B.V. 2020. All rights reserved 11 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Table 9. Test data Input VI Load fi 3.0 V or VCC ≤ 10 MHz whichever is less 74ALVT16823 Product data sheet VEXT tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL 500 ns ≤ 2.5 ns 50 pF 500 Ω GND 6 V or VCC × 2 open All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 © tPLH, tPHL Nexperia B.V. 2020. All rights reserved 12 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 11. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3 ) A1 pin 1 index A θ Lp L 1 28 w M bp e detail X 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig. 10. Package outline SOT364-1 (TSSOP56) 74ALVT16823 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 © Nexperia B.V. 2020. All rights reserved 13 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge MIL Military MM Machine Model MOS Metal-Oxide Semiconductor TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVT16823 v.6 20201020 Product data sheet - Modifications: • • 74ALVT16823 v.5 20180122 Modifications: • • Type number 74ALVT16823DL (SOT371-1 / SSOP56) removed. Section 1 and Section 2 updated. Product data sheet - 74ALVT16823 v.4 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. 74ALVT16823 v.4 20050802 Modifications: • • • 74ALVT16823 v.5 Product data sheet - 74ALVT16823 v.3 The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. Section 2: modified ‘Jedec Std 17’ into ‘JESD78’ Section 10: changed propagation delays. 74ALVT16823 v.3 19980612 Product specification - 74ALVT16823 v.2 74ALVT16823 v.2 19980612 Product specification - 74ALVT16823 v.1 74ALVT16823 v.1 19980303 Product specification - - 74ALVT16823 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 © Nexperia B.V. 2020. All rights reserved 14 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74ALVT16823 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 © Nexperia B.V. 2020. All rights reserved 15 / 16 74ALVT16823 Nexperia 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................4 5.1. Pinning.........................................................................4 5.2. Pin description............................................................. 4 6. Functional description................................................. 5 7. Limiting values............................................................. 5 8. Recommended operating conditions..........................5 9. Static characteristics....................................................6 10. Dynamic characteristics............................................ 8 10.1. Waveforms and test circuit...................................... 10 11. Package outline........................................................ 13 12. Abbreviations............................................................ 14 13. Revision history........................................................14 14. Legal information......................................................15 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 20 October 2020 74ALVT16823 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 20 October 2020 © Nexperia B.V. 2020. All rights reserved 16 / 16