74ALVCH16821DL,512

74ALVCH16821 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state Rev. 3 — 2 February 2018 1 Product data sheet General description The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates. Each register is fully edge triggered. The state of each nDn input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s nQn output. When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2 Features and benefits • • • • • • • • • • Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Current drive ± 24 mA at 3.0 V MULTIBYTE flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimum noise and ground bounce Output drive capability 50 Ω transmission lines at 85°C All data inputs have bushold Complies with JEDEC standard no. 8-1A Complies with JEDEC standards: – JESD8-5 (2.3 V to 2.7 V) – JESD8B/JESD36 (2.7 V to 3.6 V) • ESD protection: – HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V – CDM JESD22-C101E exceeds 1000 V 3 Ordering information Table 1. Ordering information Type number 74ALVCH16821DGG Package Temperature range Name Description −40 °C to +85 °C plastic thin shrink small outline package; 56 leads; SOT364-1 body width 6.1 mm TSSOP56 Version 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 4 Functional diagram 1OE 1CP 1 56 28 2OE 29 2CP 55 54 52 51 49 48 47 45 44 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 43 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 56 1CP 1 1OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2 3 5 6 8 9 10 12 13 14 42 41 40 38 37 36 34 33 31 30 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 29 2CP 28 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 15 16 17 19 20 21 23 24 26 27 55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30 EN2 C1 EN4 C3 1D 2 3D 4 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27 001aad155 001aad153 Figure 1. Logic symbol nD0 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 Figure 2. IEC logic symbol nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nD9 D D D D D D D D D D CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q nCP nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9 001aad156 Figure 3. Logic diagram 74ALVCH16821 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 2 / 15 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 5 Pinning information 5.1 Pinning 74ALVCH16821 1OE 1 56 1CP 1Q0 2 55 1D0 1Q1 3 54 1D1 GND 4 53 GND 1Q2 5 52 1D2 1Q3 6 51 1D3 VCC 7 1Q4 8 50 VCC 49 1D4 1Q5 9 48 1D5 1Q6 10 47 1D6 GND 11 46 GND 1Q7 12 45 1D7 1Q8 13 44 1D8 1Q9 14 43 1D9 2Q0 15 42 2D0 2Q1 16 41 2D1 2Q2 17 40 2D2 GND 18 39 GND 2Q3 19 38 2D3 2Q4 20 37 2D4 2Q5 21 36 2D5 VCC 22 2Q6 23 35 VCC 34 2D6 2Q7 24 33 2D7 GND 25 32 GND 2Q8 26 31 2D8 2Q9 27 30 2D9 2OE 28 29 2CP aaa-028138 Figure 4. Pin configuration SOT364-1 (TSSOP56) 74ALVCH16821 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 3 / 15 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 5.2 Pin description Table 2. Pin description Symbol Pin Description 1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7, 1D8, 1D9 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 data inputs 2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7, 2D8, 2D9 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 data inputs 1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7, 1Q8, 1Q9 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 data outputs 2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7, 2Q8, 2Q9 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 data outputs 1OE, 2OE 1, 28 output enable inputs (active LOW) 1CP, 2CP 56, 29 clock pulse inputs (active rising edge) GND 4, 11, 18, 25, 32, 39, 46, 53 ground (0 V) VCC 7, 22, 35, 50 supply voltage 6 Functional description Table 3. Function table Operating mode [1] Internal register Output Input nOE nCP nDn L ↑ l L L L ↑ h H H Hold L NC X NC NC Disable outputs H NC X NC Z H ↑ nDn nDn Z Load and read register nQn [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; NC = no change; X = don’t care; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition. 74ALVCH16821 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 4 / 15 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 7 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI Conditions input voltage Min Max Unit −0.5 +4.6 V For control pins [1] −0.5 +4.6 V For data inputs [1] −0.5 VCC + 0.5 V [1] −0.5 VCC + 0.5 V −50 - mA VO output voltage IIK input clamping current VI < 0 V IOK output clamping current VO > VCC or VO < 0 V - ±50 mA VO = 0 V to VCC - ±50 mA IO(sink/source) output sink or source current ICC supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C - 600 mW Ptot total power dissipation Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Above 55 °C the value of Ptot derates linearly with 8 mW/K. 8 Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC supply voltage 2.5 V range for maximum speed performance at 30 pF output load 2.3 2.7 V 3.3 V range for maximum speed performance at 50 pF output load 3.0 3.6 V VI input voltage 0 VCC V VO output voltage 0 VCC V Tamb ambient temperature in free air -40 +85 °C Δt/ΔV input transition rise and fall rate VCC = 2.3 V to 3.0 V - 20 ns/V VCC = 3.0 V to 3.6 V - 10 ns/V 74ALVCH16821 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 5 / 15 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 9 Static characteristics Table 6. Static characteristics At recommended operating conditions; Tamb = −40 °C to +85 °C; voltages are referenced to GND (ground = 0 V). [1] Symbol Parameter Conditions Min Typ VIH HIGH-level input voltage VCC = 2.3 V to 2.7 V 1.7 1.2 - V VCC = 2.7 V to 3.6 V 2.0 1.5 - V LOW-level input voltage VCC = 2.3 V to 2.7 V - 1.2 0.7 V VCC = 2.7 V to 3.6 V - 1.5 0.8 V HIGH-level output voltage VI = VIH or VIL IO = -100 μA; VCC = 2.3 V to 3.6 V VCC - 0.2 VCC - V IO = -6 mA; VCC = 2.3 V VCC - 0.3 VCC - 0.08 - V IO = -12 mA; VCC = 2.3 V VCC - 0.6 VCC - 0.26 - V IO = -12 mA; VCC = 2.7 V VCC - 0.5 VCC - 0.14 - V IO = -12 mA; VCC = 3.0 V VCC - 0.6 VCC - 0.09 - V IO = -24 mA; VCC = 3.0 V VCC - 1.0 VCC - 0.28 - V IO = 100 μA; VCC = 2.3 V to 3.6 V - GND 0.20 V IO = 6 mA; VCC = 2.3 V - 0.07 0.40 V IO = 12 mA; VCC = 2.3 V - 0.15 0.70 V IO = 12 mA; VCC = 2.7 V - 0.14 0.40 V IO = 24 mA; VCC = 3.0 V - 0.27 0.55 V VIL VOH VOL LOW-level output voltage Max Unit VI = VIH or VIL II input leakage current VCC = 2.3 V to 3.6 V; VI = VCC or GND - 0.1 5 μA IOZ OFF-state output current VCC = 2.7 V to 3.6 V; VI = VIH or VIL; VO = VCC or GND - 0.1 10 μA ICC supply current VCC = 2.3 V to 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 40 µA ΔICC additional supply current VCC = 2.3 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 150 750 μA IBHL bus hold LOW current VCC = 2.3 V; VI = 0.7 V 45 - - μA VCC = 3.0 V; VI = 0.8 V 75 150 - μA bus hold HIGH current VCC = 2.3 V; VI = 1.7 V -45 - - μA VCC = 3.0 V; VI = 2.0 V -75 -175 - μA IBHLO bus hold LOW overdrive current per data input; VCC = 3.6 V 500 - - μA IBHHO bus hold HIGH overdrive current per data input; VCC = 3.6 V -500 - - μA CI input capacitance - 5.0 - pF IBHH [1] All typical values are measured at Tamb = 25 °C. 74ALVCH16821 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 6 / 15 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 10 Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol tpd Parameter propagation delay Conditions Min Typ VCC = 2.3 V to 2.7 V 1.0 VCC = 2.7 V Max Unit 2.6 5.8 ns 1.0 2.8 5.3 ns 1.0 2.5 4.5 ns VCC = 2.3 V to 2.7 V 1.0 2.8 6.6 ns VCC = 2.7 V 1.0 3.2 6.2 ns 1.0 2.3 5.1 ns VCC = 2.3 V to 2.7 V 1.0 2.2 5.7 ns VCC = 2.7 V 1.0 3.1 5.0 ns VCC = 3.0 V to 3.6 V 1.0 2.8 4.6 ns VCC = 2.3 V to 2.7 V 1.4 0.3 - ns VCC = 2.7 V 1.2 0.3 - ns VCC = 3.0 V to 3.6 V 1.0 0.2 - ns VCC = 2.3 V to 2.7 V 0.4 0.0 - ns VCC = 2.7 V 0.6 -0.3 - ns VCC = 3.0 V to 3.6 V 0.8 0.4 - ns VCC = 2.3 V to 2.7 V 3.0 1.8 - ns VCC = 2.7 V 3.3 1.7 - ns VCC = 3.0 V to 3.6 V 3.3 0.2 - ns VCC = 2.3 V to 2.7 V 150 250 - MHz VCC = 2.7 V 150 300 - MHz 150 350 - MHz outputs enabled - 33 - pF outputs disabled - 17 - pF nCP to nQn; see Figure 5 [2] VCC = 3.0 V to 3.6 V ten enable time nOE to nQn; see Figure 7 [2] VCC = 3.0 V to 3.6 V tdis tsu th tW fmax disable time set-up time hold time pulse width maximum frequency nOE to nQn; see Figure 7 [2] nDn to nCP; see Figure 6 nDn to nCP; see Figure 6 nCP HIGH or LOW; see Figure 5 nCP; see Figure 5 VCC = 3.0 V to 3.6 V CPD power dissipation capacitance [1] per latch; VI = GND to VCC [3] [1] Typical values are measured at Tamb = 25 °C Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V. Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V. [2] tpd is the same as tPLH and tPHL; ten is the same as tPZL and tPZH; tdis is the same as tPLZ and tPHZ. 2 2 [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC × fi × N + ∑ (CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; 2 VCC = supply voltage in Volts; N = total load switching outputs; ∑(CL × VCC × fo) = sum of outputs. 74ALVCH16821 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 7 / 15 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 10.1 Waveforms and test circuit 1/fmax VI nCP input VM VM GND tW t PHL t PLH VOH VM nQn output VOL 001aaa256 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 5. Propagation delay clock input (nCP) to output (nQn), clock pulse (nCP) width and maximum clock frequency VI VM nCP input GND t su t su th th VI VM nDn input GND VOH VM nQn output VOL 001aaa257 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 6. Set-up times and hold times data input (nDn) to clock input (nCP) 74ALVCH16821 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 8 / 15 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state VI nOE input VM VM GND tPLZ nQn output LOW-to-OFF OFF-to-LOW tPZL VCC VM VX VOL tPZH tPHZ nQn output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND outputs enabled outputs disabled outputs enabled 001aal795 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 7. OFF-state to HIGH and LOW propagation delays and LOW and HIGH to OFF-state propagation delays Table 8. Measurement points VCC Input Output VI VM VM VX VY < 2.7 V VCC 0.5 x VCC 0.5 x VCC VOL + 0.15 V VOH - 0.15 V ≥ 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74ALVCH16821 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 9 / 15 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state VI negative pulse tW 90 % VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator; VEXT = External voltage for measuring switching times. Figure 8. Test circuit for measuring switching times Table 9. Test data Input Load VEXT VCC VI tr, tf RL CL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL < 2.7 V VCC ≤ 2.0 ns 500 Ω 30 pF GND 2 × VCC open ≥ 2.7 V 2.7 V ≤ 2.5 ns 500 Ω 50 pF GND 2 × VCC open 74ALVCH16821 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 10 / 15 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 11 Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3 ) A1 pin 1 index A θ Lp L 1 28 w M bp e detail X 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Figure 9. Package outline SOT364-1 (TSSOP56) 74ALVCH16821 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 11 / 15 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 12 Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test TTL Transistor-Transistor Logic 13 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVCH16821 v.3 20180202 Product data sheet - 74ALVCH16821 v.2 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Type number 74ALVCH16821DL (SOT371-1 / SSOP56) removed 74ALVCH16821 v.2 19980529 Product specification - 74ALVCH16821 v.1 74ALVCH16821 v.1 19980529 Product specification - - 74ALVCH16821 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 12 / 15 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 14 Legal information 14.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia's aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical 74ALVCH16821 Product data sheet systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 13 / 15 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer 74ALVCH16821 Product data sheet design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 3 — 2 February 2018 © Nexperia B.V. 2018. All rights reserved. 14 / 15 74ALVCH16821 Nexperia 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 10.1 11 12 13 14 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 1 Functional diagram ............................................. 2 Pinning information ............................................ 3 Pinning ............................................................... 3 Pin description ................................................... 4 Functional description ........................................4 Limiting values .................................................... 5 Recommended operating conditions ................ 5 Static characteristics .......................................... 6 Dynamic characteristics .....................................7 Waveforms and test circuit ................................ 8 Package outline .................................................11 Abbreviations .................................................... 12 Revision history ................................................ 12 Legal information .............................................. 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2018. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 2 February 2018 Document identifier: 74ALVCH16821