74ALVCH16823
18-bit bus-interface D-type flip-flop with reset and enable;
3-state
Rev. 3 — 1 February 2018
1
Product data sheet
General description
The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs
for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold
data inputs which eliminate the need for external pull-up resistors to hold unused inputs.
The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock
(nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clockenable (nCE) input are provided for each total 9-bit section.
With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of
their individual nDn-inputs that meet the set-up and hold time requirements on the
LOW-to-HIGH nCP transition. Taking nCE HIGH disables the clock buffer, thus latching
the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go
LOW independently of the clock.
When nOE is LOW, the contents of the flip-flops are available at the outputs. When the
nOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the nOE
input does not affect the state of flip-flops.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2
Features and benefits
•
•
•
•
•
•
•
•
•
•
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
Output drive capability 50 Ω transmission lines at 85°C
All data inputs have bushold
Complies with JEDEC standard no. 8-1A
Complies with JEDEC standards:
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
– CDM JESD22-C101E exceeds 1000 V
74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
3
Ordering information
Table 1. Ordering information
Type number
Package
74ALVCH16823DGG
4
Temperature range Name
Description
−40 °C to +85 °C
plastic thin shrink small outline package; 56 leads; SOT364-1
body width 6.1 mm
TSSOP56
Version
Functional diagram
28
1
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
56
29
2MR
1OE
1MR
2OE
1D0
1Q0
1D1
1Q1
1D2
1Q2
1D3
1Q3
1D4
1Q4
1D5
1Q5
1D6
1Q6
1D7
1Q7
1D8
1Q8
2D0
2Q0
2D1
2Q1
2D2
2Q2
2D3
2Q3
2D4
2Q4
2D5
2Q5
2D6
2Q6
2D7
2Q7
2D8
2Q8
1CP
2CE
2CP
1CE
1OE
1MR
1CE
1CP
2OE
2MR
2CE
2CP
2
27
3
5
6
1D0
8
1D1
9
1D2
10
1D3
12
1D4
13
1D5
14
1D6
15
1D7
16
1D8
17
2D0
19
2D1
20
2D2
21
2D3
23
2D4
24
26
2D5
30
2D7
2D6
2D8
55
2
1
55
56
27
28
30
29
54
52
EN1
R2
G3
3C4
EN5
R6
G7
7C8
4D
1,2
3
5
51
6
49
8
48
9
47
10
45
12
44
13
43
14
42
41
8D
5,6
15
16
40
17
38
19
37
20
36
21
34
23
33
24
31
26
aaa-028141
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
001aad242
Figure 1. Logic symbol
Figure 2. IEC logic symbol
VCC
data input
to internal circuit
001aad245
Figure 3. Bushold circuit (one data input)
74ALVCH16823
Product data sheet
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2 / 18
74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
nCE
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nCP
CP
nD
R
CP
nD
Q
R
CP
nD
Q
R
CP
nD
Q
R
CP
nD
Q
R
CP
nD
Q
R
CP
nD
Q
R
CP
nD
Q
R
CP
nD
Q
R
Q
nMR
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
001aad243
Figure 4. Logic diagram
74ALVCH16823
Product data sheet
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3 / 18
74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
5
Pinning information
5.1 Pinning
74ALVCH16823
1MR
1
56 1CP
1OE
2
55 1CE
1Q0
3
54 1D0
GND
4
53 GND
1Q1
5
52 1D1
1Q2
6
51 1D2
VCC
7
50 VCC
1Q3
8
49 1D3
1Q4
9
48 1D4
1Q5 10
47 1D5
GND 11
46 GND
1Q6 12
45 1D6
1Q7 13
44 1D7
1Q8 14
43 1D8
2Q0 15
42 2D0
2Q1 16
41 2D1
2Q2 17
40 2D2
GND 18
39 GND
2Q3 19
38 2D3
2Q4 20
37 2D4
2Q5 21
36 2D5
VCC 22
35 VCC
2Q6 23
34 2D6
2Q7 24
33 2D7
GND 25
32 GND
2Q8 26
31 2D8
2OE 27
30 2CE
2MR 28
29 2CP
aaa-028142
Figure 5. Pin configuration SOT364-1 (TSSOP56)
74ALVCH16823
Product data sheet
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4 / 18
74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
5.2 Pin description
Table 2. Pin description
Symbol
Pin
Description
1D0, 1D1, 1D2, 1D3, 1D4,
1D5, 1D6, 1D7, 1D8
54, 52, 51, 49, 48,
47, 45, 44, 43
data inputs
1Q0, 1Q1, 1Q2, 1Q3, 1Q4,
1Q5, 1Q6, 1Q7, 1Q8
3, 5, 6, 8, 9,
10, 12, 13, 14
data outputs
2D0, 2D1, 2D2, 2D3, 2D4,
2D5, 2D6, 2D7, 2D8
42, 41, 40, 38, 37,
36, 34, 33, 31
data inputs
2Q0, 2Q1, 2Q2, 2Q3, 2Q4,
2Q5, 2Q6, 2Q7, 2Q8
15, 16, 17, 19, 20,
21, 23, 24, 26
data outputs
1MR, 2MR
1, 28
master reset inputs (active-LOW)
1OE, 2OE
2, 27
output enable inputs (active LOW)
1CP, 2CP
56, 29
clock pulse inputs (active rising edge)
1CE, 2CE
55, 30
clock enable inputs (active-LOW)
GND
4, 11, 18, 25,
32, 39, 46, 53
ground (0 V)
VCC
7, 22, 35, 50
supply voltage
6
Functional description
Table 3. Function table
Operating mode
[1]
Input
Output
nOE
nMR
nCE
nCP
nDn
nQn
clear
L
L
X
X
X
L
load and read data
L
H
L
↑
h
H
L
H
L
↑
l
L
L
H
L
L
X
NC
L
H
H
X
X
NC
H
X
X
X
X
Z
hold
disable outputs
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
74ALVCH16823
Product data sheet
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74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
VI
Conditions
input voltage
Min
Max
Unit
−0.5
+4.6
V
For control pins
[1]
−0.5
+5.5
V
For data inputs
[1]
−0.5
VCC + 0.5
V
[1]
−0.5
VCC + 0.5
V
−50
-
mA
VO
output voltage
IIK
input clamping current
VI < 0 V
IOK
output clamping current
VO > VCC or VO < 0 V
-
±50
mA
VO = 0 V to VCC
-
±50
mA
IO(sink/source) output sink or source current
ICC
supply current
-
100
mA
IGND
ground current
−100
-
mA
Tstg
storage temperature
−65
+150
°C
-
600
mW
Ptot
total power dissipation
Tamb = −40 °C to +125 °C
[2]
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Above 55 °C the value of Ptot derates linearly with 8 mW/K.
8
Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
2.5 V range for maximum speed
performance at 30 pF output load
2.3
2.7
V
3.3 V range for maximum speed
performance at 50 pF output load
3.0
3.6
V
for low-voltage applications
1.2
3.6
V
for data inputs
0
VCC
V
for control inputs
0
5.5
V
0
VCC
V
-40
+85
°C
VI
input voltage
VO
output voltage
Tamb
ambient temperature
in free air
Δt/ΔV
input transition rise and fall rate
VCC = 2.3 V to 3.0 V
-
20
ns/V
VCC = 3.0 V to 3.6 V
-
10
ns/V
74ALVCH16823
Product data sheet
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74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
9
Static characteristics
Table 6. Static characteristics
At recommended operating conditions; Tamb = −40 °C to +85 °C; voltages are referenced to GND (ground = 0 V).
[1]
Symbol Parameter
Conditions
Min
Typ
VIH
VCC = 1.2 V
VCC
-
-
V
VCC = 1.8 V
0.7VCC
0.9
-
V
VCC = 2.3 V to 2.7 V
1.7
1.2
-
V
VCC = 2.7 V to 3.6 V
2.0
1.5
-
V
VCC = 1.2 V
-
-
GND
V
VCC = 1.8 V
-
0.9
0.2VCC
V
VCC = 2.3 V to 2.7 V
-
1.2
0.7
V
VCC = 2.7 V to 3.6 V
-
1.5
0.8
V
IO = -100 μA; VCC = 1.8 V to 3.6 V
VCC - 0.2
VCC
-
V
IO = -6 mA; VCC = 1.8 V
VCC - 0.4
VCC - 0.10
-
V
IO = -6 mA; VCC = 2.3 V
VCC - 0.3
VCC - 0.08
-
V
IO = -12 mA; VCC = 2.3 V
VCC - 0.5
VCC - 0.17
-
V
IO = -18 mA; VCC = 2.3 V
VCC - 0.6
VCC - 0.26
-
V
IO = -12 mA; VCC = 2.7 V
VCC - 0.5
VCC - 0.14
-
V
IO = -24 mA; VCC = 3.0 V
VCC - 1.0
VCC - 0.28
-
V
IO = 100 μA; VCC = 1.8 V to 3.6 V
-
GND
0.20
V
IO = 6 mA; VCC = 1.8 V
-
0.09
0.30
V
IO = 6 mA; VCC = 2.3 V
-
0.07
0.20
V
IO = 12 mA; VCC = 2.3 V
-
0.15
0.40
V
IO = 18 mA; VCC = 2.3 V
-
0.23
0.60
V
IO = 12 mA; VCC = 2.7 V
-
0.14
0.40
V
IO = 24 mA; VCC = 3.0 V
-
0.27
0.55
V
per control pin; VCC = 1.8 V to 3.6 V;
VI = 5.5 V or GND
-
0.1
5
μA
per data pin; VCC = 1.8 V to 3.6 V;
VI = VCC or GND
-
0.1
5
μA
VCC = 1.8 V to 2.7 V; VI = VIH or VIL;
VO = VCC or GND
-
0.1
5
μA
VCC = 2.7 V to 3.6 V; VI = VIH or VIL;
VO = VCC or GND
-
0.1
10
μA
VIL
VOH
VOL
II
IOZ
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
input
leakage current
OFF-state
output current
Max
Unit
VI = VIH or VIL
VI = VIH or VIL
ICC
supply current
VCC = 2.3 V to 3.6 V; VI = VCC or GND; IO = 0 A
-
0.2
40
µA
ΔICC
additional
supply current
VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A
-
150
750
μA
74ALVCH16823
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74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
[1]
Symbol Parameter
Conditions
IBHL
bus hold LOW
current
VCC = 2.3 V; VI = 0.7 V
45
-
-
μA
VCC = 3.0 V; VI = 0.8 V
75
150
-
μA
bus hold HIGH
current
VCC = 2.3 V; VI = 1.7 V
-45
-
-
μA
VCC = 3.0 V; VI = 2.0 V
-75
-175
-
μA
bus hold LOW
overdrive current
VCC = 2.7 V
300
-
-
μA
VCC = 3.0 V
450
-
-
μA
bus hold HIGH
overdrive current
VCC = 2.7 V
-300
-
-
μA
VCC = 3.6 V
-450
-
-
μA
-
5.0
-
pF
IBHH
IBHLO
IBHHO
CI
Min
input capacitance
Typ
Max
Unit
[1] All typical values are measured at Tamb = 25 °C.
10 Dynamic characteristics
Table 7. Dynamic characteristics
At recommended operating conditions; Tamb = −40 °C to +85 °C; voltages are referenced to GND (ground = 0 V);
for test circuit see Figure 10
Symbol
tpd
Parameter
propagation delay
Conditions
Min
nCP to nQn; see Figure 6
Typ
[1]
Max
Unit
[2]
VCC = 1.2 V
-
10.6
-
ns
VCC = 1.8 V
1.5
4.5
7.5
ns
VCC = 2.3 V to 2.7 V
1.0
2.8
4.9
ns
VCC = 2.7 V
1.0
2.7
4.3
ns
VCC = 3.0 V to 3.6 V
1.0
2.5
3.7
ns
VCC = 1.2 V
-
9.9
-
ns
VCC = 1.8 V
1.5
4.6
7.4
ns
VCC = 2.3 V to 2.7 V
1.0
2.9
5.0
ns
VCC = 2.7 V
1.0
3.1
4.6
ns
1.0
2.6
4.0
ns
VCC = 1.2 V
-
10.4
-
ns
VCC = 1.8 V
1.5
4.4
7.7
ns
VCC = 2.3 V to 2.7 V
1.0
2.8
5.3
ns
VCC = 2.7 V
1.0
3.1
5.2
ns
VCC = 3.0 V to 3.6 V
1.0
2.5
4.3
ns
nMR to nQn; see Figure 8
VCC = 3.0 V to 3.6 V
ten
enable time
74ALVCH16823
Product data sheet
nOE to nQn; see Figure 9
[3]
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74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
Symbol
tdis
tsu
Parameter
disable time
set-up time
Conditions
Min
nOE to nQn; see Figure 9
Typ
[1]
Max
Unit
[4]
VCC = 1.2 V
-
6.7
-
ns
VCC = 1.8 V
1.5
3.3
5.5
ns
VCC = 2.3 V to 2.7 V
1.0
2.2
4.1
ns
VCC = 2.7 V
1.0
3.1
4.3
ns
VCC = 3.0 V to 3.6 V
1.0
2.8
3.9
ns
VCC = 1.8 V
1.5
0.2
-
ns
VCC = 2.3 V to 2.7 V
1.2
0.2
-
ns
VCC = 2.7 V
1.5
0.4
-
ns
VCC = 3.0 V to 3.6 V
1.2
0.2
-
ns
VCC = 1.8 V
2.0
-0.2
-
ns
VCC = 2.3 V to 2.7 V
1.8
-0.2
-
ns
VCC = 2.7 V
1.9
-0.1
-
ns
VCC = 3.0 V to 3.6 V
1.5
-0.1
-
ns
VCC = 1.8 V
0.6
-0.2
-
ns
VCC = 2.3 V to 2.7 V
0.8
-0.1
-
ns
VCC = 2.7 V
0.6
-0.2
-
ns
VCC = 3.0 V to 3.6 V
0.8
0.0
-
ns
VCC = 1.8 V
0.3
0.2
-
ns
VCC = 2.3 V to 2.7 V
0.3
0.2
-
ns
VCC = 2.7 V
0.4
0.1
-
ns
VCC = 3.0 V to 3.6 V
0.5
0.1
-
ns
VCC = 1.8 V
4.0
2.0
-
ns
VCC = 2.3 V to 2.7 V
3.0
1.6
-
ns
VCC = 2.7 V
3.0
1.6
-
ns
VCC = 3.0 V to 3.6 V
2.5
1.4
-
ns
VCC = 1.8 V
4.0
0.8
-
ns
VCC = 2.3 V to 2.7 V
3.0
0.4
-
ns
VCC = 2.7 V
3.0
0.6
-
ns
VCC = 3.0 V to 3.6 V
2.5
0.3
-
ns
nDn to nCP; see Figure 7
nCE to nCP; see Figure 7
th
hold time
nDn to nCP; see Figure 7
nCE to nCP; see Figure 7
tW
pulse width
nCP HIGH or LOW; see Figure 6
nMR HIGH or LOW; see Figure 8
74ALVCH16823
Product data sheet
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74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
Symbol
Parameter
Conditions
trec
recovery time
nMR to nCP; see Figure 8
fmax
maximum frequency
Typ
VCC = 1.8 V
0.8
0.2
-
ns
VCC = 2.3 V to 2.7 V
1.0
0.3
-
ns
VCC = 2.7 V
0.8
0.1
-
ns
VCC = 3.0 V to 3.6 V
1.0
0.2
-
ns
power dissipation
capacitance
Max
Unit
VCC = 1.8 V
125
250
-
MHz
VCC = 2.3 V to 2.7 V
150
300
-
MHz
VCC = 2.7 V
150
300
-
MHz
200
350
-
MHz
outputs enabled
-
16
-
pF
outputs disabled
-
10
-
pF
nCP; see Figure 6
VCC = 3.0 V to 3.6 V
CPD
[1]
Min
per latch; VI = GND to VCC
[5]
[1] Typical values are measured at Tamb = 25 °C
Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V.
Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V.
[2] tpd is the same as tPLH and tPHL.
[3] ten is the same as tPZL and tPZH.
[4] tdis is the same as tPLZ and tPHZ.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
2
2
PD = CPD × VCC × fi × N + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
2
∑(CL × VCC × fo) = sum of outputs.
74ALVCH16823
Product data sheet
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Rev. 3 — 1 February 2018
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10 / 18
74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
10.1 Waveforms and test circuit
1/fmax
VI
nCP input
VM
VM
GND
tW
t PHL
t PLH
VOH
VM
nQn output
VOL
001aaa256
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 6. Propagation delay clock input (nCP) to output (nQn), clock pulse (nCP) width and maximum clock (nCP)
frequency
VI
input nDn,
nCE
VM
GND
VM
t su(H)
VM
t h(H)
VM
t su(L)
t h(L)
VI
input nCP
VM
VM
GND
001aad401
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 7. Data set-up and hold times for the nDn or nCE input to the nCP input
VI
VM
input nMR
VM
GND
t WL
t rec
VI
input nCP
VM
GND
t PHL
VOH
VM
output nQn
VOL
001aad400
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 8. Master reset (nMR) pulse width, master reset (nMR) to output (nQn) propagation delay and master reset
(nMR) to clock (nCP) recovery time
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74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
VI
nOE input
VM
VM
GND
tPLZ
nQn output
LOW-to-OFF
OFF-to-LOW
tPZL
VCC
VM
VX
VOL
tPZH
tPHZ
nQn output
HIGH-to-OFF
OFF-to-HIGH
VOH
VY
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aal795
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 9. OFF-state to HIGH and LOW propagation delays and LOW and HIGH to OFF-state propagation delays
Table 8. Measurement points
VCC
Input
Output
VI
VM
VM
VX
VY
< 2.7 V
VCC
0.5 x VCC
0.5 x VCC
VOL + 0.15 V
VOH - 0.15 V
≥ 2.7 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH - 0.3 V
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74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
VI
negative
pulse
tW
90 %
VM
0V
VI
tf
tr
tr
tf
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VEXT
VCC
PULSE
GENERATOR
VI
RL
VO
DUT
RT
CL
RL
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator;
VEXT = External voltage for measuring switching times.
Figure 10. Test circuit for measuring switching times
Table 9. Test data
Input
Load
VEXT
VCC
VI
tr, tf
RL
CL
tPHZ, tPZH
tPLZ, tPZL
tPLH, tPHL
< 2.7 V
VCC
≤ 2.0 ns
500 Ω
30 pF
GND
2 × VCC
open
≥ 2.7 V
2.7 V
≤ 2.5 ns
500 Ω
50 pF
GND
2 × VCC
open
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74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
11 Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
HE
y
v M A
Z
56
29
Q
A2
(A 3 )
A1
pin 1 index
A
θ
Lp
L
1
28
w M
bp
e
detail X
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.5
0.1
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT364-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Figure 11. Package outline SOT364-1 (TSSOP56)
74ALVCH16823
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14 / 18
74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
12 Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
TTL
Transistor-Transistor Logic
13 Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74ALVCH16823 v.3
20180201
Product data sheet
-
74ALVCH16823 v.2
Modifications:
• The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Type number 74ALVCH16823DL (SOT371-1 / SSOP56) removed
74ALVCH16823 v.2
19980729
Product specification
-
74ALVCH16823 v.1
74ALVCH16823 v.1
19980729
Product specification
-
-
74ALVCH16823
Product data sheet
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15 / 18
74ALVCH16823
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18-bit bus-interface D-type flip-flop with reset and enable; 3-state
14 Legal information
14.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local Nexperia
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory. Notwithstanding any damages that
customer might incur for any reason whatsoever, Nexperia's aggregate and
cumulative liability towards customer for the products described herein shall
be limited in accordance with the Terms and conditions of commercial sale of
Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
74ALVCH16823
Product data sheet
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification. Customers are responsible for the
design and operation of their applications and products using Nexperia
products, and Nexperia accepts no liability for any assistance with
applications or customer product design. It is customer’s sole responsibility
to determine whether the Nexperia product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products. Nexperia does not accept
any liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using Nexperia products in order to avoid a default of the
applications and the products or of the application or use by customer’s third
party customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 1 February 2018
© Nexperia B.V. 2018. All rights reserved.
16 / 18
74ALVCH16823
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications. In the event that customer
uses the product for design-in and use in automotive applications to
automotive specifications and standards, customer (a) shall use the product
without Nexperia's warranty of the product for such automotive applications,
use and specifications, and (b) whenever customer uses the product for
automotive applications beyond Nexperia's specifications such use shall be
solely at customer’s own risk, and (c) customer fully indemnifies Nexperia
for any liability, damages or failed product claims resulting from customer
74ALVCH16823
Product data sheet
design and use of the product for automotive applications beyond Nexperia's
standard warranty and Nexperia's product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
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Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
10.1
11
12
13
14
General description ............................................ 1
Features and benefits .........................................1
Ordering information .......................................... 2
Functional diagram ............................................. 2
Pinning information ............................................ 4
Pinning ............................................................... 4
Pin description ................................................... 5
Functional description ........................................5
Limiting values .................................................... 6
Recommended operating conditions ................ 6
Static characteristics .......................................... 7
Dynamic characteristics .....................................8
Waveforms and test circuit .............................. 11
Package outline .................................................14
Abbreviations .................................................... 15
Revision history ................................................ 15
Legal information .............................................. 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© Nexperia B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 1 February 2018
Document identifier: 74ALVCH16823
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