Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com (email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
- © Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Rev. 6 — 10 July 2012
Product data sheet
1. General description
The 74ALVCH16373 is 16-bit D-type transparent latch featuring separate D-type inputs for
each latch and 3-state outputs for bus oriented applications.
Incorporates bus hold data inputs which eliminate the need for external pull-up or
pull-down resistors to hold unused inputs.
One latch enable (LE) input and one output enable (OE) are provided per 8-bit section.
The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-state
true outputs. When LE is HIGH, data at the nDn inputs enter the latches. In this condition
the latches are transparent, therefore a latch output will change each time its
corresponding D-input changes.
When LE is LOW, the latches store the information that was present at the nDn inputs at a
set-up time preceding the LOW-to-HIGH transition of LE. When OE is LOW, the contents
of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
latches.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50 transmission lines at 85 C
Current drive 24 mA at VCC = 3.0 V
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
74ALVCH16373DL
Temperature range
40 C to +85 C
74ALVCH16373DGG 40 C to +85 C
Package
Name
Description
Version
SSOP48
plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
TSSOP48
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
4. Functional diagram
Fig 1.
1
24
1OE
2OE
47
1D0
1Q0
2
46
1D1
1Q1
3
44
1D2
1Q2
5
43
1D3
1Q3
6
41
1D4
1Q4
8
40
1D5
1Q5
9
38
1D6
1Q6
11
37
1D7
1Q7
12
36
2D0
2Q0
13
35
2D1
2Q1
14
33
2D2
2Q2
16
32
2D3
2Q3
17
30
2D4
2Q4
19
29
2D5
2Q5
20
27
2D6
2Q6
22
26
2D7
2Q7
23
1LE
2LE
48
25
001aam007
Logic symbol
74ALVCH16373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
2 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
1OE
1LE
2OE
2LE
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1
48
24
25
47
1EN
C1
2EN
C4
3D
2
1
46
3
44
5
43
6
41
8
40
9
38
11
37
12
36
4D
13
2
35
14
33
16
32
17
30
19
29
20
27
22
26
23
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
001aam009
Fig 2.
IEC logic symbol
VCC
data input
to internal circuit
mna705
Fig 3.
Bus hold circuit
1D0
D
Q
1Q0
2D0
D
Q
LATCH
1
LATCH
9
LE
LE
LE
1LE
2LE
1OE
2OE
to 7 other channels
2Q0
LE
to 7 other channels
001aam010
Fig 4.
Logic diagram
74ALVCH16373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
3 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
74ALVCH16373
1OE
1
48 1LE
1Q0
2
47 1D0
1Q1
3
46 1D1
GND
4
45 GND
1Q2
5
44 1D2
1Q3
6
43 1D3
VCC
7
42 VCC
1Q4
8
41 1D4
1Q5
9
40 1D5
GND 10
39 GND
1Q6 11
38 1D6
1Q7 12
37 1D7
2Q0 13
36 2D0
2Q1 14
35 2D1
GND 15
34 GND
2Q2 16
33 2D2
2Q3 17
32 2D3
VCC 18
31 VCC
2Q4 19
30 2D4
2Q5 20
29 2D5
GND 21
28 GND
2Q6 22
27 2D6
2Q7 23
26 2D7
2OE 24
25 2LE
001aam008
Fig 5.
Pin configuration
74ALVCH16373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
4 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1OE, 2OE
1, 24
output enable input (active LOW)
1Q0 to 1Q7
2, 3, 5, 6, 8, 9, 11, 12
data outputs
2Q0 to 2Q7
13, 14, 16, 17, 19, 20, 22, 23
data outputs
GND
4, 10, 15, 21, 28, 34, 39, 45
ground (0 V)
VCC
7, 18, 31, 42
positive supply voltage
1D0 to 1D7
47, 46, 44, 43, 41, 40, 38, 37
data inputs
2D0 to 2D7
36, 35, 33, 32, 30, 29, 27, 26
data inputs
1LE, 2LE
48, 25
latch enable input (active HIGH)
6. Functional description
6.1 Function table
Table 3.
Function table[1]
Inputs
nOE
nLE
Internal latches Outputs nQn
Operating mode
enable and read register
(transparent mode)
nDn
L
H
L
L
L
L
H
H
H
H
L
L
l
L
L
L
L
h
H
H
latch and read register
(hold mode)
H
L
l
L
Z
latch register and disable outputs
H
L
h
H
Z
[1]
H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH LE transition;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH LE transition;
Z = high-impedance OFF-state.
74ALVCH16373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
5 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI < 0 V
50
-
mA
VI
input voltage
control inputs
[1]
0.5
+4.6
V
data inputs
[1]
0.5
VCC + 0.5
V
-
50
mA
output clamping current
IOK
Conditions
VO > VCC or VO < 0 V
Min
Max
Unit
0.5
+4.6
V
0.5
VCC + 0.5
V
-
50
mA
supply current
-
100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
VO
output voltage
IO
output current
ICC
[1]
VO = 0 V to VCC
Tamb = 40 C to +125 C
SSOP48 package
[2]
-
850
mW
TSSOP48 package
[3]
-
600
mW
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
Above 55 C the value of Ptot derates linearly with 11.3 mW/K.
[3]
Above 55 C the value of Ptot derates linearly with 8 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
VCC
supply voltage
maximum speed performance
VI
input voltage
Min
Typ
Max
Unit
CL = 30 pF
2.3
-
2.7
V
CL = 50 pF
3.0
-
3.6
V
low voltage applications
1.2
-
3.6
V
data inputs
0
-
VCC
V
control inputs
0
-
5.5
V
0
-
VCC
V
40
-
+85
C
VO
output voltage
Tamb
ambient temperature
t/V
input transition rise and fall rate VCC = 2.3 V to 3.0 V
0
-
20
ns/V
VCC = 3.0 V to 3.6 V
0
-
10
ns/V
74ALVCH16373
Product data sheet
in free air
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
6 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Tamb = 40 C to +85 C
VIH
VIL
VOH
VOL
II
IOZ
ILIZ
ICC
HIGH-level input
voltage
LOW-level input
voltage
HIGH-level output
voltage
LOW-level output
voltage
input leakage current
OFF-state output
current
VCC = 1.2 V
VCC
-
-
V
VCC = 1.8 V
0.7VCC
0.9
-
V
VCC = 2.3 V to 2.7 V
1.7
1.2
-
V
VCC = 2.7 V to 3.6 V
2.0
1.5
-
V
0
V
VCC = 1.2 V
-
-
VCC = 1.8 V
-
0.9
VCC = 2.3 V to 2.7 V
-
1.2
0.7
V
VCC = 2.7 V to 3.6 V
-
1.5
0.8
V
IO = 100 A; VCC = 1.8 V to 3.6 V
VCC 0.2
VCC
-
V
IO = 6 mA; VCC = 1.8 V
VCC 0.4
VCC 0.1
-
V
IO = 6 mA; VCC = 2.3 V
VCC 0.3
VCC 0.08
-
V
IO = 12 mA; VCC = 2.3 V
VCC 0.5
VCC 0.17
-
V
IO = 12 mA; VCC = 2.7 V
VCC 0.5
VCC 0.14
-
V
IO = 18 mA; VCC = 2.3 V
VCC 0.6
VCC 0.26
-
V
IO = 24 mA; VCC = 3.0 V
VCC 1.0
VCC 0.28
-
V
IO = 100 A; VCC = 1.8 V to 3.6 V
-
0
0.20
V
IO = 6 mA; VCC = 1.8 V
-
0.09
0.30
V
IO = 6 mA; VCC = 2.3 V
-
0.07
0.20
V
VI = VIH or VIL
VI = VIH or VIL
IO = 12 mA; VCC = 2.3 V
-
0.15
0.40
V
IO = 12 mA; VCC = 2.7 V
-
0.14
0.40
V
IO = 18 mA; VCC = 2.3 V
-
0.23
0.60
V
IO = 24 mA; VCC = 3.0 V
-
0.27
0.55
V
control input; VI = 5.5 V or GND
-
0.1
5
A
data input; VI = VCC or GND
-
0.1
5
A
VCC = 1.8 V to 2.7 V
-
0.1
5
A
VCC = 2.7 V to 3.6 V
-
0.1
10
A
VCC = 1.8 V to 2.7 V
-
0.1
10
A
VCC = 3.6 V
-
0.1
15
A
VCC = 1.8 V to 2.7 V
-
0.2
40
A
VCC = 2.7 V to 3.6 V
-
0.2
40
A
VCC = 1.8 V to 3.6 V
VI = VIH or VIL; VO = VCC or GND
OFF-state input
leakage current
VI = VCC or GND
supply current
VI = VCC or GND; IO = 0 A;
74ALVCH16373
Product data sheet
0.2VCC V
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
7 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
ICC
additional supply
current
VI = VCC 0.6 V; IO = 0 A;
VCC = 2.7 V to 3.6 V
bus hold LOW current
IBHL
IBHH
IBHLO
IBHHO
bus hold HIGH current
bus hold LOW
overdrive current
bus hold HIGH
overdrive current
Min
Max
Unit
per control input
-
5
500
A
per data I/O input
-
150
750
A
VCC = 2.3 V; VI = 0.7 V
[2]
45
-
-
A
VCC = 3.0 V; VI = 0.8 V
[2]
75
150
-
A
VCC = 2.3 V; VI = 1.7 V
[2]
45
-
-
A
VCC = 3.0 V; VI = 2.0 V
[2]
75
175
-
A
VCC = 2.7 V
[2]
300
-
-
A
VCC = 3.6 V
[2]
450
-
-
A
VCC = 2.7 V
[2]
300
-
-
A
VCC = 3.6 V
[2]
450
-
-
A
-
5.0
-
pF
Max
Unit
input capacitance
CI
Typ[1]
[1]
All typical values are measured at Tamb = 25 C.
[2]
Valid for data inputs of bus hold parts only.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 10.
Symbol
Parameter
Conditions
Min
Typ[1]
Tamb = 40 C to +85 C
tpd
propagation delay
nDn to nQn; see Figure 6
[2]
VCC = 1.2 V
-
8.8
-
ns
VCC = 1.8 V
1.5
3.2
5.7
ns
1.0
2.1
3.9
ns
1.0
2.3
3.7
ns
1.0
2.1
3.3
ns
-
7.4
-
ns
1.5
3.4
5.9
ns
VCC = 2.3 V to 2.7 V
[3]
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
[4]
nLE to nQn; see Figure 7
[2]
VCC = 1.2 V
VCC = 1.8 V
VCC = 2.3 V to 2.7 V
[3]
VCC = 2.7 V
ten
enable time
VCC = 3.0 V to 3.6 V
[4]
nOE to nQn; see Figure 8
[2]
3.9
ns
2.2
3.5
ns
1.0
2.2
3.2
ns
VCC = 1.2 V
-
8.9
-
ns
1.5
4.0
7.3
ns
1.0
2.6
5.2
ns
1.0
2.9
4.9
ns
1.0
2.3
4.2
ns
[3]
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
Product data sheet
2.2
VCC = 1.8 V
VCC = 2.3 V to 2.7 V
74ALVCH16373
1.0
1.0
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
[4]
© NXP B.V. 2012. All rights reserved.
8 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Table 7.
Dynamic characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 10.
Symbol
tdis
Parameter
disable time
Conditions
nOE to nQn; see Figure 8
VCC = 1.2 V
VCC = 1.8 V
VCC = 2.3 V to 2.7 V
[3]
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
pulse width
tW
[4]
VCC = 2.3 V to 2.7 V
[3]
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
set-up time
[4]
VCC = 2.3 V to 2.7 V
[3]
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
hold time
[4]
VCC = 2.3 V to 2.7 V
[3]
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
power dissipation
capacitance
[1]
[2]
-
8.9
-
1.5
3.2
5.6
ns
1.0
2.2
4.1
ns
1.0
3.1
4.7
ns
1.0
2.8
4.1
ns
3.5
1.0
-
ns
3.0
1.0
-
ns
3.0
1.0
-
ns
2.5
1.0
-
ns
1.0
0.1
-
ns
1.0
0.1
-
ns
1.0
0.1
-
ns
1.0
0.0
-
ns
1.2
0.1
-
ns
1.5
0.2
-
ns
1.5
0.4
-
ns
1.2
0.2
-
ns
Unit
ns
nDn to nLE; see Figure 9
VCC = 1.8 V
CPD
Max
nDn to nLE; see Figure 9
VCC = 1.8 V
th
Typ[1]
nLE HIGH; see Figure 7
VCC = 1.8 V
tsu
Min
[2]
per flip-flop; VI = GND to VCC
[4]
[5]
outputs enabled
-
16
-
pF
outputs disabled
-
10
-
pF
All typical values are measured at Tamb = 25 C.
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3]
Typical values are measured at VCC = 2.5 V.
[4]
Typical values are measured at VCC = 3.3 V.
[5]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
74ALVCH16373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
9 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
11. Waveforms
VI
nDn input
VM
VM
tPHL
tPLH
GND
VOH
nQn output
VM
VM
VOL
001aam011
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig 6.
Propagation delay, input (nDn) to data output (nQn)
VI
nLE input
VM
VM
VM
GND
tW
tPHL
tPLH
VOH
nQn output
VM
VM
VOL
001aam012
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig 7.
Propagation delay, latch enable input (nLE) to data output (nQn), and pulse width
VI
nOE input
VM
VM
GND
tPLZ
tPZL
VCC
nQn output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPZH
tPHZ
VOH
VY
nQn output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aal795
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig 8.
3-state enable and disable times
74ALVCH16373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
10 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
VI
nDn input
VM
GND
th
tsu
th
tsu
VI
nLE input
VM
GND
001aam013
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9.
Table 8.
Data setup and hold times for input (nDn) to input (nLE)
Measurement points
Supply voltage
Input
VCC
VI
Output
VM
VM
VX
VY
2.3 V to 2.7 V and < 2.3 V VCC
0.5 VCC
0.5 VCC
VOL + 0.15 V
VOH 0.15 V
2.7 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH 0.3 V
3.0 V to 3.6 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH 0.3 V
74ALVCH16373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
11 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
12. Test information
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
mna616
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Load circuit for measuring switching times
Table 9.
Test data
Supply voltage
Input
VCC
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
2.3 V to 2.7 V and
< 2.3 V
VCC
2.0 ns
30 pF
500
open
2 VCC
GND
2.7 V
2.7 V
2.5 ns
50 pF
500
open
2 VCC
GND
3.0 V to 3.6 V
2.7 V
2.5 ns
50 pF
500
open
2 VCC
GND
74ALVCH16373
Product data sheet
Load
VEXT
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
12 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
13. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
HE
v M A
Z
25
48
Q
A2
A1
A
(A 3)
θ
pin 1 index
Lp
L
24
1
detail X
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.8
0.4
0.2
2.35
2.20
0.25
0.3
0.2
0.22
0.13
16.00
15.75
7.6
7.4
0.635
10.4
10.1
1.4
1.0
0.6
1.2
1.0
0.25
0.18
0.1
0.85
0.40
8o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT370-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-118
Fig 11. Package outline SOT370-1 (SSOP48)
74ALVCH16373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
13 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
HE
y
v M A
Z
48
25
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
detail X
24
w M
bp
e
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.8
0.4
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT362-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 12. Package outline SOT362-1 (TSSOP48)
74ALVCH16373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
14 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
14. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
TTL
Transistor-Transistor Logic
15. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74ALVCH16373 v.6
20120710
Product data sheet
-
74ALVCH16373 v.5
-
74ALVCH16373 v.4
Modifications:
74ALVCH16373 v.5
Modifications:
•
Table 8 corrected (errata).
20111117
•
Product data sheet
Legal pages updated.
74ALVCH16373 v.4
20100531
Product data sheet
-
74ALVCH16373 v.3
74ALVCH16373 v.3
19990920
Product specification
-
74ALVCH16373 v.2
74ALVCH16373 v.2
19980629
Product specification
-
74ALVCH16373 v.1
74ALVCH16373 v.1
19970321
Product specification
-
-
74ALVCH16373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
15 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74ALVCH16373
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
16 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74ALVCH16373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 July 2012
© NXP B.V. 2012. All rights reserved.
17 of 18
74ALVCH16373
NXP Semiconductors
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
18. Contents
1
2
3
4
5
5.1
5.2
6
6.1
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Test information . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 July 2012
Document identifier: 74ALVCH16373
工商网监
湘ICP备2023018690号
