74ALVCH16373DL,118

74ALVCH16373 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state Rev. 8 — 22 November 2021 Product data sheet 1. General description The 74ALVCH16373 is a 16-bit D-type transparent latch with bus hold inputs and 3-state outputs. The device can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The device features two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • • • • Wide supply voltage range from 1.2 V to 3.6 V CMOS low power dissipation MULTIBYTE flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold Latch-up performance exceeds 100 mA per JESD78 Class II Level B Output drive capability 50 Ω transmission lines at 85 °C Complies with JEDEC standards: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V Current drive ±24 mA at VCC = 3.0 V Specified from -40 °C to +85 °C 3. Ordering information Table 1. Ordering information Type number Temperature range 74ALVCH16373DGG -40 °C to +85 °C Package Name Description Version TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 74ALVCH16373 Nexperia 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state 4. Functional diagram 1 1OE 1OE 1LE 2OE 47 1D0 1Q0 2 46 1D1 1Q1 3 44 1D2 1Q2 5 43 1D3 1Q3 6 41 1D4 1Q4 8 40 1D5 1Q5 9 38 1D6 1Q6 11 37 1D7 1Q7 12 36 2D0 2Q0 13 35 2D1 2Q1 14 33 2D2 2Q2 16 32 2D3 2Q3 17 30 2D4 2Q4 19 29 2D5 2Q5 20 27 2D6 2Q6 22 26 2D7 2Q7 23 1LE 48 Fig. 1. 24 2OE 2LE 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2LE 25 2D6 2D7 001aam007 1 48 24 25 47 46 1EN C1 2EN C4 3D 2 1 3 44 5 43 6 41 8 40 9 38 11 37 12 36 35 4D 13 2 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 001aam009 Logic symbol Fig. 2. IEC logic symbol VCC data input to internal circuit mna705 Fig. 3. Bus hold circuit 1D0 D Q 1Q0 2D0 D Q LATCH 1 LATCH 9 LE LE LE 1LE 2LE 1OE 2OE to 7 other channels 2Q0 LE to 7 other channels 001aam010 Fig. 4. Logic diagram 74ALVCH16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2021 © Nexperia B.V. 2021. All rights reserved 2 / 14 74ALVCH16373 Nexperia 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state 5. Pinning information 5.1. Pinning 74ALVCH16373 1OE 1 48 1LE 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 42 VCC 1Q4 8 41 1D4 1Q5 9 40 1D5 GND 10 39 GND 1Q6 11 38 1D6 1Q7 12 37 1D7 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 31 VCC 2Q4 19 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2LE 001aam008 Fig. 5. Pin configuration SOT362-1 (TSSOP48) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1OE, 2OE 1, 24 output enable input (active LOW) 1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7 2, 3, 5, 6, 8, 9, 11, 12 data outputs 2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7 13, 14, 16, 17, 19, 20, 22, 23 data outputs GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V) VCC 7, 18, 31, 42 positive supply voltage 1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7 47, 46, 44, 43, 41, 40, 38, 37 data inputs 2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7 36, 35, 33, 32, 30, 29, 27, 26 data inputs 1LE, 2LE 48, 25 latch enable input (active HIGH) 74ALVCH16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2021 © Nexperia B.V. 2021. All rights reserved 3 / 14 74ALVCH16373 Nexperia 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state 6. Functional description Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH LE transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH LE transition; Z = high-impedance OFF-state. Inputs Internal latches Outputs nQn Operating mode L L L H H H H enable and read register (transparent mode) L L l L L L L h H H H L l L Z H L h H Z nOE nLE nDn L H L latch and read register (hold mode) latch register and disable outputs 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +4.6 V -50 - VCC supply voltage IIK input clamping current VI < 0 V VI input voltage control inputs [1] -0.5 +4.6 V data inputs [1] -0.5 VCC + 0.5 V IOK output clamping current - ±50 VO output voltage -0.5 VCC + 0.5 IO output current - ±50 mA ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] VO > VCC or VO < 0 V [1] VO = 0 V to VCC Tamb = -40 °C to +85 °C mA mA V The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 74ALVCH16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2021 © Nexperia B.V. 2021. All rights reserved 4 / 14 74ALVCH16373 Nexperia 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC VI Min Typ Max Unit CL = 30 pF 2.3 - 2.7 V CL = 50 pF 3.0 - 3.6 V low voltage applications maximum speed performance supply voltage input voltage 1.2 - 3.6 V data inputs 0 - VCC V control inputs 0 - 5.5 V 0 - VCC V -40 - +85 °C VO output voltage Tamb ambient temperature in free air Δt/ΔV input transition rise and fall rate VCC = 2.3 V to 3.0 V 0 - 20 ns/V VCC = 3.0 V to 3.6 V 0 - 10 ns/V Conditions Min Typ [1] Max Unit VCC = 1.2 V VCC - - V VCC = 1.8 V 0.7VCC 0.9 - V VCC = 2.3 V to 2.7 V 1.7 1.2 - V VCC = 2.7 V to 3.6 V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 °C to +85 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage 74ALVCH16373 Product data sheet 2.0 1.5 - V VCC = 1.2 V - - 0 V VCC = 1.8 V - 0.9 0.2VCC V VCC = 2.3 V to 2.7 V - 1.2 0.7 V VCC = 2.7 V to 3.6 V - 1.5 0.8 V IO = -100 μA; VCC = 1.8 V to 3.6 V VCC - 0.2 VCC - V IO = -6 mA; VCC = 1.8 V VCC - 0.4 VCC - 0.1 - V IO = -6 mA; VCC = 2.3 V VCC - 0.3 VCC - 0.08 - V IO = -12 mA; VCC = 2.3 V VCC - 0.5 VCC - 0.17 - V IO = -12 mA; VCC = 2.7 V VCC - 0.5 VCC - 0.14 - V IO = -18 mA; VCC = 2.3 V VCC - 0.6 VCC - 0.26 - V IO = -24 mA; VCC = 3.0 V VCC - 1.0 VCC - 0.28 - V VI = VIH or VIL VI = VIH or VIL IO = 100 μA; VCC = 1.8 V to 3.6 V - 0 0.20 V IO = 6 mA; VCC = 1.8 V - 0.09 0.30 V IO = 6 mA; VCC = 2.3 V - 0.07 0.20 V IO = 12 mA; VCC = 2.3 V - 0.15 0.40 V IO = 12 mA; VCC = 2.7 V - 0.14 0.40 V IO = 18 mA; VCC = 2.3 V - 0.23 0.60 V IO = 24 mA; VCC = 3.0 V - 0.27 0.55 V All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2021 © Nexperia B.V. 2021. All rights reserved 5 / 14 74ALVCH16373 Nexperia 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state Symbol Parameter Conditions II VCC = 1.8 V to 3.6 V input leakage current IOZ OFF-state output current ILIZ OFF-state input leakage current ICC supply current ΔICC additional supply current Min Typ [1] Max Unit control input; VI = 5.5 V or GND - 0.1 5 μA data input; VI = VCC or GND - 0.1 5 μA VCC = 1.8 V to 2.7 V - 0.1 5 μA VCC = 2.7 V to 3.6 V - 0.1 10 μA VCC = 1.8 V to 2.7 V - 0.1 10 μA VCC = 3.6 V - 0.1 15 μA VCC = 1.8 V to 2.7 V - 0.2 40 μA VCC = 2.7 V to 3.6 V - 0.2 40 μA per control input - 5 500 μA per data I/O input - 150 750 μA VI = VIH or VIL; VO = VCC or GND VI = VCC or GND VI = VCC or GND; IO = 0 A; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V bus hold LOW current VCC = 2.3 V; VI = 0.7 V [2] 45 - - μA VCC = 3.0 V; VI = 0.8 V [2] 75 150 - μA bus hold HIGH current VCC = 2.3 V; VI = 1.7 V [2] -45 - - μA VCC = 3.0 V; VI = 2.0 V [2] -75 -175 - μA bus hold LOW overdrive current VCC = 2.7 V [2] 300 - - μA VCC = 3.6 V [2] 450 - - μA IBHHO bus hold HIGH overdrive current VCC = 2.7 V [2] -300 - - μA VCC = 3.6 V [2] -450 - - μA CI input capacitance - 5.0 - pF IBHL IBHH IBHLO [1] [2] All typical values are measured at Tamb = 25 °C. Valid for data inputs of bus hold parts only. 74ALVCH16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2021 © Nexperia B.V. 2021. All rights reserved 6 / 14 74ALVCH16373 Nexperia 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 10. Symbol Parameter Conditions Min Typ [1] Max Unit VCC = 1.2 V - 8.8 - ns VCC = 1.8 V 1.5 3.2 5.7 ns 1.0 2.1 3.9 ns 1.0 2.3 3.7 ns 1.0 2.1 3.3 ns VCC = 1.2 V - 7.4 - ns VCC = 1.8 V 1.5 3.4 5.9 ns 1.0 2.2 3.9 ns 1.0 2.2 3.5 ns 1.0 2.2 3.2 ns VCC = 1.2 V - 8.9 - ns VCC = 1.8 V 1.5 4.0 7.3 ns 1.0 2.6 5.2 ns 1.0 2.9 4.9 ns 1.0 2.3 4.2 ns VCC = 1.2 V - 8.9 - ns VCC = 1.8 V 1.5 3.2 5.6 ns 1.0 2.2 4.1 ns 1.0 3.1 4.7 ns 1.0 2.8 4.1 ns 3.5 1.0 - ns 3.0 1.0 - ns 3.0 1.0 - ns 2.5 1.0 - ns 1.0 -0.1 - ns 1.0 -0.1 - ns 1.0 -0.1 - ns 1.0 0.0 - ns Tamb = -40 °C to +85 °C tpd propagation delay nDn to nQn; see Fig. 6 VCC = 2.3 V to 2.7 V [2] [3] VCC = 2.7 V VCC = 3.0 V to 3.6 V nLE to nQn; see Fig. 7 VCC = 2.3 V to 2.7 V [4] [2] [3] VCC = 2.7 V ten enable time VCC = 3.0 V to 3.6 V [4] nOE to nQn; see Fig. 8 [5] VCC = 2.3 V to 2.7 V [3] VCC = 2.7 V tdis disable time VCC = 3.0 V to 3.6 V [4] nOE to nQn; see Fig. 8 [6] VCC = 2.3 V to 2.7 V [3] VCC = 2.7 V VCC = 3.0 V to 3.6 V tW pulse width [4] nLE HIGH; see Fig. 7 VCC = 1.8 V VCC = 2.3 V to 2.7 V [3] VCC = 2.7 V VCC = 3.0 V to 3.6 V tsu set-up time [4] nDn to nLE; see Fig. 9 VCC = 1.8 V VCC = 2.3 V to 2.7 V [3] VCC = 2.7 V VCC = 3.0 V to 3.6 V 74ALVCH16373 Product data sheet [4] All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2021 © Nexperia B.V. 2021. All rights reserved 7 / 14 74ALVCH16373 Nexperia 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state Symbol Parameter Conditions th nDn to nLE; see Fig. 9 hold time Min Typ [1] Max 1.2 0.1 - ns 1.5 0.2 - ns 1.5 0.4 - ns 1.2 0.2 - ns outputs enabled - 16 - pF outputs disabled - 10 - pF VCC = 1.8 V VCC = 2.3 V to 2.7 V [3] VCC = 2.7 V VCC = 3.0 V to 3.6 V CPD [1] [2] [3] [4] [5] [6] [7] power dissipation capacitance [4] per flip-flop; VI = GND to VCC Unit [7] All typical values are measured at Tamb = 25 °C. tpd is the same as tPLH and tPHL. Typical values are measured at VCC = 2.5 V. Typical values are measured at VCC = 3.3 V. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of the outputs. 10.1. Waveforms and test circuit VI nDn input VM VM tPHL tPLH GND VOH nQn output VM VM VOL 001aam011 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig. 6. Propagation delay, input (nDn) to data output (nQn) VI nLE input VM GND VOH nQn output VM tW tPHL VM tPLH VM VOL VM 001aam012 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig. 7. Propagation delay, latch enable input (nLE) to data output (nQn), and pulse width 74ALVCH16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2021 © Nexperia B.V. 2021. All rights reserved 8 / 14 74ALVCH16373 Nexperia 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state VI nOE input VM VM GND tPLZ nQn output LOW-to-OFF OFF-to-LOW tPZL VCC VM VX VOL tPZH tPHZ nQn output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND outputs enabled outputs disabled outputs enabled 001aal795 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig. 8. 3-state enable and disable times VI nDn input VM GND th th tsu VI nLE input tsu VM GND 001aam013 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 9. Data setup and hold times for input (nDn) to input (nLE) Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 2.3 V to 2.7 V and < 2.3 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74ALVCH16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2021 © Nexperia B.V. 2021. All rights reserved 9 / 14 74ALVCH16373 Nexperia 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state VEXT VCC G VI RL VO DUT RT CL RL mna616 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 10. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 2.3 V to 2.7 V and < 2.3 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 Ω open 2 × VCC GND 74ALVCH16373 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2021 © Nexperia B.V. 2021. All rights reserved 10 / 14 74ALVCH16373 Nexperia 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state 11. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 A1 (A3) pin 1 index A θ Lp 1 L 24 bp e detail X w 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit max nom min mm A 1.2 A1 A2 0.15 1.05 0.05 0.85 A3 0.25 bp c D(1) E(2) 0.28 0.2 12.6 6.2 0.17 0.1 12.4 6.0 e HE 0.5 8.3 7.9 L 1 Lp Q 0.8 0.50 0.4 0.35 v w 0.25 0.08 y 0.1 Z θ 0.8 8° 0.4 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Fig. 11. Package outline SOT362-1 (TSSOP48) 74ALVCH16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2021 © Nexperia B.V. 2021. All rights reserved 11 / 14 74ALVCH16373 Nexperia 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge DUT Device Under Test HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVCH16373 v.8 20211122 Product data sheet - 74ALVCH16373 v.7 Modifications: • 74ALVCH16373 v.7 20190130 - 74ALVCH16373 v.6 Modifications: • • • • Section 1 and Section 2 updated. The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74ALVCH16373DL (SOT370-1) removed. Package outline drawing SOT362-1 (TSSOP48) updated. 74ALVCH16373 v.6 20120710 Modifications: • 74ALVCH16373 v.5 20111117 Modifications: • 74ALVCH16373 v.4 20100531 74ALVCH16373 v.3 19990920 74ALVCH16373 v.2 74ALVCH16373 v.1 74ALVCH16373 Product data sheet Product data sheet Product data sheet - 74ALVCH16373 v.5 - 74ALVCH16373 v.4 Product data sheet - 74ALVCH16373 v.3 Product specification - 74ALVCH16373 v.2 19980629 Product specification - 74ALVCH16373 v.1 19970321 Product specification - - Table 8 corrected (errata). Product data sheet Legal pages updated. All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2021 © Nexperia B.V. 2021. All rights reserved 12 / 14 74ALVCH16373 Nexperia 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state 14. Legal information injury, death or severe property or environmental damage. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2021 © Nexperia B.V. 2021. All rights reserved 13 / 14 74ALVCH16373 Nexperia 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 7 10.1. Waveforms and test circuit........................................ 8 11. Package outline........................................................ 11 12. Abbreviations............................................................ 12 13. Revision history........................................................12 14. Legal information......................................................13 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 22 November 2021 74ALVCH16373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 November 2021 © Nexperia B.V. 2021. All rights reserved 14 / 14