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74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 series termination
resistors; 5 V tolerant inputs/outputs; 3-state
Rev. 4 — 14 May 2013
Product data sheet
1. General description
The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with
separate D-type inputs with bus hold (74LVCH162373A only) for each latch and 3-state
outputs for bus-oriented applications. One latch enable (pin nLE) input and one output
enable (pin nOE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V
devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow
the use of these devices in mixed 3.3 V and 5 V applications. The device consists of two
sections of eight D-type transparent latches with 3-state true outputs. When pin nLE is
HIGH, data at the corresponding data inputs (pins nDn) enter the latches. In this condition,
the latches are transparent, that is, the latch output changes each time its corresponding
data inputs changes. When pin nLE is LOW, the latches store the information that was
present at the data inputs a set-up time preceding the HIGH to LOW transition of pin
nLE.When pin nOE is LOW, the contents of the eight latches are available at the outputs.
When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the
nOE input does not affect the state of the latches.
The device is designed with 30 series termination resistors in both HIGH and LOW
output stages to reduce line noise. Bus hold on data inputs eliminates the need for
external pull-up resistors to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH162373A only)
High-impedance when VCC = 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
74LVC162373ADGG
Temperature
range
Name
Description
Version
40 C to +125 C
TSSOP48
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
40 C to +125 C
SSOP48
plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
74LVCH162373ADGG
74LVC162373ADL
74LVCH162373ADL
4. Functional diagram
1
24
1LE
1OE
2OE
1D0
1Q0
2
46
1D1
1Q1
3
44
1D2
1Q2
5
43
1D3
1Q3
6
1D1
41
1D4
1Q4
8
1D2
40
1D5
1Q5
9
1D3
38
1D6
1Q6
11
1D4
37
1D7
1Q7
12
1D5
36
2D0
2Q0
13
1D6
35
2D1
2Q1
14
1D7
33
2D2
2Q2
16
2D0
32
2D3
2Q3
17
2D1
30
2D4
2Q4
19
2D2
29
2D5
2Q5
20
2D3
27
2D6
2Q6
22
2D4
26
2D7
2Q7
23
2D5
48
Fig 1.
2OE
47
1LE
Logic symbol
74LVC_LVCH162373A
Product data sheet
2LE
1D0
2LE
25
1
1OE
2D6
2D7
mgu768
48
24
25
47
1EN
C3
2EN
C4
3D
1
2
46
3
44
5
43
6
41
8
40
9
38
11
37
12
36
4D
2
13
35
14
33
16
32
17
30
19
29
20
27
22
26
23
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
mgu770
Fig 2.
IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
2 of 18
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
1D0
1Q0
Q
D
2D0
D
LATCH
1
LE
2Q0
Q
LATCH
9
LE
LE
1LE
2LE
1OE
2OE
to 7 other channels
LE
to 7 other channels
mgu769
Fig 3.
Logic diagram
VCC
input
to internal circuit
mna428
Fig 4.
Bus hold circuit
74LVC_LVCH162373A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
3 of 18
NXP Semiconductors
74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
5. Pinning information
5.1 Pinning
1OE
1
48 1LE
1Q0
2
47 1D0
1Q1
3
46 1D1
GND
4
45 GND
1Q2
5
44 1D2
1Q3
6
43 1D3
VCC
7
42 VCC
1Q4
8
41 1D4
1Q5
9
40 1D5
GND 10
39 GND
1Q6 11
38 1D6
1Q7 12
2Q0 13
162373A
37 1D7
36 2D0
2Q1 14
35 2D1
GND 15
34 GND
2Q2 16
33 2D2
2Q3 17
32 2D3
VCC 18
31 VCC
2Q4 19
30 2D4
2Q5 20
29 2D5
GND 21
28 GND
2Q6 22
27 2D6
2Q7 23
26 2D7
2OE 24
25 2LE
001aaa336
Fig 5.
Pin configuration (T)SSOP48
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1OE
1
output enable input (active LOW)
2OE
24
output enable input (active LOW)
GND
4, 10, 15, 21, 28, 34, 39, 45
ground (0 V)
VCC
7, 18, 31, 42
supply voltage
1LE
48
latch enable input (active HIGH)
2LE
25
latch enable input (active HIGH)
1D[0:7]
47, 46, 44, 43, 41, 40, 38, 37
data input
2D[0:7]
36, 35, 33, 32, 30, 29, 27, 26
data input
1Q[0:7]
2, 3, 5, 6, 8, 9, 11, 12
data output
2Q[0:7]
13, 14, 16, 17, 19, 20, 22, 23
data output
74LVC_LVCH162373A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
4 of 18
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
6. Functional description
Table 3.
Functional table (per section of 8 bits)[1]
Operating modes
Input
Internal Latch
Output nQn
L
L
nOE
nLE
nDn
Enable and read register
(transparent mode)
L
H
L
L
H
H
H
H
Latch and read register
L
L
l
L
L
L
L
h
H
H
Latch register and disable outputs H
L
l
L
Z
H
L
h
H
Z
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = high-impedance OFF-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
Conditions
VI < 0 V
[1]
Min
Max
Unit
0.5
+6.5
V
50
-
mA
0.5
+6.5
V
-
50
mA
VI
input voltage
IOK
output clamping current
VO > VCC or VO < 0 V
VO
output voltage
output HIGH or LOW state
[2]
0.5
VCC + 0.5
V
output 3-state
[2]
0.5
+6.5
V
IO
output current
-
50
mA
ICC
supply current
-
100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
-
500
mW
total power dissipation
Ptot
VO = 0 V to VCC
Tamb = 40 C to +125 C
[3]
[1]
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2]
The output voltage ratings may be exceeded if the output current ratings are observed.
[3]
Above 60 C, the value of Ptot derates linearly with 5.5 mW/K.
74LVC_LVCH162373A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
5 of 18
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
Conditions
functional
VI
input voltage
VO
output voltage
Min
Typ
Max
Unit
1.65
-
3.6
V
1.2
-
-
V
0
-
5.5
V
output HIGH or LOW state
0
-
VCC
V
output 3-state
0
-
5.5
V
Tamb
ambient temperature
in free air
40
-
+125
C
t/V
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
0
-
20
ns/V
VCC = 2.7 V to 3.6 V
0
-
10
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
Min
VIH
VIL
VOH
VOL
II
HIGH-level input VCC = 1.2 V
voltage
VCC = 1.65 V to 1.95 V
LOW-level input
voltage
HIGH-level
output voltage
LOW-level
output voltage
input leakage
current
74LVC_LVCH162373A
Product data sheet
1.08
Typ[1]
40 C to +125 C
Max
Min
Unit
Max
-
-
1.08
-
V
0.65 VCC -
-
0.65 VCC -
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
-
0.12
V
VCC = 1.2 V
-
-
0.12
VCC = 1.65 V to 1.95 V
-
-
0.35 VCC -
0.35 VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC 0.2
VCC
-
VCC 0.3
-
V
IO = 2 mA; VCC = 1.65 V 1.2
-
-
1.05
-
V
IO = 4 mA; VCC = 2.3 V
1.7
-
-
1.55
-
V
IO = 6 mA; VCC = 2.7 V
2.2
-
-
2.05
-
V
IO = 12 mA; VCC = 3.0 V 2.2
-
-
2.0
-
V
VI = VIH or VIL
IO = 100 A;
VCC = 1.65 V to 3.6 V
VI = VIH or VIL
IO = 100 A;
VCC = 1.65 V to 3.6 V
-
-
0.2
-
0.3
V
IO = 2 mA; VCC = 1.65 V
-
-
0.45
-
0.65
V
IO = 4 mA; VCC = 2.3 V
-
-
0.6
-
0.8
V
IO = 6 mA; VCC = 2.7 V
-
-
0.4
-
0.6
V
IO = 12 mA; VCC = 3.0 V
-
-
0.55
-
0.8
V
-
0.1
5
-
20
A
VCC = 3.6 V;
VI = 5.5 V or GND [2]
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
6 of 18
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
Min
Typ[1]
40 C to +125 C
Max
Min
Unit
Max
IOZ
OFF-state output VI = VIH or VIL; VCC = 3.6 V; current
VO = 5.5 V or GND [2]
0.1
5
-
20
A
IOFF
power-off
leakage current
VCC = 0 V; VI or VO = 5.5 V
-
0.1
10
-
20
A
ICC
supply current
VCC = 3.6 V;
VI = VCC or GND; IO = 0 A
-
0.1
20
-
80
A
ICC
additional supply per input pin;
current
VCC = 2.7 V to 3.6 V;
VI = VCC 0.6 V; IO = 0 A
-
5
500
-
5000
A
CI
input
capacitance
VCC = 0 V to 3.6 V;
VI = GND to VCC
-
5.0
-
-
-
pF
IBHL
bus hold LOW
current
VCC = 1.65; VI = 0.58 V [3][4]
10
-
-
10
-
A
VCC = 2.3; VI = 0.7 V
30
-
-
25
-
A
VCC = 3.0; VI = 0.8 V
75
-
-
60
-
A
VCC = 1.65; VI = 1.07 V [3][4]
10
-
-
10
-
A
VCC = 2.3; VI = 1.7 V
30
-
-
25
-
A
VCC = 3.0; VI = 2.0 V
75
-
-
60
-
A
200
-
-
200
-
A
300
-
-
300
-
A
500
-
-
500
-
A
200
-
-
200
-
A
300
-
-
300
-
A
500
-
-
500
-
A
IBHH
IBHLO
bus hold HIGH
current
bus hold LOW
VCC = 1.95 V
overdrive current V = 2.7 V
CC
[3][5]
VCC = 3.6 V
IBHHO
bus hold HIGH
VCC = 1.95 V
overdrive current V = 2.7 V
CC
VCC = 3.6 V
[1]
[3][5]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
[2]
The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input pin.
[3]
Valid for data inputs (74LVCH162373A) only; control inputs do not have a bus hold circuit.
[4]
The specified sustaining current at the data inputs holds the input below the specified VI level.
[5]
The specified overdrive current at the data input forces the data input to the opposite logic input state.
74LVC_LVCH162373A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
7 of 18
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter
tpd
propagation delay
Tamb = 40 C to +85 C 40 C to +125 C Unit
Conditions
Min
Typ[1]
Max
Min
Max
-
12
-
-
-
ns
VCC = 1.65 V to 1.95 V
1.5
6.6
15.0
1.5
17.2
ns
VCC = 2.3 V to 2.7 V
1.0
3.5
7.4
1.0
8.5
ns
nDn to nQn; see Figure 6
[2]
VCC = 1.2 V
VCC = 2.7 V
1.5
3.5
6.7
1.5
8.5
ns
VCC = 3.0 V to 3.6 V
1.0
3.0
5.9
1.0
7.5
ns
-
14
-
-
-
ns
VCC = 1.65 V to 1.95 V
2.4
7.6
16.0
2.4
18.5
ns
VCC = 2.3 V to 2.7 V
1.7
4.0
7.9
1.7
9.1
ns
VCC = 2.7 V
1.5
3.7
7.0
1.5
9.0
ns
1.5
3.4
6.1
1.5
8.0
ns
-
18
-
-
-
ns
VCC = 1.65 V to 1.95 V
1.7
7.1
15.6
1.7
17.9
ns
VCC = 2.3 V to 2.7 V
1.5
4.0
8.2
1.5
9.4
ns
nLE to nQn; see Figure 7
VCC = 1.2 V
VCC = 3.0 V to 3.6 V
ten
enable time
nOE to nQn; see Figure 8
[2]
VCC = 1.2 V
tdis
disable time
VCC = 2.7 V
1.5
4.2
7.5
1.5
9.5
ns
VCC = 3.0 V to 3.6 V
1.0
3.2
6.1
1.0
8.0
ns
-
11
-
-
-
ns
nOE to nQn; see Figure 8
[2]
VCC = 1.2 V
tW
tsu
pulse width
set-up time
74LVC_LVCH162373A
Product data sheet
VCC = 1.65 V
2.5
4.2
8.5
2.5
9.8
ns
VCC = 2.3 V to 2.7 V
1.0
2.3
4.6
1.0
5.3
ns
VCC = 2.7 V
1.5
3.2
4.8
1.5
6.0
ns
VCC = 3.0 V to 3.6 V
1.5
2.9
4.6
1.5
6.0
ns
VCC = 1.65 V to 1.95 V
5.0
-
-
5.0
-
ns
VCC = 2.3 V to 2.7 V
4.0
-
-
4.0
-
ns
VCC = 2.7 V
3.0
-
-
3.0
-
ns
VCC = 3.0 V to 3.6 V
3.0
2.0
-
3.0
-
ns
VCC = 1.65 V to 1.95 V
3.0
-
-
3.0
-
ns
VCC = 2.3 V to 2.7 V
2.5
-
-
2.5
-
ns
VCC = 2.7 V
2.0
-
-
2.0
-
ns
VCC = 3.0 V to 3.6 V
2.0
1.0
-
2.0
-
ns
nLE HIGH; see Figure 7
nDn to nLE; see Figure 9
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
8 of 18
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter
th
hold time
Tamb = 40 C to +85 C 40 C to +125 C Unit
Conditions
Min
Typ[1]
Max
Min
Max
nDn to nLE; see Figure 9
VCC = 1.65 V to 1.95 V
2.5
-
-
2.5
-
ns
VCC = 2.3 V to 2.7 V
2.0
-
-
2.0
-
ns
VCC = 2.7 V
0.9
-
-
0.9
-
ns
+0.9
1.0
-
+0.9
-
ns
-
-
1.0
-
1.5
ns
VCC = 1.65 V to 1.95 V
-
10.8
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
13.0
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
15.0
-
-
-
pF
VCC = 3.0 V to 3.6 V
tsk(o)
output skew time
VCC = 3.0 V to 3.6 V
[3]
CPD
power dissipation
capacitance
per input; VI = GND to VCC
[4]
[1]
Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2]
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3]
[4]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs
74LVC_LVCH162373A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
9 of 18
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
11. AC waveforms
VI
VM
nDn input
GND
t PHL
t PLH
VOH
VM
nQn output
VOL
mna429
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
Input (nDn) to output (nQn) propagation delays
VI
VM
nLE input
GND
tW
t PHL
t PLH
VOH
nQn output
VM
VOL
mna430
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
Latch enable (nLE) pulse width, and the latch enable input to output (nQn) propagation delays
74LVC_LVCH162373A
Product data sheet
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Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
10 of 18
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
VI
nOE input
VM
GND
t PLZ
t PZL
VCC
nQn output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
t PHZ
t PZH
VOH
VY
nQn output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
mna432
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8.
3-state enable and disable times
VI
VM
nDn input
GND
th
t su
th
t su
VI
VM
nLE input
GND
mna431
Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable
output performance.
Fig 9.
Table 8.
Data set-up and hold times for the nDn input to the nLE input
Measurement points
Supply voltage
Input
VCC
VI
VM
VM
VX
VY
1.2 V
VCC
0.5 VCC
0.5 VCC
VOL + 0.15 V
VOH 0.15 V
1.65 V to 1.95 V
VCC
0.5 VCC
0.5 VCC
VOL + 0.15 V
VOH 0.15 V
2.3 V to 2.7 V
VCC
0.5 VCC
0.5 VCC
VOL + 0.15 V
VOH 0.15 V
2.7 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH 0.3 V
3.0 V to 3.6 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH 0.3 V
74LVC_LVCH162373A
Product data sheet
Output
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
11 of 18
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VEXT
VCC
VI
RL
VO
G
DUT
RT
RL
CL
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
Input
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
1.2 V
VCC
2 ns
30 pF
1 k
open
2 VCC
GND
1.65 V to 1.95 V
VCC
2 ns
30 pF
1 k
open
2 VCC
GND
2.3 V to 2.7 V
VCC
2 ns
30 pF
500
open
2 VCC
GND
2.7 V
2.7 V
2.5 ns
50 pF
500
open
2 VCC
GND
3.0 V to 3.6 V
2.7 V
2.5 ns
50 pF
500
open
2 VCC
GND
74LVC_LVCH162373A
Product data sheet
Load
VEXT
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
12 of 18
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
12. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
HE
v M A
Z
25
48
Q
A2
A1
A
(A 3)
θ
pin 1 index
Lp
L
24
1
detail X
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.8
0.4
0.2
2.35
2.20
0.25
0.3
0.2
0.22
0.13
16.00
15.75
7.6
7.4
0.635
10.4
10.1
1.4
1.0
0.6
1.2
1.0
0.25
0.18
0.1
0.85
0.40
8o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT370-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-118
Fig 11. Package outline SOT370-1 (SSOP48)
74LVC_LVCH162373A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
13 of 18
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
HE
y
v M A
Z
48
25
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
detail X
24
w M
bp
e
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.8
0.4
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT362-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 12. Package outline SOT362-1 (TSSOP48)
74LVC_LVCH162373A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
14 of 18
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
74LVC_LVCH162373A v.4 20130514
Modifications:
•
Change notice
Supersedes
Product data sheet
-
74LVC_LVCH162373A v.3
Typenumbers: 74LVC162373ADGG and 74LVC162373ADL added.
74LVC_LVCH162373A v.3 20130118
Modifications:
Data sheet status
Product data sheet
-
74LVC_LVCH162373A v.2
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges.
74LVC_LVCH162373A v.2 20040205
Product specification
-
74LVC_LVCH162373A v.1
74LVC_LVCH162373A v.1 19980805
Product specification
-
-
74LVC_LVCH162373A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
15 of 18
74LVC162373A; 74LVCH162373A
NXP Semiconductors
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC_LVCH162373A
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
16 of 18
NXP Semiconductors
74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC_LVCH162373A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
17 of 18
NXP Semiconductors
74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch; 30 resistors; 5 V tolerance; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 May 2013
Document identifier: 74LVC_LVCH162373A
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