74ALVCH16843DGG,11

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia INTEGRATED CIRCUITS 74ALVCH16843 18-bit bus-interface D-type latch (3-State) Product specification IC24 Data Handbook
     1998 Aug 04 Philips Semiconductors Product specification 18-bit bus interface D-type latch (3-State) FEATURES 74ALVCH16843 PIN CONFIGURATION • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.0 V • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple VCC and GND pins for minimum noise and ground bounce • All data inputs have bus hold • Output drive capability 50Ω transmission lines @ 85°C DESCRIPTION The 74ALVCH16843 has two 9–bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE), clear (nCLR), preset (nPRE) and output enable (nOE) control gates. When nOE is LOW, the data in the registers appear at the outputs. When nOE is HIGH, the outputs are in the high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16843 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 1CLR 1 56 1OE 2 55 1Q0 3 54 1D0 GND 4 53 GND 1Q1 5 52 1D1 1Q2 6 51 1D2 VCC 7 50 VCC 1Q3 8 49 1D3 1Q4 9 48 1D4 1Q5 10 47 1D5 GND 11 46 GND 1Q6 12 45 1D6 1Q7 13 44 1D7 1Q8 14 43 1D8 2Q0 15 42 2D0 2Q1 16 41 2D1 2Q2 17 40 2D2 GND 18 39 GND 2Q3 19 38 2D3 2Q4 20 37 2D4 1LE 1PRE 2Q5 21 36 2D5 VCC 22 35 VCC 2Q6 23 34 2D6 2Q7 24 33 2D7 GND 25 32 GND 2Q8 26 31 2D8 2OE 27 30 2PRE 2CLR 28 29 2LE SH00143 QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns PARAMETER SYMBOL Propagation delay nDn to nQn tPHL/tPLH Propagation delay nLE to nQn CI Input capacitance CPD Power dissipation dissi ation capacitance ca acitance per er buffer CONDITIONS VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF VI = GND to VCC1 TYPICAL 2.2 2.1 2.3 2.0 5.0 transparent mode Output enabled Output disabled 17 3 Clocked mode Output enabled Output disabled 19 9 UNIT ns ns pF pF F NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi +
(CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES 56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II 1998 Aug 04 TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DRAWING NUMBER –40°C to +85°C 74ALVCH16843 DGG ACH16843 DGG SOT364-1 2 853–2108 019833 Philips Semiconductors Product specification 18-bit bus interface D-type latch (3-State) PIN DESCRIPTION LOGIC SYMBOL PIN NUMBER SYMBOL 1 1CLR Clear input (active LOW) 2 1OE Output enable input (active LOW) 55 1CLR 1PRE 52 6 1LE Latch enable input (active HIGH) 1Q2 1D2 51 8 1Q3 1D3 49 9 1Q4 1D4 48 10 1Q5 1D5 47 12 1Q6 1D6 45 13 1Q7 1D7 44 14 1Q8 1D8 43 15 2Q0 2D0 42 16 2Q1 2D1 41 17 2Q2 2D2 40 19 2Q3 2D3 38 20 2Q4 2D4 37 21 2Q5 2D5 36 23 2Q6 2D6 34 24 2Q7 2D7 33 26 2Q8 2D8 31 GND Data inputs Data outputs Ground (0V) VCC Positive supply voltage Output enable input (active LOW) 2OE 2CLR Clear input (active LOW) 2LE Latch enable input (active HIGH) 2PRE Preset input (active LOW) 42, 41, 40, 38, 37, 36, 34, 33, 31 2D0 to 2D8 Data inputs 15, 16, 17, 19, 20, 21, 23, 24, 26 2Q0 to 2Q8 Data outputs 2CLR 2PRE 28 FUNCTION TABLE 30 2OE 2LE 27 29 SH00144 INPUTS OUTPUT nPRE nCLR nOE LE DX Q L X L X X H H L L X X L H H L H L L H H L H H H H H L H X Q0 X H H X Z HIGH voltage level LOW voltage level Don’t care High impedance “off” state 1998 Aug 04 1LE 54 29 = = = = 1OE 1D1 27 X 1Q0 56 1D0 7, 22, 35, 50 H L X Z 3 2 1Q1 4, 11, 18, 25, 32, 39, 46, 53 30 55 5 1Q0 to 1Q8 28 1 Preset input (active LOW) 1D0 to 1D8 3, 5, 6, 8, 9, 10, 12, 13, 14 NAME AND FUNCTION 1PRE 56 54, 52, 51, 49, 48, 47, 45, 44, 43 74ALVCH16843 3 Philips Semiconductors Product specification 18-bit bus interface D-type latch (3-State) LOGIC DIAGRAM LOGIC SYMBOL (IEEE/IEC) nD0 1OE D CLR PRE D LE nCLR nPRE nLE nOE nQ0 SH00146 2 VCC To internal circuit EN4 1PRE 56 S2 1CLR R3 1 1LE 56 C1 2OE 27 EN8 2PRE 30 S6 2CLR 28 R7 2LE 29 C5 1D0 54 1D 2, 3, 4 ∇ 3 1Q0 1D1 52 5 1Q1 1D2 51 6 1Q2 1D3 49 8 1Q3 1D4 48 9 1Q4 1D5 47 10 1Q5 1D6 45 12 1Q6 1D7 44 13 1Q7 1D8 43 14 1Q8 15 2Q0 2D1 41 16 2Q1 2D2 40 17 2Q2 2D3 38 19 2Q3 2D4 37 20 2Q4 2D5 36 21 2Q5 2D6 34 23 2Q6 2D7 33 24 2Q7 2D8 31 26 2Q8 2D0 42 BUS HOLD CIRCUIT Data Input 74ALVCH16843 5D 6, 7, 8 ∇ SH00145 SW00044 1998 Aug 04 4 Philips Semiconductors Product specification 18-bit bus interface D-type latch (3-State) 74ALVCH16843 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER MIN MAX DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load) 2.3 2.7 DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load) 3.0 3.6 0 VCC VI DC Input voltage range VO DC output voltage range Tamb Operating free-air temperature range tr, tf Input rise and fall times CONDITIONS UNIT V V 0 VCC V –40 +85 °C 0 0 20 10 ns/V VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK PARAMETER CONDITIONS DC supply voltage DC input diode current VI 0 mA –0.5 to VCC +0.5 DC output diode current VO VCC or VO  0 VO DC output voltage Note 2 IO DC output source or sink current VO = 0 to VCC DC VCC or GND current Storage temperature range Power dissipation per package –plastic medium-shrink (SSOP) –plastic thin-medium-shrink (TSSOP) –50 For data inputs2 IOK PTOT V –0.5 to +4.6 DC in input ut voltage Tstg UNIT For control pins2 VI IGND, ICC RATING –0.5 to +4.6 For temperature range: –40 to +125 °C above +55°C derate linearly with 11.3 mW/K above +55°C derate linearly with 8 mW/K
50 V mA –0.5 to VCC +0.5 V
50 mA
100 mA –65 to +150 °C 850 600 mW NOTE: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Aug 04 5 Philips Semiconductors Product specification 18-bit bus interface D-type latch (3-State) 74ALVCH16843 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER VIH HIGH level Input voltage VIL LOW level Input voltage VOH O HIGH level output voltage TEST CONDITIONS Temp = -40°C to +85°C MIN TYP1 VCC = 2.3 to 2.7V 1.7 1.2 VCC = 2.7 to 3.6V 2.0 1.5 UNIT MAX V VCC = 2.3 to 2.7V 1.2 0.7 VCC = 2.7 to 3.6V 1.5 0.8 V 3 to 3 6V; VI = VIH or VIL; IO = –100µA 100µA VCC = 2 2.3 3.6V; 02 VCC
0.2 VCC VCC = 2.3V; VI = VIH or VIL; IO = –6mA VCC
0.3 VCC
0.08 VCC = 2.3V; VI = VIH or VIL; IO = –12mA VCC
0.6 VCC
0.26 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC
0.5 VCC
0.14 VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC
0.6 VCC
0.09 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC
1.0 VCC
0.28 V VCC = 2 2.3 3 to 3 3.6V; 6V; VI = VIH or VIL; IO = 100µA GND 0 20 0.20 V VCC = 2.3V; VI = VIH or VIL; IO = 6mA 0.07 0.40 V VCC = 2.3V; VI = VIH or VIL; IO = 12mA 0.15 0.70 VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.14 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 24mA 0.27 0.55 Input leakage g current VCC = 2 2.3 3 to 3 3.6V; 6V; VI = VCC or GND 0.1 5 µA µ IOZ 3-State output OFF-state current VCC = 2.3 to 3.6V; VI = VIH or VIL; VO = VCC or GND 0.1 10 µA ICC Quiescent supply current VCC = 2.3 to 3.6V; VI = VCC or GND; IO = 0 0.2 40 µA ∆ICC Additional quiescent supply current VCC = 2.3V to 3.6V; VI = VCC – 0.6V; IO = 0 150 750 µA IBHL2 Bus hold LOW sustaining current IBHH2 Bus hold HIGH sustaining current IBHLO2 IBHHO2 VOL II LOW level output voltage VCC = 2.3V; VI = 0.7V 45 – VCC = 3.0V; VI = 0.8V 75 150 VCC = 2.3V; VI = 1.7V –45 VCC = 3.0V; VI = 2.0V –75 Bus hold LOW overdrive current VCC = 3.6V 500 µA Bus hold HIGH overdrive current VCC = 3.6V –500 µA NOTES: 1. All typical values are at Tamb = 25°C. 2. Valid for data inputs of bus hold parts. 1998 Aug 04 V 6 –175 µA µA Philips Semiconductors Product specification 18-bit bus interface D-type latch (3-State) 74ALVCH16843 AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE GND = 0V; tr = tf ≤ 2.0ns; CL = 30pF LIMITS SYMBOL PARAMETER WAVEFORM VCC = 2.3 to 2.7V UNIT MIN TYP1 MAX Propagation delay nDn to nQn 1, 6 1.0 2.2 4.3 Propagation delay nLE to nQn 2, 6 1.0 2.3 4.6 Propagation delay nPRE to nQn 1, 6 1.0 2.5 4.8 Propagation delay nCLR to nQn 1, 6 1.0 2.5 4.8 tPZH/tPZL 3-State output enable time nOE to nQn 5, 6 1.0 2.8 5.8 ns tPHZ/tPLZ 3-State output disable time nOE to nQn 5, 6 1.1 2.2 4.3 ns Set-up time nDn to nLE 3, 6 0.5 –0.1 – ns Hold time nDn to nLE 3, 6 0.9 0.5 – ns nLE pulse width HIGH 2, 6 1.5 0.5 – nPRE pulse width LOW 4, 6 1.5 0.5 – nCLR pulse width LOW 4, 6 1.5 0.5 – Recovery time nPRE to nLE 4, 6 0.5 1.1 – Recovery time nCLR to nLE 4, 6 0.5 1.0 – tPHL/tPLH tSU th tW tREM ns ns ns NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF SYMBOL PARAMETER WAVEFORM LIMITS LIMITS VCC = 3.3 ± 0.3V VCC = 2.7V MIN TYP1, 2 MAX MIN TYP1 MAX UNIT Propagation delay nDn to nQn 1, 6 1.0 2.1 3.5 1.0 2.3 4.0 Propagation delay nLE to nQn 2, 6 1.0 2.0 3.5 1.0 2.1 3.9 Propagation delay nPRE to nQn 1, 6 1.0 2.2 3.8 1.0 2.6 4.5 Propagation delay nCLR to nQn 1, 6 1.0 2.3 3.9 1.0 2.5 4.3 tPZH/tPZL 3-State output enable time nOE to nQn 5, 6 1.0 2.5 4.4 1.0 3.0 5.3 ns tPHZ/tPLZ 3-State output disable time nOE to nQn 5, 6 1.3 2.6 4.0 1.3 2.8 4.4 ns Set-up time nDn to nLE 3, 6 0.5 0.0 – 0.5 –0.3 – ns Hold time nDn to nLE 3, 6 0.9 0.5 – 0.9 0.5 – ns nLE pulse width HIGH 2, 6 1.5 0.5 – 1.5 0.5 – nPRE pulse width LOW 4, 6 1.5 0.5 – 1.5 0.6 – nCLR pulse width LOW 4, 6 1.5 0.5 – 1.5 0.5 – Recovery time nPRE to nLE 4, 6 1.0 0.4 – 0.8 –0.2 – Recovery time nCLR to nLE 4, 6 0.8 0.2 – 0.6 –0.4 – tPHL/tPLH tSU th tW tREM ns NOTES: 1. All typical values are measured Tamb = 25°C. 2. Typical value is measured at VCC = 3.3V 1998 Aug 04 7 ns ns Philips Semiconductors Product specification 18-bit bus interface D-type latch (3-State) 74ALVCH16843 ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ AC WAVEFORMS FOR VCC = 2.3V TO 2.7V AND VCC < 2.3V RANGE VI Dn INPUT VM = 0.5 V VX = VOL + 0.15V VY = VOH –0.15V VOL and VOH are the typical output voltage drop that occur with the output load. V =V CC I VM GND th th tSU tSU VI LE INPUT VM GND AC WAVEFORMS FOR VCC = 3.0V TO 3.6V AND VCC = 2.7V RANGE NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 1.5 V VX = VOL + 0.3V VY = VOH –0.3V VOL and VOH are the typical output voltage drop that occur with the output load. V = 2.7V I CLR, Dn SH00149 Waveform 3. Data set-up and hold times for the Dn input to the LE input VI VI CLR, PRE VM PRE VM GND GND tPHL tW(L) tPLH tREM VI VOH Qn OUTPUT LE VM VM GND VOL SH00148 SH00147 Waveform 4. Clear (CLR) and preset (PRE) pulse width, the clear (CLR) and preset (PRE) to latch (LE) removal time Waveform 1. Data input (Dn) to output (Qn), clear input (CLR) to output (Qn) and preset input (PRE) to output (Qn) propagation delay VI VI LE INPUT GND nOE INPUT VM GND tW tPHL tPLH tPLZ VOH Qn OUTPUT VM VM tPZL VCC VM OUTPUT LOW-to-OFF OFF-to-LOW VOL VM VX VOL SH00150 Waveform 2. Latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delay tPHZ tPZH VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VY VM GND outputs enabled outputs disabled outputs enabled SH00137 Waveform 5. 3-State enable and disable times 1998 Aug 04 8 Philips Semiconductors Product specification 18-bit bus interface D-type latch (3-State) TEST CIRCUIT S1 VCC RL = 500 Ω VO VI PULSE GENERATOR 2 * VCC Open GND D.U.T. RT RL = 500 Ω CL Test Circuit for switching times DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. SWITCH POSITION TEST tPLH/tPHL S1 Open tPLZ/tPZL 2
VCC tPHZ/tPZH GND VCC VI < 2.7V VCC 2.7–3.6V 2.7V SV00906 Waveform 6. Load circuitry for switching times 1998 Aug 04 9 74ALVCH16843 Philips Semiconductors Product specification 18-bit bus interface D-type latch (3-State) TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 1998 Aug 04 10 74ALVCH16843 SOT364-1 Philips Semiconductors Product specification 18-bit bus interface D-type latch (3-State) NOTES 1998 Aug 04 11 74ALVCH16843 Philips Semiconductors Product specification 18-bit bus interface D-type latch (3-State) 74ALVCH16843 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number:
     1998 Aug 04 12 Date of release: 07-98 9397-750-04562