74HCT193PW,112

74HC193; 74HCT193 Presettable synchronous 4-bit binary up/down counter Rev. 7 — 8 September 2021 Product data sheet 1. General description The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time to guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • • • • • • • • • • • • Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Input levels: • For 74HC193: CMOS level • For 74HCT193: TTL level Synchronous reversible 4-bit binary counting Asynchronous parallel load Asynchronous reset Expandable without external logic Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V. Specified from -40 °C to +85 °C and -40 °C to +125 °C. 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter 3. Ordering information Table 1. Ordering information Type number Package 74HC193D Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT193D 74HC193PW 74HCT193PW 4. Functional diagram 15 11 5 4 14 1 D0 PL D1 9 D2 D3 TCU CPU COUNTER CPD MR TCD 12 13 FLIP-FLOPS Q0 3 Fig. 1. 10 Q1 2 Q2 6 Fig. 2. 11 5 4 14 15 1 10 9 C3 2+ G1 1G2 R D1 D2 D3 11 15 1 10 9 5 12 TCU CPD 4 13 TCD 001aag405 Functional diagram D0 CPU 14 3 2 6 7 MR Q0 Q1 Q2 Q3 Q3 7 PL 001aag409 Logic symbol CTR4 3 2 6 7 3D 2CT = 0 1CT = 15 13 12 001aag410 Fig. 3. IEC logic symbol 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 2 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter D0 D1 D2 D3 PL CPU TCU SD T SD Q FF1 RD T Q SD Q FF2 RD T Q SD Q FF3 RD T Q Q FF4 RD Q TCD CPD MR Q0 Fig. 4. Q1 Q2 Q3 001aag412 Logic diagram 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 3 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter 5. Pinning information 5.1. Pinning 74HC193 74HCT193 D1 1 16 VCC Q1 2 15 D0 Q0 3 14 MR CPD 4 13 TCD CPU 5 12 TCU Q2 6 11 PL Q3 7 GND 8 74HC193 74HCT193 D3 1 2 16 VCC 15 D0 Q0 3 14 MR CPD 4 13 TCD CPU 5 12 TCU Q2 6 11 PL Q3 7 10 D2 GND 8 10 D2 9 D1 Q1 D3 001aag407 001aag406 Fig. 5. 9 Pin configuration for SOT109-1 (SO16) Fig. 6. Pin configuration for SOT403-1 (TSSOP16) 5.2. Pin description Table 2. Pin description Symbol Pin Description D0, D1, D2, D3 15, 1, 10, 9 data input Q0, Q1, Q2, Q3 3, 2, 6, 7 flip-flop output CPD 4 count down clock input; LOW-to-HIGH, edge triggered CPU 5 count up clock input; LOW-to-HIGH, edge triggered GND 8 ground (0 V) PL 11 asynchronous parallel load input (active LOW) TCU 12 terminal count up (carry) output (active LOW) TCD 13 terminal count down (borrow) output (active LOW) MR 14 asynchronous master reset input (active HIGH) VCC 16 supply voltage 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 4 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition. Operating mode Inputs Outputs MR PL CPU CPD D0 D1 D2 D3 Q0 Q1 Q2 Q3 TCU TCD H X X L X X X X L L L L H L H X X H X X X X L L L L H H L L X L L L L L L L L L H L L L X H L L L L L L L L H H L L L X H H H H H H H H L H L L H X H H H H H H H H H H Count up L H ↑ H X X X X count up H [1] H Count down L H H ↑ X X X X count down H Reset (clear) Parallel load [1] [2] H [2] TCU = CPU at terminal count up (HHHH) TCD = CPD at terminal count down (LLLL). 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 5 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter MR(1) PL D0 D1 D2 D3 CPU(2) CPD(2) Q0 Q1 Q2 Q3 TCU TCD 0 13 CLEAR PRESET 14 15 0 COUNT UP 1 2 1 0 15 14 COUNT DOWN 13 001aag411 (1) Clear overrides load, data and count inputs. (2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input (CPU) must be HIGH. Sequence: Clear (reset outputs to zero); Load (preset) to binary thirteen; Count up to fourteen, fifteen, terminal count up, zero, one and two; Count down to one, zero, terminal count down, fifteen, fourteen and thirteen. Fig. 7. Typical clear, load and count sequence 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 6 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Max Unit VCC supply voltage -0.5 +7.0 V IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V IO output current VO = -0.5 V to VCC + 0.5 V [1] - ±20 mA - ±25 mA ICC supply current - 50 mA IGND ground current - -50 mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] Conditions [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC193 74HCT193 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C Δt/ΔV input transition rise and fall rate VCC supply voltage VI 74HC_HCT193 Product data sheet VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 7 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter 9. Static characteristics Table 6. Static characteristics type 74HC193 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.2 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V Tamb = 25 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL - - - IO = -20 μA; VCC = 2.0 V 1.9 2.0 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - V IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - V IO = 20 μA; VCC = 2.0 V - 0 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 V VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 μA Ci input capacitance - 3.5 - pF 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 8 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 - - V IO = -20 μA; VCC = 4.5 V 4.4 - - V IO = -20 μA; VCC = 6.0 V 5.9 - - V IO = -4.0 mA; VCC = 4.5 V 3.84 - - V IO = -5.2 mA; VCC = 6.0 V 5.34 - - V IO = 20 μA; VCC = 2.0 V - - 0.1 V IO = 20 μA; VCC = 4.5 V - - 0.1 V IO = 20 μA; VCC = 6.0 V - - 0.1 V IO = 4.0 mA; VCC = 4.5 V - - 0.33 V IO = 5.2 mA; VCC = 6.0 V - - 0.33 V Tamb = -40 °C to +85 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 80 μA VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 - - V IO = -20 μA; VCC = 4.5 V 4.4 - - V IO = -20 μA; VCC = 6.0 V 5.9 - - V IO = -4.0 mA; VCC = 4.5 V 3.7 - - V IO = -5.2 mA; VCC = 6.0 V 5.2 - - V IO = 20 μA; VCC = 2.0 V - - 0.1 V IO = 20 μA; VCC = 4.5 V - - 0.1 V IO = 20 μA; VCC = 6.0 V - - 0.1 V IO = 4.0 mA; VCC = 4.5 V - - 0.4 V IO = 5.2 mA; VCC = 6.0 V - - 0.4 V Tamb = -40 °C to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 160 μA 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 9 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter Table 7. Static characteristics type 74HCT193 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = -20 μA 4.4 4.5 - V IO = -4.0 mA 3.98 4.32 - V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 μA - 0 0.1 V IO = 4.0 mA - 0.15 0.26 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±0.1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 μA ΔICC additional supply current per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pin Dn - 35 126 μA pins CPU, CPD - 140 504 μA pin PL - 65 234 μA pin MR - 105 378 μA - 3.5 - pF Ci input capacitance Tamb = -40 °C to +85 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = -20 μA 4.4 - - V IO = -4.0 mA 3.84 - - V IO = 20 μA - - 0.1 V IO = 4.0 mA - - 0.33 V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 80 μA ΔICC additional supply current per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pin Dn - - 157.5 μA pins CPU, CPD - - 630 μA pin PL - - 292.5 μA pin MR - - 472.5 μA 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 10 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter Symbol Parameter Conditions Min Typ Max Unit Tamb = -40 °C to +125 °C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = -20 μA 4.4 - - V IO = -4.0 mA 3.7 - - V IO = 20 μA - - 0.1 V IO = 4.0 mA - - 0.4 V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 160 μA ΔICC additional supply current per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V pin Dn - - 171.5 μA pins CPU, CPD - - 686 μA pin PL - - 318.5 μA pin MR - - 514.5 μA 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 11 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter 10. Dynamic characteristics Table 8. Dynamic characteristics type 74HC193 Symbol Parameter Conditions 25 °C Min tpd propagation delay CPU, CPD to Qn; see Fig. 8 [1] -40 °C to +85 °C Typ Max -40 °C to +125 °C Unit Min Max Min Max - VCC = 2.0 V - 63 215 - 270 - 325 ns VCC = 4.5 V - 23 43 - 54 - 65 ns VCC = 6.0 V - 18 37 - 46 - 55 ns VCC = 2.0 V - 39 125 - 155 - 190 ns VCC = 4.5 V - 14 25 - 31 - 38 ns VCC = 6.0 V - 11 21 - 26 - 32 ns VCC = 2.0 V - 39 125 - 155 - 190 ns VCC = 4.5 V - 14 25 - 31 - 38 ns VCC = 6.0 V - 11 21 - 26 - 32 ns VCC = 2.0 V - 69 220 - 275 - 330 ns VCC = 4.5 V - 25 44 - 55 - 66 ns VCC = 6.0 V - 20 37 - 47 - 56 ns VCC = 2.0 V - 58 200 - 250 - 300 ns VCC = 4.5 V - 21 40 - 50 - 60 ns VCC = 6.0 V - 17 34 43 - 51 ns VCC = 2.0 V - 69 210 - 265 - 315 ns VCC = 4.5 V - 25 42 - 53 - 63 ns VCC = 6.0 V - 20 36 - 45 - 54 ns VCC = 2.0 V - 80 290 - 365 - 435 ns VCC = 4.5 V - 29 58 - 73 - 87 ns VCC = 6.0 V - 23 49 - 62 - 74 ns VCC = 2.0 V - 74 285 - 355 - 430 ns VCC = 4.5 V - 27 57 - 71 - 86 ns VCC = 6.0 V - 22 48 - 60 - 73 ns VCC = 2.0 V - 80 290 - 365 - 435 ns VCC = 4.5 V - 29 58 - 73 - 87 ns VCC = 6.0 V - 23 49 - 62 - 74 ns CPU to TCU; see Fig. 9 CPD to TCD; see Fig. 9 PL to Qn; see Fig. 10 MR to Qn; see Fig. 11 Dn to Qn; see Fig. 10 PL to TCU, PL to TCD; see Fig. 13 MR to TCU, MR to TCD; see Fig. 13 Dn to TCU, Dn to TCD; see Fig. 13 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 12 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter Symbol Parameter Conditions 25 °C Min tTHL tTLH tW -40 °C to +85 °C Typ Max -40 °C to +125 °C Unit Min Max Min Max HIGH to LOW see Fig. 11 output VCC = 2.0 V transition time VCC = 4.5 V - 19 75 - 95 - 110 ns - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns LOW to HIGH see Fig. 11 output VCC = 2.0 V transition time VCC = 4.5 V - 19 75 - 95 - 110 ns - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 100 22 - 125 - 150 - ns VCC = 4.5 V 20 8 - 25 - 30 - ns VCC = 6.0 V 17 6 - 21 - 26 - ns VCC = 2.0 V 100 25 - 125 - 150 - ns VCC = 4.5 V 20 9 - 25 - 30 - ns VCC = 6.0 V 17 7 - 21 - 26 - ns VCC = 2.0 V 100 19 - 125 - 150 - ns VCC = 4.5 V 20 7 - 25 - 30 - ns VCC = 6.0 V 17 6 - 21 - 26 - ns VCC = 2.0 V 50 8 - 65 - 75 - ns VCC = 4.5 V 10 3 - 13 - 15 - ns VCC = 6.0 V 9 2 - 11 - 13 - ns VCC = 2.0 V 50 0 - 65 - 75 - ns VCC = 4.5 V 10 0 - 13 - 15 - ns VCC = 6.0 V 9 0 - 11 - 13 - ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 0 -14 - 0 - 0 - ns VCC = 4.5 V 0 -5 - 0 - 0 - ns VCC = 6.0 V 0 -4 - 0 0 - ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 8 6 - 17 - 20 - ns pulse width CPU, CPD; HIGH or LOW; see Fig. 8 MR HIGH; see Fig. 11 PL LOW; see Fig. 10 trec recovery time PL to CPU, CPD; see Fig. 10 MR to CPU, CPD; see Fig. 11 tsu th set-up time hold time Dn to PL; see Fig. 12; CPU = CPD = HIGH Dn to PL; see Fig. 12 CPU to CPD, CPD to CPU; see Fig. 14 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 13 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter Symbol Parameter fmax maximum frequency CPD [1] [2] power dissipation capacitance Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 4.0 13.5 - 3.2 - 2.6 - MHz VCC = 4.5 V 20 41 - 16 - 13 - MHz VCC = 6.0 V 24 49 - 19 - 15 - MHz - 24 - - - - - pF CPU, CPD; see Fig. 8 VI = GND to VCC; VCC = 5 V; [2] fi = 1 MHz tpd is the same as tPHL and tPLH. CPD is used to determine the dynamic power dissipation (PD in μW): 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL x VCC x fo) = sum of outputs. Table 9. Dynamic characteristics type 74HCT193 Symbol Parameter Conditions 25 °C Min tpd propagation delay -40 °C to +85 °C Typ Max -40 °C to +125 °C Unit Min Max Min Max CPU, CPD to Qn; see Fig. 8 [1] VCC = 4.5 V - 23 43 - 54 - 65 ns - 15 27 - 34 - 41 ns - 15 27 - 34 - 41 ns - 26 46 - 58 - 69 ns - 22 40 - 50 - 60 ns - 27 46 - 58 - 69 ns - 31 55 - 69 - 83 ns - 29 55 - 69 - 83 ns CPU to TCU; see Fig. 9 VCC = 4.5 V CPD to TCD; see Fig. 9 VCC = 4.5 V PL to Qn; see Fig. 10 VCC = 4.5 V MR to Qn; see Fig. 11 VCC = 4.5 V Dn to Qn; see Fig. 10 VCC = 4.5 V PL to TCU, PL to TCD; see Fig. 13 VCC = 4.5 V MR to TCU, MR to TCD; see Fig. 13 VCC = 4.5 V Dn to TCU, Dn to TCD; see Fig. 13 tTHL tTLH VCC = 4.5 V - 32 58 - 73 - 87 ns HIGH to LOW see Fig. 11 output VCC = 4.5 V transition time - 7 15 - 19 - 22 ns LOW to HIGH see Fig. 11 output VCC = 4.5 V transition time - 7 15 - 19 - 22 ns 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 14 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter Symbol Parameter Conditions 25 °C Min tW pulse width -40 °C to +85 °C Typ Max -40 °C to +125 °C Unit Min Max Min Max CPU, CPD; HIGH or LOW; see Fig. 8 VCC = 4.5 V 25 11 - 31 - 38 - ns 20 7 - 25 - 30 - ns 20 8 - 25 - 30 - ns 10 2 - 13 - 15 - ns 10 0 - 13 - 15 - ns 16 8 - 20 - 24 - ns 0 -6 - 0 - 0 - ns 16 7 - 20 - 24 - ns 20 43 - 16 - 13 - MHz - 26 - - - - - pF MR HIGH; see Fig. 11 VCC = 4.5 V PL LOW; see Fig. 10 VCC = 4.5 V trec recovery time PL to CPU, CPD; see Fig. 10 VCC = 4.5 V MR to CPU, CPD; see Fig. 11 VCC = 4.5 V tsu set-up time Dn to PL; see Fig. 12; CPU = CPD = HIGH VCC = 4.5 V th hold time Dn to PL; see Fig. 12 VCC = 4.5 V CPU to CPD, CPD to CPU; see Fig. 14 VCC = 4.5 V fmax CPD [1] [2] maximum frequency CPU, CPD; see Fig. 8 power dissipation capacitance VI = GND to VCC - 1.5 V; VCC = 5 V; fi = 1 MHz VCC = 4.5 V [2] tpd is the same as tPHL and tPLH. CPD is used to determine the dynamic power dissipation (PD in μW): 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL x VCC x fo) = sum of outputs. 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 15 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter 10.1. Waveforms and test circuit 1/fmax VI CPU, CPD input VM GND tW t PHL t PLH VOH VM Qn output 001aag413 VOL Measurement points are given in Table 10. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the maximum clock pulse frequency VI CPU, CPD input VM GND tPHL tPLH VOH TCU, TCD output VM VOL 001aag414 Measurement points are given in Table 10. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 9. The clock (CPU, CPD) to terminal count output (TCU, TCD) propagation delays VI Dn input VM GND VI PL input VM GND VI CPU, CPD input t rec tW VM GND t PLH t PHL VOH Qn output VM VOL 001aag415 Measurement points are given in Table 10. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 10. The parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock input (CPU, CPD) 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 16 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter VI MR input VM GND tW CPU, CPD input t rec VI VM GND t PHL VOH 90 % VM Qn output 10 % VOL t THL t TLH 001aag416 Measurement points are given in Table 10. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 11. The master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal time and output transition times VI VM Dn input GND tsu VI th tsu th VM PL input GND VOH Qn output VOL 001aag417 Measurement points are given in Table 10. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 12. The data input (Dn) to parallel load input (PL) set-up and hold times PL, MR, Dn input VI VM GND tPLH tPHL VOH TCU, TCD output VM VOL 001aag418 Measurement points are given in Table 10. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 13. The data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs (TCU, TCD) propagation delays 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 17 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter VI CPU or CPD input VM GND th VI CPD or CPU input VM GND 001aag419 Measurement points are given in Table 10. Fig. 14. The CPU to CPD or CPD to CPU hold times Table 10. Measurement points Type Input Output VM VI VM 74HC193 0.5 × VCC GND to VCC 0.5 × VCC 74HCT193 1.3 V GND to 3 V 1.3 V VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI VCC VO DUT RT RL S1 open CL 001aad983 Test data is given in Table 11. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistor S1 = Test selection switch Fig. 15. Test circuit for measuring switching times Table 11. Test data Type Input S1 position Load VI tr, tf CL RL tPHL, tPLH 74HC193 VCC 6 ns 15 pF, 50 pF 1 kΩ open 74HCT193 3V 6 ns 15 pF, 50 pF 1 kΩ open 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 18 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter 11. Application information data input D0 D1 D2 D3 D0 D1 D2 D3 up clock CPU TCU CPU TCU down clock CPD IC1 TCD CPD IC2 TCD PL asynchronous parallel load reset MR PL Q0 Q1 Q2 Q3 carry borrow MR Q0 Q1 Q2 Q3 data output 001aag420 Fig. 16. Application for cascaded up/down counter with parallel load 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 19 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 17. Package outline SOT109-1 (SO16) 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 20 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 18. Package outline SOT403-1 (TSSOP16) 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 21 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter 13. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT193 v.7 20210908 Product data sheet - 74HC_HCT193 v.6 Modifications: • • 74HC_HCT193 v.6 20210205 Modifications: • • 74HC_HCT193 v.5 20160129 Modifications: • 74HC_HCT193 v.4 20130624 Modifications: • 74HC_HCT193 v.3 20070523 Modifications: • • • 74HC_HCT193_CNV v.2 74HC_HCT193 Product data sheet Section 2 updated. Type number 74HCT193DB (SOT338-1/SSOP16) removed. Product data sheet - 74HC_HCT193 v.5 Type number 74HC193DB (SOT338-1/SSOP16) removed. Section 7: Derating values for Ptot total power dissipation updated. Product data sheet - 74HC_HCT193 v.4 Type numbers 74HC193N and 74HCT193N (SOT38-4) removed. Product data sheet - 74HC_HCT193 v.3 - 74HC_HCT193_CNV v.2 General description updated. Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Family specification included. 19970828 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 - © Nexperia B.V. 2021. All rights reserved 22 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter 15. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74HC_HCT193 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 23 / 24 74HC193; 74HCT193 Nexperia Presettable synchronous 4-bit binary up/down counter Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Functional diagram.......................................................2 5. Pinning information......................................................4 5.1. Pinning.........................................................................4 5.2. Pin description............................................................. 4 6. Functional description................................................. 5 7. Limiting values............................................................. 7 8. Recommended operating conditions..........................7 9. Static characteristics....................................................8 10. Dynamic characteristics.......................................... 12 10.1. Waveforms and test circuit...................................... 16 11. Application information............................................19 12. Package outline........................................................ 20 13. Abbreviations............................................................ 22 14. Revision history........................................................22 15. Legal information......................................................23 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 8 September 2021 74HC_HCT193 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 8 September 2021 © Nexperia B.V. 2021. All rights reserved 24 / 24