Nuvoton
ExpressCard™
Power Interface Switch
W83L351 YG/YCG
W83L351 YG/YCG
W83L351 YG/YCG
Data Sheet Revision History
VERSION
NO
PAGES
DATES
VERSION
1.
All
Apr. /07
1.0
N.A
All versions before 1.0 are preliminary
versions.
2.
28
July 5, 2007
1.1
YES
Update the ordering information and add
the taping spec.
3.
All
May 22, 2008
1.2
YES
Remove the EOL part number W83L351G
ON WEB
-I-
MAIN CONTENTS
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
Table of Contents1.
FEATURES ................................................................................................................................. 1
2.
PIN CONFIGURATION AND DESCRIPTION ............................................................................ 2
3.
APPLICATION CIRCUIT............................................................................................................. 5
4.
INTERNAL BLOCK DIAGRAM ................................................................................................... 6
5.
ABSOLUTE MAXIMUM RATINGS ............................................................................................. 7
6.
RECOMMENDED OPERATING CONDITIONS ......................................................................... 8
7.
ELECTRICAL CHARACTERISTICS........................................................................................... 9
8.
SWITCHING CHARACTERISTICS .......................................................................................... 12
9.
FUNCTIONAL TRUTH TABLES ............................................................................................... 12
10.
TYPICAL OPERATING WAVEFORMS .................................................................................... 15
11.
EXPRESSCARD TIMING DIAGRAMS ..................................................................................... 20
12.
PACKAGE DIMENSION ........................................................................................................... 24
13.
ORDERING INFORMATION .................................................................................................... 27
14.
TOP MARKING SPECIFICATION ............................................................................................ 28
1.
FEATURES ................................................................................................................................. 1
2.
PIN CONFIGURATION AND DESCRIPTION ............................................................................ 2
3.
APPLICATION CIRCUIT............................................................................................................. 5
4.
INTERNAL BLOCK DIAGRAM ................................................................................................... 6
5.
ABSOLUTE MAXIMUM RATINGS ............................................................................................. 7
6.
RECOMMENDED OPERATING CONDITIONS ......................................................................... 8
7.
ELECTRICAL CHARACTERISTICS........................................................................................... 9
8.
SWITCHING CHARACTERISTICS .......................................................................................... 12
9.
FUNCTIONAL TRUTH TABLES ............................................................................................... 12
10.
TYPICAL OPERATING WAVEFORMS .................................................................................... 15
11.
EXPRESSCARD TIMING DIAGRAMS ..................................................................................... 20
12.
PACKAGE DIMENSION ........................................................................................................... 24
13.
ORDERING INFORMATION .................................................................................................... 27
14.
TOP MARKING SPECIFICATION ............................................................................................ 28
-II-
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
1. FEATURES
•
Meets the ExpressCard™ Standard (ExpressCard|34 or ExpressCard|54)
•
Compliant with the ExpressCard™ Compliance Checklists
•
ExpressCard Compliance ID: EC100115 (W83L351YG/YCG)
•
Fully Satisfies the ExpressCard™ Implementation Guidelines
•
Supports System with WAKE Function
•
TTL-Logic Compatible Inputs
•
Short Circuit and Thermal Protection
•
0℃ to 70℃ Ambient Operating Temperature Range
•
Available in a 20-pin QFN
-1-
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
2. PIN CONFIGURATION AND DESCRIPTION
NC 16
AUXIN 17
RCLKEN 18
OC# 19
SHDN# 20
STBY#
1
15
AUXOUT
3.3VIN
2
14
NC
3.3VOUT
3
13
NC
NC
4
12
1.5VIN
NC
5
11
1.5VOUT
9
PERST#
CPUSB#
10 CPPE#
8
GND
SYSRST#
7
6
W83L351YG
W83L351YCG
(Top View)
-2-
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
SYMBOL
SYSRST#
SHDN#
STBY#
PIN
YG/YCG
6
20
1
I/O
FUNCTION
I(*)
System Reset input – active low, logic level signal. Internally pulled
up to AUXIN. This input is driven by the host system and directly
affects PERST#. Asserting SYSRST# (logic low) forces PERST# to
assert. RCLKEN is not affected by the assertion of SYSRST#.
I(*)
Shutdown input – active low, logic level signal. Internally pulled up
to AUXIN. When asserted (logic low), this input instructs the power
switch to turn off all voltage outputs and the discharge FETs are
activated.
I(*)
Standby input – active low, logic level signal. Internally pulled up to
AUXIN. When asserted (logic low) after the card is inserted, this
input places the power switch in standby mode by turning off the
3.3V and 1.5V power switches and keeping the AUX switch on. If
the signal is asserted prior to the card being present, STBY#
places the power switch in OFF Mode by turning off the AUX, 3.3V,
and 1.5V power switches.
A logic level power good (with delay). When powered up, this
output remains asserted (logic level low) until all power rails are
within the tolerance. Once all power rails are within the tolerance
and RCLKEN has been released (logic high), PERST# is deasserted (logic high) after a time delay, as shown in the parametric
table. When powered down, this output is asserted whenever any
of the power rails drops below their voltage tolerance.
The PERST# signal is an output from the host system and an input
to the ExpressCard module. This signal is only used by PCI
Express-based modules and its function is to place the
ExpressCard module in a reset state.
PERST#
8
O
During power up, power down, or whenever power to the
ExpressCard module is not stable or not within voltage tolerance
limits, the ExpressCard standard requires that PERST# be
asserted. As a result, this signal also serves as a power-good
indicator to the ExpressCard module, and the relationship between
the power rails and PERST# are explicitly defined in the
ExpressCard standard.
The host can also place the ExpressCard module in a reset state
by asserting a system reset SYSRST#. This system reset
generates a PERST# signal to the ExpressCard module without
disrupting the voltage rails. This is normally called a warm reset.
However, in a cold start situation, the system reset can also be
used to prolong the assertion time of PERST#.
CPUSB#
9
I(*)
Card Present input for USB cards. Internally pulled up to AUXIN. A
logic low level on this input indicates that the card present supports
the USB functions. When a card is inserted, CPUSB# is physically
connected to ground if the card supports USB functions.
-3-
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
Continued
SYMBOL
CPPE#
RCLKEN
PIN
YG/YCG
10
18
I/O
FUNCTION
I(*)
Card Present input for PCI Express cards. Internally pulled up to
AUXIN. A logic low level on this input indicates that the card
present supports the PCI Express functions. When a card is
inserted, CPPE# is physically connected to ground if the card
supports PCI Express functions.
Reference Clock Enable signal. As an output, it is a logic level
power good to the host (no delay – open drain). As an input, if the
signal is kept inactive (low) by the host, PERST# will be prevented
from being de-asserted. Internally pulled up to AUXIN. This pin
serves both as an input and an output. When powered up, a
discharge FET keeps this signal at a low state as long as any of the
output power rails is out of their tolerance range. Once all output
power rails are within the tolerance, the switch releases RCLKEN,
I(*)/O allowing it to transit to a high state (internally pulled up to AUXIN).
The transition of RCLKEN from a low to a high state starts an
internal timer for the purpose of de-asserting PERST#. As an input,
RCLKEN can be kept low to delay the start of the PERST# internal
timer. Because RCLKEN is internally connected to a discharge
FET, this pin can only be driven low and should never be driven
high as a logic input. When an external circuit drives this pin low,
RCLKEN becomes an input; otherwise, this pin is an output.
Over current status output (open drain). This pin is an open-drain
output. When any of the three power switches (AUX, 3.3V, and
1.5V) is in an over current condition, OC# is asserted (logic low) by
an internal discharge FET with a deglitch delay. Otherwise, the
discharge FET is open, and the pin can be pulled up to a power
supply through an external resistor.
OC#
19
OD
3.3VIN
2
I
Primary voltage source, 3.3V input for 3.3VOUT
1.5VIN
12
I
Secondary voltage source, 1.5V input for 1.5VOUT
AUXIN
17
I
Auxiliary voltage source, AUX input for AUXOUT and chip power.
3.3VOUT
3
O
Switched output that delivers 0V, 3.3V or high impedance to the
card.
1.5VOUT
11
O
Switched output that delivers 0V, 1.5V or high impedance to the
card.
AUXOUT
15
O
Switched output that delivers 0V, AUX or high impedance to the
card.
GND
7
NC
4, 5, 13, 14,
16
Notice:
(*)
Ground
No connection
Be aware that no input pins can be driven HIGH before the Auxiliary voltage is VALID.
-4-
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
3. APPLICATION CIRCUIT
AUXIN
R1
2K
AUXOUT
1.5VOUT
C9
0.1U
C10
4.7U
C11
0.1U
5
C12
22U
SY SRST#
-5-
16
NC
17
AUXIN
18
NC
3.3VOUT
W83L351YG/YCG
NC
NC
1.5VIN
NC
1.5VOUT
6
1.5VIN
3.3VIN
15
AUXOUT
14
13
12
11
1.5VIN
1.5VOUT
CPPE#
4
AUXOUT
CPUSB#
3
STBY#
10
3.3VIN
3.3VOUT
2
PERST#
C8
22U
9
C7
0.1U
GND
C6
4.7U
8
1
STBY #
C5
0.1U
RCLKEN
3.3VOUT
OC#
U1
19
RCLKEN
SHDN#
C4
22U
SYSRST#
3.3VIN
C3
0.1U
20
C2
4.7U
SHDN#
C1
0.1U
7
AUXIN
CPPE#
CPUSB#
PERST#
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
4. INTERNAL BLOCK DIAGRAM
1.5VOUT
1.5VI N
SW1
SW4
3.3VIN
3.3VOUT
SW2
SW5
AUXIN
AUXOUT
SW3
SW6
Detctor
CPUSB #
Current Limit
CPPE #
Thermal protection
Control Logic
OC #
STBY #
SHDN #
GND
POWER_GOOD_ALL
AUXIN
RCLKEN
AUXIN
PERST #
SYSRST #
-6-
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
5. ABSOLUTE MAXIMUM RATINGS
ITEM
Input Voltage
SYMBOL
RATING
UNIT
VI(3.3VIN)
-0.3 to 6
V
VI(1.5VIN)
-0.3 to 6
V
VI(AUXIN)
-0.3 to 6
V
-0.3 to 6
V
VO(3.3VOUT)
-0.3 to 6
V
VO(1.5VOUT)
-0.3 to 6
V
VO(AUXOUT)
-0.3 to 6
V
Logic Input/Output Voltage
Output Voltage
Output Current
IO(3.3OUT)
Internally limited
IO(1.5OUT)
Internally limited
IO(AUXOUT)
Internally limited
Topt
0 to 70
℃
Human Body Mode
±2
kV
Machine Mode
±200
V
Latch-Up
±100
mA
Operating Temperature Range
Electrostatic discharge protection
-7-
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
6. RECOMMENDED OPERATING CONDITIONS
ITEM
Input Voltage
MAX
UNIT
VI(3.3VIN)
3.3VIN is only required for its respective
functions
3
3.6
VI(1.5VIN)
1.5VIN is only required for its respective
functions
1.35
1.65
VI(AUXIN)
AUXIN is required for all circuit operations
3
3.6
0
1.3
A
0
650
mA
0
275
mA
IO(3.3VOUT)
Continuous output
current
MIN
IO(1.5VOUT)
TJ=120℃
IO(AUXOUT)
-8-
V
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
7. ELECTRICAL CHARACTERISTICS
TA = 25℃, VI (3.3VIN) = VI (AUXIN) = 3.3 V, VI (1.5VIN) = 1.5 V, VI (SHDN#), VI (STBY#) = 3.3 V, VI (CPPE#) = VI
(CPUSB#) = 0 V, VI (SYSRST) = 3.3 V, OC# and RCLKEN and PERST# are open, all voltage outputs
unloaded (unless otherwise noted)
PARAMETER
TEST CONDITIONS
3.3VIN to 3.3VOUT with
two switches on for dual
Power
switch
resistance
1.5VIN to 1.5VOUT with
two switches on for dual
AUXIN to AUXOUT with
two switches on for dual
IOS
Short –
circuit
output
current
Thermal
Shutdown
TA = 25°C, I = 1305 mA
each
TA = 70°C, I = 1305 mA
each
TA = 25°C, I = 660 mA each
TA = 70°C, I = 660 mA each
TA = 25°C, I = 285 mA each
TA = 70°C, I = 285 mA each
IOS(3.3VOUT) (steady-state
value)
IOS(1.5VOUT) (steady-state
value)
IOS(AUXOUT) (steady-state
value)
Output powered into a short
Trip point, TJ
Rising temperature, not in
over current condition
Over current condition
II(AUXIN)
Normal
operation
II(3.3VIN)
II(1.5VIN)
II(AUXIN)
Shutdown
mode
II(3.3VIN)
II(1.5VIN)
II(AUXIN)
Standby
mode (1)
II(3.3VIN)
II(1.5VIN)
II(AUXIN)
Standby
mode (2)
II(3.3VIN)
II(1.5VIN)
TYP
MAX
105
mΩ
90
110
110
126
1.3
5
0.6
7
1.7
2.5
A
1.1
1.3
A
400
600
mA
155
℃
130
10
Outputs are unloaded
(include CPPE# and
CPUSB# logic pull-up
currents)
140
210
10.
5
15
2.2
10
CPUSB# = CPPE# = 0 V
SHDN# = 0 V (discharge
FETs are on) (include
CPPE# and CPUSB# logic
pull-up currents and SHDN#
pull-up current)
CPUSB# = CPPE# = 0 V
STBY# = 0 V (include
CPPE# and CPUSB# logic
pull-up currents and STBY#
pull-up current)
170
270
6
10
CPUSB# = CPPE# = 0 V
3.3VIN = 0 V (include
CPPE# and CPUSB# logic
pull-up currents)
-9-
UNIT
90
275
Hysteresis
II
Total input
quiescent
current
(Note: 1)
MIN
uA
uA
2.2
10
170
270
6
10
2.2
10
160
210
0
0.1
2.2
10
uA
uA
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
Continued
PARAMETER
TEST CONDITIONS
II(AUXIN)
Standby
mode (3)
II(3.3VIN)
II(1.5VIN)
II(AUXIN)
Ilkg(FWD)
II(3.3VIN)
Forward
leakage
current
II(1.5VIN)
MIN
TYP
MAX
CPUSB# = CPPE# = 0 V
1.5VIN = 0 V (include
CPPE# and CPUSB# logic
pull-up currents)
160
210
6
10
0
0.1
SHDN# = 3.3 V, CPUSB# =
CPPE# = 3.3 V (no card
present, discharge FETs are
on);current measured at
input pins, includes RCLKEN
pull- up current
22
50
0
50
0
50
UNIT
uA
uA
LOGIC SECTION (SYSRST, SHDN#, STBY#, PERST#, RCLKEN , OC#, CPUSB#, CPPE#)
SYSRST# = 3.6 V, sinking
I(SYSRS#)
Input
SYSRST# = 0 V, sourcing
0
10
SHDN# = 3.6 V, sinking
Logic input
supply
current
I(SHDN#)
Input
I(STBY#)
Input
I(RCLKEN )
Input
SHDN# = 0 V, sourcing
I(CPPE#)
Logic input
voltage
inputs
10
17.
5
10
17.
5
30
RCLKEN = 0 V, sourcing
10
18
30
CPUSB# or CPPE# = 0 V,
sinking
CPUSB# or CPPE# = 3.6 V,
sourcing
10
17.
5
IO(RCLKEN) = 60 µA
PERST# assertion delay from output
voltage
3.3VOUT, AUXOUT,
1.5VOUT falling
PERST# de-assertion
output voltage
3.3VOUT, AUXOUT, or
1.5VOUT rising within
tolerance
from
uA
30
0.4
3.3VOUT falling
2.7
3
AUXOUT falling
2.7
3
1.5VOUT falling
1.2
1.5
-10-
uA
uA
0.8
PERST# assertion threshold of output
voltage (PERST# asserted when any
output voltage falls below the
threshold)
uA
0
2
Output
uA
0
Low level
delay
30
STBY# = 0 V, sourcing
High level
RCLKEN output low
voltage
30
0
STBY# = 3.6 V, sinking
I(CPUSB#) or
17.
5
500
1
20
V
V
V
ns
ms
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
Continued
PARAMETER
PERST#
assertion
SYSRST#
delay
TEST CONDITIONS
from
tW(PERST#) PERST# minimum pulse width
MIN
Max time from SYSRST
asserted
3.3VOUT, AUXOUT, or
1.5VOUT falling out of
tolerance or triggered by
SYSRST#
100
TYP
MAX
UNIT
25
500
ns
340
PERST# output low voltage
us
0.4
V
IO(PERST#) = 500 µA
PERST# output high voltage
2.4
OC# output low voltage
IO(OC#) = 2 mA
OC# deglitch
Falling into or out of an over
current condition
V
0.4
20
V
ms
UNDERVOLTAGE LOCKOUT (UVLO)
3.3VIN UVLO
3.3VIN level, below which
3.3VIN and 1.5VIN switches
are off
2.6
2.9
1.5VIN UVLO
1.5VIN level, below which
3.3VIN and 1.5VIN switches
are off
1.0
1.25
2.6
2.9
AUXIN UVLO
AUXIN level, below which all
switches are off
UVLO hysteresis
100
V
mV
Note 1: In the Shutdown mode or the Standby mode (1), the AUXIN quiescent current includes a normal operation current,
SHDN# or STBY# internal pull-up current and RCLKEN internal pull-up current. In the Standby modes (2) & (3), the
AUXIN quiescent current includes a normal operation current and a RCLKEN internal-up current.
-11-
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
8. SWITCHING CHARACTERISTICS
TA = 25℃, VI (3.3VIN) = VI (AUXIN) = 3.3 V, VI (1.5VIN) = 1.5 V, VI (SHDN#), VI (STBY#) = 3.3 V, VI (CPPE#) = VI
(CPUSB#) = 0 V, VI (SYSRST) = 3.3 V, OC# and RCLKEN and PERST# are open, all voltage outputs
unloaded (unless otherwise noted)
PARAMETER
tr
Output rise times
TEST CONDITIONS
0.1
6
AUXIN to AUXOUT
CL(AUXVOUT)=0.1uF, IO(AUXOUT)=0A
0.1
6
1.5VIN to 1.5VOUT
CL(1.5VOUT)=0.1uF, IO(1.5VOUT)=0A
0.1
6
3.3VIN to 3.3VOUT
CL(3.3VOUT)=100uF, RL=VI(3.3VIN)/1A
0.1
6
0.1
6
0.1
6
10
10
10
5
5
5
10
150
150
150
30
30
30
150
3.3VIN to 3.3VOUT
AUXIN to AUXOUT
CL(AUXVOUT)=0.1uF, IO(AUXOUT)=0A
10
150
1.5VIN to 1.5VOUT
CL(1.5VOUT)=0.1uF, IO(1.5VOUT)=0A
CL(3.3VOUT)=100uF, RL=VI(3.3VIN)/1A
CL(AUXVOUT)=100uF,
RL=VI(AUXININ)/0.250A
CL(1.5VOUT)=100uF,
RL=VI(1.5VIN)/0.500A
CL(3.3VOUT)=0.1uF, IO(3.3VOUT)=0A
CL(AUXVOUT)=0.1uF, IO(AUXOUT)=0A
CL(1.5VOUT)=0.1uF, IO(1.5VOUT)=0A
CL(3.3VOUT)=100uF, RL=VI(3.3VIN)/1A
CL(AUXVOUT)=100uF,
RL=VI(AUXININ)/0.250A
CL(1.5VOUT)=100uF,
RL=VI(1.5VIN)/0.500A
10
0.1
150
3
0.1
3
0.1
3
0.1
6
0.1
6
0.1
6
0.1
6
0.1
6
0.1
6
3.3VIN to 3.3VOUT
AUXIN to AUXOUT
1.5VIN to 1.5VOUT
3.3VIN to 3.3VOUT
AUXIN to AUXOUT
1.5VIN to 1.5VOUT
3.3VIN to 3.3VOUT
AUXIN to AUXOUT
3.3VIN to 3.3VOUT
AUXIN to AUXOUT
1.5VIN to 1.5VOUT
3.3VIN to 3.3VOUT
AUXIN to AUXOUT
1.5VIN to 1.5VOUT
UNIT
ms
CL(AUXVOUT)=100uF,
RL=VI(AUXININ)/0.250A
CL(1.5VOUT)=100uF,
RL=VI(1.5VIN)/0.500A
CL(3.3VOUT)=0.1uF, IO(3.3VOUT)=0A
CL(AUXVOUT)=0.1uF, IO(AUXOUT)=0A
CL(1.5VOUT)=0.1uF, IO(1.5VOUT)=0A
CL(3.3VOUT)=20uF, IO(3.3VOUT)=0A
CL(AUXVOUT)=20uF, IO(AUXOUT)=0A
CL(1.5VOUT)=20uF, IO(1.5VOUT)=0A
CL(3.3VOUT)=0.1uF, IO(3.3VOUT)=0A
1.5VIN to 1.5VOUT
Tpd(on)
Turn on
propagation
delay
MAX
CL(3.3VOUT)=0.1uF, IO(3.3VOUT)=0A
1.5VIN to 1.5VOUT
tf
Output fall times
when SHDN#
asserted (card is
present)
TYP
3.3VIN to 3.3VOUT
AUXIN to AUXOUT
tf
Output fall times
when card
removed (both
CPUSB# and
CPPE# deasserted)
MIN
us
ms
us
ms
ms
9. FUNCTIONAL TRUTH TABLES
Truth Table for Voltage Outputs
VOLTAGES INPUTS
AUXIN
3.3VIN
(1)
1.5VIN
VOLTAGE OUTPUTS(2)
LOGIC INPUTS
SHDN# STBY#
CP#
(4)
-12-
MODE(3)
AUXOUT 3.3VOUT 1.5VOUT
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
Off
X
X
X
X
X
Off
Off
Off
Off
On
Off
Off
1
1
X
Off
Off
Off
Off
On
On
On
1
0
0
Off
Off
Off
Off(5)
On
On
On
1
0
X
Off
Off
Off
Off(6)
On
X
X
0
X
X
GND
GND
GND
Shutdown
On
X
X
1
X
1
GND
GND
GND
No Card
On
On
On
1
0
0
On
Off
Off
Standby
On
On →
Off
On →
Off
1
1
0
On
Off
Off
Standby(7)
On
On
On
1
1
0
On
On
On
Card
Inserted
(1)
For input voltages, On means the respective input voltage is higher than its turn on threshold voltage; otherwise, the
voltage is Off (for AUX input, Off means the voltage is close to zero volt).
(2)
For output voltages, On means the respective power switch is turned on so the input voltage is connected to the output;
Off means the power switch and its output discharge FET are both off; Gnd means the power switch is off but the output
discharge FET is on so the voltage on the output is pulled down to 0 V.
(3)
Mode assigns each set of input conditions and respective output voltage results to a different name. These modes are
referred to as input conditions in the following Truth Table for Logic Outputs.
(4)
CP# = CPUSB# and CPPE# equal to 1 when both CPUSB# and CPPE# signals are logic high, or equal to 0 when either
CPUSB# or CPPE# is low.
(5)
STBY# is asserted (logic low) prior to the card being present.
(6)
STBY# is asserted (logic low) prior to the voltage inputs being present.
(7)
The card is inserted prior to the removal of the Primary or Secondary power (either 3.3VIN or 1.5VIN or both) at the input
of the ExpressCard power switch, then only the primary and secondary power (both 3.3VOUT and 1.5VOUT) are
removed and the auxiliary power is sent to the ExpressCard slot.
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
Truth Table for Logic Outputs
INPUT CONDITIONS
MODE
SYSRST#
LOGIC OUTPUTS
RCLKEN
(1)
PERST#
RCLKEN (2)
Off
Shutdown
No Card
X
X
0
0
0
Hi - Z
0
1
0
0
0
0
1
Hi - Z
1
1
1
0
0
0
Standby
Card Inserted
(1)
RCLKEN as a logic input in this column. RCLKEN is an I/O pin and it can be driven low externally, left open, or
connected to high-impedance terminals, such as the gate of a MOSFET. It must not be driven high externally.
(2)
RCLKEN as a logic output in this column.
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
10. TYPICAL OPERATING WAVEFORMS
CH1 CPPE#
CH2 3.3VOUT
CH3 1.5VOUT
CH4 AUXOUT
Fig.1 Output Voltage When Card Is Inserted
CH1 3.3VOUT
CH2 RCLKEN
CH3 PERST#
Fig.2 RCLKEN and PERST# Voltage During Power Up
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
CH1 AUXOUT
CH2 RCLKEN
CH3 PERST#
Fig.3 RCLKEN and PERST# Voltage During Power Down
CH1 SYSRST#
CH2 PERST#
Fig.4 PERST# Asserted by SYSRST# When Power Is On
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
CH1 SYSRST#
CH2 PERST#
Fig.5 PERST# De-Asserted by SYSRST# When Power Is On
CH1 3.3VIN
CH2 3.3VOUT
CH3 1.5VOUT
CH4 AUXOUT
Fig.6 Output Voltage When 3.3VIN Is Removed
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
CH1 1.5VIN
CH2 3.3VOUT
CH3 1.5VOUT
CH4 AUXOUT
Fig.7 Output Voltage When 1.5VIN Is Removed
CH1 OC#
CH2 AUXOUT
Fig.8 OC# Response When AUXOUT Power Into A Short
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
CH1 OC#
CH2 3.3VOUT
Fig.9 OC# Response When 3.3VOUT Power Into A Short
CH1 OC#
CH2 1.5VOUT
Fig.10 OC# Response When 1.5VOUT Power Into A Short
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
11. EXPRESSCARD TIMING DIAGRAMS
Tpd Min Max Units
a
System
dependent
b
100
us
c
10
ms
d
100
e
1
us
20
ms
Fig.11 Card Present Before Host Power (Note.1)
Tpd Min Max Units
a
100
us
b
10
ms
20
ms
c
1
Fig.12 Host Power Is On Prior To Card Insertion (Note.2)
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
Fig.13 Host System In Standby Prior to Card Insertion
Tpd Min
Max Units
a
System
dependent
b
Load
dependent
c
500
ns
d
500
ns
Fig.14 Host Controlled Power Down (Note.3)
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
Tpd Min Max Units
a
System
dependent
b
System
dependent
c
Load
dependent
d
500
ns
e
500
ns
Fig.15 Controlled Power Down When SHDN# Asserted (Note.4)
Tpd Min Max Units
a
Load
dependent
b
500
ns
c
500
ns
Fig.16 Surprise Card Removal
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
Note.1: According to the electrical specifications of ExpressCard Standard, the minimum propagation
delay time of e (Power stable to PERST# inactive) is 1ms.
Note.2: RCLKEN could be treated as a power good signal when card power is over 86% of nominal
voltage.
Note.3: The propagation delay time of c is SYSRST# assertion to PERST# assertion. The propagation
delay time of d is card power is under 86% of nominal voltage to RCLKEN de-assertion.
Note 4: RCLEKN de-assertion is prior to PERST# assertion when card power lost in any situation.
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
12. PACKAGE DIMENSION
W83L351YG - QFN20, Thermal Pad Dimension: 2.0mm X 2.0mm
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
W83L351YCG - QFN20, Thermal Pad Dimension: 2.7mm X 2.7mm
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
¾ Taping Specification
20 Pin QFN Package
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
13. ORDERING INFORMATION
PART
NUMBER
W83L351YG
W83L351YCG
PACKAGE TYPE
SUPPLIED AS
PRODUCTION FLOW
20PIN QFN (Pb-free package)
E Shape: 490 units/Tray
Thermal Pad Size: 2.0X2.0 ㎜²
T Shape: 4,000
units/T&R
20PIN QFN (Pb-free package)
E Shape: 490 units/Tray
Thermal Pad Size: 2.7X2.7 ㎜²
T Shape: 4,000
units/T&R
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Commercial, 0℃ to +70℃
Commercial, 0℃ to +70℃
Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
14. TOP MARKING SPECIFICATION
Winbond
351YG
636XARB
Winbond
351YCG
636XARB
1st line: Winbond – company name
2nd line: 351YG/351YCG – the part number
3rd line: Tracking code 636 X ARB
636: Packages assembled in Year 06’, week 36
X: Assembly house ID
ARB: The IC version
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Publication Date: May 22, 2008
Revision 1.2
W83L351 YG/YCG
Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Nuvoton products are not intended for applications wherein failure
of Nuvoton products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper
use or sales.
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Publication Date: May 22, 2008
Revision 1.2
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