2019
Motorcomm
YT8512C YT8512H
Datasheet
FAST ETHERNET TRANSCEIVER
V1.11
DATE 2020/04/24
苏州裕太车通 | Motorcomm
Motorcomm YT8512C YT8512H Datasheet
Revision History
Revision
Release Date
Summary
1.0
2019/07/11
Add POS, WOL description
Update Register table
1.01
2019/09/04
Update Electrical Characteristics
1.02
2019/09/11
Modify RBIAS resistor to 2.49k ohm
1.03
2019/10/16
Modify errors
1.04
2019/11/05
Update Register
1.05
2019/11/12
Update Block diagram
1.06
2020/01/13
Add EPAD description
1.07
2020/03/16
Modify package information, ordering information
Add thermal resistance
1.08
2020/03/23
Add Copyright Statement and Disclaimer
Add Reg ext 0x200a
Modify Rbias pin description
1.09
2020/03/26
Add Packaging Type
Release
1.10
2020/04/22
Modify Thermal resistance description
Pin 30,31,32 pin Description
1.11
2020/04/24
Update Register
Modify RMII description
1
Motorcomm YT8512C YT8512H Datasheet
版权声明
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reserved. No company or individual may copy, disseminate, disclose or otherwise distribute any part of this document
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This document only provides periodic information, and its contents will/may be updated from time to time according
to actual situation of Motorcomm’s products without further notice. Motorcomm will not take any responsibility for
any direct or indirect losses caused due to improper use of this document.
2
Motorcomm YT8512C YT8512H Datasheet
CONTENT
1.
General Description ......................................................................................................................... 8
Target Application ........................................................................................................................... 8
Block Diagram................................................................................................................................. 9
2.
Feature ........................................................................................................................................... 10
3.
Pin Assigment ................................................................................................................................ 11
YT8512C YT8512H QFN32 5x5mm ............................................................................................ 11
Pin Descriptions............................................................................................................................. 12
Power on strapping ........................................................................................................................ 16
Mode config........................................................................................................................... 17
PHY address .......................................................................................................................... 17
Wake on LAN selection......................................................................................................... 18
3
Function Description ..................................................................................................................... 19
Application Diagram ..................................................................................................................... 19
100Base-Tx/10Base-Te application ....................................................................................... 19
MII interface .................................................................................................................................. 19
RMII interface ............................................................................................................................... 20
Management interface ................................................................................................................... 20
DAC............................................................................................................................................... 20
ADC............................................................................................................................................... 20
Adaptive equalizer ......................................................................................................................... 21
Auto- negotiation ........................................................................................................................... 21
Polarity detection and auto correction ........................................................................................... 21
EEE................................................................................................................................................ 21
4
Operational Description ................................................................................................................. 22
Reset .............................................................................................................................................. 22
PHY Address ................................................................................................................................. 22
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Motorcomm YT8512C YT8512H Datasheet
XMII interface ............................................................................................................................... 23
MII ......................................................................................................................................... 23
RMII ...................................................................................................................................... 23
REMII interface ..................................................................................................................... 24
Loopback mode ............................................................................................................................. 25
Internal loopback: .................................................................................................................. 25
External loopback .................................................................................................................. 25
Remote loopback ................................................................................................................... 25
WoL Wake on lan .......................................................................................................................... 27
WOL ...................................................................................................................................... 27
WOL mechanism ................................................................................................................... 27
WOL Interrupt ....................................................................................................................... 28
5
Register Overview ......................................................................................................................... 29
MII Management Interface Clause 22 Register Programming ...................................................... 29
MII Registers ................................................................................................................................. 30
Mii register 00h: Basic control register ................................................................................. 30
Mii register 01h: Basic status register .................................................................................... 31
Mii register 02h: PHY identification register1 ...................................................................... 33
Mii register 03h: PHY identification register2 ...................................................................... 33
MII register 04h: Auto-Negotiation advertisement ................................................................ 33
MII register 05h: Auto-Negotiation link partner ability ........................................................ 36
MII register 06h: Auto-Negotiation expansion register ......................................................... 38
MII register 07h: Auto-Negotiation Next Page register......................................................... 39
MII register 08h: Auto-Negotiation link partner Received Next Page register ..................... 39
MII register 0Ah: MASTER-SLAVE status register ............................................................. 40
MII register 0Dh: MMD access control register .................................................................... 41
MII register 0Eh: MMD access data register ......................................................................... 42
Mii register 0Fh: Extended status register ............................................................................. 42
MII register 10h: PHY specific function control register ...................................................... 42
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Motorcomm YT8512C YT8512H Datasheet
MII register 11h: PHY specific status register ....................................................................... 43
MII register 12h: Interrupt Mask Register ............................................................................. 45
MII register 13h: Interrupt Status Register ............................................................................ 46
MII register 14h: Speed Auto Downgrade Control Register ................................................. 47
MII register 15h: Rx Error Counter Register ......................................................................... 48
MII register 1Eh: Debug Register’s Address Offset Register ................................................ 48
MII register 1Fh: Debug Register’s Data Register ................................................................ 48
Extended register ........................................................................................................................... 49
EXT 200Ah: 10BT Power control, Register .......................................................................... 49
EXT 4000h: extended combo control1 .................................................................................. 49
EXT 4001h: extended pad control ......................................................................................... 50
EXT 4003h: extended combo control2 .................................................................................. 50
EXT 4004h: WOL MAC Address ......................................................................................... 51
EXT 4005h: WOL MAC Address ......................................................................................... 51
EXT 4006h: WOL MAC Address ......................................................................................... 51
EXT 40A0h: pkg_selftest control .......................................................................................... 52
EXT 40A1h: pkg_selftest control .......................................................................................... 53
EXT 40A2h: pkg_selftest control .......................................................................................... 53
EXT 40A3h: pkg_selftest status ............................................................................................ 53
EXT 40A4h: pkg_selftest status ............................................................................................ 53
EXT 40A5h: pkg_selftest status ............................................................................................ 54
EXT 40A6h: pkg_selftest status ............................................................................................ 54
EXT 40A7h: pkg_selftest status ............................................................................................ 54
EXT 40A8h: pkg_selftest status ............................................................................................ 54
EXT 40A9h: pkg_selftest status ............................................................................................ 54
EXT 40Aah: pkg_selftest status ............................................................................................ 55
EXT 40Abh: pkg_selftest status ............................................................................................ 55
EXT 40Ach: pkg_selftest status ............................................................................................ 55
EXT 40Adh: pkg_selftest status ............................................................................................ 55
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Motorcomm YT8512C YT8512H Datasheet
EXT 40Aeh: pkg_selftest status ............................................................................................ 55
EXT 40Afh: pkg_selftest status ............................................................................................. 56
EXT 40B0h: pkg_selftest status ............................................................................................ 56
EXT 40B1h: pkg_selftest status ............................................................................................ 56
EXT 40B2h: pkg_selftest status ............................................................................................ 56
EXT 40B3h: pkg_selftest status ............................................................................................ 56
EXT 40B4h: pkg_selftest status ............................................................................................ 56
EXT 40B5h: pkg_selftest status ............................................................................................ 57
EXT 40B6h: pkg_selftest status ............................................................................................ 57
EXT 40B7h: pkg_selftest control .......................................................................................... 57
EXT 40B8h: pkg_selftest control .......................................................................................... 57
EXT 40B9h: pkg_selftest control .......................................................................................... 57
EXT 40BAh: pkg_selftest control ......................................................................................... 58
EXT 40C0h: LED0 control .................................................................................................... 58
EXT 40C1h: LED0/1 control................................................................................................. 61
EXT 40C2h: LED0/1 control................................................................................................. 62
EXT 40C3h: LED1 control .................................................................................................... 63
6
Timing and electrical characteristics ............................................................................................. 66
Absolute Maximum Ratings .......................................................................................................... 66
Recommended Operating Condition ............................................................................................. 66
Crystal Requirement ...................................................................................................................... 66
Oscillator/External Clock Requirement ......................................................................................... 67
DC Characteristics ......................................................................................................................... 67
MDC/MDIO Timing...................................................................................................................... 68
Power On Sequence/Clock/Reset .................................................................................................. 68
MII Transmission Cycle Timing ................................................................................................... 69
MII Reception Cycle Timing ......................................................................................................... 70
RMII Transmission and Reception Cycle Timing ......................................................................... 71
7
Power Requirements ...................................................................................................................... 72
6
Motorcomm YT8512C YT8512H Datasheet
Power consumption ....................................................................................................................... 72
MII mode ............................................................................................................................... 72
RMII mode ............................................................................................................................ 72
Maximum Power Consumption MII MODE ................................................................................. 72
8
Package information ...................................................................................................................... 73
RoHS-Compliant Packaging.......................................................................................................... 73
Thermal resistance ......................................................................................................................... 73
9
Mechanical Information ................................................................................................................ 74
10
Ordering Information ..................................................................................................................... 76
7
Motorcomm YT8512C YT8512H Datasheet
1.
GENERAL DESCRIPTION
The YT8512C YT8512H is a low power single-port 10/100 Mbps Ethernet PHY. It provides all
physical layer functions needed to transmit and receive data over both standard twisted pair cables
transceiver. Additionally, the YT8512C YT8512H provides flexibility to connect to a MAC through a
standard MII and RMII interface.
The YT8512C YT8512H uses mixed-signal processing to perform equalization, data recovery, and
error correction to achieve robust operation over CAT5 twisted-pair cable.
The YT8512C YT8512H offers integrated built-in self-test and loopback capabilities for ease of use.
The YT8512C YT8512H offers innovative and robust approach for reducing power consumption
through EEE, WoL and other programmable energy savings modes.
TARGET APPLICATION
⚫
General Embedded Applications
⚫
Video Surveillance
⚫
Industrial Controls
⚫
Factory Automation
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Motorcomm YT8512C YT8512H Datasheet
BLOCK DIAGRAM
9
Motorcomm YT8512C YT8512H Datasheet
2.
FEATURE
⚫
EEE 802.3az, EEE
⚫
100Base-TX
⚫
10Base-Te
⚫
MII mode
⚫
RMII mode
⚫
Full/Half duplex
⚫
Auto-negotiation
⚫
Power down mode
⚫
Base Line Wander (BLW) compensation
⚫
Auto MDIX
⚫
Interrupt function
⚫
WOL, Wake on Lan
⚫
Automatic Polarity correction
⚫
2 sets LED indicator
⚫
25 MHz crystal or OSC
⚫
Provide 50Mhz clock source for MAC
⚫
Single Power supply, internal LDO
⚫
Package QFN 32, 5x 5mm
10
Motorcomm YT8512C YT8512H Datasheet
3.
PIN ASSIGMENT
YT8512C YT8512H QFN32 5X5MM
11
Motorcomm YT8512C YT8512H Datasheet
PIN DESCRIPTIONS
⚫
I = Input
⚫
O = Output
⚫
I/O = Bidirectional
⚫
OD = Open-drain output
⚫
PU = Internal pull-up
⚫
PD = Internal pull-down
⚫
HZ= High Impendence during power on reset
⚫
PWR= Power related
⚫
XT= Crystal related
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Motorcomm YT8512C YT8512H Datasheet
No.
Name
Type
Description
1
RBIAS
I
Bias Resistor.
An external 2.49 kΩ±1% resistor must be connected
between the RBIAS pin and GND
2
AVDDL_REG
PWR/O
Power Output.
Be sure to connect a 1uF +0.1uF ceramic capacitor for
decoupling purposes.
3
TRXP0
IO
Transmit/Receive Pairs for channel 0. Differential data
from copper media is transmitted and received on the
single TRD± signal pair. There are 50Ω internal
4
TRXN0
IO
terminations on each pin. Since this device incorporates
voltage driven DAC, it does not require a center-tap
power supply.
5
TRXP1
IO
Transmit/Receive Pairs for channel 1. Differential data
from copper media is transmitted and received on the
single TRD± signal pair. There are 50Ω internal
terminations on each pin. Since this device incorporates
6
TRXN1
IO
voltage driven DAC, it does not require a center-tap
power supply.
7
AVDD33
PWR
3.3V Analog Power Input.
3.3V power supply for analog circuit; should be well
decoupled.
8
RX_DV
O/PD
Receive Data Valid.
This pin’s signal is asserted high when received data is
present on the RXD[3:0] lines. The signal is de-asserted
at the end of the packet. The signal is valid on the rising
edge of the RXC.
This pin should be pulled low when operating in MII
mode.
Power On Strapping for MII/RMII selection.
0: MII mode
1: RMII mode
An internal weakly pulled low resistor sets this to the
default of MII mode. It is possible to use an external
4.7KΩ pulled high resistor to enable RMII mode.
After power on, the pin operates as the Receive Data
Valid pin.
9
RXD[0]
O/PD
Receive Data [0]
10
RXD[1]
O/PD
Receive Data [1]
An internal weakly pulled low resistor sets RXD[1] to the
LED function (default). Use an external 4.7KΩ pulled
high resistor to enable the WOL function.
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Motorcomm YT8512C YT8512H Datasheet
11
RXD[2]/INT_N
O/OD/
Receive Data [2]
PD
When in RMII mode, this pin is used for the interrupt
function.
12
RXD[3]/CLK_CTL
O/PD
Receive Data [3]
RXD[3]/CLK_CTL pin is the Power On Strapping in
RMII Mode.
1: REF_CLK input mode, RMII1 mode
0: REF_CLK output mode, RMII2 mode
Note: An internal weakly pulled low resistor sets
RXD[3]/CLK_CTL to REF_CLK output mode (default).
13
RXC
O/PD
Receive Clock.
This pin provides a continuous clock reference for
RX_DV and RXD [0:3] signals. RXC is 25MHz in
100Mbps mode and 2.5MHz in 10Mbps mode.
14
DVDD33
PWR
3.3V Digital Power Input.
3.3V power supply for digital circuit.
15
TXC
IO/PD
MII Mode
Transmit Clock.
This pin provides a continuous clock as a timing
reference for TXD [3:0] and TXEN signals.
TXC is 25MHz in 100Mbps mode and 2.5MHz in
10Mbps mode
RMII Mode
Synchronous 50MHz Clock Reference for Receive,
Transmit, and Control Interface.
The default direction is reference clock output mode if
RXD[3]/CLK_CTL pin floating.
16
TXD[0]
I/PD
Transmit Data [0]
17
TXD[1]
I/PD
Transmit Data [1]
18
TXD[2]
I/PD
Transmit Data [2]
19
TXD[3]
I/PD
Transmit Data [3]
20
TX_EN
I/PD
MII/RMII Mode
Transmit Enable.
The input signal indicates the presence of valid nibble
data on TXD [3:0]. An internal weakly pulled low
resistor prevents the bus floating.
21
RESET_N
I,HZ
RESET. Active-low, reset pin for chip.
22
MDC
I/PU
Management Data Clock. This pin provides a clock
synchronous to MDIO, which may be asynchronous to
the transmit TXC and receive RXC clocks. The clock
rate can be up to 12.5MHz.
Use an internal weakly pulled high resistor to prevent the
bus floating.
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Motorcomm YT8512C YT8512H Datasheet
23
MDIO
IO/PU
Management Data Input/Output.
This pin provides the bi-directional signal used to
transfer management information
24
25
LED0/
O/OD/
LED 0, Link 10Mpbs On, Active blink.
PHYAD[0]
PD
PHY address 0 selection
LED1/
O/PD
LED 1, Link 100Mpbs On, Active blink.
PHYAD[1]
26
CRS/CRS_DV
PHY address 1 selection
O/PD
MI mode:
Carrier Sense.
This pin’s signal is asserted high if the media is not in
Idle state.
RMII mode:
Carrier Sense/Receive Data Valid. CRS_DV shall be
asserted by the PHY when the receive medium is nonidle.
27
COL
O/PD
Collision Detect.
COL is asserted high when a collision is detected
on the media.
28
RXER
O/PD
Receive Error.
29
DVDDL_REG
PWR/O
DVDDL Power Output.
Be sure to connect a 1uF +0.1uF ceramic capacitor for
decoupling purposes.
30
NC
NC
Connect to AVDD33 is not obstructed
31
XTAL_IN
XT
25 MHz Crystal Input Pin.
If use external oscillator or clock from another device.
1.
When an external 25Hhz oscillator or clock from
another device drivers XTAL_OUT. XTAL_IN must
be shorted to GND
2.
When an external 25Hhz oscillator or clock from
another device drivers XTAL_IN; keep the
XTAL_OUT floating.
32
XTAL_OUT
XT
25 MHz Crystal Output Pin.
If use external oscillator or clock from another device.
1.
When an external 25Hhz oscillator or clock from
another device drivers XTAL_OUT. XTAL_IN must
be shorted to GND
2.
When an external 25Hhz oscillator or clock from
another device drivers XTAL_IN; keep the
XTAL_OUT floating.
EPAD
EPAD
GND
Exposed ground pad on back of the chip, tie to ground
15
Motorcomm YT8512C YT8512H Datasheet
POWER ON STRAPPING
No.
Name
POS
Internal
Description
Pull/Down
24
LED0/
phy_address[0]
Pull Down
The power-on strapping value of
PAD RXD1, wol_led_sel,
PHYAD[0]
determines the PAD LED0
working as LED0 or PMEB.
Wol_led_sel=0, this PAD works
as LED0, it could be external PU
or PD,
Wol_led_sel=1, this PAD works
as PMEB, it shall be external pullup, then phy_address[0] always
=1;
25
LED1/
phy_address[1]
Pull Down
PHYAD[1]
10
RXD[1]
The PHY address is 00000~00011
config by phy_address[1:0]
Wol_led_sel
Pull Down
The power-on strapping value of
PAD RXD1, Wol_led_sel,
(Wake on LAN
determines the PAD LED0
selection)
working as LED0 or PMEB.
1, LED0 works as PMEB (WOL
interrupt)
0, LED0 works as LED0.
12
RXD[3]/CLK_CTL
Clock control
Pull Down
8
RX_DV
MII mode
Pull Down
The power-on strapping value of
{RX_DV, RXD3} determines the
xMII mode:
selection
{RX_DV, RXD3}=2’b00 means
MII mode;
{RX_DV, RXD3}=2’b01 means
ReMII mode;
16
Motorcomm YT8512C YT8512H Datasheet
{RX_DV, RXD3}=2’b10 means
RMII2 mode; TXC 50Mhz
reference clock is output
{RX_DV, RXD3}=2’b11 means
RMII1 mode; TXC 50Mhz
reference clock is input
MODE CONFIG
Pin 8
Pin 12
Mode
RX_DV (PD)
RXD3 (PD)
0
0
MII
0
1
ReMII,
Reverse MII Mode
1
0
RMII2,
TXC 50Mhz reference clock is output by default
1
1
RMII1,
TXC 50Mhz reference clock is input
PHY ADDRESS
Pin 24
Pin 25
PHY address
LED0/ PHYAD[0] (PD)
LED1/ PHYAD[1] (PD)
0
0
00000
0
1
00010
1
0
00001
1
1
00011
17
Motorcomm YT8512C YT8512H Datasheet
WAKE ON LAN SELECTION
Pin 10
Function
Mote
0
LED Mode
Pin 24 is LED0
1
WOL Mode
Pin 24 is PMEB,
RXD1 (PD)
Must external pull up
18
Motorcomm YT8512C YT8512H Datasheet
3
FUNCTION DESCRIPTION
APPLICATION DIAGRAM
100BASE-TX/10BASE-TE APPLICATION
100Base-Tx
SWITCH/MAC
MII/RMII/RGMII
YT8512
RXD[3:0]
TXD[3:0]
10Base-Te
CMC and
Capacitive
Coupling
MII INTERFACE
The Media Independent Interface (MII) is the digital data interface between the MAC and the physical
layer that can be enabled when the device is functioning in 10BASE-Te, 100BASE-TX,. The original
MII transmit signals include TX_EN, TXC, TXD[3:0], and TX_ER. The receive signals include
RX_DV, RXC, RXD[3:0], and RX_ER. The media status signals include CRS and COL. Due to pincount limitations, the YT8512 supports a subset of MII signals. This subset includes all MII signals
except TX_ER.
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Motorcomm YT8512C YT8512H Datasheet
RMII INTERFACE
Reduced media-independent interface (RMII) is a standard which was developed to reduce the number
of signals required to connect a PHY to a MAC. If this interface is active, the number of data signal
pins required to and from the MAC is reduced to half by doubling clock frequency.
MANAGEMENT INTERFACE
The Status and Control registers of the device are accessible through the MDIO and MDC serial
interface. The functional and electrical properties of this management interface comply with IEEE
802.3, Section 22 and also support MDC clock rates up to 12.5 MHz
DAC
The digital-to-analog converter (DAC) transmits MLT3, and Manchester coded
symbols. The
transmit DAC performs signal wave shaping that reduces electromagnetic interference (EMI). The
transmit DAC uses voltage driven output with internal terminations and hence does not require external
components or magnetic supply for operation.
ADC
Receive channel has its own analog-to-digital converter (ADC) that samples the incoming data on the
receive channel and feeds the output to the digital data path.
20
Motorcomm YT8512C YT8512H Datasheet
ADAPTIVE EQUALIZER
The digital adaptive equalizer removes inter-symbol interference (ISI) created by the channel. The
equalizer accepts sampled data from the analog-to-digital converter (ADC) on channel and produces
equalized data. The coefficients of the equalizer are adaptive to accommodate varying conditions of
cable quality and cable length.
AUTO- NEGOTIATION
The YT8512 negotiates its operation mode using the auto negotiation mechanism according to IEEE
802.3 clause 28 over the copper media. Auto negotiation supports choosing the mode of operation
automatically by comparing its own abilities and received abilities from link partner. The advertised
abilities include:
a)
Speed: 10/100Mbps
b)
Duplex mode: full duplex and/or half duplex
c)
Pause
Auto negotiation is initialized when the following scenarios happen:
a)
Power-up/Hardware/Software reset
b)
Auto negotiation restart
c)
Transition from power-down to power up
d)
Link down
Auto negotiation is enabled for YT8512 by default, and can be disable by software control.
POLARITY DETECTION AND AUTO CORRECTION
YT8512 can detect and correct two types of cable errors: swapping of pairs within the UTP cable and
swapping of wires within a pair.
For 10BASE-Te/100BASE-TX, YT8512 can handle both cable errors at the same time.
EEE
EEE is IEEE 802.3az, an extension of the IEEE 802.3 standard. EEE defines support for the PHY to
operate in Low Power Idle (LPI) mode which, when enabled, supports QUIET times during low link
utilization allowing both link partners to disable portions of each PHY's circuitry and save power.
21
Motorcomm YT8512C YT8512H Datasheet
4
OPERATIONAL DESCRIPTION
RESET
YT8512 have a hardware reset pin(RESET_N) which is low active. RESET_N should be active for at
least 10ms to make sure all internal logic is reset to a known state. Hardware reset should be applied
after power up.
RESET_N is also used as enable for power on strapping. After RESET_N is released , YT8512 latches
input value on POS related pins are used as configuration information which provides flexibility in
application without mdio access.
YT8512 also provides a software reset control registers which are used to reset all internal logic except
some mdio configuration registers. For detailed information about what register will be reset by
software reset, please refer to register table.
PHY ADDRESS
For YT8512, phy_address[1:0] is used to generate phy address.
Please refer to the POS setting as below. PHY address
Pin 24
Pin 25
PHY address
LED0/ PHYAD[0] (PD)
LED1/ PHYAD[1] (PD)
0
0
00000
0
1
00010
1
0
00001
1
1
00011
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Motorcomm YT8512C YT8512H Datasheet
XMII INTERFACE
YT8512 support 4 kinds of MII related interfaces: MII, RMII1, RMII2 and REMII.
MII
The Media Independent Interface (MII) is the digital data interface between the MAC and the
physical layer that can be enabled when the device is functioning in 10BASE-Te, 100BASE-TX, The
original MII transmit signals include TX_EN, TXC, TXD[3:0], and TX_ER. The receive signals
include RX_DV, RXC, RXD[3:0], and RX_ER. The media status signals include CRS and COL. Due
to pin-count limitations, the YT8512 supports a subset of MII signals. This subset includes all MII
signals except TX_ER. For 100M application, TXC and RXC are 25MHz; for 10M application, TXC
and RXC are 2.5MHz. TXC and RXC are output in this case.
RXC
RXDV
YT8512
MII mode
13
8
XTAL_IN
XTAL_OUT
9,10,11,12
RXD[0,3]
:4
28
RXER
15
TXC
20
TXEN
16,17,18,19
TXD[0,3]
COL
CRS/CRS_DV
27
26
RXC
RXDV
RXD[0,3]
RXER
TXC
MAC
TXEN
:4
TXD[0,3]
TXER
COL
CRS
25M
Figure . connection diagram of MII
RMII
Reduced media-independent interface (RMII) is a standard which was developed to reduce the
number of signals required to connect a PHY to a MAC. If this interface is active, the number of data
signal pins required to and from the MAC is reduced to half by doubling clock speed compared to MII.
It has 7 signals: REF_CLK, TX_EN, TXD[1:0], RX_DV and RXD[1:0]. In YT8512, we use TXC as
REF_CLK. For 100M application, REF_CLK is 50MHz; for 10M application, REF_CLK is still
50MHz, data will be duplicated for 10 times in 20ns cycles. YT8512 supports two types of connection
method;
1. RMII1 mode: This is fully conforming to RMII standard.
2. RMII2 mode: TXC will be 50MHz output to MAC.
23
Motorcomm YT8512C YT8512H Datasheet
YT8512
RMII1 mode
XTAL_IN
XTAL_OUT
9,10
RXD[0,1]
RXER 28
15
TXC
20
TXEN
16,17
TXD[0,1]
CRS/CRS_DV
RXD[0,1]
RXER
TXC
:2
MAC
TXEN
:2
26
TXD[0,1]
CRS_DV or CRS_RXDV
25M
Figure .connection diagram of RMII1(with 25MHz and 50MHz clock)
YT8512
RMII2 mode
XTAL_IN
XTAL_OUT
9,10
RXD[0,1]
RXER 28
15
TXC
20
TXEN
16,17
TXD[0,1]
CRS/CRS_DV
26
RXD[0,1]
RXER
TXC
:2
MAC
TXEN
:2
TXD[0,1]
CRS_DV or CRS_RXDV
25M
Figure .connection diagram of RMII2
REMII INTERFACE
Reverse media independent interface is the opposite of MII interface. The only difference is the
direction of tx clock and rx clock. For MII, tx clock and rx clock are output; for REMII, tx clock and rx
clock are input. REMII interface are used for back to back connection of two phys.
TXC
RXC
RXDV
RXD[0,3]
TXC
TXEN
TXEN
TXD[0,3]
RXC
RXDV
YT8512
RXD[0,3]
MII mode
YT8512
REMII
mode
XTAL_IN
XTAL_OUT
TXD[0,3]
RXER
COL
CRS/CRS_DV
No used
RXER
COL
CRS/CRS_DV
25M
25M
Figure .connection diagram of REMII
24
Motorcomm YT8512C YT8512H Datasheet
LOOPBACK MODE
There are three loopback modes in YT8512.
INTERNAL LOOPBACK:
In Internal loopback mode, YT8512 feed transmit data to receive path in chip.
Configure bit 14 of mii register(address 0h0) to enable internal loopback mode. For 10Base-Te and
100Base-Tx, YT8512 feeds digital DAC data to ADC directly.
Figure . Internal loopback
EXTERNAL LOOPBACK
In external loopback mode, YT8512 feed transmit data to receive path out of chip. For 10Base-Te and
100Base-Tx, just connect TRX_P0/N0 to TRX_P1/N1.
Figure . external loopback
REMOTE LOOPBACK
In remote loopback mode, YT8512 feed MII receive data to transmit path in chip. Configure bit 11 of
extended register(address 0h4000) and for TRX interface, just connect to link partner normally.
25
Motorcomm YT8512C YT8512H Datasheet
Figure . remote loopback
26
Motorcomm YT8512C YT8512H Datasheet
WOL WAKE ON LAN
WOL
Wake-on-LAN (WOL) is a mechanism to manage and regulate the total network power consumption.
WOL MECHANISM
YT8512 supports automatic detection of a specific frame and notification via dedicated hardware
interrupt pin or general PHY interrupt pin. The specific frame contains a specific data sequence located
anywhere inside the packet. The data sequence consists of 6 bytes of consecutive 1
(0xFFFFFFFFFFFF), followed by 16 repetitions of the MAC address of the computer to be waked up.
The 48-bit MAC address is written in EXT 0x4004, 0x4005, 0x4006 registers.
For example, to write a specific MAC address (0xAAAABBBBCCCC) to PHY, write EXT 0x4004 =
0xAAAA, 0x4005 = 0xBBBB, and 0x4006 = 0xCCCC. The PHY internal MAC address can be set to
any value.
NOTE:
The MAC address is not a real MAC address and is only a symbol to indicate the content of
the frame.
The WOL mechanism is enabled via EXT 0x4000 bit2. POS RXD[1] can’t control enable or disable
the WOL mechanism but only control pad LED0 working as WOL interrupt.
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Motorcomm YT8512C YT8512H Datasheet
WOL INTERRUPT
YT8512 support dedicated WOL interrupt pin. When the pad RXD[1] is externally PULL UP, pad
LED0 will work as WOL interrupt.
If EXT 0x4003 bit7 is 0, the dedicated WOL interrupt is programmed to a level, otherwise, it’s
programed to a pulse; either is active low. When it’s programmed to a pulse, the pulse width can be
programmed via EXT 0x4003 bit9:8.
WOL interrupt is also wire-and to general PHY interrupt RXD[2]_INTN when the bit6 INT_WOL in
Interrupt enable register (MII Register 0x12) is set to 1. If the general PHY interrupt is triggered by
WOL, it can be cleared by reading MII register 0x13 bit6.
NOTE:
When general PHY interrupt is used to monitor WOL interrupt, EXT 0x4003 bit7 should be 1,
otherwise, the general PHY interrupt can’t be read cleared.
Because PHY requires to receive packets from the line side, PHY cannot be powered down. If the link
partner supports Energy Efficient Ethernet function, both ends can use EEE mode to save more power.
MII register 0x0 bit10 ISOLATE: When this bit is set to 1, the xMII output pins are HighZ. The xMII
inputs are ignored.
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Motorcomm YT8512C YT8512H Datasheet
5
REGISTER OVERVIEW
MII MANAGEMENT INTERFACE CLAUSE 22 REGISTER PROGRAMMING
The YT8512 transceiver is designed to be fully compliant with the MII clause of the IEEE 802.3u
Ethernet specification.
The MII management interface registers are written and read serially, using the MDIO and MDC pins.
A clock of up to 12.5 MHz must drive the MDC pin of the YT8512. Data transferred to and from the
MDIO pin is synchronized with the MDC clock. The following sections describe what each MII read or
write instruction contains.
Notation
Description
RW
Read and write
SC
Self-clear
RO
Read only
LH
Latch high
LL
Latch Low
RC
Read clear
SWC
Software reset clear
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Motorcomm YT8512C YT8512H Datasheet
MII REGISTERS
MII REGISTER 00H: BASIC CONTROL REGISTER
Bit
Symbol
Access
Default
Description
15
Reset
RW SC
1’b0
PHY Software Reset. Writing 1 to this bit causes
immediate PHY reset. Once the operation is done, this
bit is cleared automatically.
0: Normal operation
1: PHY reset
14
Loopback
RW
1’b0
SWC
Internal loopback control
1’b0: disable loopback
1’b1: enable loopback
13
Speed
RW
1’b0
Selection(LSB)
LSB of speed_selection[1:0]. Link speed can be
selected via either the Auto-Negotiation process, or
manual speed selection speed_selection[1:0].
Speed_selection[1:0] is valid when Auto-Negotiation
is disabled by clearing bit 0.12 to zero.
12
Autoneg_En
RW
1’b1
Bit 6
Bit 13
1
1
Reserved
1
0
1000Mb/s
0
1
100Mb/s
0
0
10Mb/s
1: to enable auto-negotiation;
0: auto-negotiation is disabled.
11
Power_down
RW
SWC
1’b0
=1: Power down
=0: Normal operation
When the port is switched from power down to
normal operation, software reset and AutoNegotiation are performed even bit[15] RESET and
bit[9] RESTART_AUTO_NEGOTIATION are not
set by the user.
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Motorcomm YT8512C YT8512H Datasheet
10
Isolate
RW
1’b0
SWC
Isolate phy from MII/RMII: PHY will not respond to
xMII TXD/TX_EN, and present high impedance on
RXD/RX_DV.
1’b0: Normal mode
1’b1: Isolate mode
9
Re_Autoneg
RW
1’b0
Auto-Negotiation automatically restarts after
SWS
hardware or software reset regardelss of bit[9]
SC
RESTART.
=1: Restart Auto-Negotiation Process
=0: Normal operation
8
Duplex_Mode
RW
1’b1
The duplex mode can be selected via either the AutoNegotiation process or manual duplex selection.
Manual duplex selection is allowed when AutoNegotiation is disabled by setting bit[12]
AUTO_NEGOTIATION to 0.
=1: Full Duplex
=0: Half Duplex
7
Collision_Test
RW
1’b0
SWC
Setting this bit to 1 makes the COL signal asserted
whenever the TX_EN signal is asserted.
=1: Enable COL signal test
=0: Disable COL signal test
6
Speed_
RW
1’b1
See bit13.
RO
5’b0
Reserved. Write as 0, ignore on read
Selection(MSB)
5:0
Reserved
MII REGISTER 01H: BASIC STATUS REGISTER
Bit
Symbol
Access
Default
Description
15
100Base-T4
RO
1’b0
PHY doesn’t support 100BASE-T4
14
100Base-X_Fd
RO
1’b1
PHY supports 100BASE-X_FD
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Motorcomm YT8512C YT8512H Datasheet
13
100Base-X_Hd
RO
1’b1
PHY supports 100BASE-X_HD
12
10Mbps_Fd
RO
1’b1
PHY supports 10Mbps_Fd
11
10Mbps_Hd
RO
1’b1
PHY supports 10Mbps_Hd
10
100Base-T2_Fd
RO
1’b0
PHY doesn’t support 100Base-T2_Fd
9
100Base-T2_Hd
RO
1’b0
PHY doesn’t support 100Base-T2_Hd
8
Extended_Status
RO
1’b1
Whether support extended status register in 0Fh
0: Not supported
1: Supported
7
Unidirect_Ability
RO
1’b0
1’b0: PHY able to transmit from MII only
when the PHY has determined that a valid
link has been established
1’b1: PHY able to transmit from MII
regardless of whether the PHY has
determined that a valid link has been
established
6
Mf_Preamble_Sup
RO
1’b1
1’b0: PHY will not accept management
frames with preamble suppressed
pression
1’b1: PHY will accept management frames
with preamble suppressed
5
4
Autoneg_Complet
RO
e
SWC
Remote_Fault
RO RC
1’b0
1’b0: Auto-negotiation process not completed
1’b1: Auto-negotiation process completed
1’b0
SWC
1’b0: no remote fault condition detected
1’b1: remote fault condition detected
LH
3
Autoneg_Ability
RO
1’b1
1’b0: PHY not able to perform Auto-negotiation
1’b1: PHY able to perform Auto-negotiation
2
Link_Status
RO
LL
1’b0
Link status
1’b0: Link is down
SWC
1’b1: Link is up
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Motorcomm YT8512C YT8512H Datasheet
1
Jabber_Detect
1’b0
RO RC
10BaseTe jabber detected
LH
1’b0: no jabber condition detected
SWC
1’b1: Jabber condition detected
0
Extended_Capabili
1’b1
RO
To indicate whether support EXTs, to access from
ty
address register 1Eh and data register 1Fh
1’b0: Not supported
1’b1: Supported
MII REGISTER 02H: PHY IDENTIFICATION REGISTER1
Bit
Symbol
Access
Default
Description
15:0
Phy_Id
RO
16’b0
Bits 3 to 18 of the Organizationally Unique
Identifier
MII REGISTER 03H: PHY IDENTIFICATION REGISTER2
Bit
Symbol
Access
Default
Description
15:10
Phy_Id
RO
6’b0
Bits 19 to 24 of the Organizationally Unique
Identifier
9:4
Type_No
RO
6’h12
3:0
Revision_No
RO
4’h8
4 bits manufacturer’s revision number
MII REGISTER 04H: AUTO-NEGOTIATION ADVERTISEMENT
Bit
Symbol
Access
Default
Description
15
Next_Page
RW
1’b0
This bit is updated immediately after the writing
operation; however the configuration does not take effect
until any of the following occurs:
•
Software reset is asserted by writing register 0x0
bit[15]
•
Restart Auto-Negotiation is triggered by writing
register 0x0 bit[9]
•
The port is switched from power down to normal
operation by writing register 0x0 bit[11]
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Motorcomm YT8512C YT8512H Datasheet
•
Link goes down
If 1000BASE-T is advertised, the required next pages are
automatically transmitted. This bit must be set to 0 if no
additional next page is needed.
=1: Advertise
=0: Not advertised
14
Reserved
RO
1’b0
Reserved
13
Remote_Fault
RW
1’b0
=1: Set Remote Fault bit
=0: Do not set Remote Fault bit
12
Extended_Next
RW
1’b1
_Page
Extended next page enable control bit
=1: Local device supports transmission of extended next
pages
=0: Local device does not support transmission of
extended next pages.
11
Asymmetric_Pa
RW
1’b1
use
This bit is updated immediately after the writing
operation; however the configuration does not take effect
until any of the following occurs:
•
Software reset is asserted by writing register 0x0
bit[15]
•
Restart Auto-Negotiation is triggered by writing
register 0x0 bit[9]
•
The port is switched from power down to normal
operation by writing register 0x0 bit[11]
•
Link goes down
=1: Asymmetric Pause
=0: No asymmetric Pause
10
Pause
RW
1’b1
This bit is updated immediately after the writing
operation; however the configuration does not take effect
until any of the following occurs:
•
Software reset is asserted by writing register 0x0
bit[15]
•
Restart Auto-Negotiation is triggered by writing
register 0x0 bit[9]
•
The port is switched from power down to normal
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Motorcomm YT8512C YT8512H Datasheet
operation by writing register 0x0 bit[11]
•
Link goes down
=1: MAC PAUSE implemented
=0: MAC PAUSE not implemented
9
100BASE-T4
RO
1’b0
=1: Able to perform 100BASE-T4
=0: Not able to perform 100BASE-T4
Always 0
8
100BASE-
RW
1’b1
This bit is updated immediately after the writing
TX_Full_Duple
operation; however the configuration does not take effect
x
until any of the following occurs:
•
Software reset is asserted by writing register 0x0
bit[15]
•
Restart Auto-Negotiation is triggered by writing
register 0x0 bit[9]
•
The port is switched from power down to normal
operation by writing register 0x0 bit[11]
•
Link goes down
=1: Advertise
=0: Not advertised
7
100BASE-
RW
1’b1
This bit is updated immediately after the writing
TX_Half_Duple
operation; however the configuration does not take effect
x
until any of the following occurs:
•
Software reset is asserted by writing register 0x0
bit[15]
•
Restart Auto-Negotiation is triggered by writing
register 0x0 bit[9]
•
The port is switched from power down to normal
operation by writing register 0x0 bit[11]
•
Link goes down
=1: Advertise
=0: Not advertised
6
10BASETe_Full_Duplex
RW
1’b1
This bit is updated immediately after the writing
operation; however the configuration does not take effect
until any of the following occurs:
•
Software reset is asserted by writing register 0x0
bit[15]
35
Motorcomm YT8512C YT8512H Datasheet
•
Restart Auto-Negotiation is triggered by writing
register 0x0 bit[9]
•
The port is switched from power down to normal
operation by writing register 0x0 bit[11]
•
Link goes down
=1: Advertise
=0: Not advertised
5
10BASE-
RW
1’b1
This bit is updated immediately after the writing
Te_Half_Duple
operation; however the configuration does not take effect
x
until any of the following occurs:
•
Software reset is asserted by writing register 0x0
bit[15]
•
Restart Auto-Negotiation is triggered by writing
register 0x0 bit[9]
•
The port is switched from power down to normal
operation by writing register 0x0 bit[11]
•
Link goes down
=1: Advertise
=0: Not advertised
4:0
Selector_Field
RW
5’b00001
Selector Field mode.
00001 = IEEE 802.3
MII REGISTER 05H: AUTO-NEGOTIATION LINK PARTNER ABILITY
Bit
Symbol
Access
Default
Description
15
1000Base-X_Fd
RO
1’b0
Received Code Word Bit 15
=1: Link partner is capable of next page
SWC
=0: Link partner is not capable of next page
14
ACK
RO
1’b0
SWC
Acknowledge. Received Code Word Bit 14
=1: Link partner has received link code word
=0: Link partner has not received link code
word
13
REMOTE_FAULT
RO
SWC
1’b0
Remote Fault. Received Code Word Bit 13
=1: Link partner has detected remote fault
36
Motorcomm YT8512C YT8512H Datasheet
=0: Link partner has not detected remote
fault
12
RESERVED
RO
1’b0
SWC
11
ASYMMETRIC_PAUSE
RO
Technology Ability Field. Received Code
Word Bit 12
1’b0
SWC
Technology Ability Field. Received Code
Word Bit 11
=1: Link partner requests asymmetric pause
=0: Link partner does not request
asymmetric
pause
10
PAUSE
RO
1’b0
SWC
Technology Ability Field. Received Code
Word Bit 10
=1: Link partner supports pause operation
=0: Link partner does not support pause
operation
9
100BASE-T4
RO
1’b0
SWC
Technology Ability Field. Received Code
Word Bit 9
=1: Link partner supports 100BASE-T4
=0: Link partner does not support100BASET4
8
100BASE-
RO
TX_FULL_DUPLEX
SWC
1’b0
Technology Ability Field. Received Code
Word Bit 8
=1: Link partner supports 100BASE-TX fullduplex
=0: Link partner does not support 100BASETX full-duplex
7
100BASE-
RO
TX_HALF_DUPLEX
SWC
1’b0
Technology Ability Field. Received Code
Word Bit 7
=1: Link partner supports 100BASE-TX
half-duplex
37
Motorcomm YT8512C YT8512H Datasheet
=0: Link partner does not support 100BASETX
half-duplex
6
10BASE-
RO
Te_FULL_DUPLEX
SWC
1’b0
Technology Ability Field. Received Code
Word Bit 6
=1: Link partner supports 10BASE-Te fullduplex
=0: Link partner does not support 10BASETe full-duplex
5
10BASE-
RO
Te_HALF_DUPLEX
SWC
1’b0
Technology Ability Field. Received Code
Word Bit 5
=1: Link partner supports 10BASE-Te halfduplex
=0: Link partner does not support 10BASETe half-duplex
4:0
SELECTOR_FIELD
RO
5’h0
Selector Field Received Code Word Bit 4:0
SWC
MII REGISTER 06H: AUTO-NEGOTIATION EXPANSION REGISTER
Bit
Symbol
Access
Default
Description
15:5
Reserved
RO
11’h0
Always 0
4
Parallel_Detection_fault
RO RC LH
1’b0
=1: Fault is detected
SWC
3
Link_partner_next_page able
RO LH SWC
=0: No fault is detected
1’b0
=1: Link partner supports Next
page
=0: Link partner does not support
next page
2
Local_Next_Page_able
RO
1’b1
=1: Local Device supports Next
Page
=0: Local Device does not Next
Page
38
Motorcomm YT8512C YT8512H Datasheet
1
Page_received
RO RC LH
1’b0
=1: A new page is received
=0: No new page is received
0
Link_Partner_Auto_negotiati
RO
1’b0
on_able
=1: Link partner supports autonegotiation
=0: Link partner does not support
auto-negotiation
MII REGISTER 07H: AUTO-NEGOTIATION NEXT PAGE REGISTER
Bit
Symbol
Access
Default
Description
15
Next_Page
RW
1’b0
Transmit Code Word Bit 15
=1: The page is not the last page
=0: The page is the last page
14
Reserved
RO
1’b0
Transmit Code Word Bit 14
13
Message_page_mode
RW
1’b1
Transmit Code Word Bit 13
=1: Message Page
=0: Unformatted Page
12
Ack2
RW
1’b0
Transmit Code Word Bit 12
=1: Comply with message
=0: Cannot comply with message
11
Toggle
RO
1’b0
Transmit Code Word Bit 11
=1: This bit in the previously exchanged Code
Word is logic 0
=0: The Toggle bit in the previously exchanged
Code Word is logic 1
10:0
Message_Unformatte
D_Field
RW
11’h1
Transmit Code Word Bits [10:0].
These bits are encoded as Message Code Field
when bit[13] is set to 1, or as Unformatted Code
Field when bit[13] is set to 0.
MII REGISTER 08H: AUTO-NEGOTIATION LINK PARTNER RECEIVED NEXT
PAGE REGISTER
39
Motorcomm YT8512C YT8512H Datasheet
Bit
Symbol
Access
Default
Description
15
Next_Page
RO
1’b0
Received Code Word Bit 15
=1: This page is not the last page
=0: This page is the last page
14
Reserved
RO
1’b0
Received Code Word Bit 14
13
Message_page_mode
RO
1’b0
Received Code Word Bit 13
=1: Message Page
=0: Unformatted Page
12
Ack2
RO
1’b0
Received Code Word Bit 12
=1: Comply with message
=0: Cannot comply with message
11
Toggle
RO
1’b0
Received Code Word Bit 11
=1: This bit in the previously exchanged Code
Word is logic 0
=0: The Toggle bit in the previously exchanged
Code Word is logic 1
10:0
Message_Unformatte
RO
11’b0
D_Field
Received Code Word Bit 10:0
These bits are encoded as Message Code Field
when bit[13] is set to 1, or as Unformatted Code
Field when bit[13] is set to 0.
MII REGISTER 0AH: MASTER-SLAVE STATUS REGISTER
Bit
Symbol
Access
Default
Description
15
Master_Slave_Conf
RO RC
1’b0
This register bit will clear on read, rising of MII
iguration_Fault
SWC
0.12 and rising of AN complete.
LH
=1: Master/Slave configuration fault detected
=0: No fault detected
14
Master_Slave_Conf
iguration_Resolutio
RO
1’b0
This bit is not valid unless register 0x1 bit5 is 1.
=1: Local PHY configuration resolved to Master
n
=0: Local PHY configuration resolved to Slave
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Motorcomm YT8512C YT8512H Datasheet
13
Local_Receiver_Sta
RO
1’b0
tus
=1: Local Receiver OK
=0: Local Receiver not OK
Always 0.
12
Remote_Receiver_
RO
1’b0
Status
=1: Remote Receiver OK
=0: Remote Receiver not OK
Always 0.
11
Link Partner_
RO
1’b0
This bit is not valid unless register 0x1 bit5 is 1.
1000Base-
=1: Link Partner supports 1000BASE-T half
T_Full_Duplex_Ca
duplex
pability
=0: Link Partner does not support 1000BASE-T
half duplex
10
Link_Partner_1000
RO
1’b0
Base-
This bit is not valid unless register 0x1 bit5 is 1.
=1: Link Partner supports 1000Base-T full duplex
T_Half_Duplex_Ca
=0: Link Partner does not support 1000Base-T full
pability
duplex
9:8
Reserved
RO
2’b0
Always 0
7:0
Idle_Error_Count
RO SC
8’b0
Counter for Idle errors
MII REGISTER 0DH: MMD ACCESS CONTROL REGISTER
Bit
Symbol
Access
Default
Description
15:14
Function
RW
2’b0
00 = Address
01 = Data, no post increment
10 = Data, post increment on reads and writes
11 = Data, post increment on writes only
13:5
Reserved
RO
9’b0
Always 0
4:0
DEVAD
RW
5’b0
MMD register device address.
00001 = MMD1
00011 = MMD3
00111 = MMD7
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Motorcomm YT8512C YT8512H Datasheet
MII REGISTER 0EH: MMD ACCESS DATA REGISTER
Bit
Symbol
Access
Default
Description
15:0
Address_data
RW
16’b0
If register 0xD bits [15:14] are 00, this register
is used as MMD DEVAD address register.
Otherwise, this register is used as MMD
DEVAD data register as indicated by its address
register.
MII REGISTER 0FH: EXTENDED STATUS REGISTER
Bit
Symbol
Access
Default
Description
15
1000Base-X_Fd
RO
1’b0
PHY not able to support 1000Base-X_Fd
14
1000Base-
RO
1’b0
PHY not able to support 1000Base-X_Hd
X_Hd
13
1000Base-T_Fd
RO
1’b0
PHY not able to support 1000Base-T_Fd
12
1000Base-
RO
1’b0
PHY not able to support 1000Base-T_Hd
T_Hd
11:8
Reserved
RO
1’b0
Reserved
7
100Base-T1
RO
1’b1
Reserved
6
1000Base-T1
RO
1’b0
Reserved
5:0
Reserved
RO
6’b0
Reserved
MII REGISTER 10H: PHY SPECIFIC FUNCTION CONTROL REGISTER
Bit
Symbol
Access
Default
Description
15:7
Reserved
RO
9’b0
Always 0.
6:5
Cross_md
RW
2’b11
Changes made to these bits disrupt normal
operation, thus a software reset is mandatory
after the change. And the configuration does
not take effect until software reset.
00 = Manual MDI configuration
01 = Manual MDIX configuration
10 = Reserved
42
Motorcomm YT8512C YT8512H Datasheet
11 = Enable automatic crossover for all
modes
4
Int_polar_sel
RW
1’b0
No use.
3
Crs_on_tx
RW
1’b0
This bit is effective in 10BASE-Te halfduplex mode and 100BASE-TX mode:
=1: Assert CRS on transmitting or receiving
=0: Never assert CRS on transmitting, only
assert it on receiving.
2
En_sqe_test
RW
1’b0
=1: SQE test enabled
=0: SQE test disabled
Note: SQE Test is automatically disabled in
full-duplex mode regardless the setting in
this bit.
1
En_pol_inv
RW
1’b1
If polarity reversal is disabled, the polarity
is forced to be normal in 10BASE-Te.
=1: Polarity Reversal Enabled
=0: Polarity Reversal Disabled
0
Dis_jab
RW
1’b0
Jabber takes effect only in 10BASE-Te
=1: Disable jabber function
=0: Enable jabber function
MII REGISTER 11H: PHY SPECIFIC STATUS REGISTER
Bit
Symbol
Access
Default
Description
15:14
Speed_mode
RO
2’b00
This status bit is valid only when bit11 is
1. Bit11 is set when Auto-Negotiation is
completed or Auto-Negotiation is
disabled.
11 = Reserved
10 = 1000 Mbps
01 = 100 Mbps
00 = 10 Mbps
43
Motorcomm YT8512C YT8512H Datasheet
13
Duplex
RO
1’b0
This status bit is valid only when bit11 is
1. Bit11 is set when Auto-Negotiation is
completed or Auto-Negotiation is
disabled.
=1: Full-duplex
=0: Half-duplex
12
Page_Received
RO
1’b0
_real-time
11
Speed_and_Du
=1: Page received
=0: Page not received
RO
1’b0
plex_Resolved
This bit is set when Auto-Negotiation is
completed or Auto-Negotiation is disabled
=1: Resolved
=0: Not resolved
10
Link_status_re
RO
1’b0
al-time
=1: Link up
=0: Link down
9:7
Reserced
RO
3’b111
Always 3’b111.
6
MDI_Crossove
RO
1’b0
This status bit is valid only when bit11 is
r_Status
1. Bit11 is set when Auto-Negotiation is
completed or Auto-Negotiation is
disabled.
The bit value depends on register 0x10
“PHY specific function control register”
bits6~bit5 configurations. Register 0x10
configurations take effect after software
reset.
=1: MDIX
=0: MDI
5
Wirespeed_do
RO
1’b0
wngrade
=1: Downgrade
=0: No Downgrade
4:2
Reserved
RO
3’b0
Always 0.
1
Polarity_Real_
RO
1’b0
=1: Reverted polarity
Time
=0: Normal polarity
44
Motorcomm YT8512C YT8512H Datasheet
0
Jabber_Real_T
1’b0
RO
ime
=1: Jabber is asserted.
=0: No jabber
MII REGISTER 12H: INTERRUPT MASK REGISTER
Bit
Symbol
Access
Default
Description
15
Auto-
RW
1’b0
=1: Interrupt enable
Negotiation_Error_int
=0: Interrupt disable
_mask
14
Speed_Changed_int_ma
RW
1’b0
sk
13
Duplex_changed_int_m
=0: Interrupt disable
RW
1’b0
ask
12
Page_Received_int_mas
Link_Failed_int_mask
=1: Interrupt enable
=0: Interrupt disable
RW
1’b0
k
11
=1: Interrupt enable
=1: Interrupt enable
=0: Interrupt disable
RW
1’b0
=1: Interrupt enable
=0: Interrupt disable
10
Link_Succeed_int_mask
RW
1’b0
=1: Interrupt enable
=0: Interrupt disable
9
Reserved
RW
1’b0
Reserved
8
Reserved
RW
1’b0
Reserved
7
Reserved
RW
1’b0
Reserved
6
WOL_int_mask
RW
1’b0
=1: Interrupt enable
=0: Interrupt disable
5
Wirespeed_downgraded
RW
1’b0
_int_mask
=1: Interrupt enable
=0: Interrupt disable
4:2
Reserved
RW
3’b0
No used.
1
Polarity_changed_int_m
RW
1’b0
=1: Interrupt enable
ask
=0: Interrupt disable
45
Motorcomm YT8512C YT8512H Datasheet
0
Jabber_Happened_int_
RW
1’b0
mask
=1: Interrupt enable
=0: Interrupt disable
MII REGISTER 13H: INTERRUPT STATUS REGISTER
Bit
Symbol
Access
Default
Description
15
Auto-
RO RC
1’b0
Error can take place when any of
Negotiation_Error_
the following
INT
happens:
•
MASTER/SLAVE does not
resolve correctly
•
Parallel detect fault
•
No common HCD
•
Link does not come up after
negotiation is complete
•
Selector Field is not equal
•
flp_receive_idle=true while
Autoneg Arbitration FSM is
in NEXT PAGE WAIT state
=1: Auto-Negotiation Error takes
place
=0: No Auto-Negotiation Error
takes place
14
Speed_Changed_IN
RO RC
1’b0
T
13
Duplex_changed_I
=0: Speed not changed
RO RC
1’b0
NT
12
Page_Received_IN
Link_Failed_INT
=1: duplex changed
=0: duplex not changed
RO RC
1’b0
T
11
=1: Speed changed
=1: Page received
=0: Page not received
RO RC
1’b0
=1: Link down takes place
=0: No link down takes place
10
Link_Succeed_INT
RO RC
1’b0
=1: Link up takes place
=0: No link up takes place
9
Reserved
RO
1’b0
Always 0.
46
Motorcomm YT8512C YT8512H Datasheet
8
Reserved
RO
1’b0
Always 0.
7
Reserved
RO
1’b0
Always 0.
6
WOL_INT
RO RC
1’b0
=1: PHY received WOL magic
frame.
=0: PHY didn’t receive WOL
magic frame.
5
Wirespeed_downgr
1’b0
RO RC
aded_INT
=1: speed downgraded.
=0: Speed didn’t downgrade.
4:2
Reserved
RO
3’b0
Always 0.
1
Polarity_changed_I
RO RC
1’b0
=1: PHY revered MDI polarity
NT
0
Jabber_Happened_I
=0: PHY didn’t revert MDI
polarity
1’b0
RO RC
NT
=1: 10BaseTe TX jabber
happened
=0: 10BaseTe TX jabber didn’t
happen
MII REGISTER 14H: SPEED AUTO DOWNGRADE CONTROL REGISTER
Bit
Symbol
Access
Default
Description
15:12
Reserved
RO
4’b0
Always 0.
11
En_mdio_latch
RW
1’b1
=1: To latch MII/MMD register’s read
out value during MDIO read
=0: Do not latch MII/MMD register’s
read out value during MDIO read
10:6
Reserved
RW SC
5’b0
Reserved
5
En_speed_downgrade
RW
1’b1
When this bit is set to 1, the PHY
enables smart-speed function. Writing
this bit requires a software reset to
update.
4:2
Autoneg retry limit predowngrade
RW
3’b011
If these bits are set to 3, the PHY
attempts five times (set value 3 +
additional 2) before downgrading. The
47
Motorcomm YT8512C YT8512H Datasheet
number of attempts can be changed by
these bits.
1
Bp_autospd_timer
RW
1’b0
=1: the wirespeed downgrade FSM will
bypass the timer used for link stability
check;
=0: not bypass the timer, then links that
established but hold for less than 2.5s
would still be taken as failure, autoneg
retry counter will increase by 1.
0
Reserved
RO
1’b0
Always 0.
MII REGISTER 15H: RX ERROR COUNTER REGISTER
Bit
Symbol
Access
Default
Description
15:0
Rx_err_counter
RO
16’b0
This counter increase by 1 at the 1st
rising of RX_ER when RX_DV is 1.
The counter will hold at maximum
16’hFFFF and not roll over.
If speed mode is 2’b01, it counts for
fe_100 RX_ER;
Else, it’s 0.
MII REGISTER 1EH: DEBUG REGISTER’S ADDRESS OFFSET REGISTER
Bit
Symbol
Access
Default
Description
15:0
Extended_Register_Addr
RW
16’h0
It’s the address offset of the EXT
ess _Offset
that will be Write or Read
MII REGISTER 1FH: DEBUG REGISTER’S DATA REGISTER
Bit
Symbol
Access
Default
Description
15:0
Extended_Register_Datas
RW
16’b0
It’s the data to be written to the EXT
indicated by the address offset in
register 0x1E, or the data read out
from that debug register.
48
Motorcomm YT8512C YT8512H Datasheet
EXTENDED REGISTER
EXT 200AH: 10BT POWER CONTROL, REGISTER
Bit
Symbol
Access
Default
Description
15:11
Reserved
RW
5’b11001
Reserved
10
En_10bt_idl
RW
1’b1
=1: In 10BT mode , if there’s no data
or NLP to transmit, shut off DAC;
otherwise turn on the DAC;
=0: In 10BT, DAC will not be turn off.
9:0
Reserved
RW
10’b1000001000
Reserved
EXT 4000H: EXTENDED COMBO CONTROL1
Bit
Symbol
Access
default
15:12
Reserved
RO
4’b0
11
Remote_Loopback
RW
1’b0
Description
Remote loopback control
1’b0: disable
1’b1: enable
10:9
Reserved
RW
2’b0
Reserved
8
Reserved
RW
1’b0
Reserved
7:6
Reserved
RW
2’b00
Reserved
5
Jumbo_Enable
RW
1’b0
Enable Jumbo frame reception up to
18KB frame, when disabled only up to
4.5KB frame supported
0: disable jumbo frame reception
1: enable jumbo frame reception
4
Rmii_RX_DV_sel
RW
1’b0
Drive PAD CRS_DV of RMII by
CRS_DV or RX_DV.
0: by CRS_DV
1: by RX_DV
3
Reserved
RW
1’b0
Reserved
49
Motorcomm YT8512C YT8512H Datasheet
2
Wol_en
1’b0
RW
1: enable WOL mechanism.
0: disable WOL.
1
Rmii_en
1’b0
RW
Its default value is determined by
power on strapping.
1: enable RMII mode;
0: disable RMII mode.
0
Clk_sel
1’b0
RW
Its default value is determined by
power on strapping.
1: input TXC/RXC;
0: output TXC/RXC.
{rmii_en, clk_sel}:
2’b00: MII mode;
2’b01: REMII mode;
2’b10: RMII2 mode;
2’b11: RMII1 mode.
EXT 4001H: EXTENDED PAD CONTROL
Bit
Symbol
Access
default
Description
15
Output_int_or_wol
RW
1’b1
YT8512, control to output general
INTn or WOL INTn to PAD
LED0_INTN_PMEB, when
power on strapping value of
RXD[1] is 1.
1’b1: output general INTn;
1’b0: output WOL INTn.
14:6
Reserved
RW
9’b000000011
Reserved
5:4
Xmii_Dr
RW
2’b10
Xmii interface driver strength
control in non-scan mode.
3:2
Mdio_Dr
RW
2’b11
Mdio pin driver strength control
in non-scan mode.
1:0
Reserved
RW
2’b11
Reserved
EXT 4003H: EXTENDED COMBO CONTROL2
Bit
Symbol
Access
default
Description
50
Motorcomm YT8512C YT8512H Datasheet
15
Reserved
RW
1’b0
Reserved
14
Slave_jitter_test
RW
1’b0
Mux clk_dac to rxc in slave jitter
test mode
1: enable
0: disable
13:10
Reserved
RW
4’b0
Reserved
9:7
Wol_lth_sel
RW
3’b100
Wol_lth_sel[0] control WOL INTn
to be a level or a pulse.
1’b1: a pulse;
1’b0: a level.
Wol_lth_sel[2:1] control WOL
INTn pulse width when
Wol_lth_sel[0] is 1.
2’b00: 10us;
2’b01: 100us;
2’b10: 1ms;
2’b11: 10ms.
6
En_isolate_txc
RW
1’b1
When isolate (mii.0.10) is 1,
control to make TXC input or not.
1’b1: input;
1’b0: keep TXC previous direction.
5
En_isolate_rxc
RW
1’b1
When isolate (mii.0.10) is 1,
control to make RXC input or not.
1’b1: input;
1’b0: keep RXC previous direction.
4:0
Reserved
RW
5’b01111
Reserved
EXT 4004H: WOL MAC ADDRESS
Bit
Symbol
Access
default
Description
15:0
Mac_addr_loc[47:32]
RW
16’b0
mac address for WOL
EXT 4005H: WOL MAC ADDRESS
Bit
Symbol
Access
default
Description
15:0
Mac_addr_loc[31:16]
RW
16’b0
mac address for WOL
EXT 4006H: WOL MAC ADDRESS
Bit
Symbol
Access
default
Description
15:0
Mac_addr_loc[15:0]
RW
16’b0
mac address for WOL
51
Motorcomm YT8512C YT8512H Datasheet
EXT 40A0H: PKG_SELFTEST CONTROL
Bit
Symbol
Access
default
Description
15
Pkg_chk_en
RW
1’b0
1: to enable RX/TX package checker. RX
checker checks the MII data at transceiver’s
PCS RX; TX checker checks the MII data at
mii_bridge’s TX.
14
Pkg_en_gate
RW
1’b1
1: to enable gate all the clocks to package selftest module when bit15 pkg_chk_en is 0, bit13
bp_pkg_gen is 1 and bit12 pkg_gen_en is 0;
0: not gate the clocks.
13
Bp_pkg_gen
RW
1’b1
1: normal mode, to send xMII TX data from
PAD;
0: test mode, to send out the MII data
generated by pkg_gen module.
12
Pkg_gen_en
RW SC
1’b0
1: to enable pkg_gen generating MII packages.
But, the data will only be sent to transceiver
when Bit13 bp_pkg_gen is 1’b0.
If pkg_burst_size is 0, continuous packages
will be generated and will be stopped only
when pkg_gen_en is set to 0;
Otherwise, after the expected packages are
generated, pkg_gen will stop, pkg_gen_en will
be self-cleared.
11:8
Pkg_prm_lth
RW
4’d8
The preamble length of the generated
packages, in Byte unit. Pkg_gen function only
support >=2 Byte preamble length. Values
smaller than 2 will be ignored by the pkg_gen
module.
7:4
Pkg_ipg_lth
RW
4’d12
The IPG of the generated packages, in Byte
unit. Pkg_gen function only support >=2 Byte
preamble length. Values smaller than 2 will be
ignored by the pkg_gen module.
52
Motorcomm YT8512C YT8512H Datasheet
3
Xmit_mac_force_
1’b0
RW
1: To enable pkg_gen to send out the
gen
generated data even when the link is not
established.
2
Pkg_corrupt_crc
1’b0
RW
1: to make pkg_gen to send out CRC error
packages.
0: pkg_gen sends out CRC good packages.
1:0
Pkg_payload
2’b0
RW
Control the payload of the generated packages.
00: increased Byte payload;
01: random payload;
10: fix pattern 0x5AA55AA5…
11: reserved.
EXT 40A1H: PKG_SELFTEST CONTROL
Bit
Symbol
Access
default
Description
15:0
Pkg_length
RW
16’d64
To set the length of the generated packages.
EXT 40A2H: PKG_SELFTEST CONTROL
Bit
Symbol
Access
default
Description
15:0
Pkg_burst_size
RW
16’b0
To set the number of packages in a burst of
package generation.
0: continuous packages will be generated.
EXT 40A3H: PKG_SELFTEST STATUS
Bit
Symbol
Access
default
Description
15:0
Pkg_ib_valid_high
RO
16’b0
Pkg_ib_valid[31:16], pkg_ib_valid is the
number of RX packages from wire whose
CRC are good and length are >=64Byte and
=64Byte and
1518Byte.
EXT 40A6H: PKG_SELFTEST STATUS
Bit
Symbol
Access
default
Description
15:0
Pkg_ib_os_good_low
RO
16’b0
Pkg_ib_os_good[15:0], pkg_ib_os_good is
the number of RX packages from wire whose
CRC are good and length are >1518Byte.
EXT 40A7H: PKG_SELFTEST STATUS
Bit
Symbol
Access
default
Description
15:0
Pkg_ib_us_good_high
RO
16’b0
Pkg_ib_us_good[31:0], pkg_ib_us_good is
the number of RX packages from wire whose
CRC are good and length are 1518Byte.
EXT 40A9H: PKG_SELFTEST STATUS
Bit
Symbol
Access
default
Description
54
Motorcomm YT8512C YT8512H Datasheet
15:0
Pkg_ib_err
RO
16’b0
pkg_ib_err is the number of RX packages
from wire whose CRC are wrong and length
are >=64Byte, =1518Byte.
EXT 40ABH: PKG_SELFTEST STATUS
Bit
Symbol
Access
default
Description
15:0
Pkg_ib_frag
RO
16’b0
pkg_ib_frag is the number of RX packages
from wire whose length are =64Byte and
=64Byte and
1518Byte.
EXT 40B0H: PKG_SELFTEST STATUS
Bit
Symbol
Access
default
Description
15:0
Pkg_ob_os_good_low
RO
16’b0
Pkg_ob_os_good[15:0], pkg_ob_os_good is
the number of TX packages from MII whose
CRC are good and length are >1518Byte.
EXT 40B1H: PKG_SELFTEST STATUS
Bit
Symbol
Access
default
Description
15:0
Pkg_ob_us_good_high
RO
16’b0
Pkg_ob_us_good[31:0], pkg_ob_us_good is
the number of TX packages from MII whose
CRC are good and length are 1518Byte.
EXT 40B3H: PKG_SELFTEST STATUS
Bit
Symbol
Access
default
Description
15:0
Pkg_ob_err
RO
16’b0
pkg_ob_err is the number of TX packages
from MII whose CRC are wrong and length
are >=64Byte, =1518Byte.
EXT 40B5H: PKG_SELFTEST STATUS
Bit
Symbol
Access
default
Description
15:0
Pkg_ob_frag
RO
16’b0
pkg_ob_frag is the number of TX packages
from MII whose length are Led_act_level_th*42ms, then the
traffic is heavy; otherwise, traffic is not
heavy.
61
Motorcomm YT8512C YT8512H Datasheet
EXT 40C2H: LED0/1 CONTROL
Bit
Symbol
Access
default
Description
15:12
Freq_sel_c0
RW
4’d14
Control the LED blink frequency in Blink
mode 0.
ON/OFF duty cycle could be reverted by
40C1h bit9 invert_led_duty. Below
description is the default ON/OFF cycle,
that is invert_led_duty=0.
4’d0=LED blink once every 10s, 6%
OFF;
4’d1=LED blink once every 9.4s, 7%
OFF;
4’d2=LED blink once every 8s, 8% OFF;
4’d3=LED blink once every 7.4s, 9%
OFF;
4’d4=LED blink once every 6s, 11%
OFF;
4’d5=LED blink once every 5s, 6% OFF;
4’d6=LED blink once every 4s, 8% OFF;
4’d7=LED blink once every 3s, 11%
OFF;
4’d8=LED blink once every 2s, 16%
OFF;
4’d9=LED blink once every 1s, 16%
OFF;
4’d10=LED blink at 2Hz, 50% OFF;
4’d11=LED blink at 3Hz, 50% OFF;
4’d12=LED blink at 4Hz, 50% OFF;
4’d13=LED blink at 6Hz, 50% OFF;
4’d14=LED blink at 8Hz, 50% OFF;
4’d15=LED blink at 10Hz, 50% OFF;
62
Motorcomm YT8512C YT8512H Datasheet
11:8
Freq_sel_c1
RW
4’d12
Control the LED blink frequency in Blink
mode 1.
See description in bit15~12 Freq_sel_c0
for detail.
7:4
Freq_sel_c2
RW
4’d7
Control the LED blink frequency in Blink
mode 2.
See description in bit15~12 Freq_sel_c0
for detail.
3:0
Freq_sel_c3
RW
4’d5
Control the LED blink frequency in Blink
mode 3. See description in bit15~12
Freq_sel_c0 for detail.
EXT 40C3H: LED1 CONTROL
Bit
Symbol
Access
default
Description
15
Led_force_en
RW
1’b0
To enable LED force mode.
14:13
Led_force_mode
RW
2’b0
Valid when bit15 led_force_en is set.
00 = force LED OFF;
01 = force LED ON;
10 = force LED to blink at Blink Mode1;
11 = force LED to blink at Blink Mode0.
There are 4 Blink Mode, which are
different at blink frequency.
Refer to EXT 40C2 for detail of Blink
Mode0~3.
63
Motorcomm YT8512C YT8512H Datasheet
12
Led_act_blk_ind
RW
1’b0
When traffic is present, make LED BLINK
no matter the previous LED status is ON or
OFF, or make LED blink only when the
previous LED is ON.
when any *_blk_en in bit9~8 and bit3~1 is
set and chip do work at corresponding
status,
=1: LED will blink, no matter bit11~10
(duplex control) and bit5~4 (speed control)
are 1 or 0;
=0: LED will not blink, unless one (more)
of bit11~10 (duplex control) and bit5~4
(speed control) is (are) 1 and related status
is (are) matched (ON at certain speed or
duplex mode is/are activated);.
11
Led_fdx_on_en
RW
1’b0
If BLINK status is not activated, when
PHY link up and duplex mode is full
duplex,
=1: make LED ON;
=0: don’t make LED ON;
10
Led_hdx_on_en
RW
1’b0
If BLINK status is not activated, when
PHY link up and duplex mode is half
duplex,
=1: make LED ON;
=0: don’t make LED ON;
9
Led_txact_blk_en
RW
1’b1
If bit12 Led_act_blk_ind is 1, or it is 0 and
LED ON at certain speed or duplex more
is/are activated, when PHY link up and TX
is active,
=1: make LED BLINK at Blink mode 0 or
1 based on traffic weight;
=0: don’t make LED BLINK.
64
Motorcomm YT8512C YT8512H Datasheet
8
Led_rxact_blk_en
RW
1’b1
If bit12 Led_act_blk_ind is 1, or it is 0 and
LED ON at certain speed or duplex more
is/are activated, when PHY link up and RX
is active,
=1: make LED BLINK at Blink mode 0 or
1 based on traffic weight;
=0: don’t make LED BLINK.
7
Led_txact_on_en
RW
1’b0
=1: if BLINK status is not activated, when
PHY link up and TX is active, make LED
ON at least 10ms;
6
Led_rxact_on_en
RW
1’b0
=1: if BLINK status is not activated, when
PHY link up and RX is active, make LED
ON at least 10ms;
5
Led_ht_on_en
RW
1’b1
=1: if BLINK status is not activated, when
PHY link up and speed mode is 100Mbps,
make LED ON;
4
Led_bt_on_en
RW
1’b0
=1: if BLINK status is not activated, when
PHY link up and speed mode is 10Mbps,
make LED ON;
3
Led_col_blk_en
RW
1’b0
=1: if PHY link up at FE and collision
happen, make LED BLINK at Blink mode
0 or 1 based on 40C1h bit6 col_blk_sel;
2
Led_ht_blk_en
RW
1’b0
=1: if PHY link up and speed mode is
100Mbps, make LED BLINK at Blink
mode 2;
1
Led_bt_blk_en
RW
1’b0
=1: if PHY link up and speed mode is
10Mbps, make LED BLINK at Blink mode
3;
0
Reserved
RO
1’b0
Always 0.
65
Motorcomm YT8512C YT8512H Datasheet
6
TIMING AND ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Symbol
Description
Min
Max
Unit
DVDD33
3.3 V power supply
-0.3
3.70
V
AVDD33
3.3 V power supply
-0.3
3.70
V
AVDDL
1.2 V power supply
-0.2
1.50
V
DVDDL
1.2 V power supply
-0.2
1.50
V
RECOMMENDED OPERATING CONDITION
Description
Power supply
Pins
DVDD33
AVDD33
AVDDL
DVDDL
YT8512C Ambient Operation Temperature Ta
YT8512H Ambient Operation Temperature Ta
Maximum Junction Temperature
Min
2.97
2.97
1.08
1.08
0
-40
Typ
3.30
3.30
1.20
1.20
-
Max
3.63
3.63
1.32
1.32
70
85
125
Unit
V
V
V
V
°C
°C
CRYSTAL REQUIREMENT
Symbol
F ref
F ref Tolerance
Duty Cycle
ESR
DL
Vih
Vil
Description
Crystal Reference
Frequency
Crystal Reference
Frequency tolerance
Reference clock input
duty cycle
Equivalent Series
Resistance
Drive Level
Crystal output high level
Crystal output low level
Min
-
Typ
25
Max
-
Unit
MHz
-50
-
50
ppm
40
-
60
%
50
ohm
0.5
0.4
mW
V
V
1.4
-
-
66
Motorcomm YT8512C YT8512H Datasheet
OSCILLATOR/EXTERNAL CLOCK REQUIREMENT
Parameter
Frequency
Frequency tolerance
Duty Cycle
Peak to Peak Jitter
Vih
Vil
Rise Time
Fall Time
Temperature Range
Temperature Range
Condition
Min
Ta= -40~85 C
-50
40
Typ
25
-
1.4
10%~90%
10%~90%
YT8512C
YT851H
0
-40
Max
50
60
200
AVDD33+0.3
0.4
10
10
70
85
Unit
MHz
PPM
%
ps
V
V
ns
ns
°C
°C
DC CHARACTERISTICS
Symbol
Description
Min
Typ
Max
Unit
DVDD33
3.3V power supply
2.97
3.3
3.63
V
AVDD33
3.3V power supply
2.97
3.3
3.63
V
DVDDL
1.2V power supply
1.08
1.2
1.32
V
AVDDL
1.2V power supply
1.08
1.2
1.32
V
Voh 3.3V
Minimum High Level Voltage Output
2.4
-
3.6
V
-0.3
-
0.4
V
Voltage
Vol 3.3V
Minimum Low Level Voltage Output
Voltage
Vih 3.3V
Maximum High Level Input Voltage
2
-
-
V
Vil 3.3V
Maximum Low Level Input Voltage
-
-
0.8
V
67
Motorcomm YT8512C YT8512H Datasheet
MDC/MDIO TIMING
Symbol
Description
Min
Typ
Max
Unit
20
ns
T DLY_MDIO
MDC to MDIO Output Delay Time
T SU_MDIO
MDIO Input to MDC Setup Time
10
ns
T HD_MDIO
MDIO Input to MDC Hold Time
10
ns
T P_MDC
MDC Period
80
ns
T H_MDC
MDC High
30
ns
T L_MDC
MDC Low
30
ns
Maximum Frequency = 12.5M Hz
POWER ON SEQUENCE/CLOCK/RESET
When using crystal, the clock is generated internally after power is stable. For a reliable power on
reset, suggest to keep asserting the reset low long enough (100ms) to ensure the clock is stable and
clock-to-reset 10ms requirement is satisfied.
68
Motorcomm YT8512C YT8512H Datasheet
MII TRANSMISSION CYCLE TIMING
Symbol
t1
t2
t3
t4
t5
t6
t7
Description
Minimum
Typical
Maximum
Unit
100Mbps
14
20
26
ns
10Mbps
140
200
260
ns
100Mbps
14
20
26
ns
10Mbps
140
200
260
ns
100Mbps
-
40
-
ns
10Mbps
-
400
-
ns
TXEN, TXD[0:3]
100Mbps
10
-
-
ns
Setup to TXCLK Rising Edge
10Mbps
5
-
-
ns
TXEN, TXD[0:3]
100Mbps
0
-
-
ns
Hold After TXCLK Rising Edge
10Mbps
0
-
-
ns
TXEN Sampled to CRS High
100Mbps
-
-
40
ns
10Mbps
-
-
400
ns
100Mbps
-
-
160
ns
10Mbps
-
-
2000
ns
TXCLK High Pulse Width
TXCLK Low Pulse Width
TXCLK Period
TXEN Sampled to CRS Low
69
Motorcomm YT8512C YT8512H Datasheet
MII RECEPTION CYCLE TIMING
Symbol
t1
Description
RXCLK High Pulse Width
Minimum
Typical
Maximum
Unit
100Mbps
14
20
26
ns
10Mbps
14
200
260
ns
0
t2
RXCLK Low Pulse Width
100Mbps
14
20
26
ns
10Mbps
14
200
260
ns
0
t3
100Mbps
-
40
-
ns
10Mbps
-
400
-
ns
RXER, RX_DV,RXD[0:3]
Setup to RXCLK Rising Edge
100Mbps
10
-
-
ns
10Mbps
10
-
-
ns
t5
RXER, RX_DV, RXD[0:3]
100Mbps
10
-
-
ns
10Mbps
10
-
-
ns
t6
Hold After RXCLK Rising
Edge
Receive Frame to CRS High
100Mbps
-
-
130
ns
10Mbps
-
-
2000
ns
End of Receive Frame to CRS
Low
100Mbps
-
-
240
ns
10Mbps
-
-
1000
ns
Receive Frame to Sampled
Edge of RX_DV
100Mbps
-
-
150
ns
10Mbps
-
-
3200
ns
End of Receive Frame to
Sampled Edge of RX_DV
100Mbps
-
-
120
ns
10Mbps
-
-
1000
ns
t4
t7
t8
t9
RXCLK Period
70
Motorcomm YT8512C YT8512H Datasheet
RMII TRANSMISSION AND RECEPTION CYCLE TIMING
Symbol
Description
Minimum
Typical
Maximum
Unit
REFCLK Frequency
Frequency of Reference Clock
-
50
-
REFCLK Duty Cycle
Duty Cycle of Reference Clock
35
-
65
%
T_ipsu_tx_rmii
TXD[1:0]/TXEN Setup Time to REFCLK
4
-
-
ns
T_iphd_tx_rmii
TXD[1:0]/TXEN Hold Time from REFCLK
2
-
-
ns
T_ophd_rx_rmii
RXD[1:0]/CRS_DV/RXER Output Delay
Time from REFCLK
2
-
-
ns
MHz
71
Motorcomm YT8512C YT8512H Datasheet
7
POWER REQUIREMENTS
POWER CONSUMPTION
MII MODE
Condition
3.3V(Pull up)
AVDD33
DVDD33
Reset
Power down
Hibernation
Active
Link
10M
100M
Traffic
10M
100M
0
0
0
0
4.2
3.9
1.9
1.8
5.2
5.4
6
44.3
19.3
56.6
37.9
56.7
0
0.1
0.1
0.7
0.6
4.9
0.8
6
3.3V(Pull up)
AVDD33
DVDD33
0
0
0
0
4.1
3.9
2.2
2.1
5.2
5.4
6
44.3
19.4
56.6
37.2
56.8
0
0.1
0
0
0.1
0.2
0.3
1.1
3.3V
total(mA)
5.2
5.5
6.1
45
24.1
65.4
40.6
65.5
RMII MODE
Condition
Reset
Power down
Hibernation
Active
Link
10M
100M
Traffic
10M
100M
3.3V
total(mA)
5.2
5.5
6
44.3
23.6
60.7
39.7
60.9
Unit is mA
Note: The power consumption is measured under room temperature with typical process DUT.
MAXIMUM POWER CONSUMPTION MII MODE
Condition
Traffic
100M
3.3V(Pull up)
AVDD33
DVDD33
2.3
68.1
8
3.3V
total(mA)
78.4
Note: The Maximum power consumption is measured under high temperature(TA=85°C) with
FF corner process (fast nmos and fast pmos)DUT.
72
Motorcomm YT8512C YT8512H Datasheet
8
PACKAGE INFORMATION
ROHS-COMPLIANT PACKAGING
Motor-comm offers a RoHS package that is compliant with RoHS
Part Number
Status
Package
Op temp (℃)
YT8512C
Active
QFN 32 5x5mm
0 to 70
YT8512H
Active
QFN 32 5x5mm
-40 to 85
Note
THERMAL RESISTANCE
Symbol
Parameter
C o n di t on
Ty p
37.8
Units
θJA
Thermal resistance - junction
to ambient
JEDEC
33.3
°C/W
JEDEC with no air flow
35
°C/W
JEDEC with no air flow
16.3
°C/W
θJA = (TJ - TA)/ P
3 in. x 4.5 in. 4-layer PCB
with no air flow TA=25°C
P = Total power dissipation
JEDEC
°C/W
3 in. x 4.5 in. 4-layer PCB
with no air flow TA=125°C
θJC
Thermal resistance - junction
to case
θJC = (TJ - TC)/ Ptop
Ptop = Power dissipation from
the top of the package
θJB
Thermal resistance - junction
to board
θJB = (TJ - TB)/ Pbottom
Pbottom = Power dissipation
from the bottom of the package
to the PCB surface.
73
Motorcomm YT8512C YT8512H Datasheet
9
MECHANICAL INFORMATION
74
Motorcomm YT8512C YT8512H Datasheet
75
Motorcomm YT8512C YT8512H Datasheet
10 ORDERING INFORMATION
Part Number
Grade
Package
Packaging
Status
Operation temp(℃)
YT8512C
Consumer
QFN 32
3000ea ;Tape & Reel,
Mass
0 to 70 ℃
5x5mm
4900ea ;Tray
Production
QFN 32
3000ea ;Tape & Reel,
Mass
5x5mm
4900ea ;Tray
Production
YT8512H
Industrial
-40 to 85 ℃
76
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