GS61008P-MR

GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Features • • • • • • • • • • • • • • • 100 V enhancement mode power transistor Bottom-side cooled configuration RDS(on) = 7 mΩ IDS(max) = 90 A Ultra-low FOM die Low inductance GaNPX® package Simple gate drive requirements (0 V to 6 V) Transient tolerant gate drive (-20 V / +10 V) Very high switching frequency (> 10 MHz) Fast and controllable fall and rise times Reverse current capability Zero reverse recovery loss Small 7.6 x 4.6 mm2 PCB footprint Source Sense (SS) pin for optimized gate drive RoHS 3 (6 + 4) compliant Package Outline Circuit Symbol The thermal pad (pad 5) must be connected to Source, S (pad 4) Applications Description • • • • • • • The GS61008P is an enhancement mode GaN-on-silicon Energy Storage Systems AC-DC Converters (secondary side) Uninterruptable Power Supplies Industrial Motor Drives Fast Battery Charging Class D Audio amplifiers Traction Drive power transistor. The properties of GaN allow for high current, high voltage breakdown and high switching frequency. GaN Systems innovates with industry leading advancements such as patented Island Technology® and GaNPX® packaging. Island Technology® cell layout realizes high-current die and high yield. GaNPX® packaging enables low inductance & low thermal resistance in a small package. The GS61008P is a bottom-side cooled transistor that offers very low junction-to-case thermal resistance for demanding high power applications. These features combine to provide very high efficiency power switching. Rev 200227 © 2009-2020 GaN Systems Inc. 1 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Absolute Maximum Ratings (Tcase = 25 °C except as noted) Parameter Symbol Value Unit Operating Junction Temperature TJ -55 to +150 °C Storage Temperature Range TS -55 to +150 °C Drain-to-Source Voltage VDS 100 V VDS(transient) 120 V VGS -10 to +7 V VGS(transient) -20 to +10 V Continuous Drain Current (Tcase = 25 °C) IDS 90 A Continuous Drain Current (Tcase = 100 °C) IDS 65 A IDS Pulse 140 A Symbol Value Units Thermal Resistance (junction-to-case) RΘJC 0.55 °C /W Thermal Resistance (junction-to-top) RΘJT 10 °C /W Thermal Resistance (junction-to-ambient) (note 2) RΘJA 23 °C /W Maximum Soldering Temperature (MSL3 rated) TSOLD 260 °C Drain-to-Source Voltage - transient (note 1) Gate-to-Source Voltage Gate-to-Source Voltage - transient (note 1) Pulse Drain Current (Pulse width 50 µs, VGS = 6 V) (1) Pulse < 1 µs Thermal Characteristics (Typical values unless otherwise noted) Parameter (2) Device mounted on 1.6 mm PCB thickness FR4, 4-layer PCB with 2 oz. copper on each layer. The recommendation for thermal vias under the thermal pad are 0.3 mm diameter (12 mil) with 0.635 mm pitch (25 mil). The copper layers under the thermal pad and drain pad are 25 x 25 mm2 each. The PCB is mounted in horizontal position without air stream cooling. Ordering Information Ordering code Package type Packing method Qty Reel Diameter Reel Width GS61008P-TR GaNPX® bottom cooled Tape-and-Reel 3000 13” (330mm) 16mm GS61008P-MR GaNPX® bottom cooled Mini-Reel 250 7” (180mm) 16mm Rev 200227 © 2009-2020 GaN Systems Inc. 2 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Electrical Characteristics (Typical values at TJ = 25 °C, VGS = 6 V unless otherwise noted) Parameters Sym. Min. Drain-to-Source Blocking Voltage V(BL)DSS 100 Drain-to-Source On Resistance RDS(on) 7 Drain-to-Source On Resistance RDS(on) 17.5 Gate-to-Source Threshold VGS(th) Gate-to-Source Current 1.1 Typ. Max. Units Conditions V 1.7 9.5 2.6 VGS = 0 V, IDSS = 50 µA mΩ VGS = 6 V, TJ = 25 °C IDS = 27 A mΩ VGS = 6 V, TJ = 150 °C IDS = 27 A V VDS = VGS, IDS = 7 mA VGS = 6 V, VDS = 0 V IGS 200 µA Gate Plateau Voltage Vplat 3.5 V VDS = 50 V, IDS = 90 A Drain-to-Source Leakage Current IDSS 0.5 µA VDS = 100 V, VGS = 0 V TJ = 25 °C Drain-to-Source Leakage Current IDSS 100 µA VDS = 100 V, VGS = 0 V TJ = 150 °C Internal Gate Resistance RG 0.77 Ω f = 5 MHz, open drain Input Capacitance CISS 600 pF Output Capacitance COSS 250 pF Reverse Transfer Capacitance CRSS 12 pF Effective Output Capacitance, Energy Related (Note 3) CO(ER) 351 pF Effective Output Capacitance, Time Related (Note 4) CO(TR) 433 pF Total Gate Charge QG 8 nC Gate-to-Source Charge QGS 3.5 nC Gate threshold charge QG(th) 1.9 nC Gate switching charge QG(sw) 4.1 nC Gate-to-Drain Charge QGD 1.7 nC Output Charge QOSS 21.3 nC Reverse Recovery Charge QRR 0 nC 50 VDS = 50 V VGS = 0 V f = 100 kHz VGS = 0 V VDS = 0 to 50 V VGS = 0 to 6 V VDS = 50 V IDS = 90 A VGS = 0 V, VDS = 50 V (3) CO(ER) is the fixed capacitance that would give the same stored energy as COSS while VDS is rising from 0 V to the stated VDS (4) CO(TR) is the fixed capacitance that would give the same charging time as COSS while VDS is rising from 0 V to the stated VDS. Rev 200227 © 2009-2020 GaN Systems Inc. 3 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Electrical Characteristics cont’d (Typical values at TJ = 25 °C, VGS = 6 V unless otherwise noted) Parameters Sym. Min. Typ. Max. Units Conditions Output Capacitance Stored Energy EOSS 0.39 µJ Switching Energy during turn-on Eon 2.8 µJ Switching Energy during turn-off Eoff 1.6 µJ VDS = 50 V VGS = 0 V f = 100 kHz VDS = 50 V, IDS = 20 A VGS = -3 - 6 V, RG(on) = 4.7 Ω, RG(off) = 1 Ω L = 28 µH LP = 3.8 nH (notes 5, 6) (5) LP is the switching circuit parasitic inductance. (6) See Figure 16 for switching loss test circuit. Rev 200227 © 2009-2020 GaN Systems Inc. 4 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Electrical Performance Graphs IDS vs. VDS Characteristic IDS vs. VDS Characteristic Figure 1: Typical IDS vs. VDS @ TJ = 25 ⁰C Figure 2: Typical IDS vs. VDS @ TJ = 150 ⁰C RDS(on) vs. IDS Characteristic RDS(on) vs. IDS Characteristic Figure 3: RDS(on) vs. IDS at TJ = 25 ⁰C Figure 4: RDS(on) vs. IDS at TJ = 150 ⁰C Rev 200227 © 2009-2020 GaN Systems Inc. 5 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Electrical Performance Graphs IDS vs. VDS, TJ dependence Gate Charge, QG Characteristic Figure 5: Typical IDS vs. VDS @ VGS = 6 V Figure 6: Typical VGS vs. QG Capacitance Characteristics Stored Energy Characteristic Figure 7: Typical CISS, COSS, CRSS vs. VDS Figure 8: Typical COSS Stored Energy Rev 200227 © 2009-2020 GaN Systems Inc. 6 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Electrical Performance Graphs Reverse Conduction Characteristics Reverse Conduction Characteristics Figure 9: Typical ISD vs. VSD at TJ = 25 ⁰C Figure 10: Typical ISD vs. VSD at TJ = 150 ⁰C IDS vs. VGS Characteristic RDS(on) Temperature Dependence Figure 11: Typical IDS vs. VGS Figure 12: Normalized RDS(on) as a function of TJ Rev 200227 © 2009-2020 GaN Systems Inc. 7 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Thermal Performance Graphs IDS - VDS SOA Power Dissipation – Temperature Derating Figure 13: Safe Operating Area @ Tcase = 25 °C Figure 14: Power Derating vs. Tcase Transient RθJC Figure 15: Transient Thermal Impedance 1.00 = Nominal DC thermal impedance Rev 200227 © 2009-2020 GaN Systems Inc. 8 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Test Circuits Figure 16: Switching Loss Test Circuit Application Information Gate Drive The recommended gate drive voltage range, VGS, is 0 V to + 6 V for optimal RDS(on) performance. Also, the repetitive gate to source voltage, maximum rating, VGS(AC), is +7 V to -10 V. The gate can survive non-repetitive transients up to +10 V and – 20 V for pulses up to 1 µs. These specifications allow designers to easily use 6.0 V or 6.5 V gate drive settings. At 6 V gate drive voltage, the enhancement mode high electron mobility transistor (E-HEMT) is fully enhanced and reaches its optimal efficiency point. A 5 V gate drive can be used but may result in lower operating efficiency. Inherently, GaN Systems E-HEMT do not require negative gate bias to turn off. Negative gate bias, typically VGS = -3 V, ensures safe operation against the voltage spike on the gate, however it may increase reverse conduction losses if not driven properly. For more details, please refer to the gate driver application note "GN001 How to Drive GaN Enhancement Mode Power Switching Transistors” at www.gansystems.com Similar to a silicon MOSFET, the external gate resistor can be used to control the switching speed and slew rate. Adjusting the resistor to achieve the desired slew rate may be needed. Lower turn-off gate resistance, RG(OFF) is recommended for better immunity to cross conduction. Please see the gate driver application note (GN001) for more details. A standard MOSFET driver can be used as long as it supports 6V for gate drive and the UVLO is suitable for 6V operation. Gate drivers with low impedance and high peak current are recommended for fast switching speed. GaN Systems E-HEMTs have significantly lower QG when compared to equally sized RDS(on) MOSFETs, so high speed can be reached with smaller and lower cost gate drivers. Rev 200227 © 2009-2020 GaN Systems Inc. 9 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Many non-isolated half bridge MOSFET drivers are not compatible with 6 V gate drive for GaN enhancement mode HEMT due to their high under-voltage lockout threshold. Also, a simple bootstrap method for high side gate drive will not be able to provide tight tolerance on the gate voltage. Therefore, special care should be taken when you select and use the half bridge drivers. Alternatively, isolated drivers can be used for a high side device. Please see the gate driver application note (GN001) for more details. Parallel Operation Design wide tracks or polygons on the PCB to distribute the gate drive signals to multiple devices. Keep the drive loop length to each device as short and equal length as possible. GaN enhancement mode HEMTs have a positive temperature coefficient on-state resistance which helps to balance the current. However, special care should be taken in the driver circuit and PCB layout since the device switches at very fast speed. It is recommended to have a symmetric PCB layout and equal gate drive loop length (star connection if possible) on all parallel devices to ensure balanced dynamic current sharing. Adding a small gate resistor (1-2 Ω) on each gate is strongly recommended to minimize the gate parasitic oscillation. Source Sensing The GS61008P has a dedicated source sense pin. The GaNPX® packaging utilizes no wire bonds so the source connection is very low inductance. The dedicated source sense pin will further enhance performance by eliminating the common source inductance if a dedicated gate drive signal kelvin connection is created. This can be achieved connecting the gate drive signal from the driver to the gate pad on the GS61008P and returning from the source sense pad on the GS61008P to the driver ground reference. Thermal The substrate is internally connected to the thermal pad on the bottom-side of the GS61008P. The source pad must be electrically connected to the thermal pad for optimal performance. The transistor is designed to be cooled using the printed circuit board. The Drain pad is not as thermally conductive as the thermal pad. However, adding more copper under this pad will improve thermal performance by reducing the package temperature. Thermal Modeling RC thermal models are available to support detailed thermal simulation using SPICE. The thermal models are created using the Cauer model, an RC network model that reflects the real physical property and packaging structure of our devices. This thermal model can be extended to the system level by adding extra Rθ and Cθ to simulate the Thermal Interface Material (TIM) or Heatsink. RC thermal model: Rev 200227 © 2009-2020 GaN Systems Inc. 10 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet RC breakdown of RΘJC Rθ (°C/W) Cθ (W∙s/°C) Rθ1 = 0.017 Cθ1 = 7.0E-05 Rθ2 = 0.253 Cθ2 = 6.7E-04 Rθ3 = 0.264 Cθ3 = 5.9E-03 Rθ4 = 0.016 Cθ4 = 1.8E-03 For more detail, please refer to Application Note GN007 “Modeling Thermal Behavior of GaN Systems’ GaNPX® Using RC Thermal SPICE Models” available at www.gansystems.com Reverse Conduction GaN Systems enhancement mode HEMTs do not need an intrinsic body diode and there is zero reverse recovery charge. The devices are naturally capable of reverse conduction and exhibit different characteristics depending on the gate voltage. Anti-parallel diodes are not required for GaN Systems transistors as is the case for IGBTs to achieve reverse conduction performance. On-state condition (VGS = +6 V): The reverse conduction characteristics of a GaN Systems enhancement mode HEMT in the on-state is similar to that of a silicon MOSFET, with the I-V curve symmetrical about the origin and it exhibits a channel resistance, RDS(on), similar to forward conduction operation. Off-state condition (VGS ≤ 0 V): The reverse characteristics in the off-state are different from silicon MOSFETs as the GaN device has no body diode. In the reverse direction, the device starts to conduct when the gate voltage, with respect to the drain, VGD, exceeds the gate threshold voltage. At this point the device exhibits a channel resistance. This condition can be modeled as a “body diode” with slightly higher VF and no reverse recovery charge. If negative gate voltage is used in the off-state, the source-drain voltage must be higher than VGS(th)+VGS(off) in order to turn the device on. Therefore, a negative gate voltage will add to the reverse voltage drop “VF” and hence increase the reverse conduction loss. Blocking Voltage The blocking voltage rating, V(BL)DSS, is defined by the drain leakage current. The hard (unrecoverable) breakdown voltage is approximately 30 % higher than the rated V(BL)DSS,. As a general practice, the maximum drain voltage should be de-rated in a similar manner as IGBTs or silicon MOSFETs. All GaN E-HEMTs do not avalanche and thus do not have an avalanche breakdown rating. The maximum drain-to-source rating is 100 V and does not change with negative gate voltage. GaN Systems tests devices in production with a 120 V Drain-to-source voltage pulse to insure blocking voltage margin. Rev 200227 © 2009-2020 GaN Systems Inc. 11 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Packaging and Soldering The package material is high temperature epoxy-based PCB material which is similar to FR4 but has a higher temperature rating, thus allowing the GS61008P device to be specified to 150 °C. The device can handle at least 3 reflow cycles. It is recommended to use the reflow profile in IPC/JEDEC J-STD-020 REV D.1 (March 2008) The basic temperature profiles for Pb-free (Sn-Ag-Cu) assembly are: • Preheat/Soak: 60 - 120 seconds. Tmin = 150 °C, Tmax = 200 °C. • Reflow: Ramp up rate 3 °C/sec, max. Peak temperature is 260 °C and time within 5 °C of peak temperature is 30 seconds. • Cool down: Ramp down rate 6 °C/sec max. Using “No-Clean” soldering paste and operating at high temperatures may cause a reactivation of the “NonClean” flux residues. In extreme conditions, unwanted conduction paths may be created. Therefore, when the product operates at greater than 100 °C it is recommended to also clean the “No-Clean” paste residues. Rev 200227 © 2009-2020 GaN Systems Inc. 12 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Recommended PCB Footprint Rev 200227 © 2009-2020 GaN Systems Inc. 13 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Package Dimensions Part Marking Rev 200227 © 2009-2020 GaN Systems Inc. 14 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Tape and Reel Information Rev 200227 © 2009-2020 GaN Systems Inc. 15 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback GS61008P Bottom-side cooled 100 V E-mode GaN transistor Preliminary Datasheet Tape and Reel Box Dimensions www.gansystems.com Important Notice – Unless expressly approved in writing by an authorized representative of GaN Systems, GaN Systems components are not designed, authorized or warranted for use in lifesaving, life sustaining, military, aircraft, or space applications, nor in products or systems where failure or malfunction may result in personal injury, death, or property or environmental damage. The information given in this document shall not in any event be regarded as a guarantee of performance. GaN Systems hereby disclaims any or all warranties and liabilities of any kind, including but not limited to warranties of non-infringement of intellectual property rights. All other brand and product names are trademarks or registered trademarks of their respective owners. Information provided herein is intended as a guide only and is subject to change without notice. The information contained herein or any use of such information does not grant, explicitly, or implicitly, to any party any patent rights, licenses, or any other intellectual property rights. GaN Systems standard terms and conditions apply. All rights reserved. Rev 200227 © 2009-2020 GaN Systems Inc. 16 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit Datasheet Feedback