HEF4013BTT,112

HEF4013B Dual D-type flip-flop Rev. 10 — 23 November 2021 Product data sheet 1. General description The HEF4013B is a dual D-type flip-flop with set and reset; positive-edge trigger. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. 2. Features and benefits • • • • • • • • • • Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Tolerant of slow clock rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from -40 °C to +125 °C Complies with JEDEC standard JESD 13-B ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V 3. Applications • • • Counters and dividers Registers Toggle flip-flops 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF4013BT -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 HEF4013BTT -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 HEF4013B Nexperia Dual D-type flip-flop 5. Functional diagram 1SD 1D 6 5 SD D 1 Q 1Q FF1 1CP 1CD 2SD 2D 3 CP 2 Q 1Q CD 4 8 9 SD D Q 13 2Q FF2 2CP 2CD 11 10 CP Q 12 2Q CD 001aag084 Fig. 1. Functional diagram CP C C Q C C C C C C D Q C C SD CD 001aag086 Fig. 2. Logic diagram (one flip-flop) HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 23 November 2021 © Nexperia B.V. 2021. All rights reserved 2 / 14 HEF4013B Nexperia Dual D-type flip-flop 6. Pinning information 6.1. Pinning 1Q 1 14 VDD 1Q 2 13 2Q 1CP 3 12 2Q 1CD 4 1D 5 1SD 6 9 2D VSS 7 8 2SD HEF4013B 11 2CP 10 2CD 001aag085 Fig. 3. Pin configuration for SOT108-1 (SO14) and SOT402-1 (TSSOP14) 6.2. Pin description Table 2. Pin description Symbol Pin Description 1Q, 2Q 1, 13 true output 1Q, 2Q 2, 12 complement output 1CP, 2CP 3, 11 clock input (LOW to HIGH edge-triggered) 1CD, 2CD 4, 10 asynchronous clear-direct input (active HIGH) 1D, 2D 5, 9 data input 1SD, 2SD 6, 8 asynchronous set-direct input (active HIGH) VSS 7 ground (0 V) VDD 14 supply voltage 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition. Control Input Output nSD nCD nCP nD nQ nQ H L X X H L L H X X L H H H X X H H L L ↑ L L H L L ↑ H H L HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 23 November 2021 © Nexperia B.V. 2021. All rights reserved 3 / 14 HEF4013B Nexperia Dual D-type flip-flop 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O Min Max Unit -0.5 +18 V - ±10 mA -0.5 VDD + 0.5 - ±10 mA input/output current - ±10 mA IDD supply current - 50 mA Tstg storage temperature -65 +150 °C Tamb ambient temperature -40 +125 °C Ptot total power dissipation Tamb = -40 °C to +125 °C - 500 mW P power dissipation per output - 100 mW [1] Conditions VI < -0.5 V or VI > VDD + 0.5 V VO < -0.5 V or VO > VDD + 0.5 V [1] V For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD supply voltage VI input voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate HEF4013B Product data sheet Conditions Min Max Unit 3 15 V 0 VDD V -40 +125 °C VDD = 5 V - 3.75 μs/V VDD = 10 V - 0.5 μs/V VDD = 15 V - 0.08 μs/V All information provided in this document is subject to legal disclaimers. Rev. 10 — 23 November 2021 © Nexperia B.V. 2021. All rights reserved 4 / 14 HEF4013B Nexperia Dual D-type flip-flop 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage |IO| < 1 μA |IO| < 1 μA |IO| < 1 μA VDD Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit Min Max Min Max Min Max Min Max 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 5V LOW-level output voltage |IO| < 1 μA 15 V - 0.05 - 0.05 - 0.05 - 0.05 V HIGH-level output current VO = 2.5 V 5V - -1.7 - -1.4 - -1.1 - -1.1 mA VO = 4.6 V 5V - -0.64 - -0.5 - -0.36 - -0.36 mA VO = 9.5 V 10 V - -1.6 - -1.3 - -0.9 - -0.9 mA VO = 13.5 V 15 V - -4.2 - -3.4 - -2.4 - -2.4 mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA 15 V - ±0.1 - ±0.1 - ±1.0 - ±1.0 μA 5V - 1.0 - 1.0 - 30 - 30 μA 10 V - 2.0 - 2.0 - 60 - 60 μA 15 V - 4.0 - 4.0 - 120 - 120 μA - - - - 7.5 - - - - pF LOW-level output current II input leakage current IDD supply current CI Conditions input capacitance HEF4013B Product data sheet all valid input combinations; |IO| = 0 A All information provided in this document is subject to legal disclaimers. Rev. 10 — 23 November 2021 © Nexperia B.V. 2021. All rights reserved 5 / 14 HEF4013B Nexperia Dual D-type flip-flop 11. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 °C, unless otherwise specified. For test circuit see Fig. 6. Symbol Parameter Conditions VDD tPHL nCP to nQ, nQ; see Fig. 4 5V HIGH to LOW propagation delay 10 V 15 V tPLH LOW to HIGH propagation delay tsu th tW set-up time hold time pulse width 45 90 ns ns 10 V 29 + 0.23 × CL - 40 80 ns 15 V 22 + 0.16 × CL - 30 60 ns [1] 73 + 0.55 × CL - 100 200 ns 10 V 29 + 0.23 × CL - 40 80 ns 15 V 22 + 0.16 × CL - 30 60 ns [1] 68 + 0.55 × CL - 95 190 ns 10 V 29 + 0.23 × CL - 40 80 ns 15 V 22 + 0.16 × CL - 30 60 ns [1] 48 + 0.55 × CL - 75 150 ns 10 V 24 + 0.23 × CL - 35 70 ns 15 V 17 + 0.16 × CL - 25 50 ns [1] 33 + 0.55 × CL - 60 120 ns 19 + 0.23 × CL - 30 60 ns 12 + 0.16 × CL - 20 40 ns [1] 10 + 1.00 × CL - 60 120 ns 10 V 9 + 0.42 × CL - 30 60 ns 15 V 6 + 0.28 × CL - 20 40 ns 40 20 - ns 10 V 25 10 - ns 15 V 15 5 - ns 20 0 - ns 10 V 20 0 - ns 15 V 15 0 - ns 5V 60 30 - ns 10 V 30 15 - ns 15 V 20 10 - ns 5V 50 25 - ns 10 V 24 12 - ns 15 V 20 10 - ns 5V 50 25 - ns 10 V 24 12 - ns 15 V 20 10 - ns nD to nCP; see Fig. 4 5 V nCP input LOW; see Fig. 4 nCD input HIGH; see Fig. 5 Product data sheet - nD to nCP; see Fig. 4 5 V nSD input HIGH; see Fig. 5 HEF4013B 34 + 0.23 × CL 60 5V see Fig. 4 220 ns 200 ns 15 V transition time 110 30 10 V tt - 100 5V nCD to nQ [1] 83 + 0.55 × CL - 5V nSD to nQ Max Unit - 5V nCP to nQ, nQ; see Fig. 4 Typ 22 + 0.16 × CL 5V nCD to nQ Min [1] 73 + 0.55 × CL 5V nSD to nQ Extrapolation formula All information provided in this document is subject to legal disclaimers. Rev. 10 — 23 November 2021 © Nexperia B.V. 2021. All rights reserved 6 / 14 HEF4013B Nexperia Dual D-type flip-flop Symbol Parameter Conditions trec nSD input; see Fig. 5 5 V recovery time VDD Extrapolation formula Min Typ +15 -5 - ns 10 V 15 0 - ns 15 V 15 0 - ns 40 25 - ns 10 V 25 10 - ns 15 V 25 10 - ns 5V 7 14 - MHz 10 V 14 28 - MHz 15 V 20 40 - MHz nCD input; see Fig. 5 5 V fclk(max) [1] maximum clock frequency see Fig. 4 Max Unit Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas (CL in pF). Table 8. Dynamic power dissipation VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter PD VDD dynamic power dissipation 5 V Typical formula Where 2 PD = 850 × fi + Σ(fo × CL) × VDD μW 2 10 V PD = 3600 × fi + Σ(fo × CL) × VDD μW 2 15 V PD = 9000 × fi + Σ(fo × CL) × VDD μW fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; Σ(fo × CL) = sum of the outputs; VDD = supply voltage in V. 11.1. Waveforms and test circuit tW 1/fclk(max) VI VM input nCP 0V tsu tsu th tf th tr VI VM input nD 0V tPLH tPHL tt VOH output nQ VOL tt VY VM VX 001aah016 Set-up and hold times are shown as positive values but may be specified as negative values. The shaded areas indicate when the input is permitted to change for predictable output performance. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Measurement points are given in Table 9. Fig. 4. Set-up time, hold time, minimum clock pulse width, propagation delays and transition times HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 23 November 2021 © Nexperia B.V. 2021. All rights reserved 7 / 14 HEF4013B Nexperia Dual D-type flip-flop VI input nCP VM 0V trec VI input nSD trec VM 0V tW VI VM input nCD 0V tW VOH output nQ 001aag088 VOL Recovery times are shown as positive values but may be specified as negative values. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Measurement points are given in Table 9. Fig. 5. nSD, nCD recovery time and pulse width Table 9. Measurement points Supply voltage Input Output VDD VM VM VX VY 5 V to 15 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD VDD G VI VO DUT CL RT 001aag182 Test and measurement data is given in Table 10; Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig. 6. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD ≤ 20 ns 50 pF HEF4013B Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 10 — 23 November 2021 © Nexperia B.V. 2021. All rights reserved 8 / 14 HEF4013B Nexperia Dual D-type flip-flop 12. Application information D D Q D FF 1 Q D FF 2 CP Q CP Q FF n Q CP Q clock Fig. 7. 001aag089 N-stage shift register D Q D FF 1 clock Q D FF 2 CP Q CP Q Q FF n Q CP Q T-type flip-flop Fig. 8. Q 001aag090 n Binary ripple up-counter; divide-by-2 D Q FF 1 CP D Q FF 2 Q CP D Q Q FF n Q CP Q clock 001aag091 Fig. 9. Modified ring counter; divide-by-(n + 1) HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 23 November 2021 © Nexperia B.V. 2021. All rights reserved 9 / 14 HEF4013B Nexperia Dual D-type flip-flop 13. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 10. Package outline SOT108-1 (SO14) HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 23 November 2021 © Nexperia B.V. 2021. All rights reserved 10 / 14 HEF4013B Nexperia Dual D-type flip-flop TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 11. Package outline SOT402-1 (TSSOP14) HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 23 November 2021 © Nexperia B.V. 2021. All rights reserved 11 / 14 HEF4013B Nexperia Dual D-type flip-flop 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4013B v.10 20211123 Product data sheet - HEF4013B v.9 Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 and Section 2 updated. Table 4: Derating values for Ptot total power dissipation updated. HEF4013B v.9 20151210 Modifications: • HEF4013B v.8 20111121 Modifications: • • HEF4013B v.7 20110913 Product data sheet - HEF4013B v.6 HEF4013B v.6 20091027 Product data sheet - HEF4013B v.5 HEF4013B v.5 20090619 Product data sheet - HEF4013B v.4 HEF4013B v.4 20080515 Product data sheet - HEF4013B_CNV v.3 HEF4013B_CNV v.3 19950101 Product specification - HEF4013B_CNV v.2 HEF4013B_CNV v.2 19950101 Product specification - - HEF4013B Product data sheet Product data sheet - HEF4013B v.8 Type number HEF4013BP (SOT27-1) removed. Product data sheet - HEF4013B v.7 Legal pages updated. Changes in "General description", "Features and benefits" and "Applications". All information provided in this document is subject to legal disclaimers. Rev. 10 — 23 November 2021 © Nexperia B.V. 2021. All rights reserved 12 / 14 HEF4013B Nexperia Dual D-type flip-flop 16. Legal information injury, death or severe property or environmental damage. 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Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 10 — 23 November 2021 © Nexperia B.V. 2021. All rights reserved 13 / 14 HEF4013B Nexperia Dual D-type flip-flop Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................1 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................6 11.1. Waveforms and test circuit........................................ 7 12. Application information............................................. 9 13. Package outline........................................................ 10 14. Abbreviations............................................................ 12 15. Revision history........................................................12 16. Legal information......................................................13 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 23 November 2021 HEF4013B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 23 November 2021 © Nexperia B.V. 2021. All rights reserved 14 / 14