nRF52811
Product Specification
v1.1
4454_140 v1.1 / 2021-12-21
Feature list
Features:
•
®
Bluetooth 5.1, IEEE 802.15.4-2006, 2.4 GHz transceiver
•
®
-97 dBm sensitivity in 1 Mbps Bluetooth low energy mode
Nordic SoftDevice ready
-104 dBm sensitivity in 125 kbps Bluetooth low energy mode (long range)
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Support for concurrent multi-protocol
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-20 to +4 dBm TX power, configurable in 4 dB steps
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12-bit, 200 ksps ADC that has 8 configurable channels with
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On-air compatible with nRF52, nRF51, nRF24L, and nRF24AP Series
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Supported data rates:
®
programmable gain
®
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Bluetooth 5.1: 2 Mbps, 1 Mbps, 500 kbps, and 125 kbps
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IEEE 802.15.4-2006: 250 kbps
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Proprietary 2.4 GHz: 2 Mbps, 1 Mbps
Angle-of-arrival (AoA) and angle-of-departure (AoD) direction finding using
®
Bluetooth .
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Single-ended antenna output (on-chip balun)
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4.6 mA peak current in TX (0 dBm)
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4.6 mA peak current in RX
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192 kB flash and 24 kB RAM
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•
•
•
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RSSI (1 dB resolution)
®
®
ARM Cortex -M4 32-bit processor, 64 MHz
®
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144 EEMBC CoreMark score running from flash memory
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34.4 µA/MHz running CoreMark from flash memory
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32.8 µA/MHz running CoreMark from RAM memory
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Serial wire debug (SWD)
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64 level comparator
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Temperature sensor
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Up to 32 general purpose I/O pins
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4-channel pulse width modulator (PWM) unit with EasyDMA
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Digital microphone interface (PDM)
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3x 32-bit timer with counter mode
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2x SPI master/slave with EasyDMA
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I2C compatible two-wire master/slave
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UART (CTS/RTS) with EasyDMA
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Programmable peripheral interconnect (PPI)
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Quadrature decoder (QDEC)
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AES HW encryption with EasyDMA
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2x real-time counter (RTC)
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Single crystal operation
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Package variants
Flexible power management
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1.7 V to 3.6 V supply voltage range
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Fully automatic LDO and DC/DC regulator system
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Fast wake-up using 64 MHz internal oscillator
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0.3 µA at 3 V in System OFF mode, no RAM retention
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0.5 µA at 3 V in System OFF mode with full 24 kB RAM retention
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1.5 µA at 3 V in System ON mode, with full 24 kB RAM retention, wake on
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QFN48 package, 6 x 6 mm
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QFN32 package, 5 x 5 mm
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WLCSP package, 2.482 x 2.464 mm
RTC
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1.4 µA at 3 V in System ON mode, no RAM retention, wake on RTC
Applications:
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Computer peripherals and I/O devices
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Health and medical
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Mouse
•
Enterprise lighting
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Keyboard
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Industrial
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Mobile HID
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Commercial
•
Retail
•
CE remote controls
•
Network processor
•
Beacons
•
Wearables
•
Connectivity device in multi-chip solutions
•
Virtual reality headsets
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Contents
Feature list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
1
Revision history.
2
About this document.
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2.1 Document status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Peripheral chapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Register tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Fields and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 DUMMY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Block diagram.
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Core components.
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4.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 CPU and support module configuration . . . . . . . . . . . . . . . . . . . . .
4.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 RAM - Random access memory . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Flash - Non-volatile memory . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4 Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 NVMC — Non-volatile memory controller . . . . . . . . . . . . . . . . . . . . . .
4.3.1 Writing to flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 Erasing a page in flash . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3 Writing to user information configuration registers (UICR) . . . . . . . . . . . . .
4.3.4 Erasing user information configuration registers (UICR) . . . . . . . . . . . . . . .
4.3.5 Erase all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.6 Partial erase of a page in flash . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 FICR — Factory information configuration registers . . . . . . . . . . . . . . . . . .
4.4.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 UICR — User information configuration registers . . . . . . . . . . . . . . . . . . .
4.5.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1 EasyDMA error handling . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2 EasyDMA array list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 AHB multilayer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.1 DAP - Debug access port . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.2 Access port protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3 CTRL-AP - Control access port . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.4 Debug Interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.5 Real-time debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Power and clock management.
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5.1 Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 POWER — Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2 System OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 System ON mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.4 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.5 RAM power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.7 Retained registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.8 Reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 CLOCK — Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1 HFCLK clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2 LFCLK clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Peripherals.
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6.1 Peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.1.1 Peripheral ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.1.2 Peripherals with shared ID . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.3 Peripheral registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
6.1.4 Bit set and clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.5 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.6 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.7 Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2 AAR — Accelerated address resolver . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2.2 Resolving a resolvable address . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2.3 Use case example for chaining RADIO packet reception with address resolution using AAR . 81
6.2.4 IRK data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.2.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.2.6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3 BPROT — Block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.4 CCM — AES CCM mode encryption . . . . . . . . . . . . . . . . . . . . . . . . 88
6.4.1 Keystream generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.4.2 Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.4.3 Decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.4.4 AES CCM and RADIO concurrent operation . . . . . . . . . . . . . . . . . . . . 90
6.4.5 Encrypting packets on-the-fly in radio transmit mode . . . . . . . . . . . . . . . 90
6.4.6 Decrypting packets on-the-fly in RADIO receive mode . . . . . . . . . . . . . . . 91
6.4.7 CCM data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.4.8 EasyDMA and ERROR event . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.4.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.4.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.5 COMP — Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.5.1 Differential mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.5.2 Single-ended mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.5.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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6.5.4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 ECB — AES electronic codebook mode encryption . . . . . . . . . . . . . . . . . .
6.6.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.2 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.3 ECB data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 EGU — Event generator unit . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8 GPIO — General purpose input/output . . . . . . . . . . . . . . . . . . . . . .
6.8.1 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9 GPIOTE — GPIO tasks and events . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.1 Pin events and tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.2 Port event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.3 Tasks and events pin configuration . . . . . . . . . . . . . . . . . . . . . .
6.9.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 PDM — Pulse density modulation interface . . . . . . . . . . . . . . . . . . . .
6.10.1 Master clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.2 Module operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.3 Decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.4 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.5 Hardware example . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 PPI — Programmable peripheral interconnect . . . . . . . . . . . . . . . . . . .
6.11.1 Pre-programmed channels . . . . . . . . . . . . . . . . . . . . . . . . .
6.11.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 PWM — Pulse width modulation . . . . . . . . . . . . . . . . . . . . . . . .
6.12.1 Wave counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.2 Decoder with EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 QDEC — Quadrature decoder . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.1 Sampling and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.2 LED output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.3 Debounce filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.4 Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.5 Output/input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14 RADIO — 2.4 GHz radio . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.1 Packet configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.2 Address configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.3 Data whitening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.4 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.5 Radio states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.6 Transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6.14.7 Receive sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.8 Received signal strength indicator (RSSI) . . . . . . . . . . . . . . . . . . . .
6.14.9 Interframe spacing (IFS) . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.10 Device address match . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.11 Bit counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.12 Direction finding . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.13 IEEE 802.15.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.14 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.15 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.16 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15 RNG — Random number generator . . . . . . . . . . . . . . . . . . . . . . .
6.15.1 Bias correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15.2 Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15.4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16 RTC — Real-time counter . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.1 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.2 Resolution versus overflow and the PRESCALER . . . . . . . . . . . . . . . . .
6.16.3 COUNTER register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.4 Overflow features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.5 TICK event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.6 Event control feature . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.7 Compare feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.8 TASK and EVENT jitter/delay . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.9 Reading the COUNTER register . . . . . . . . . . . . . . . . . . . . . . .
6.16.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17 SAADC — Successive approximation analog-to-digital converter . . . . . . . . . . . .
6.17.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.3 Digital output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.4 Analog inputs and channels . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.5 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.6 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.7 Resistor ladder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.8 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.9 Acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.10 Limits event monitoring . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.11 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.12 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.13 Performance factors . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.18 SPI — Serial peripheral interface master . . . . . . . . . . . . . . . . . . . . .
6.18.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.18.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.18.3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19 SPIM — Serial peripheral interface master with EasyDMA . . . . . . . . . . . . . .
6.19.1 SPI master transaction sequence . . . . . . . . . . . . . . . . . . . . . . .
6.19.2 Master mode pin configuration . . . . . . . . . . . . . . . . . . . . . . .
6.19.3 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19.4 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19.6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20 SPIS — Serial peripheral interface slave with EasyDMA . . . . . . . . . . . . . . . .
6.20.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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190
190
191
192
192
197
206
207
242
248
248
248
248
251
251
251
251
252
253
253
253
254
256
258
259
264
264
264
264
265
266
266
268
269
270
270
271
272
286
287
287
288
291
294
295
296
297
298
298
298
307
308
309
6.20.2 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20.3 SPI slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20.4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20.6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.21 SWI — Software interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.21.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.22 TEMP — Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . .
6.22.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.22.2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23 TWI — I2C compatible two-wire interface . . . . . . . . . . . . . . . . . . . . .
6.23.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23.2 Master mode pin configuration . . . . . . . . . . . . . . . . . . . . . . .
6.23.3 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23.4 Master write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23.5 Master read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23.6 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . .
6.23.7 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23.9 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24 TIMER — Timer/counter . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24.1 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24.2 Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24.3 Task delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24.4 Task priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25 TWIM — I2C compatible two-wire interface master with EasyDMA . . . . . . . . . . .
6.25.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25.2 Master write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25.3 Master read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25.4 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . .
6.25.5 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25.6 Master mode pin configuration . . . . . . . . . . . . . . . . . . . . . . .
6.25.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25.9 Pullup resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.26 TWIS — I2C compatible two-wire interface slave with EasyDMA . . . . . . . . . . . .
6.26.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.26.2 TWI slave responding to a read command . . . . . . . . . . . . . . . . . . .
6.26.3 TWI slave responding to a write command . . . . . . . . . . . . . . . . . . .
6.26.4 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . .
6.26.5 Terminating an ongoing TWI transaction . . . . . . . . . . . . . . . . . . . .
6.26.6 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.26.7 Slave mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . .
6.26.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.26.9 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27 UART — Universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . .
6.27.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.3 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.4 Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.5 Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.6 Suspending the UART . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.7 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4454_140 v1.1
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309
311
312
322
324
324
324
325
331
331
331
332
332
333
333
334
335
335
343
344
345
345
345
345
346
350
351
352
353
354
355
355
355
366
367
367
370
370
371
372
373
373
373
374
384
384
385
385
385
385
386
387
387
6.27.8 Using the UART without flow control . . . . . . . . . . . . . . . . . . . . .
6.27.9 Parity and stop bit configuration . . . . . . . . . . . . . . . . . . . . . . .
6.27.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28 UARTE — Universal asynchronous receiver/transmitter with EasyDMA . . . . . . . . .
6.28.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.2 Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.3 Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.4 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.5 Using the UARTE without flow control . . . . . . . . . . . . . . . . . . . .
6.28.6 Parity and stop bit configuration . . . . . . . . . . . . . . . . . . . . . . .
6.28.7 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.8 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29 WDT — Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.1 Reload criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.2 Temporarily pausing the watchdog . . . . . . . . . . . . . . . . . . . . . .
6.29.3 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Hardware and layout.
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1 QFN48 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.2 QFN32 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.3 WLCSP ball assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.4 GPIO pins located near the radio . . . . . . . . . . . . . . . . . . . . . . .
7.2 Mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1 QFN48 6 x 6 mm package . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2 QFN32 5 x 5 mm package . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.3 WLCSP 2.482 x 2.464 mm package . . . . . . . . . . . . . . . . . . . . . .
7.3 Reference circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.1 Schematic QFAA QFN48 with internal LDO regulator setup . . . . . . . . . . . . .
7.3.2 Schematic QFAA QFN48 with DC/DC regulator setup . . . . . . . . . . . . . . .
7.3.3 Schematic QCAA QFN32 with internal LDO regulator setup . . . . . . . . . . . . .
7.3.4 Schematic QCAA QFN32 with DC/DC regulator setup . . . . . . . . . . . . . . .
7.3.5 Schematic CAAA WLCSP with internal LDO regulator setup . . . . . . . . . . . . .
7.3.6 Schematic CAAA WLCSP with DC/DC regulator setup . . . . . . . . . . . . . . .
7.3.7 Schematic CAAA WLCSP with two layers . . . . . . . . . . . . . . . . . . . .
7.3.8 PCB guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.9 PCB layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
9
Recommended operating conditions.
387
387
387
396
396
397
397
398
400
400
400
400
401
401
414
414
415
415
415
415
419
420
420
420
422
424
427
427
427
428
428
429
429
430
431
432
433
434
436
437
438
. . . . . . . . . . . . . . . . . . .
440
8.1 WLCSP light sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
440
Absolute maximum ratings.
10 Ordering information.
10.1
10.2
10.3
10.4
. . . . . . . . . . . . . . . . . . . . . . . .
441
. . . . . . . . . . . . . . . . . . . . . . . . . . .
442
Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Box labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Code ranges and values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4454_140 v1.1
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442
443
444
10.5 Product options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 Legal notices.
4454_140 v1.1
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ix
445
447
1
Revision history
Date
Version
Description
December 2021
1.1
The following content has been added or updated:
• POWER — Power supply on page 51 - Added Wake
from System OFF reset source for the WDT in reference to
Erratum-213
• Debug on page 38 - Updated access port protection
• UICR - Added NRFMDK registers and updated access port
protection
• RADIO - Updated conversion formula for PRF and registers
DFEPACKET.MAXCNT, DFEGPIO, and EDSAMPLE
• Updated minimum valid value for EasyDMA registers
MAXCNT and AMOUNT in the following:
•
•
•
•
•
February 2019
4454_140 v1.1
1.0
• SPIM
• SPIS
• TWIM
• TWIS
• UARTE
TWIM - Updated tTWIM,HD_STA parameters
Mechanical specifications on page 427 - Updated
WLCSP mechanical specification
Absolute maximum ratings on page 441 - Updated flash
memory retention to 10 years at 85 °C
Ordering information on page 442 - Updated product
options and box labels
Editorial
First release
10
2
About this document
This document is organized into chapters that are based on the modules and peripherals available in the
IC.
2.1 Document status
The document status reflects the level of maturity of the document.
Document name
Description
Objective Product Specification (OPS)
Applies to document versions up to 1.0.
This document contains target specifications for
product development.
Product Specification (PS)
Applies to document versions 1.0 and higher.
This document contains final product
specifications. Nordic Semiconductor ASA reserves
the right to make changes at any time without
notice in order to improve design and supply the
best possible product.
Table 1: Defined document names
2.2 Peripheral chapters
Every peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used for
identification and reference. This name is used in chapter headings and references, and it will appear in
the ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer to
identify the peripheral.
The peripheral instance name, which is different from the peripheral name, is constructed using the
peripheral name followed by a numbered postfix, starting with 0, for example, TIMER0. A postfix is
normally only used if a peripheral can be instantiated more than once. The peripheral instance name is
also used in the CMSIS to identify the peripheral instance.
The chapters describing peripherals may include the following information:
• A detailed functional description of the peripheral
• Register configuration for the peripheral
• Electrical specification tables, containing performance data which apply for the operating conditions
described in Recommended operating conditions on page 440.
2.3 Register tables
Individual registers are described using register tables. These tables are built up of two sections. The first
three colored rows describe the position and size of the different fields in the register. The following rows
describe the fields in more detail.
4454_140 v1.1
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About this document
2.3.1 Fields and values
The Id (Field Id) row specifies the bits that belong to the different fields in the register. If a field has
enumerated values, then every value will be identified with a unique value id in the Value Id column.
A blank space means that the field is reserved and read as undefined, and it also must be written as 0
to secure forward compatibility. If a register is divided into more than one field, a unique field name is
specified for each field in the Field column. The Value Id may be omitted in the single-bit bit fields when
values can be substituted with a Boolean type enumerator range, e.g. true/false, disable(d)/enable(d), on/
off, and so on.
Values are usually provided as decimal or hexadecimal. Hexadecimal values have a 0x prefix, decimal
values have no prefix.
The Value column can be populated in the following ways:
• Individual enumerated values, for example 1, 3, 9.
• Range of values, e.g. [0..4], indicating all values from and including 0 and 4.
• Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or
alternatively the field's translation and limitations are described in the text instead.
If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all but
the first field. Subsequent fields will indicate inheritance with '..'.
A feature marked Deprecated should not be used for new designs.
2.3.2 Permissions
Different fields in a register might have different access permissions enforced by hardware.
The access permission for each register field is documented in the Access column in the following ways:
Access
Description
Hardware behavior
RO
Read-only
Field can only be read. A write will be ignored.
WO
Write-only
Field can only be written. A read will return an undefined value.
RW
Read-write
Field can be read and written multiple times.
W1
Write-once
Field can only be written once per reset. Any subsequent write will be ignored. A read will return an undefined value.
RW1
Read-write-once
Field can be read multiple times, but only written once per reset. Any subsequent write will be ignored.
Table 2: Register field permission schemes
2.4 Registers
Register
Offset
Description
DUMMY
0x514
Example of a register controlling a dummy feature
Table 3: Register overview
2.4.1 DUMMY
Address offset: 0x514
Example of a register controlling a dummy feature
4454_140 v1.1
12
About this document
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D D D D
Reset 0x00050002
ID
Access
Field
A
RW FIELD_A
C C C
B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value ID
Value
Description
Example of a read-write field with several enumerated
values
Disabled
0
The example feature is disabled
NormalMode
1
The example feature is enabled in normal mode
ExtendedMode
2
The example feature is enabled along with extra
functionality
B
RW FIELD_B
C
RW FIELD_C
D
RW FIELD_D
Example of a deprecated read-write field
Disabled
0
The override feature is disabled
Enabled
1
The override feature is enabled
Example of a read-write field with a valid range of values
ValidRange
[2..7]
Example of allowed values for this field
Example of a read-write field with no restriction on the
values
4454_140 v1.1
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Deprecated
Block diagram
This block diagram illustrates the overall system. Arrows with white heads indicate signals that share
physical pins with other signals.
CTRL-AP
NVIC
slave
slave
slave
CPU
ARM
CORTEX-M4
slave
AHB multilayer
AHB-AP
nRESET
P0
(P0.0 – P0.31)
GPIO
slave
RAM2
slave
SW-DP
RAM1
slave
SWCLK
SWDIO
RAM0
slave
nRF52811
master
AHB TO APB
BRIDGE
FICR
UICR
Flash
SysTick
NVMC
RNG
POWER
RTC [0..1]
TIMER [0..2]
WDT
TEMP
PPI
XC1
XC2
XL1
XL2
CLOCK
ANT
RADIO
ECB
master
EasyDMA
master
EasyDMA
master
mast AAR
er
EasyDMA
CCM
EasyDMA
master
APB0
3
P0
(P0.0 – P0.31)
SPIM [0..1]
master
GPIOTE
COMP
AIN0 – AIN7
EasyDMA
LED
A
B
OUT[0] - OUT[3]
master
EasyDMA
master
EasyDMA
TWIM
master
QDEC
UARTE
PWM
EasyDMA
CLK
DIN
master
master
PDM
EasyDMA
master
Figure 1: Block diagram
14
SCL
SDA
SCL
SDA
RTS
CTS
TXD
RXD
EasyDMA
SPIS [0..1]
master
4454_140 v1.1
EasyDMA
TWIS
SAADC
SCK
MOSI
MISO
EasyDMA
CSN
MISO
MOSI
SCK
4
Core components
4.1 CPU
The ARM® Cortex®-M4 processor has a 32-bit instruction set (Thumb®-2 technology) that implements a
superset of 16- and 32-bit instructions to maximize code density and performance.
This processor implements several features that enable energy-efficient arithmetic and high-performance
signal processing including:
•
•
•
•
Digital signal processing (DSP) instructions
Single-cycle multiply and accumulate (MAC) instructions
Hardware divide
8- and 16-bit single instruction multiple data (SIMD) instructions
The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the
ARM Cortex processor series is implemented and available for the M4 CPU.
Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling
events at configurable priority levels via the nested vectored interrupt controller (NVIC).
Executing code from flash will have a wait state penalty on the nRF52 Series. The section Electrical
specification on page 15 shows CPU performance parameters including wait states in different modes,
CPU current and efficiency, and processing power and efficiency based on the CoreMark® benchmark.
The ARM System Timer (SysTick) is present on the device. The SysTick's clock will only tick when the CPU is
running or when the system is in debug interface mode.
4.1.1 Electrical specification
4.1.1.1 CPU performance
The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is
executing the CoreMark® benchmark. It includes power regulator and clock base currents. All other blocks
are IDLE.
Symbol
Description
Min.
WFLASH
CPU wait states, running from flash
0
Typ.
Max.
Units
WRAM
CPU wait states, running from RAM
CMFLASH
CoreMark1, running from flash
144
CoreMark
CMFLASH/MHz
CoreMark per MHz, running from flash
2.25
CoreMark/
CMFLASH/mA
CoreMark per mA, running from flash, DCDC 3V
65
2
0
MHz
CoreMark/
mA
4.1.2 CPU and support module configuration
The ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on the
device.
1
Using IAR v6.50.1.4452 with flags --endian=little --cpu=Cortex-M4 -e --fpu=VFPv4_sp –Ohs -no_size_constraints
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Core components
Option / Module
Description
Implemented
NVIC
Nested vector interrupt controller
30 vectors
PRIORITIES
Priority bits
3
WIC
Wakeup interrupt controller
NO
Endianness
Memory system endianness
Little endian
Bit-banding
Bit banded memory
NO
DWT
Data watchpoint and trace
NO
SysTick
System tick timer
YES
MPU
Memory protection unit
YES
FPU
Floating-point unit
NO
DAP
Debug access port
YES
ETM
Embedded trace macrocell
NO
ITM
Instrumentation trace macrocell
NO
TPIU
Trace port interface unit
NO
ETB
Embedded trace buffer
NO
FPB
Flash patch and breakpoint unit
YES
HTM
AMBA AHB trace macrocell
Core options
Modules
®
NO
4.2 Memory
The nRF52811 contains flash and RAM that can be used for code and data storage.
The amount of RAM and flash differs depending on variant, see Memory variants on page 16.
Device name
RAM
Flash
nRF52811-QFAA
24 kB
192 kB
nRF52811-QCAA
24 kB
192 kB
nRF52811-CAAA
24 kB
192 kB
Table 4: Memory variants
The CPU and peripherals with EasyDMA can access memory via the AHB multilayer interconnect. The CPU
is also able to access peripherals via the AHB multilayer interconnect, as illustrated in Memory layout on
page 17.
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Core components
AHB2APB
APB
CPU
System bus
EasyDMA
ICODE
EasyDMA
DMA bus
Peripheral
DMA bus
Peripheral
DCODE
ARM Cortex-M4
Data RAM
System
Code RAM
ICODE/DCODE
RAM2
AHB slave
Section 1
0x20005000
0x00805000
Section 0
0x20004000
0x00804000
RAM1
AHB slave
Section 1
0x20003000
0x00803000
Section 0
0x20002000
0x00802000
RAM0
AHB slave
Section 1
0x20001000
0x00801000
Section 0
0x20000000
0x00800000
AHB multilayer interconnect
NVMC
DCODE
AHB
slave
ICODE
AHB
AHB
slave
Page 47
Flash
ICODE/DCODE
0x0002F000
Page 3..46
0x00003000
Page 2
Page 1
Page 0
0x00002000
0x00001000
Block 7
0x00000E00
Block 2..6
0x00000400
Block 1
0x00000200
Block 0
0x00000000
Figure 2: Memory layout
See AHB multilayer on page 38 and EasyDMA on page 35 for more information about the AHB
multilayer interconnect and the EasyDMA.
The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to the
application to partition the RAM within these regions so that one does not corrupt the other.
4.2.1 RAM - Random access memory
The RAM interface is divided into three RAM AHB slaves.
RAM AHB slaves 0 to 2 are connected to two 4 kB RAM sections each, as shown in Memory layout on page
17.
Each RAM section has separate power control for System ON and System OFF mode operation, which is
configured via RAM register (see the POWER — Power supply on page 51).
4.2.2 Flash - Non-volatile memory
The flash can be read an unlimited number of times by the CPU, but it has restrictions on the number of
times it can be written and erased, and also on how it can be written.
Writing to flash is managed by the non-volatile memory controller (NVMC), see NVMC — Non-volatile
memory controller on page 19.
The flash is divided into multiple 4 kB pages that can be accessed by the CPU via both the ICODE and
DCODE buses as shown in, Memory layout on page 17. Each page is divided into 8 blocks.
4.2.3 Memory map
The complete memory map is shown in Memory map on page 18. As described in Memory on page
16, Code RAM and Data RAM are the same physical RAM.
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Core components
Cortex M4 system address map
0xFFFFFFFF
0xE0100000
0xE0000000
Private peripheral bus
0x5FFFFFFF
AHB peripherals
0x50000000
APB peripherals
0x1FFFFFFF
0x10002000
0x40000000
UICR
0x10001000
FICR
0x10000000
0x00806000
Code RAM
0x00800000
0x00030000
Peripheral
0.5GB
SRAM
0.5GB
Code
0.5GB
0x3FFFFFFF
0x20006000
Data RAM
Flash
0x20000000
0x00000000
Figure 3: Memory map
4.2.4 Instantiation
ID
Base address
Peripheral
Instance
Description
0
0x40000000
APPROTECT
APPROTECT
APPROTECT control
0
0x40000000
BPROT
BPROT
Block protect
0
0x40000000
CLOCK
CLOCK
Clock control
0
0x40000000
POWER
POWER
Power control
0
0x50000000
GPIO
P0
General purpose input and output
1
0x40001000
RADIO
RADIO
2.4 GHz radio
2
0x40002000
UART
UART0
Universal asynchronous receiver/transmitter
2
0x40002000
UARTE
UARTE0
Universal asynchronous receiver/transmitter with EasyDMA
3
0x40003000
SPI
SPI1
SPI master 1
3
0x40003000
SPIM
SPIM1
SPI master 1
3
0x40003000
SPIS
SPIS1
SPI slave 1
3
0x40003000
TWI
TWI0
Two-wire interface master
3
0x40003000
TWIM
TWIM0
Two-wire interface master
3
0x40003000
TWIS
TWIS0
Two-wire interface slave
4
0x40004000
SPI
SPI0
SPI master 0
4
0x40004000
SPIM
SPIM0
SPI master 0
4
0x40004000
SPIS
SPIS0
SPI slave 0
6
0x40006000
GPIOTE
GPIOTE
GPIO tasks and events
7
0x40007000
SAADC
SAADC
Analog-to-digital converter
8
0x40008000
TIMER
TIMER0
Timer 0
9
0x40009000
TIMER
TIMER1
Timer 1
10
0x4000A000
TIMER
TIMER2
Timer 2
11
0x4000B000
RTC
RTC0
Real-time counter 0
12
0x4000C000
TEMP
TEMP
Temperature sensor
13
0x4000D000
RNG
RNG
Random number generator
14
0x4000E000
ECB
ECB
AES Electronic Codebook (ECB) mode block encryption
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Deprecated
Deprecated
Deprecated
Deprecated
Core components
ID
Base address
Peripheral
Instance
Description
15
0x4000F000
AAR
AAR
Accelerated address resolver
15
0x4000F000
CCM
CCM
AES CCM mode encryption
16
0x40010000
WDT
WDT
Watchdog timer
17
0x40011000
RTC
RTC1
Real-time counter 1
18
0x40012000
QDEC
QDEC
Quadrature decoder
19
0x40013000
COMP
COMP
General purpose comparator
20
0x40014000
EGU
EGU0
Event generator unit 0
20
0x40014000
SWI
SWI0
Software interrupt 0
21
0x40015000
EGU
EGU1
Event generator unit 1
21
0x40015000
SWI
SWI1
Software interrupt 1
22
0x40016000
SWI
SWI2
Software interrupt 2
23
0x40017000
SWI
SWI3
Software interrupt 3
24
0x40018000
SWI
SWI4
Software interrupt 4
25
0x40019000
SWI
SWI5
Software interrupt 5
28
0x4001C000
PWM
PWM0
Pulse-width modulation unit 0
29
0x4001D000
PDM
PDM
Pulse-density modulation (digital microphone interface)
30
0x4001E000
NVMC
NVMC
Non-volatile memory controller
31
0x4001F000
PPI
PPI
Programmable peripheral interconnect
N/A
0x10000000
FICR
FICR
Factory information configuration
N/A
0x10001000
UICR
UICR
User information configuration
Table 5: Instantiation table
4.3 NVMC — Non-volatile memory controller
The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory
and the UICR (user information configuration registers).
The CONFIG on page 21 is used to enable the NVMC for writing (CONFIG.WEN) and erasing
(CONFIG.EEN). The user must make sure that writing and erasing are not enabled at the same time. Having
both enabled at the same time may result in unpredictable behavior.
The CPU must be halted before initiating a NVMC operation from the debug system.
4.3.1 Writing to flash
When writing is enabled, full 32-bit words are written to word-aligned addresses in flash.
As illustrated in Memory on page 16, the flash is divided into multiple pages. The same 32-bit word in
the flash can only be written nWRITE number of times before a page erase must be performed.
The NVMC is only able to write 0 to bits in the flash that are erased (set to 1). It cannot rewrite a bit back
to 1. Only full 32-bit words can be written to flash using the NVMC interface. To write less than 32 bits,
write the data as a full 32-bit word and set all the bits that should remain unchanged in the word to 1.
Note that the restriction on the number of writes (nWRITE) still applies in this case.
Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.
The time it takes to write a word to flash is specified by tWRITE. The CPU is halted while the NVMC is writing
to the flash.
4.3.2 Erasing a page in flash
When erase is enabled, the flash memory can be erased page by page using the ERASEPAGE on page
21.
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Core components
After erasing a flash page, all bits in the page are set to 1. The time it takes to erase a page is specified
by tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the
flash.
See Partial erase of a page in flash on page 20 for information on dividing the page erase time into
shorter chunks.
4.3.3 Writing to user information configuration registers (UICR)
User information configuration registers (UICR) are written in the same way as flash. After UICR has been
written, the new UICR configuration will take effect after a reset.
UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR on
page 23 or ERASEALL on page 22. The time it takes to write a word to UICR is specified by tWRITE.
The CPU is halted while the NVMC is writing to the UICR.
4.3.4 Erasing user information configuration registers (UICR)
When erase is enabled, UICR can be erased using the ERASEUICR on page 23.
After erasing UICR all bits in UICR are set to 1. The time it takes to erase UICR is specified by tERASEPAGE. The
CPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation.
4.3.5 Erase all
When erase is enabled, flash and UICR can be erased completely in one operation by using ERASEALL on
page 22. This operation will not erase the factory information configuration registers (FICR).
The time it takes to perform an ERASEALL command is specified by tERASEALL. The CPU is halted if the CPU
executes code from the flash while the NVMC performs the erase operation.
4.3.6 Partial erase of a page in flash
Partial erase is a feature in the NVMC to split a page erase time into shorter chunks, so this can be used to
prevent longer CPU stalls in time-critical applications. Partial erase is only applicable to the code area in
the flash and does not work with UICR.
When erase is enabled, the partial erase of a flash page can be started by writing to ERASEPAGEPARTIAL
on page 23. The duration of a partial erase can be configured in ERASEPAGEPARTIALCFG on page
23. A flash page is erased when its erase time reaches tERASEPAGE. Use ERASEPAGEPARTIAL N number
of times so that N * ERASEPAGEPARTIALCFG ≥ tERASEPAGE, where N * ERASEPAGEPARTIALCFG gives the
cumulative (total) erase time. Every time the cumulative erase time reaches tERASEPAGE, it counts as one
erase cycle.
After the erase is done, all bits in the page are set to '1'. The CPU is halted if the CPU executes code from
the flash while the NVMC performs the partial erase operation.
The bits in the page are undefined if the flash page erase is incomplete, i.e. if a partial erase has started
but the total erase time is less than tERASEPAGE.
4.3.7 Registers
Base address
Peripheral
Instance
Description
0x4001E000
NVMC
NVMC
Non-volatile memory controller
Configuration
Table 6: Instances
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Core components
Register
Offset
Description
READY
0x400
Ready flag
CONFIG
0x504
Configuration register
ERASEPAGE
0x508
Register for erasing a page in code area
ERASEPCR1
0x508
Register for erasing a page in code area. Equivalent to ERASEPAGE.
ERASEALL
0x50C
Register for erasing all non-volatile user memory
ERASEPCR0
0x510
Register for erasing a page in code area. Equivalent to ERASEPAGE.
ERASEUICR
0x514
Register for erasing user information configuration registers
ERASEPAGEPARTIAL
0x518
Register for partial erase of a page in code area
ERASEPAGEPARTIALCFG
0x51C
Register for partial erase configuration
Deprecated
Deprecated
Table 7: Register overview
4.3.7.1 READY
Address offset: 0x400
Ready flag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000001
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value ID
Value
Description
Busy
0
NVMC is busy (ongoing write or erase operation)
Ready
1
NVMC is ready
READY
NVMC is ready or busy
4.3.7.2 CONFIG
Address offset: 0x504
Configuration register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A
Reset 0x00000000
ID
Access
Field
A
RW WEN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Program memory access mode. It is strongly recommended
to activate erase and write modes only when they are
actively used.
Ren
0
Read only access
Wen
1
Write enabled
Een
2
Erase enabled
4.3.7.3 ERASEPAGE
Address offset: 0x508
Register for erasing a page in code area
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Core components
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW ERASEPAGE
Value ID
Value
Description
Register for starting erase of a page in code area.
The value is the address to the page to be erased (addresses
of first word in page). Note that the erase must be enabled
using CONFIG.WEN before the page can be erased.
Attempts to erase pages that are outside the code area may
result in undesirable behavior, e.g. the wrong page may be
erased.
4.3.7.4 ERASEPCR1 ( Deprecated )
Address offset: 0x508
Register for erasing a page in code area. Equivalent to ERASEPAGE.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW ERASEPCR1
Value ID
Value
Description
Register for erasing a page in code area. Equivalent to
ERASEPAGE.
4.3.7.5 ERASEALL
Address offset: 0x50C
Register for erasing all non-volatile user memory
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW ERASEALL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Erase all non-volatile memory including UICR registers. Note
that the erase must be enabled using CONFIG.WEN before
the non-volatile memory can be erased.
NoOperation
0
No operation
Erase
1
Start erase of chip
4.3.7.6 ERASEPCR0 ( Deprecated )
Address offset: 0x510
Register for erasing a page in code area. Equivalent to ERASEPAGE.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW ERASEPCR0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Register for starting erase of a page in code area. Equivalent
to ERASEPAGE.
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Core components
4.3.7.7 ERASEUICR
Address offset: 0x514
Register for erasing user information configuration registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW ERASEUICR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Register starting erase of all user information configuration
registers. Note that the erase must be enabled using
CONFIG.WEN before the UICR can be erased.
NoOperation
0
No operation
Erase
1
Start erase of UICR
4.3.7.8 ERASEPAGEPARTIAL
Address offset: 0x518
Register for partial erase of a page in code area
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW ERASEPAGEPARTIAL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Register for starting partial erase of a page in code area
The value is the address to the page to be partially erased
(address of the first word in page). Note that the erase must
be enabled using CONFIG.WEN before every erase page
partial and disabled using CONFIG.WEN after every erase
page partial. Attempts to erase pages that are outside the
code area may result in undesirable behaviour, e.g. the
wrong page may be erased.
4.3.7.9 ERASEPAGEPARTIALCFG
Address offset: 0x51C
Register for partial erase configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A
Reset 0x0000000A
ID
Access
Field
A
RW DURATION
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
Value ID
Value
Description
Duration of the partial erase in milliseconds
The user must ensure that the total erase time is long
enough for a complete erase of the flash page.
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Core components
4.3.8 Electrical specification
4.3.8.1 Flash programming
Symbol
Description
nWRITE
Number of times a 32-bit word can be written before erase
Min.
nENDURANCE
Erase cycles per page
tWRITE
Time to write one 32-bit word
tERASEPAGE
Time to erase one page
tERASEALL
Time to erase all flash
Typ.
Max.
Units
2
10000
µs
412
ms
2
85
169
tERASEPAGEPARTIAL,acc Accuracy of the partial page erase duration. Total
2
ms
1.052
execution time for one partial page erase is defined as
ERASEPAGEPARTIALCFG * tERASEPAGEPARTIAL,acc.
4.4 FICR — Factory information configuration registers
Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by
the user. These registers contain chip-specific information and configuration.
4.4.1 Registers
Base address
Peripheral
Instance
Description
Configuration
0x10000000
FICR
FICR
Factory information configuration
Table 8: Instances
Register
Offset
Description
CODEPAGESIZE
0x010
Code memory page size
CODESIZE
0x014
Code memory size
DEVICEID[0]
0x060
Device identifier
DEVICEID[1]
0x064
Device identifier
ER[0]
0x080
Encryption root, word 0
ER[1]
0x084
Encryption root, word 1
ER[2]
0x088
Encryption root, word 2
ER[3]
0x08C
Encryption root, word 3
IR[0]
0x090
Identity root, word 0
IR[1]
0x094
Identity root, word 1
IR[2]
0x098
Identity root, word 2
IR[3]
0x09C
Identity root, word 3
DEVICEADDRTYPE
0x0A0
Device address type
DEVICEADDR[0]
0x0A4
Device address 0
DEVICEADDR[1]
0x0A8
Device address 1
INFO.PART
0x100
Part code
INFO.VARIANT
0x104
Part variant, hardware version and production configuration
INFO.PACKAGE
0x108
Package option
INFO.RAM
0x10C
RAM variant
INFO.FLASH
0x110
Flash variant
INFO.UNUSED8[0]
0x114
2
Reserved
HFXO is used here
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Core components
Register
Offset
Description
INFO.UNUSED8[1]
0x118
INFO.UNUSED8[2]
0x11C
TEMP.A0
0x404
Slope definition A0
TEMP.A1
0x408
Slope definition A1
TEMP.A2
0x40C
Slope definition A2
TEMP.A3
0x410
Slope definition A3
TEMP.A4
0x414
Slope definition A4
TEMP.A5
0x418
Slope definition A5
TEMP.B0
0x41C
Y-intercept B0
TEMP.B1
0x420
Y-intercept B1
TEMP.B2
0x424
Y-intercept B2
TEMP.B3
0x428
Y-intercept B3
TEMP.B4
0x42C
Y-intercept B4
TEMP.B5
0x430
Y-intercept B5
TEMP.T0
0x434
Segment end T0
TEMP.T1
0x438
Segment end T1
TEMP.T2
0x43C
Segment end T2
TEMP.T3
0x440
Segment end T3
TEMP.T4
0x444
Segment end T4
Reserved
Reserved
Table 9: Register overview
4.4.1.1 CODEPAGESIZE
Address offset: 0x010
Code memory page size
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00001000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
CODEPAGESIZE
Code memory page size
4.4.1.2 CODESIZE
Address offset: 0x014
Code memory size
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000030
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
Value ID
Value
Description
CODESIZE
Code memory size in number of pages
Total code space is: CODEPAGESIZE * CODESIZE
4.4.1.3 DEVICEID[n] (n=0..1)
Address offset: 0x060 + (n × 0x4)
Device identifier
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Core components
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
R
Value ID
Value
Description
DEVICEID
64 bit unique device identifier
DEVICEID[0] contains the least significant bits of the device
identifier. DEVICEID[1] contains the most significant bits of
the device identifier.
4.4.1.4 ER[n] (n=0..3)
Address offset: 0x080 + (n × 0x4)
Encryption root, word n
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
ER
Encryption root, word n
4.4.1.5 IR[n] (n=0..3)
Address offset: 0x090 + (n × 0x4)
Identity root, word n
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
R
Value ID
Value
Description
IR
Identity root, word n
4.4.1.6 DEVICEADDRTYPE
Address offset: 0x0A0
Device address type
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
DEVICEADDRTYPE
Device address type
Public
0
Public address
Random
1
Random address
4.4.1.7 DEVICEADDR[n] (n=0..1)
Address offset: 0x0A4 + (n × 0x4)
Device address n
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26
Core components
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
R
Value ID
Value
Description
DEVICEADDR
48 bit device address
DEVICEADDR[0] contains the least significant bits of
the device address. DEVICEADDR[1] contains the most
significant bits of the device address. Only bits [15:0] of
DEVICEADDR[1] are used.
4.4.1.8 INFO.PART
Address offset: 0x100
Part code
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00052811
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1
Value ID
Value
Description
N52810
0x52810
nRF52810
N52811
0x52811
nRF52811
N52832
0x52832
nRF52832
Unspecified
0xFFFFFFFF
Unspecified
PART
Part code
4.4.1.9 INFO.VARIANT
Address offset: 0x104
Part variant, hardware version and production configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
R
Value ID
Value
Description
VARIANT
Part variant, hardware version and production
configuration, encoded as ASCII
AAAA
0x41414141
AAAA
AAA0
0x41414130
AAA0
AABA
0x41414241
AABA
AABB
0x41414242
AABB
AAB0
0x41414230
AAB0
AACA
0x41414341
AACA
AACB
0x41414342
AACB
AAC0
0x41414330
AAC0
Unspecified
0xFFFFFFFF
Unspecified
4.4.1.10 INFO.PACKAGE
Address offset: 0x108
Package option
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27
Core components
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
R
Value ID
Value
Description
QF
0x2000
QFxx - 48-pin QFN
QC
0x2003
QCxx - 32-pin QFN
CA
0x2004
CAxx - WLCSP
Unspecified
0xFFFFFFFF
Unspecified
PACKAGE
Package option
4.4.1.11 INFO.RAM
Address offset: 0x10C
RAM variant
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000018
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Value ID
Value
Description
K24
0x18
24 kByte RAM
Unspecified
0xFFFFFFFF
Unspecified
RAM
RAM variant
4.4.1.12 INFO.FLASH
Address offset: 0x110
Flash variant
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x000000C0
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Value ID
Value
Description
K192
0xC0
192 kByte flash
Unspecified
0xFFFFFFFF
Unspecified
FLASH
Flash variant
4.4.1.13 TEMP.A0
Address offset: 0x404
Slope definition A0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
A
A (slope definition) register
4.4.1.14 TEMP.A1
Address offset: 0x408
Slope definition A1
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Core components
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
A
A (slope definition) register
4.4.1.15 TEMP.A2
Address offset: 0x40C
Slope definition A2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
A
A (slope definition) register
4.4.1.16 TEMP.A3
Address offset: 0x410
Slope definition A3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
A
A (slope definition) register
4.4.1.17 TEMP.A4
Address offset: 0x414
Slope definition A4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
A
A (slope definition) register
4.4.1.18 TEMP.A5
Address offset: 0x418
Slope definition A5
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
A
4454_140 v1.1
A (slope definition) register
29
Core components
4.4.1.19 TEMP.B0
Address offset: 0x41C
Y-intercept B0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
B
B (y-intercept)
4.4.1.20 TEMP.B1
Address offset: 0x420
Y-intercept B1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
B
B (y-intercept)
4.4.1.21 TEMP.B2
Address offset: 0x424
Y-intercept B2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
B
B (y-intercept)
4.4.1.22 TEMP.B3
Address offset: 0x428
Y-intercept B3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
B
B (y-intercept)
4.4.1.23 TEMP.B4
Address offset: 0x42C
Y-intercept B4
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Core components
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
B
B (y-intercept)
4.4.1.24 TEMP.B5
Address offset: 0x430
Y-intercept B5
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
B
B (y-intercept)
4.4.1.25 TEMP.T0
Address offset: 0x434
Segment end T0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
T
T (segment end) register
4.4.1.26 TEMP.T1
Address offset: 0x438
Segment end T1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
T
T (segment end) register
4.4.1.27 TEMP.T2
Address offset: 0x43C
Segment end T2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
T
4454_140 v1.1
T (segment end) register
31
Core components
4.4.1.28 TEMP.T3
Address offset: 0x440
Segment end T3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
T
T (segment end) register
4.4.1.29 TEMP.T4
Address offset: 0x444
Segment end T4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
T
T (segment end) register
4.5 UICR — User information configuration registers
The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for
configuring user-specific settings.
For information on writing UICR registers, see the NVMC — Non-volatile memory controller on page
19 and Memory on page 16 chapters.
4.5.1 Registers
Base address
Peripheral
Instance
Description
0x10001000
UICR
UICR
User information configuration
Configuration
Table 10: Instances
Register
Offset
UNUSED0
0x000
Reserved
UNUSED1
0x004
Reserved
UNUSED2
0x008
Reserved
UNUSED3
0x010
NRFFW[0]
0x014
Reserved for Nordic firmware design
NRFFW[1]
0x018
Reserved for Nordic firmware design
NRFFW[2]
0x01C
Reserved for Nordic firmware design
NRFFW[3]
0x020
Reserved for Nordic firmware design
NRFFW[4]
0x024
Reserved for Nordic firmware design
NRFFW[5]
0x028
Reserved for Nordic firmware design
NRFFW[6]
0x02C
Reserved for Nordic firmware design
NRFFW[7]
0x030
Reserved for Nordic firmware design
4454_140 v1.1
Description
Reserved
32
Core components
Register
Offset
Description
NRFFW[8]
0x034
Reserved for Nordic firmware design
NRFFW[9]
0x038
Reserved for Nordic firmware design
NRFFW[10]
0x03C
Reserved for Nordic firmware design
NRFFW[11]
0x040
Reserved for Nordic firmware design
NRFFW[12]
0x044
Reserved for Nordic firmware design
NRFHW[0]
0x050
Reserved for Nordic hardware design
NRFHW[1]
0x054
Reserved for Nordic hardware design
NRFHW[2]
0x058
Reserved for Nordic hardware design
NRFHW[3]
0x05C
Reserved for Nordic hardware design
NRFHW[4]
0x060
Reserved for Nordic hardware design
NRFHW[5]
0x064
Reserved for Nordic hardware design
NRFHW[6]
0x068
Reserved for Nordic hardware design
NRFHW[7]
0x06C
Reserved for Nordic hardware design
NRFHW[8]
0x070
Reserved for Nordic hardware design
NRFHW[9]
0x074
Reserved for Nordic hardware design
NRFHW[10]
0x078
Reserved for Nordic hardware design
NRFHW[11]
0x07C
Reserved for Nordic hardware design
CUSTOMER[0]
0x080
Reserved for customer
CUSTOMER[1]
0x084
Reserved for customer
CUSTOMER[2]
0x088
Reserved for customer
CUSTOMER[3]
0x08C
Reserved for customer
CUSTOMER[4]
0x090
Reserved for customer
CUSTOMER[5]
0x094
Reserved for customer
CUSTOMER[6]
0x098
Reserved for customer
CUSTOMER[7]
0x09C
Reserved for customer
CUSTOMER[8]
0x0A0
Reserved for customer
CUSTOMER[9]
0x0A4
Reserved for customer
CUSTOMER[10]
0x0A8
Reserved for customer
CUSTOMER[11]
0x0AC
Reserved for customer
CUSTOMER[12]
0x0B0
Reserved for customer
CUSTOMER[13]
0x0B4
Reserved for customer
CUSTOMER[14]
0x0B8
Reserved for customer
CUSTOMER[15]
0x0BC
Reserved for customer
CUSTOMER[16]
0x0C0
Reserved for customer
CUSTOMER[17]
0x0C4
Reserved for customer
CUSTOMER[18]
0x0C8
Reserved for customer
CUSTOMER[19]
0x0CC
Reserved for customer
CUSTOMER[20]
0x0D0
Reserved for customer
CUSTOMER[21]
0x0D4
Reserved for customer
CUSTOMER[22]
0x0D8
Reserved for customer
CUSTOMER[23]
0x0DC
Reserved for customer
CUSTOMER[24]
0x0E0
Reserved for customer
CUSTOMER[25]
0x0E4
Reserved for customer
CUSTOMER[26]
0x0E8
Reserved for customer
CUSTOMER[27]
0x0EC
Reserved for customer
CUSTOMER[28]
0x0F0
Reserved for customer
CUSTOMER[29]
0x0F4
Reserved for customer
CUSTOMER[30]
0x0F8
Reserved for customer
CUSTOMER[31]
0x0FC
Reserved for customer
NRFMDK[0]
0x100
Reserved for Nordic MDK
NRFMDK[1]
0x104
Reserved for Nordic MDK
NRFMDK[2]
0x108
Reserved for Nordic MDK
NRFMDK[3]
0x10C
Reserved for Nordic MDK
4454_140 v1.1
33
Core components
Register
Offset
Description
NRFMDK[4]
0x110
Reserved for Nordic MDK
NRFMDK[5]
0x114
Reserved for Nordic MDK
NRFMDK[6]
0x118
Reserved for Nordic MDK
NRFMDK[7]
0x11C
Reserved for Nordic MDK
PSELRESET[0]
0x200
Mapping of the nRESET function (see POWER chapter for details)
PSELRESET[1]
0x204
Mapping of the nRESET function (see POWER chapter for details)
APPROTECT
0x208
Access port protection
Table 11: Register overview
4.5.1.1 NRFFW[n] (n=0..12)
Address offset: 0x014 + (n × 0x4)
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
RW NRFFW
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
Reserved for Nordic firmware design
4.5.1.2 NRFHW[n] (n=0..11)
Address offset: 0x050 + (n × 0x4)
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
RW NRFHW
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
Reserved for Nordic hardware design
4.5.1.3 CUSTOMER[n] (n=0..31)
Address offset: 0x080 + (n × 0x4)
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
RW CUSTOMER
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
Reserved for customer
4.5.1.4 NRFMDK[n] (n=0..7)
Address offset: 0x100 + (n × 0x4)
Reserved for Nordic MDK
4454_140 v1.1
34
Core components
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
RW NRFMDK
Value ID
Value
Description
Reserved for Nordic MDK
4.5.1.5 PSELRESET[n] (n=0..1)
Address offset: 0x200 + (n × 0x4)
Mapping of the nRESET function (see POWER chapter for details)
All PSELRESET registers have to contain the same value for a pin mapping to be valid. If values are not
the same, there will be no nRESET function exposed on a GPIO. As a result, the device will always start
independently of the levels present on any of the GPIOs.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
RW PIN
C
RW CONNECT
Value ID
A A A A A
Value
Description
21
GPIO pin number onto which nRESET is exposed
Connection
Disconnected
1
Disconnect
Connected
0
Connect
4.5.1.6 APPROTECT
Address offset: 0x208
Access port protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
RW PALL
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
Enable or disable access port protection.
See Debug on page 38 for more information.
Disabled
0xFF
HwDisabled
0x5A
Hardware disable of access port protection for devices
where access port protection is controlled by hardware
Hardware disable of access port protection for devices
where access port protection is controlled by hardware and
software
Enabled
0x00
Enable
4.6 EasyDMA
EasyDMA is a module implemented by some peripherals to gain direct access to Data RAM.
EasyDMA is an AHB bus master similar to CPU and is connected to the AHB multilayer interconnect for
direct access to Data RAM. EasyDMA is not able to access flash.
A peripheral can implement multiple EasyDMA instances to provide dedicated channels. For example,
for reading and writing of data between the peripheral and RAM. This concept is illustrated in EasyDMA
example on page 36.
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AHB multilayer
RAM
Peripheral
READER
AHB
RAM
EasyDMA
WRITER
RAM
AHB
Peripheral
core
EasyDMA
Figure 4: EasyDMA example
An EasyDMA channel is implemented in the following way, but some variations may occur:
READERBUFFER_SIZE 5
WRITERBUFFER_SIZE 6
uint8_t readerBuffer[READERBUFFER_SIZE]
__at__ 0x20000000;
uint8_t writerBuffer[WRITERBUFFER_SIZE]
__at__ 0x20000005;
// Configuring the READER channel
MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE;
MYPERIPHERAL->READER.PTR = &readerBuffer;
// Configure the WRITER channel
MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE;
MYPERIPHERAL->WRITER.PTR = &writerBuffer;
This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels - one for
reading called READER, and one for writing called WRITER. When the peripheral is started, it is assumed
that the peripheral will:
• Read 5 bytes from the readerBuffer located in RAM at address 0x20000000.
• Process the data.
• Write no more than 6 bytes back to the writerBuffer located in RAM at address 0x20000005.
The memory layout of these buffers is illustrated in EasyDMA memory layout on page 36.
0x20000000
readerBuffer[0]
readerBuffer[1]
readerBuffer[2]
readerBuffer[3]
0x20000004
readerBuffer[4]
writerBuffer[0]
writerBuffer[1]
writerBuffer[2]
0x20000008
writerBuffer[3]
writerBuffer[4]
writerBuffer[5]
Figure 5: EasyDMA memory layout
The WRITER.MAXCNT register should not be specified larger than the actual size of the buffer
(writerBuffer). Otherwise, the channel would overflow the writerBuffer.
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Once an EasyDMA transfer is completed, the AMOUNT register can be read by the CPU to see how many
bytes were transferred. For example, CPU can read MYPERIPHERAL->WRITER.AMOUNT register to see how
many bytes WRITER wrote to RAM.
Note: The PTR register of a READER or WRITER must point to a valid memory region before use.
The reset value of a PTR register is not guaranteed to point to valid memory. See Memory on page
16 for more information about the different memory regions and EasyDMA connectivity.
4.6.1 EasyDMA error handling
Some errors may occur during DMA handling.
If READER.PTR or WRITER.PTR is not pointing to a valid memory region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 16 for more information about the different
memory regions.
If several AHB bus masters try to access the same AHB slave at the same time, AHB bus congestion might
occur. An EasyDMA channel is an AHB master. Depending on the peripheral, the peripheral may either stall
and wait for access to be granted, or lose data.
4.6.2 EasyDMA array list
EasyDMA is able to operate in Array List mode.
The Array List mode is implemented in channels where the LIST register is available.
The array list does not provide a mechanism to explicitly specify where the next item in the list is located.
Instead, it assumes that the list is organized as a linear array where items are located one after the other
in RAM.
The EasyDMA Array List can be implemented by using the data structure ArrayList_type as illustrated in
the code example below using a READER EasyDMA channel as an example:
#define BUFFER_SIZE
4
typedef struct ArrayList
{
uint8_t buffer[BUFFER_SIZE];
} ArrayList_type;
ArrayList_type ReaderList[3]
__at__ 0x20000000;
MYPERIPHERAL->READER.MAXCNT = BUFFER_SIZE;
MYPERIPHERAL->READER.PTR = &ReaderList;
MYPERIPHERAL->READER.LIST = MYPERIPHERAL_READER_LIST_ArrayList;
The data structure only includes a buffer with size equal to the size of READER.MAXCNT register. EasyDMA
uses the READER.MAXCNT register to determine when the buffer is full.
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READER.PTR = &ReaderList
0x20000000 : ReaderList[0]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000004 : ReaderList[1]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000008 : ReaderList[2]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
Figure 6: EasyDMA array list
4.7 AHB multilayer
AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access is
resolved using priorities.
Each bus master is connected to the slave devices using an interconnection matrix. The bus masters are
assigned priorities. Priorities are used to resolve access when two (or more) bus masters request access to
the same slave device. The following applies:
• If two (or more) bus masters request access to the same slave device, the master with the highest
priority is granted the access first.
• Bus masters with lower priority are stalled until the higher priority master has completed its
transaction.
• If the higher priority master pauses at any point during its transaction, the lower priority master in
queue is temporarily granted access to the slave device until the higher priority master resumes its
activity.
• Bus masters that have the same priority are mutually exclusive, thus cannot be used concurrently.
Below is a list of bus masters in the system and their priorities.
Bus master name
Description
CPU
SPIM0/SPIS0
Same priority and mutually exclusive
RADIO
CCM/ECB/AAR
Same priority and mutually exclusive
SAADC
UARTE0
TWIM0/TWIS0
Same priority and mutually exclusive
PDM
PWM
Table 12: AHB bus masters (listed in priority order, highest to lowest)
Defined bus masters are the CPU and the peripherals with implemented EasyDMA, and the available
slaves are RAM AHB slaves. How the bus masters and slaves are connected using the interconnection
matrix is illustrated in Memory on page 16.
4.8 Debug
The debug system offers a flexible and powerful mechanism for non-intrusive debugging.
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Core components
DAP
SWDCLK
External
debugger
CTRL-AP
SW-DP
NVMC
Access Port Protection Enable
SWDIO
DAP bus
interconnect
&
UICR
APPROTECT
AHB-AP
AHB
CxxxPWRUPREQ
CxxxPWRUPRACK
POWER
Power
RAM & flash
CPU
ARM Cortex-M4
APB/AHB
Peripherals
Figure 7: Debug overview
The main features of the debug system are the following:
• Two-pin serial wire debug (SWD) interface
• Flash patch and breakpoint (FPB) unit that supports the following comparators:
• Two literal comparators
• Six instruction comparators
4.8.1 DAP - Debug access port
An external debugger can access the device via the DAP.
The debug access port (DAP) implements a standard ARM® CoreSight™ serial wire debug port (SW-DP),
which implements the serial wire debug protocol (SWD). SWD is a two-pin serial interface, see SWDCLK
and SWDIO in Debug overview on page 39.
In addition to the default access port in CPU (AHB-AP), the DAP includes a custom control access port
(CTRL-AP). The CTRL-AP is described in more detail in CTRL-AP - Control access port on page 42.
Note:
• The SWDIO line has an internal pull-up resistor.
• The SWDCLK line has an internal pull-down resistor.
4.8.2 Access port protection
Access port protection blocks the debugger from read and write access to all CPU registers and memorymapped addresses when enabled.
Access port protection is enabled and disabled differently depending on the build code of the device.
Access port protection controlled by hardware
This information refers to build codes Axx and earlier.
By default, access port protection is disabled.
Access port protection is enabled by writing UICR.APPROTECT to Enabled and performing any reset. See
Reset on page 55 for more information.
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Core components
Access port protection is disabled by issuing an ERASEALL command via CTRL-AP. This command will erase
the flash, UICR, and RAM, including UICR.APPROTECT. Erasing UICR will set UICR.APPROTECT value to
Disabled. CTRL-AP is described in more detail in CTRL-AP - Control access port on page 42.
Access port protection controlled by hardware and software
This information refers to build codes Bxx and later.
By default, access port protection is enabled.
Access port protection is disabled by issuing an ERASEALL command via CTRL-AP. Read CTRLAP.APPROTECTSTATUS to ensure that access port protection is disabled, and repeat the ERASEALL
command if needed. This command will erase the flash, UICR, and RAM. CTRL-AP is described in more
detail in CTRL-AP - Control access port on page 42. Access port protection will remain disabled until
one of the following occurs:
•
•
•
•
Pin reset
Power or brownout reset
Watchdog reset if not in Debug Interface Mode, see Debug Interface mode on page 44
Wake from System OFF if not in Emulated System OFF
To keep access port protection disabled, the following actions must be performed:
• Program UICR.APPROTECT to HwDisabled. This disables the hardware part of the access port
protection scheme after the first reset of any type. The hardware part of the access port protection will
stay disabled as long as UICR.APPROTECT is not overwritten.
• Firmware must write APPROTECT.DISABLE to SwDisable. This disables the software part of the
access port protection scheme.
Note: Register APPROTECT.DISABLE is reset after pin reset, power or brownout reset, watchdog
reset, or wake from System OFF as mentioned above.
The following figure is an example on how a device with access port protection enabled can be erased,
programmed, and configured to allow debugging. Operations sent from debugger as well as registers
written by firmware will affect the access port state.
Debugger
n
Pi
CR =
UI CT
e
d
rit TE le
W PRO isab
AP wD
H
m
ra e
og ar
Pr mw
fir
t
se
re
P
-A L
RL AL
CT ASE
ER
Closed
Open
Closed Open
Access port state
Write APPROTECT.DISABLE =
SwDisable
Firmware
Figure 8: Access port unlocking
Access port protection is enabled when the disabling conditions are not present. For additional security,
it is recommended to write Enabled to UICR.APPROTECT, and have firmware write Force to
APPROTECT.FORCEPROTECT. This is illustrated in the following figure.
Note: Register APPROTECT.FORCEPROTECT is reset after any reset.
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Core components
Debugger
Pi
CR =
UI CT
e
rit TE d
W PRO ble
a
AP En
n
t
se
re
m
ra e
og ar
Pr mw
fir
P
-A L
RL AL
C T A SE
ER
Closed
Open
Closed
Access port state
Write APPROTECT.FORCEPROTECT =
Force
Firmware
Figure 9: Force access port protection
4.8.2.1 Registers
Base address
Peripheral
Instance
Description
0x40000000
APPROTECT
APPROTECT
APPROTECT control
Configuration
Table 13: Instances
Register
Offset
Description
FORCEPROTECT
0x550
Software force enable APPROTECT mechanism until next reset.
DISABLE
0x558
Software disable APPROTECT mechanism
Table 14: Register overview
4.8.2.1.1 FORCEPROTECT
Address offset: 0x550
Software force enable APPROTECT mechanism until next reset.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
RW1 FORCEPROTECT
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
Write 0x0 to force enable APPROTECT mechanism
Force
0x0
Software force enable APPROTECT mechanism
4.8.2.1.2 DISABLE
Address offset: 0x558
Software disable APPROTECT mechanism
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW DISABLE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
SwDisable
0x5A
Description
Software disable APPROTECT mechanism
Software disable APPROTECT mechanism
4.8.3 CTRL-AP - Control access port
The control access port (CTRL-AP) is a custom access port that enables control of the device when other
access ports in the DAP are disabled by the access port protection.
Access port protection is described in more detail in Access port protection on page 39.
Control access port has the following features:
• Soft reset - see Reset on page 55 for more information
• Disabling of access port protection - device control is allowed through CTRL-AP even when all other
access ports in DAP are disabled by access port protection
4.8.3.1 Registers
Register
Offset
Description
RESET
0x000
Soft reset triggered through CTRL-AP
ERASEALL
0x004
Erase all
ERASEALLSTATUS
0x008
Status register for the ERASEALL operation
APPROTECTSTATUS
0x00C
Status register for access port protection
IDR
0x0FC
CTRL-AP identification register, IDR
Table 15: Register overview
4.8.3.1.1 RESET
Address offset: 0x000
Soft reset triggered through CTRL-AP
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW RESET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Soft reset triggered through CTRL-AP. See Reset behavior in
POWER chapter for more details.
NoReset
0
Reset is not active
Reset
1
Reset is active. Device is held in reset.
4.8.3.1.2 ERASEALL
Address offset: 0x004
Erase all
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NoOperation
0
No operation
Erase
1
Erase all flash and RAM
ERASEALL
Erase all flash and RAM
4.8.3.1.3 ERASEALLSTATUS
Address offset: 0x008
Status register for the ERASEALL operation
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Ready
0
ERASEALL is ready
Busy
1
ERASEALL is busy (on-going)
ERASEALLSTATUS
Status register for the ERASEALL operation
4.8.3.1.4 APPROTECTSTATUS
Address offset: 0x00C
Status register for access port protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Enabled
0
Access port protection enabled
Disabled
1
Access port protection not enabled
APPROTECTSTATUS
Status register for access port protection
4.8.3.1.5 IDR
Address offset: 0x0FC
CTRL-AP identification register, IDR
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
E E E E D D D D C C C C C C C B B B B
Reset 0x02880000
0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
R
APID
Value ID
Value
Description
AP identification
B
R
CLASS
Access port (AP) class
NotDefined
0x0
No defined class
MEMAP
0x8
Memory access port
C
R
JEP106ID
JEDEC JEP106 identity code
D
R
JEP106CONT
JEDEC JEP106 continuation code
E
R
REVISION
Revision
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A A A A A A A A
Core components
4.8.3.2 Electrical specification
4.8.3.2.1 Control access port
Symbol
Description
Rpull
Internal SWDIO and SWDCLK pull up/down resistance
fSWDCLK
SWDCLK frequency
Min.
Typ.
Max.
13
0.125
Units
kΩ
8
MHz
4.8.4 Debug Interface mode
Before an external debugger can access either CPU's access port (AHB-AP) or the control access port
(CTRL-AP), the debugger must first request the device to power up via CxxxPWRUPREQ in the SWJ-DP.
If the device is in System OFF when power is requested via CxxxPWRUPREQ, the system will wake up and
the DIF flag in RESETREAS on page 60 will be set. The device is in the Debug Interface mode as long
as the debugger is requesting power via CxxxPWRUPREQ. Once the debugger stops requesting power
via CxxxPWRUPREQ, the device is back in normal mode. Some peripherals behave differently in Debug
Interface mode compared to normal mode. These differences are described in more detail in the chapters
of the peripherals that are affected.
When a debug session is over, the external debugger must make sure to put the device back into normal
mode since the overall power consumption is higher in Debug Interface mode than in normal mode.
For details on how to use the debug capabilities, read the debug documentation of your IDE.
4.8.5 Real-time debug
The nRF52811 supports real-time debugging.
Real-time debugging allows interrupts to execute to completion in real time when breakpoints are set
in Thread mode or lower priority interrupts. This enables developers to set breakpoints and single-step
through the code without the risk of real-time event-driven threads running at higher priority failing.
For example, this enables the device to continue to service the high-priority interrupts of an external
controller or sensor without failure or loss of state synchronization while the developer steps through
code in a low-priority thread.
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5
Power and clock management
5.1 Power management unit (PMU)
Power and clock management in nRF52811 is designed to automatically ensure maximum power
efficiency.
The core of the power and clock management system is the power management unit (PMU) illustrated in
Power management unit on page 45.
MCU
CPU
External
power sources
Internal
voltage
regulators
PMU
Memory
External
crystals
Internal
oscillators
Peripheral
Figure 10: Power management unit
The PMU automatically detects which power and clock resources are required by the different
components in the system at any given time. It will then start/stop and choose operation modes in supply
regulators and clock sources, without user interaction, to achieve the lowest power consumption possible.
5.2 Current consumption
As the system is being constantly tuned by the Power management unit (PMU) on page 45, estimating
the current consumption of an application can be challenging if the designer is not able to perform
measurements directly on the hardware. To facilitate the estimation process, a set of current consumption
scenarios are provided to show the typical current drawn from the VDD supply.
Each scenario specifies a set of operations and conditions applying to the given scenario. Current
consumption scenarios, common conditions on page 46 shows a set of common conditions used in
all scenarios, unless otherwise stated in the description of a given scenario. All scenarios are listed in
Electrical specification on page 46.
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Power and clock management
Condition
Value
VDD
3V
Temperature
25°C
CPU
WFI (wait for interrupt)/WFE (wait for event) sleep
Peripherals
All idle
Clock
Not running
Regulator
LDO
RAM
Full 24 kB retention
Compiler3
GCC v4.9.3 20150529 (arm-none-eabi-gcc).
Compiler flags: -O0 -falign-functions=16 -fno-strictaliasing -mcpu=cortex-m4 -mfloat-abi=soft -msoftfloat -mthumb.
32 MHz crystal4
SMD 2520, 32 MHz, 10 pF +/- 10 ppm
Table 16: Current consumption scenarios, common conditions
5.2.1 Electrical specification
5.2.1.1 CPU running
Symbol
Description
ICPU0
CPU running CoreMark @64 MHz from flash, Clock = HFXO,
Min.
Typ.
Max.
Units
2.2
mA
Regulator = DCDC
ICPU1
CPU running CoreMark @64 MHz from flash, Clock = HFXO
4.2
mA
ICPU2
CPU running CoreMark @64 MHz from RAM, Clock = HFXO,
2.1
mA
Regulator = DCDC
ICPU3
CPU running CoreMark @64 MHz from RAM, Clock = HFXO
4
mA
ICPU4
CPU running CoreMark @64 MHz from flash, Clock = HFINT,
2
mA
Regulator = DCDC
3
4
Applying only when CPU is running
Applying only when HFXO is running
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Power and clock management
5.2.1.2 Radio transmitting/receiving
Symbol
Description
IRADIO_TX0
Radio transmitting @ 4 dBm output power, 1 Mbps
Min.
Typ.
Max.
Units
8
mA
5.8
mA
3.4
mA
6.1
mA
10.5
mA
5.1
mA
10.8
mA
Bluetooth low energy mode, Clock = HFXO, Regulator =
DCDC
IRADIO_TX1
Radio transmitting @ 0 dBm output power, 1 Mbps
Bluetooth low energy mode, Clock = HFXO, Regulator =
DCDC
IRADIO_TX2
Radio transmitting @ -40 dBm output power, 1 Mbps
Bluetooth low energy mode, Clock = HFXO, Regulator =
DCDC
IRADIO_RX0
Radio receiving @ 1 Mbps Bluetooth low energy mode,
Clock = HFXO, Regulator = DCDC
IRADIO_TX3
Radio transmitting @ 0 dBm output power, 1 Mbps
Bluetooth low energy mode, Clock = HFXO
IRADIO_TX4
Radio transmitting @ -40 dBm output power, 1 Mbps
Bluetooth low energy mode, Clock = HFXO
IRADIO_RX1
Radio receiving @ 1 Mbps Bluetooth low energy mode,
Clock = HFXO
15
14
Current consumption [mA]
13
12
11
10
9
8
7
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
Supply voltage [V]
-40 ºC
25 ºC
85 ºC
Figure 11: Radio transmitting @ 4 dBm output power, 1 Mbps Bluetooth
low energy mode, Clock = HFXO, Regulator = DCDC (typical values)
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3.6
Power and clock management
10
9.5
9
Current consumption [mA]
8.5
8
7.5
7
6.5
6
5.5
5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Supply voltage [V]
-40 ºC
25 ºC
85 ºC
Figure 12: Radio transmitting @ 0 dBm output power, 1 Mbps Bluetooth
low energy mode, Clock = HFXO, Regulator = DCDC (typical values)
5.2.1.3 Sleep
Symbol
Description
ION_RAMOFF_EVENT
System ON, No RAM retention, Wake on any event
Min.
Typ.
0.6
Max.
Units
µA
ION_RAMON_EVENT
System ON, Full 24 kB RAM retention, Wake on any event
0.8
µA
ION_RAMON_POF
System ON, Full 24 kB RAM retention, Wake on any event,
0.8
µA
3.3
µA
0.8
µA
1.5
µA
1.4
µA
1.1
µA
1.0
µA
Power fail comparator enabled
ION_RAMON_GPIOTE
System ON, Full 24 kB RAM retention, Wake on GPIOTE input
(Event mode)
ION_RAMON_GPIOTEPORTSystem ON, Full 24 kB RAM retention, Wake on GPIOTE
PORT event
ION_RAMON_RTC
System ON, Full 24 kB RAM retention, Wake on RTC (running
from LFRC clock)
ION_RAMOFF_RTC
System ON, No RAM retention, Wake on RTC (running from
LFRC clock)
ION_RAMON_RTC_LFXO System ON, Full 24 kB RAM retention, Wake on RTC (running
from LFXO clock)
ION_RAMOFF_RTC_LFXO System ON, No RAM retention, Wake on RTC (running from
LFXO clock)
IOFF_RAMOFF_RESET
System OFF, No RAM retention, Wake on reset
0.3
µA
IOFF_RAMON_RESET
System OFF, Full 24 kB RAM retention, Wake on reset
0.5
µA
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Power and clock management
2.5
Current consumption [µA]
2
1.5
1
0.5
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Supply voltage [V]
-40 ºC
25 ºC
85 ºC
Figure 13: System OFF, No RAM retention, Wake on reset (typical values)
16
14
Current consumption [µA]
12
10
8
6
4
2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Supply voltage [V]
-40 ºC
25 ºC
85 ºC
Figure 14: System ON, Full 24 kB RAM retention, Wake on any event (typical values)
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Power and clock management
5.2.1.4 Compounded
Symbol
Description
IS0
CPU running CoreMark from flash, Radio transmitting @ 0
Min.
Typ.
Max.
Units
7.4
mA
7.6
mA
13.8
mA
14.2
mA
dBm output power, 1 Mbps Bluetooth low energy mode,
Clock = HFXO, Regulator = DCDC
IS1
CPU running CoreMark from flash, Radio receiving @ 1
Mbps Bluetooth low energy mode, Clock = HFXO, Regulator
= DCDC
IS2
CPU running CoreMark from flash, Radio transmitting @ 0
dBm output power, 1 Mbps Bluetooth low energy mode,
Clock = HFXO
IS3
CPU running CoreMark from flash, Radio receiving @ 1
Mbps Bluetooth low energy mode, Clock = HFXO
5.2.1.5 TIMER running
Symbol
Description
ITIMER0
One TIMER instance running @ 1 MHz, Clock = HFINT
Min.
Typ.
432
Max.
Units
µA
ITIMER1
Two TIMER instances running @ 1 MHz, Clock = HFINT
432
µA
ITIMER2
One TIMER instance running @ 1 MHz, Clock = HFXO
730
µA
ITIMER3
One TIMER instance running @ 16 MHz, Clock = HFINT
495
µA
ITIMER4
One TIMER instance running @ 16 MHz, Clock = HFXO
792
µA
5.2.1.6 RNG active
Symbol
Description
IRNG0
RNG running
Min.
Typ.
Max.
539
Units
µA
5.2.1.7 TEMP active
Symbol
Description
ITEMP0
TEMP started
Min.
Typ.
Max.
998
Units
µA
5.2.1.8 SAADC active
Symbol
Description
ISAADC,RUN
SAADC sampling @ 16 ksps, Acquisition time = 20 µs, Clock =
Min.
Typ.
Max.
1.1
Units
mA
HFXO, Regulator = DCDC
5.2.1.9 COMP active
Symbol
Description
ICOMP,LP
COMP enabled, low power mode
17.2
µA
ICOMP,NORM
COMP enabled, normal mode
21
µA
ICOMP,HS
COMP enabled, high-speed mode
28.7
µA
4454_140 v1.1
Min.
50
Typ.
Max.
Units
Power and clock management
5.2.1.10 WDT active
Symbol
Description
IWDT,STARTED
WDT started
Min.
Typ.
Max.
1.3
Units
µA
5.3 POWER — Power supply
This device has the following power supply features:
•
•
•
•
•
•
On-chip LDO and DC/DC regulators
Global System ON/OFF modes with individual RAM section power control
Analog or digital pin wakeup from System OFF
Supervisor HW to manage power on reset, brownout, and power fail
Auto-controlled refresh modes for LDO and DC/DC regulators to maximize efficiency
Automatic switching between LDO and DC/DC regulator based on load to maximize efficiency
Note: Two additional external passive components are required to use the DC/DC regulator.
5.3.1 Regulators
The following internal power regulator alternatives are supported:
• Internal LDO regulator
• Internal DC/DC regulator
The LDO is the default regulator.
The DC/DC regulator can be used as an alternative to the LDO regulator and is enabled through the
DCDCEN on page 62 register. Using the DC/DC regulator will reduce current consumption compared to
when using the LDO regulator, but the DC/DC regulator requires an external LC filter to be connected, as
shown in DC/DC regulator setup on page 52.
POWER
DCDCEN
REG
Supply
LDO
1.3V System power
VDD
DC/DC
DCC
DEC4
Figure 15: LDO regulator setup
4454_140 v1.1
51
GND
Power and clock management
POWER
DCDCEN
REG
Supply
LDO
1.3V System power
VDD
DC/DC
DCC
DEC4
GND
Figure 16: DC/DC regulator setup
5.3.2 System OFF mode
System OFF is the deepest power saving mode the system can enter. In this mode, the system’s core
functionality is powered down and all ongoing tasks are terminated.
The device can be put into System OFF mode using the register SYSTEMOFF on page 60. When in
System OFF mode, the device can be woken up through one of the following signals:
• The DETECT signal, optionally generated by the GPIO peripheral
• A reset
When the system wakes up from System OFF mode, it gets reset. For more details, see Reset behavior on
page 56.
One or more RAM sections can be retained in System OFF mode, depending on the settings in the
RAM[n].POWER registers.
RAM[n].POWER are retained registers, see Reset behavior. These registers are usually overwritten by the
startup code provided with the nRF application examples.
Before entering System OFF mode, the user must make sure that all on-going EasyDMA transactions have
been completed. This is usually accomplished by making sure that the EasyDMA enabled peripheral is not
active when entering System OFF.
5.3.2.1 Emulated System OFF mode
If the device is in debug interface mode, System OFF will be emulated to secure that all required resources
needed for debugging are available during System OFF.
See Debug on page 38 for more information. Required resources needed for debugging include the
following key components:
•
•
•
•
•
•
Debug on page 38
CLOCK — Clock control on page 64
POWER — Power supply on page 51
NVMC — Non-volatile memory controller on page 19
CPU
Flash
4454_140 v1.1
52
Power and clock management
• RAM
Since the CPU is kept on in an emulated System OFF mode, it is recommended to add an infinite loop
directly after entering System OFF, to prevent the CPU from executing code that normally should not be
executed.
5.3.3 System ON mode
System ON is the default state after power-on reset. In System ON, all functional blocks such as the CPU or
peripherals can be in IDLE or RUN mode, depending on the configuration set by the software and the state
of the application executing.
Register RESETREAS on page 60 provides information about the source causing the wakeup or reset.
The system can switch the appropriate internal power sources on and off, depending on how much power
is needed at any given time. The power requirement of a peripheral is directly related to its activity level,
and the activity level of a peripheral is usually raised and lowered when specific tasks are triggered or
events are generated.
5.3.3.1 Sub power modes
In System ON mode, when both the CPU and all the peripherals are in IDLE mode, the system can reside in
one of the two sub power modes.
The sub power modes are:
• Constant Latency
• Low-power
In Constant Latency mode, the CPU wakeup latency and the PPI task response are constant and kept at
a minimum. This is secured by forcing a set of basic resources to be turned on while in sleep. Having a
constant and predictable latency is at the cost of having increased power consumption. The Constant
Latency mode is selected by triggering the CONSTLAT task.
In Low-power mode, the automatic power management system described in System ON mode on page
53 ensures that the most efficient supply option is chosen to save most power. Having the lowest
power possible is at the cost of having a varying CPU wakeup latency and PPI task response. The Lowpower mode is selected by triggering the LOWPWR task.
When the system enters System ON mode, it is by default in Low-power sub power mode.
5.3.4 Power supply supervisor
The power supply supervisor initializes the system at power-on and provides an early warning of
impending power failure.
In addition, the power supply supervisor puts the system in a reset state if the supply voltage is too low for
safe operation (brownout). The power supply supervisor is illustrated in Power supply supervisor on page
54.
4454_140 v1.1
53
Power and clock management
VDD
C
Power on reset
R
VBOR
POFCON
Brownout reset
1.7V
...........
MUX
POFWARN
Vpof
2.8V
Figure 17: Power supply supervisor
5.3.4.1 Power-fail comparator
The power-fail comparator (POF) can provide the CPU with an early warning of impending power failure. It
will not reset the system, but give the CPU time to prepare for an orderly power-down.
The comparator features a hysteresis of VHYST, as illustrated in Power-fail comparator (BOR = Brownout
reset) on page 54. The threshold VPOF is set in register POFCON on page 61. If the POF is enabled
and the supply voltage falls below VPOF, the POFWARN event will be generated. This event will also be
generated if the supply voltage is already below VPOF at the time the POF is enabled, or if VPOF is reconfigured to a level above the supply voltage.
If power-fail warning is enabled and the supply voltage is below VPOF the power-fail comparator will
prevent the NVMC from performing write operations to the NVM. See NVMC — Non-volatile memory
controller on page 19 for more information about the NVMC.
VDD
VPOF+VHYST
VPOF
1.7V
POFWARN
POFWARN
MCU
t
BOR
Figure 18: Power-fail comparator (BOR = Brownout reset)
To save power, the power-fail comparator is not active in System OFF or in System ON when HFCLK is not
running.
4454_140 v1.1
54
Power and clock management
5.3.5 RAM power control
The RAM power control registers are used for configuring the following:
• The RAM sections to be retained during System OFF
• The RAM sections to be retained and accessible during System ON
In System OFF, retention of a RAM section is configured in the RETENTION field of the corresponding
RAM[n] register.
In System ON, retention and accessibility for a RAM section is configured in the RETENTION and POWER
fields of the corresponding RAM[n] register.
The following table summarizes the behavior of these registers.
Configuration
RAM section status
System on/off
RAM[n].POWER.POWER
RAM[n].POWER.RETENTION
Accessible
Retained
Off
x
Off
No
No
Off
x
On
No
Yes
On
Off
Off
No
No
On
Off1
On
No
Yes
On
On
x
Yes
Yes
Table 17: RAM section configuration
The advantage of not retaining RAM contents is that the overall current consumption is reduced.
See chapter Memory on page 16 for more information on RAM sections.
5.3.6 Reset
There are multiple sources that may trigger a reset.
After a reset has occurred, register RESETREAS can be read to determine which source generated the
reset.
5.3.6.1 Power-on reset
The power-on reset generator initializes the system at power-on.
The system is held in reset state until the supply has reached the minimum operating voltage and the
internal voltage regulators have started.
A step increase in supply voltage of 300 mV or more, with rise time of 300 ms or less, within the valid
supply range, may result in a system reset.
5.3.6.2 Pin reset
A pin reset is generated when the physical reset pin on the device is asserted.
Pin reset is configured via the PSELRESET[n] registers.
Note: Pin reset is not available on all pins.
5.3.6.3 Wakeup from System OFF mode reset
The device is reset when it wakes up from System OFF mode.
1
Not useful setting. RAM section power off gives negligible reduction in current consumption when
retention is on.
4454_140 v1.1
55
Power and clock management
The debug access port (DAP) is not reset following a wake up from System OFF mode if the device is in
Debug Interface mode. See chapter Debug on page 38 for more information.
5.3.6.4 Soft reset
A soft reset is generated when the SYSRESETREQ bit of the Application Interrupt and Reset Control
Register (AIRCR register) in the ARM® core is set.
Refer to ARM documentation for more details.
A soft reset can also be generated via the RESET on page 42 register in the CTRL-AP.
5.3.6.5 Watchdog reset
A Watchdog reset is generated when the watchdog times out.
See chapter WDT — Watchdog timer on page 414 for more information.
5.3.6.6 Brown-out reset
The brown-out reset generator puts the system in reset state if the supply voltage drops below the
brownout reset (BOR) threshold.
Refer to section Power fail comparator on page 64 for more information.
5.3.7 Retained registers
A retained register is a register that will retain its value in System OFF mode and through a reset,
depending on reset source. See individual peripheral chapters for information of which registers are
retained for the various peripherals.
5.3.8 Reset behavior
Reset source
Reset target
CPU
Peripherals
GPIO
Debuga
SWJ-DP
RAM
WDT
Retained
RESETREAS
registers
CPU lockup 5
x
x
x
Soft reset
x
x
x
Wakeup from System OFF
x
x
Watchdog reset 8
x
x
Pin reset
x
Brownout reset
x
Power on reset
x
x6
x7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
mode reset
Note: The RAM is never reset, but depending on reset source, RAM content may be corrupted.
a
5
6
7
8
All debug components excluding SWJ-DP. See Debug on page 38 for more information about the
different debug components in the system.
Reset from CPU lockup is disabled if the device is in debug interface mode. CPU lockup is not possible
in System OFF.
The Debug components will not be reset if the device is in debug interface mode.
RAM is not reset on wakeup from System OFF mode, but depending on settings in the RAM registers,
parts, or the whole RAM may not be retained after the device has entered System OFF mode.
Watchdog reset is not available in System OFF.
4454_140 v1.1
56
Power and clock management
5.3.9 Registers
Base address
Peripheral
Instance
Description
Configuration
0x40000000
POWER
POWER
Power control
For 24 kB RAM variant, only RAM[0].x to
RAM[2].x registers are in use.
Table 18: Instances
Register
Offset
Description
TASKS_CONSTLAT
0x078
Enable Constant Latency mode
TASKS_LOWPWR
0x07C
Enable Low-power mode (variable latency)
EVENTS_POFWARN
0x108
Power failure warning
EVENTS_SLEEPENTER
0x114
CPU entered WFI/WFE sleep
EVENTS_SLEEPEXIT
0x118
CPU exited WFI/WFE sleep
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
RESETREAS
0x400
Reset reason
SYSTEMOFF
0x500
System OFF register
POFCON
0x510
Power failure comparator configuration
GPREGRET
0x51C
General purpose retention register
GPREGRET2
0x520
General purpose retention register
DCDCEN
0x578
DC/DC enable register
RAM[0].POWER
0x900
RAM0 power control register. The RAM size will vary depending on product variant, and the
RAM0 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[0].POWERSET
0x904
RAM0 power control set register
RAM[0].POWERCLR
0x908
RAM0 power control clear register
RAM[1].POWER
0x910
RAM1 power control register. The RAM size will vary depending on product variant, and the
RAM1 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[1].POWERSET
0x914
RAM1 power control set register
RAM[1].POWERCLR
0x918
RAM1 power control clear register
RAM[2].POWER
0x920
RAM2 power control register. The RAM size will vary depending on product variant, and the
RAM2 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[2].POWERSET
0x924
RAM2 power control set register
RAM[2].POWERCLR
0x928
RAM2 power control clear register
RAM[3].POWER
0x930
RAM3 power control register. The RAM size will vary depending on product variant, and the
RAM3 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[3].POWERSET
0x934
RAM3 power control set register
RAM[3].POWERCLR
0x938
RAM3 power control clear register
RAM[4].POWER
0x940
RAM4 power control register. The RAM size will vary depending on product variant, and the
RAM4 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[4].POWERSET
0x944
RAM4 power control set register
RAM[4].POWERCLR
0x948
RAM4 power control clear register
RAM[5].POWER
0x950
RAM5 power control register. The RAM size will vary depending on product variant, and the
RAM5 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[5].POWERSET
0x954
RAM5 power control set register
RAM[5].POWERCLR
0x958
RAM5 power control clear register
4454_140 v1.1
57
Power and clock management
Register
Offset
Description
RAM[6].POWER
0x960
RAM6 power control register. The RAM size will vary depending on product variant, and the
RAM6 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[6].POWERSET
0x964
RAM6 power control set register
RAM[6].POWERCLR
0x968
RAM6 power control clear register
RAM[7].POWER
0x970
RAM7 power control register. The RAM size will vary depending on product variant, and the
RAM7 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[7].POWERSET
0x974
RAM7 power control set register
RAM[7].POWERCLR
0x978
RAM7 power control clear register
Table 19: Register overview
5.3.9.1 TASKS_CONSTLAT
Address offset: 0x078
Enable Constant Latency mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_CONSTLAT
Enable Constant Latency mode
Trigger task
5.3.9.2 TASKS_LOWPWR
Address offset: 0x07C
Enable Low-power mode (variable latency)
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_LOWPWR
Enable Low-power mode (variable latency)
Trigger task
5.3.9.3 EVENTS_POFWARN
Address offset: 0x108
Power failure warning
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_POFWARN
4454_140 v1.1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Power failure warning
NotGenerated
0
Event not generated
Generated
1
Event generated
58
Power and clock management
5.3.9.4 EVENTS_SLEEPENTER
Address offset: 0x114
CPU entered WFI/WFE sleep
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_SLEEPENTER
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
CPU entered WFI/WFE sleep
5.3.9.5 EVENTS_SLEEPEXIT
Address offset: 0x118
CPU exited WFI/WFE sleep
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_SLEEPEXIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
CPU exited WFI/WFE sleep
5.3.9.6 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C B
Reset 0x00000000
ID
Access
Field
A
RW POFWARN
B
C
Value ID
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to enable interrupt for event POFWARN
RW SLEEPENTER
Write '1' to enable interrupt for event SLEEPENTER
RW SLEEPEXIT
Write '1' to enable interrupt for event SLEEPEXIT
5.3.9.7 INTENCLR
Address offset: 0x308
Disable interrupt
4454_140 v1.1
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
59
Power and clock management
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C B
Reset 0x00000000
ID
Access
Field
A
RW POFWARN
B
C
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event POFWARN
RW SLEEPENTER
Write '1' to disable interrupt for event SLEEPENTER
RW SLEEPEXIT
Write '1' to disable interrupt for event SLEEPEXIT
5.3.9.8 RESETREAS
Address offset: 0x400
Reset reason
Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing '1' to it. If none
of the reset sources are flagged, this indicates that the chip was reset from the on-chip reset generator,
which will indicate a power-on-reset or a brownout reset.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
F
Reset 0x00000000
ID
Access
Field
A
RW RESETPIN
B
C
D
E
E
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotDetected
0
Not detected
Detected
1
Detected
Reset from pin-reset detected
RW DOG
Reset from watchdog detected
NotDetected
0
Not detected
Detected
1
Detected
NotDetected
0
Not detected
Detected
1
Detected
NotDetected
0
Not detected
Detected
1
Detected
RW SREQ
Reset from soft reset detected
RW LOCKUP
Reset from CPU lock-up detected
RW OFF
Reset due to wake up from System OFF mode when wakeup
is triggered from DETECT signal from GPIO
F
NotDetected
0
Not detected
Detected
1
Detected
RW DIF
Reset due to wake up from System OFF mode when wakeup
is triggered from entering into debug interface mode
NotDetected
0
Not detected
Detected
1
Detected
5.3.9.9 SYSTEMOFF
Address offset: 0x500
4454_140 v1.1
D C B A
60
Power and clock management
System OFF register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
SYSTEMOFF
Enable System OFF mode
Enter
1
Enable System OFF mode
5.3.9.10 POFCON
Address offset: 0x510
Power failure comparator configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B B B B A
Reset 0x00000000
ID
Access
Field
A
RW POF
B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable
Enabled
1
Enable
V17
4
Set threshold to 1.7 V
V18
5
Set threshold to 1.8 V
V19
6
Set threshold to 1.9 V
V20
7
Set threshold to 2.0 V
V21
8
Set threshold to 2.1 V
V22
9
Set threshold to 2.2 V
V23
10
Set threshold to 2.3 V
V24
11
Set threshold to 2.4 V
V25
12
Set threshold to 2.5 V
V26
13
Set threshold to 2.6 V
V27
14
Set threshold to 2.7 V
V28
15
Set threshold to 2.8 V
Enable or disable power failure comparator
RW THRESHOLD
Power failure comparator threshold setting
5.3.9.11 GPREGRET
Address offset: 0x51C
General purpose retention register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW GPREGRET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
General purpose retention register
This register is a retained register
5.3.9.12 GPREGRET2
Address offset: 0x520
General purpose retention register
4454_140 v1.1
61
Power and clock management
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW GPREGRET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
General purpose retention register
This register is a retained register
5.3.9.13 DCDCEN
Address offset: 0x578
DC/DC enable register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW DCDCEN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Enable or disable DC/DC converter
5.3.9.14 RAM[n].POWER (n=0..7)
Address offset: 0x900 + (n × 0x10)
RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register
will only be present if the corresponding RAM AHB slave is present on the device.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C
Reset 0x0000FFFF
ID
Access
Field
A-B
RW S[i]POWER (i=0..1)
Value ID
Value
Description
Keep RAM section Si ON or OFF in System ON mode.
RAM sections are always retained when ON, but can
also be retained when OFF dependent on the settings in
SiRETENTION. All RAM sections will be OFF in System OFF
mode.
C-D
Off
0
Off
On
1
On
RW S[i]RETENTION (i=0..1)
Keep retention on RAM section Si when RAM section is in
OFF
Off
0
Off
On
1
On
5.3.9.15 RAM[n].POWERSET (n=0..7)
Address offset: 0x904 + (n × 0x10)
RAMn power control set register
When read, this register will return the value of the POWER register.
4454_140 v1.1
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
62
Power and clock management
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C
Reset 0x0000FFFF
ID
Access
Field
A-B
W
C-D
W
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
On
1
Description
S[i]POWER (i=0..1)
Keep RAM section Si of RAMn on or off in System ON mode
On
S[i]RETENTION (i=0..1)
Keep retention on RAM section Si when RAM section is
switched off
On
1
On
5.3.9.16 RAM[n].POWERCLR (n=0..7)
Address offset: 0x908 + (n × 0x10)
RAMn power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C
Reset 0x0000FFFF
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
Value ID
A-B
W
S[i]POWER (i=0..1)
C-D
W
S[i]RETENTION (i=0..1)
Value
Description
Keep RAM section Si of RAMn on or off in System ON mode
Off
1
Off
Keep retention on RAM section Si when RAM section is
switched off
Off
1
Off
5.3.10 Electrical specification
5.3.10.1 Device startup times
Symbol
Description
tPOR
Time in Power on Reset after VDD reaches 1.7 V for all
Min.
Typ.
Max.
Units
supply voltages and temperatures. Dependent on supply rise
time. 9
tPOR,10us
VDD rise time 10 µs
1
ms
tPOR,10ms
VDD rise time 10 ms
9
ms
tPOR,60ms
VDD rise time 60 ms
23
ms
tPINR
If a GPIO pin is configured as reset, the maximum time taken
to pull up the pin and release reset after power on reset.
Dependent on the pin capacitive load (C)10: t=5RC, R = 13 kΩ
tPINR,500nF
C = 500 nF
32.5
ms
tPINR,10uF
C = 10 µF
650
ms
tR2ON
Time from reset to ON (CPU execute)
tR2ON,NOTCONF
If reset pin not configured
tPOR
ms
tR2ON,CONF
If reset pin configured
tPOR +
ms
tPINR
tOFF2ON
9
10
Time from OFF to CPU execute
16.5
µs
A step increase in supply voltage of 300 mV or more, with rise time of 300 ms or less, within the valid
supply range, may result in a system reset.
To decrease maximum time a device could hold in reset, a strong external pullup resistor can be
used.
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Symbol
Description
Min.
Typ.
Max.
Units
tIDLE2CPU
Time from IDLE to CPU execute
3.0
µs
tEVTSET,CL1
Time from HW event to PPI event in Constant Latency
0.0625
µs
0.0625
µs
System ON mode
tEVTSET,CL0
Time from HW event to PPI event in Low Power System ON
mode
5.3.10.2 Power fail comparator
Symbol
Description
Min.
VPOF
Nominal power level warning thresholds (falling supply
1.7
Typ.
Max.
Units
2.8
V
±5
%
voltage). Levels are configurable between Min. and Max. in
100 mV increments.
VPOFTOL
Threshold voltage tolerance
±1
VPOFHYST
Threshold voltage hysteresis
50
VBOR,OFF
Brown out reset voltage range SYSTEM OFF mode
1.2
1.7
V
VBOR,ON
Brown out reset voltage range SYSTEM ON mode
1.48
1.7
V
mV
5.4 CLOCK — Clock control
The clock control system can source the system clocks from a range of internal or external high and low
frequency oscillators and distribute them to modules based upon a module’s individual requirements.
Clock distribution is automated and grouped independently by module to limit current consumption in
unused branches of the clock tree.
Listed here are the main features for CLOCK:
•
•
•
•
•
•
•
64 MHz on-chip oscillator
64 MHz crystal oscillator, using external 32 MHz crystal
32.768 kHz +/-500 ppm RC oscillator
32.768 kHz crystal oscillator, using external 32.768 kHz crystal
32.768 kHz oscillator synthesized from 64 MHz oscillator
Firmware (FW) override control of oscillator activity for low latency start up
Automatic oscillator and clock control, and distribution for ultra-low power
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Power and clock management
HFCLKSTART
HFCLKSTOP
LFCLKSTART
LFCLKSTOP
CLOCK
HFINT
Internal oscillator
PCLK1M
PCLK16M
XC1
PCLK32M
HFCLK
Clock control
HFXO
Crystal oscillator
32 MHz
HCLK64M
XC2
LFRC
RC oscillator
CAL
SYNT
XL1
LFXO
Crystal oscillator
32.768 kHz
LFCLK
Clock control
PCLK32KI
XL2
HFCLKSTARTED
LFCLKSTARTED
Figure 19: Clock control
5.4.1 HFCLK clock controller
The HFCLK clock controller provides the following clocks to the system.
•
•
•
•
HCLK64M: 64 MHz CPU clock
PCLK1M: 1 MHz peripheral clock
PCLK16M: 16 MHz peripheral clock
PCLK32M: 32 MHz peripheral clock
The HFCLK controller supports the following high frequency clock (HFCLK) sources:
• 64 MHz internal oscillator (HFINT)
• 64 MHz crystal oscillator (HFXO)
For illustration, see Clock control on page 65.
When the system requests one or more clocks from the HFCLK controller, the HFCLK controller will
automatically provide them. If the system does not request any clocks provided by the HFCLK controller,
the controller will enter a power saving mode.
These clocks are only available when the system is in ON mode. When the system enters ON mode, the
internal oscillator (HFINT) clock source will automatically start to be able to provide the required HFCLK
clock(s) for the system.
The HFINT will be used when HFCLK is requested and HFXO has not been started. The HFXO is started by
triggering the HFCLKSTART task and stopped using the HFCLKSTOP task. A HFCLKSTARTED event will be
generated when the HFXO has started and its frequency is stable.
The HFXO must be running to use the RADIO or the calibration mechanism associated with the 32.768 kHz
RC oscillator.
5.4.1.1 64 MHz crystal oscillator (HFXO)
The 64 MHz crystal oscillator (HFXO) is controlled by a 32 MHz external crystal
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The crystal oscillator is designed for use with an AT-cut quartz crystal in parallel resonant mode. To achieve
correct oscillation frequency, the load capacitance must match the specification in the crystal data sheet.
Circuit diagram of the 64 MHz crystal oscillator on page 66 shows how the 32 MHz crystal is connected
to the 64 MHz crystal oscillator.
XC1
XC2
C1
C2
32 MHz
crystal
Figure 20: Circuit diagram of the 64 MHz crystal oscillator
The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by:
C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. For more
information, see Reference circuitry on page 429. Cpcb1 and Cpcb2 are stray capacitances on the PCB. Cpin
is the pin input capacitance on the XC1 and XC2 pins. See table 64 MHz crystal oscillator (HFXO) on page
75. The load capacitors C1 and C2 should have the same value.
For reliable operation, the crystal load capacitance, shunt capacitance, equivalent series resistance, and
drive level must comply with the specifications in table 64 MHz crystal oscillator (HFXO) on page 75. It
is recommended to use a crystal with lower than maximum load capacitance and/or shunt capacitance. A
low load capacitance will reduce both start up time and current consumption.
5.4.2 LFCLK clock controller
The system supports several low frequency clock sources.
As illustrated in Clock control on page 65, the system supports the following low frequency clock
sources:
• 32.768 kHz RC oscillator (LFRC)
• 32.768 kHz crystal oscillator (LFXO)
• 32.768 kHz synthesized from HFCLK (LFSYNT)
The LFCLK clock is started by first selecting the preferred clock source in register LFCLKSRC on page 74
and then triggering the LFCLKSTART task. If the LFXO is selected as the clock source, the LFCLK will initially
start running from the 32.768 kHz LFRC while the LFXO is starting up and automatically switch to using the
LFXO once this oscillator is running. The LFCLKSTARTED event will be generated when the LFXO has been
started.
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Power and clock management
The LFCLK clock is stopped by triggering the LFCLKSTOP task.
It is not allowed to write to register LFCLKSRC on page 74 when the LFCLK is running.
A LFCLKSTOP task will stop the LFCLK oscillator. However, the LFCLKSTOP task can only be triggered after
the STATE field in register LFCLKSTAT on page 74 indicates a 'LFCLK running' state.
The LFCLK clock controller and all of the LFCLK clock sources are always switched off when in OFF mode.
5.4.2.1 32.768 kHz RC oscillator (LFRC)
The default source of the low frequency clock (LFCLK) is the 32.768 kHz RC oscillator (LFRC).
The LFRC frequency will be affected by variation in temperature. The LFRC oscillator can be calibrated to
improve accuracy by using the HFXO as a reference oscillator during calibration. See Table 32.768 kHz RC
oscillator (LFRC) on page 76 for details on the default and calibrated accuracy of the LFRC oscillator.
The LFRC oscillator does not require additional external components.
5.4.2.2 Calibrating the 32.768 kHz RC oscillator
After the 32.768 kHz RC oscillator is started and running, it can be calibrated by triggering the CAL task. In
this case, the HFCLK will be temporarily switched on and used as a reference.
A DONE event will be generated when calibration has finished. The calibration mechanism will only work
as long as HFCLK is generated from the HFCLK crystal oscillator, it is therefore necessary to explicitly start
this crystal oscillator before calibration can be started, see HFCLKSTART task.
It is not allowed to stop the LFRC during an ongoing calibration.
5.4.2.3 Calibration timer
The calibration timer can be used to time the calibration interval of the 32.768 kHz RC oscillator.
The calibration timer is started by triggering the CTSTART task and stopped by triggering the CTSTOP task.
The calibration timer will always start counting down from the value specified in CTIV and generate a CTTO
timeout event when it reaches 0. The Calibration timer will stop by itself when it reaches 0.
CTSTART
CTSTOP
Calibration
timer
CTIV
CTTO
Figure 21: Calibration timer
Due to limitations in the calibration timer, only one task related to calibration, that is, CAL, CTSTART and
CTSTOP, can be triggered for every period of LFCLK.
5.4.2.4 32.768 kHz crystal oscillator (LFXO)
For higher LFCLK accuracy the low frequency crystal oscillator (LFXO) must be used.
The following external clock sources are supported:
• Low swing clock signal applied to the XL1 pin. The XL2 pin shall then be grounded.
• Rail-to-rail clock signal applied to the XL1 pin. The XL2 pin shall then be grounded or left unconnected.
The LFCLKSRC on page 74 register controls the clock source, and its allowed swing. The truth table for
various situations is as follows:
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Power and clock management
SRC
EXTERNAL
BYPASS
Comment
0
0
0
Normal operation, RC is source
0
0
1
DO NOT USE
0
1
X
DO NOT USE
1
0
0
Normal XTAL operation
1
1
0
Apply external low swing signal to XL1, ground XL2
1
1
1
Apply external full swing signal to XL1, leave XL2 grounded or unconnected
1
0
1
DO NOT USE
2
0
0
Normal operation, synth is source
2
0
1
DO NOT USE
2
1
X
DO NOT USE
Table 20: LFCLKSRC configuration depending on clock source
To achieve correct oscillation frequency, the load capacitance must match the specification in the crystal
data sheet. Circuit diagram of the 32.768 kHz crystal oscillator on page 68 shows the LFXO circuitry.
XL1
XL2
C1
C2
32.768 kHz
crystal
Figure 22: Circuit diagram of the 32.768 kHz crystal oscillator
The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by:
C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. Cpcb1 and
Cpcb2 are stray capacitances on the PCB. Cpin is the pin input capacitance on the XC1 and XC2 pins (see
32.768 kHz crystal oscillator (LFXO) on page 76). The load capacitors C1 and C2 should have the same
value.
For more information, see Reference circuitry on page 429.
5.4.2.5 32.768 kHz synthesized from HFCLK (LFSYNT)
LFCLK can also be synthesized from the HFCLK clock source. The accuracy of LFCLK will then be the
accuracy of the HFCLK.
Using the LFSYNT clock avoids the requirement for a 32.768 kHz crystal, but increases average power
consumption as the HFCLK will need to be requested in the system.
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Power and clock management
5.4.3 Registers
Base address
Peripheral
Instance
Description
0x40000000
CLOCK
CLOCK
Clock control
Configuration
Table 21: Instances
Register
Offset
Description
TASKS_HFCLKSTART
0x000
Start HFCLK crystal oscillator
TASKS_HFCLKSTOP
0x004
Stop HFCLK crystal oscillator
TASKS_LFCLKSTART
0x008
Start LFCLK source
TASKS_LFCLKSTOP
0x00C
Stop LFCLK source
TASKS_CAL
0x010
Start calibration of LFRC oscillator
TASKS_CTSTART
0x014
Start calibration timer
TASKS_CTSTOP
0x018
Stop calibration timer
EVENTS_HFCLKSTARTED
0x100
HFCLK oscillator started
EVENTS_LFCLKSTARTED
0x104
LFCLK started
EVENTS_DONE
0x10C
Calibration of LFCLK RC oscillator complete event
EVENTS_CTTO
0x110
Calibration timer timeout
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
HFCLKRUN
0x408
Status indicating that HFCLKSTART task has been triggered
HFCLKSTAT
0x40C
HFCLK status
LFCLKRUN
0x414
Status indicating that LFCLKSTART task has been triggered
LFCLKSTAT
0x418
LFCLK status
LFCLKSRCCOPY
0x41C
Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
LFCLKSRC
0x518
Clock source for the LFCLK
CTIV
0x538
Calibration timer interval
Retained
Table 22: Register overview
5.4.3.1 TASKS_HFCLKSTART
Address offset: 0x000
Start HFCLK crystal oscillator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_HFCLKSTART
Start HFCLK crystal oscillator
Trigger task
5.4.3.2 TASKS_HFCLKSTOP
Address offset: 0x004
Stop HFCLK crystal oscillator
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_HFCLKSTOP
Stop HFCLK crystal oscillator
Trigger task
5.4.3.3 TASKS_LFCLKSTART
Address offset: 0x008
Start LFCLK source
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_LFCLKSTART
Start LFCLK source
Trigger task
5.4.3.4 TASKS_LFCLKSTOP
Address offset: 0x00C
Stop LFCLK source
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_LFCLKSTOP
Stop LFCLK source
Trigger task
5.4.3.5 TASKS_CAL
Address offset: 0x010
Start calibration of LFRC oscillator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_CAL
Start calibration of LFRC oscillator
Trigger
1
Trigger task
5.4.3.6 TASKS_CTSTART
Address offset: 0x014
Start calibration timer
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_CTSTART
Start calibration timer
Trigger task
5.4.3.7 TASKS_CTSTOP
Address offset: 0x018
Stop calibration timer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_CTSTOP
Stop calibration timer
Trigger task
5.4.3.8 EVENTS_HFCLKSTARTED
Address offset: 0x100
HFCLK oscillator started
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_HFCLKSTARTED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
HFCLK oscillator started
5.4.3.9 EVENTS_LFCLKSTARTED
Address offset: 0x104
LFCLK started
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_LFCLKSTARTED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
LFCLK started
5.4.3.10 EVENTS_DONE
Address offset: 0x10C
Calibration of LFCLK RC oscillator complete event
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_DONE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Calibration of LFCLK RC oscillator complete event
5.4.3.11 EVENTS_CTTO
Address offset: 0x110
Calibration timer timeout
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_CTTO
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Calibration timer timeout
5.4.3.12 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C
Reset 0x00000000
ID
Access
Field
A
RW HFCLKSTARTED
B
C
D
Value ID
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to enable interrupt for event HFCLKSTARTED
RW LFCLKSTARTED
Write '1' to enable interrupt for event LFCLKSTARTED
RW DONE
Write '1' to enable interrupt for event DONE
RW CTTO
Write '1' to enable interrupt for event CTTO
5.4.3.13 INTENCLR
Address offset: 0x308
Disable interrupt
4454_140 v1.1
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
72
Power and clock management
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C
Reset 0x00000000
ID
Access
Field
A
RW HFCLKSTARTED
B
C
D
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event HFCLKSTARTED
RW LFCLKSTARTED
Write '1' to disable interrupt for event LFCLKSTARTED
RW DONE
Write '1' to disable interrupt for event DONE
RW CTTO
Write '1' to disable interrupt for event CTTO
5.4.3.14 HFCLKRUN
Address offset: 0x408
Status indicating that HFCLKSTART task has been triggered
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
STATUS
HFCLKSTART task triggered or not
NotTriggered
0
Task not triggered
Triggered
1
Task triggered
5.4.3.15 HFCLKSTAT
Address offset: 0x40C
HFCLK status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B
Reset 0x00000000
ID
Access
Field
A
R
B
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
SRC
Source of HFCLK
RC
0
64 MHz internal oscillator (HFINT)
Xtal
1
64 MHz crystal oscillator (HFXO)
NotRunning
0
HFCLK not running
Running
1
HFCLK running
STATE
HFCLK state
5.4.3.16 LFCLKRUN
Address offset: 0x414
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Power and clock management
Status indicating that LFCLKSTART task has been triggered
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
STATUS
LFCLKSTART task triggered or not
NotTriggered
0
Task not triggered
Triggered
1
Task triggered
5.4.3.17 LFCLKSTAT
Address offset: 0x418
LFCLK status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B
Reset 0x00000000
ID
Access
Field
A
R
B
R
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
SRC
Source of LFCLK
RC
0
32.768 kHz RC oscillator
Xtal
1
32.768 kHz crystal oscillator
Synth
2
32.768 kHz synthesized from HFCLK
STATE
LFCLK state
NotRunning
0
LFCLK not running
Running
1
LFCLK running
5.4.3.18 LFCLKSRCCOPY
Address offset: 0x41C
Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
SRC
Clock source
RC
0
32.768 kHz RC oscillator
Xtal
1
32.768 kHz crystal oscillator
Synth
2
32.768 kHz synthesized from HFCLK
5.4.3.19 LFCLKSRC
Address offset: 0x518
Clock source for the LFCLK
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C B
Reset 0x00000000
ID
Access
Field
A
RW SRC
B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
RC
0
32.768 kHz RC oscillator
Xtal
1
32.768 kHz crystal oscillator
Synth
2
32.768 kHz synthesized from HFCLK
Clock source
RW BYPASS
Enable or disable bypass of LFCLK crystal oscillator with
external clock source
C
Disabled
0
Disable (use with Xtal or low-swing external source)
Enabled
1
Enable (use with rail-to-rail external source)
Disabled
0
Disable external source (use with Xtal)
Enabled
1
Enable use of external source instead of Xtal (SRC needs to
RW EXTERNAL
Enable or disable external source for LFCLK
be set to Xtal)
5.4.3.20 CTIV ( Retained )
Address offset: 0x538
This register is a retained register
Calibration timer interval
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW CTIV
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Calibration timer interval in multiple of 0.25 seconds.
Range: 0.25 seconds to 31.75 seconds.
5.4.4 Electrical specification
5.4.4.1 64 MHz internal oscillator (HFINT)
Symbol
Description
fNOM_HFINT
Nominal output frequency
Min.
Typ.
64
fTOL_HFINT
Frequency tolerance
TASKS_EDSTART = 1; // Start
while (NRF_RADIO->EVENTS_EDEND != 1) {
// CPU can sleep here or do something else
// Use of interrupts are encouraged
}
val = NRF_RADIO->EDSAMPLE * ED_RSSISCALE; // Read level
return (uint8_t)(val>255 ? 255 : val);
scale
// Convert to IEEE 802.15.4
}
For scaling between hardware value and dBm, see equation Conversion between hardware value and dBm
on page 202.
The mlme-scan.req primitive of the MAC layer uses the ED measurement to detect channels where there
might be wireless activity. To assist this primitive, a tailored mode of operation is available where the
ED measurement runs for a defined number of iterations keeping track of the maximum ED level. This is
enganged by writing the EDCNT register to a value different from 0, where it will run the specified number
of iterations and report the maximum energy measurement in the EDSAMPLE register. The scan is started
with EDSTART task and its end indicated with the EDEND event. This significantly reduces the interrupt
frequency and therefore power consumption. The following figure shows how the ED measurement will
operate depending on the EDCNT register.
EDCNT = 0
EDSTART
EDEND
128 µs
EDCNT = N-1
EDEND
EDSTART
Scan 0
...
Scan 1
Scan N-1
128*(N) µs
Figure 82: Energy detection measurement examples
The scan is stopped by writing the EDSTOP task. It will be followed by the EDSTOPPED event when the
module has terminated.
6.14.13.4 Clear channel assessment (CCA)
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IEEE 802.15.4 implements a listen-before-talk channel access method to avoid collisions when
transmitting, known as carrier sense multiple access with collision avoidance (CSMA-CA). The key part of
this is measuring if the wireless medium is busy or not.
The following clear channel assesment modes are supported:
• CCA Mode 1 (energy above threshold) - The medium is reported busy upon detecting any energy above
the ED threshold.
• CCA Mode 2 (carrier sense only) - The medium is reported busy upon detection of a signal compliant
with the IEEE 802.15.4 standard with the same modulation and spreading characteristics.
• CCA Mode 3 (carrier sense with energy above threshold) - The medium is reported busy using a logical
combination (AND/OR) between the results from CCA Mode 1 and CCA Mode 2.
The clear channel assessment should survey a period equal to 8 symbols or 128 µs.
The RADIO must be in receive mode and be able to receive correct packets when performing the CCA. The
shortcut between READY and START must be disabled if baseband processing is not to be performed while
the measurement is running.
CCA Mode 1
CCA Mode 1 is enabled by first configuring the field CCACTRL.CCAMODE=EdMode and writing the
CCACTRL.CCAEDTHRES field to a chosen value. Once the CCASTART task is written, the RADIO will
perform a ED measurement for 8 symbols and compare the measured level with that found in the
CCACTRL.CCAEDTHRES field. If the measured value is higher than or equal to this threshold, the CCABUSY
event is generated. If the measured level is less than the threshold, the CCAIDLE event is generated.
CCA Mode 2
CCA Mode 2 is enabled by configuring CCACTRL.CCAMODE=CarrierMode. The RADIO will sample to see
if a valid SFD is found during the 8 symbols. If a valid SFD is detected, the CCABUSY event is generated
and the device should not send any data. The CCABUSY event is also generated if the scan was performed
during an ongoing frame reception. In the case where the measurement period completes with no SFD
detection, the CCAIDLE event is generated. When CCACTRL.CCACORRCNT is not zero, the algorithm will
look at the correlator output in addition to the SFD detection signal. If a SFD is reported during the scan
period, it will terminate immidiately indicating busy medium. Similarly, if the number of peaks above
CCACTRL.CCACORRTHRES crosses the CCACTRL.CCACORRCNT, the CCACTRL.CCABUSY event is generated.
If less than CCACORRCOUNT crossings are found and no SFD is reported, the CCAIDLE event will be
generated and the device can send data.
CCA Mode 3
CCA Mode 3 is enabled by configuring CCACTRL.CCAMODE=CarrierAndEdMode or
CCACTRL.CCAMODE=CarrierOrEdMode, performing the required logical combination of the result from
CCA Mode 1 and 2. The CCABUSY or CCAIDLE events are generated by ANDing or ORing the energy above
threshold and carrier detection scans.
Shortcuts
An ongoing CCA can always be stopped by issuing the CCASTOP task. This will trigger the associated
CCASTOPPED event.
For CCA mode automation, a number of shortcuts are available.
• To automatically switch between RX (when performing the CCA) and to TX where the packet is sent,
the shortcut between CCAIDLE and TXEN, in conjunction with the short between CCAIDLE and STOP
muse be used.
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• To automatically disable the RADIO whenever the CCA reports a busy medium, the shortcut between
CCABUSY and DISABLE can be used.
• To immediately start a CCA after ramping up into RX mode, the shortcut between RXREADY and
CCASTART can be used.
Conversion
The conversion from a CCAEDTHRES, LQI, or EDSAMPLE value to dBm can be done with the following
equation, where VALHARDWARE is either CCAEDTHRES, LQI, or EDSAMPLE. LQI and EDSAMPLE are hardwarereported values, while CCAEDTHRES is set by software. Constants ED_RSSISCALE and ED_RSSIOFFS are
from electrical specifications.
PRF[dBm] = ED_RSSIOFFS + VALHARDWARE
Figure 83: Conversion between hardware value and dBm
The ED_RSSISCALE constant is used to calculate power in 802.15.4 units (0-255):
PRF[802.15.4 units] = MIN( ED_RSSISCALE x VALHARDWARE, 255 )
Figure 84: Conversion between hardware value and 802.15.4 units (0-255)
6.14.13.5 Cyclic redundancy check (CRC)
IEEE 802.15.4 uses a 16-bit ITU-T cyclic redundancy check (CRC) calculated over the MAC header (MHR)
and MAC service data unit (MSDU).
The standard defines the following generator polynomial:
G(x) = x16 + x12 + x5 + 1
In receive mode the RADIO will trigger the CRC module when the first octet after the frame length (PHR)
is received. The CRC will then update on each consecutive octet received. When a complete frame
is received the CRCSTATUS register will be updated accordingly and the CRCOK or CRCERROR events
generated. When the CRC module is enabled it will not write the two last octets (CRC) to the frame Data
RAM. When transmitting, the CRC will be computed on the fly, starting with the first octet after PHR, and
inserted as the two last octets in the frame. The EasyDMA will fetch frame length minus 2 octets from
RAM and insert the CRC octets insitu.
The following code shows how to configure the CRC module for correct operation when in IEEE 802.15.4
mode. The CRCCNF is written to 16-bit CRC and the CRCPOLY is written to 0x11021. The start value used by
IEEE 802.15.4 is zero and CRCINIT is configured to reflect this.
/* 16-bit CRC with ITU-T polynomial with 0 as start condition*/
NRF_RADIO->CRCCNF = ((RADIO_CRCCNF_SKIPADDR_Ieee802154 CRCINIT = 0;
The ENDIANESS subregister must be set to little-endian since the FCS field is transmitted from left bit to
right.
6.14.13.6 Transmit sequence
The transmission is started by first putting the RADIO in receive mode and triggering the RXEN task.
An outline of the IEEE 802.15.4 transmission is illustrated in the following figure.
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TXRU
TXIDLE
FRAMESTART
READY
READY
START
TXEN
CCASTART
Lifeline
RXEN
P
H
R
SHR
CCAIDLE
Clear channel
TX
PAYLOAD
TXIDLE
TXDISABLE
CRC
DISABLED
RX
DISABLE
RXIDLE
Transmitter/Receiver
RXRU
END
State
Peripherals
Figure 85: IEEE 802.15.4 transmit sequence
The receiver will ramp up and enter the RXIDLE state where the READY event is generated. Upon receiving
the ready event, the CCA is started by triggering the CCASTART task. The chosen mode of assessment
(CCACTRL.CCAMODE register) will be performed and signal the CCAIDLE or CCABUSY event 128 µs later. If
the CCABUSY event is received, the RADIO will have to retry the CCA after a specific back-off period. This is
outlined in the IEEE 802.15.4 standard, Figure 69 in section 7.5.1.4 The CSMA-CA algorithm.
If the CCAIDLE event is generated, a write to the TXEN task register enters the RADIO in TXRU state.
The READY event will be generated when the RADIO is in TXIDLE state and ready to transmit. With the
PACKETPTR pointing to the length (PHR) field of the frame, the START task can be written. The RADIO will
send the four octet preamble sequence followed by the start of frame delimiter (SFD register). The first
byte read from the Data RAM is the length field (PHR) followed by the transmission of the number of
bytes indicated as the frame length. If the CRC module is configured it will run for PHR-2 octets. The last
two octets will be substituted with the results from running the CRC. The necessary CRC parameters are
sampled on the START task. The FCS field of the frame is little endian.
In addition to the already available shortcuts, one is provided between READY event and CCASTART task so
that a CCA can automatically start when the receiver is ready. A second shortcut has been added between
CCAIDLE event and the TXEN task, so that upon detecting a clear channel the RADIO can immediately
enter transmit mode.
6.14.13.7 Receive sequence
The reception is started by first putting the RADIO in receive mode. After writing to the RXEN task, the
RADIO will start ramping up and enter the RXRU state.
When the READY event is generated, the RADIO enters the RXIDLE mode. For the baseband processing to
be enabled, the START task must be written. An outline of the IEEE 802.15.4 reception can be found in the
following figure.
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RX
SHR
READY
PAYLOAD
RXDISABLE
CRC
START
DISABLE
Lifeline
RXEN
P
H
R
FRAMESTART
’X’
RXIDLE
DISABLED
RXIDLE
Reception
RXRU
END
State
Peripherals
Figure 86: IEEE 802.15.4 receive sequence
When a valid SHR is received, the RADIO will start storing future octets (starting with PHR) to the data
memory pointed to by PACKETPTR. After the SFD octet is received, the FRAMESTART event is generated.
If the CRC module is enabled it will start updating with the second byte received (first byte in payload)
and run for the full frame length. The two last bytes in the frame are not written to RAM when CRC is
configured. However, if the result of the CRC after running the full frame is zero, the CRCOK event will
be generated. The END event is generated when the last octet has been received and is available in data
memory.
When a packet is received, a link quality indicator (LQI) is also generated and appended immediately after
the last received octet. When using an IEEE 802.15.4 compliant frame, this will be just after the MSDU
since the FCS is not reported. In the case of a non-compliant frame, it will be appended after the full
frame. The LQI reported by hardware must be converted to IEEE 802.15.4 range by an 8-bit saturating
multiplication of 4, as shown in IEEE 802.15.4 ED measurement example on page 200. The LQI is only
valid for frames equal to or longer than three octets. When receiving a frame, the RSSI (reported as
negative dB) will be measured at three points during the reception. These three values will be sorted and
the middle one selected (median 3) to be remapped within the LQI range. The following figure illustrates
the LQI measurement and how the data is arranged in data memory.
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On air frame
160 µs
32 µs
≤4064 µs
PHY protocol data unit (PPDU)
Preamble sequence
SFD
5 octets synchronization header (SHR)
Length
PHY payload
1 octet
(PHR)
Maximum 127 octets (PSDU)
MAC protocol data unit (MPDU)
RSSI
RSSI
RSSI
Median 3
In RAM frame
Length
PHY payload
1 octet
(PHR)
Maximum 127 octets (PSDU)
LQI
FCF
2 octets
1 octet
MAC protocol data unit (MPDU)
Omitted if CRC enabled
Figure 87: IEEE 802.15.4 frame in data memory
A shortcut has been added between the FRAMESTART event and the BCSTART task. This can be used to
trigger a BCMATCH event after N bits, such as when inspecting the MAC addressing fields.
6.14.13.8 Interframe spacing (IFS)
The IEEE 802.15.4 standard defines a specific time that is alotted for the MAC sublayer to process received
data. Interframe spacing (IFS) is used to prevent two frames from being transmitted too close together. If
the transmission is requesting an acknowledgement, the space before the second frame shall be at least
one IFS period.
The IFS is determined to be one of the following:
• IFS equals macMinSIFSPeriod (12 symbols) if the MPDU is less than or equal to aMaxSIFSFrameSize (18
octets) octets
• IFS equals macMinLIFSPeriod (40 symbols) if the MPDU is larger than aMaxSIFSFrameSize
Using the efficient assisted modes in the RADIO, the TIFS will be programmed with the correct value based
on the frame being transmitted. If the assisted modes are not in use, the TIFS register must be updated
manually. The following figure provides details on what IFS period is valid in both acknowledged and
unacknowledged transmissions.
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Acknowledged transmission
Long frame
ACK
tack = 32 symbols
Short frame
tlifs = 40 symbols
ACK
tack = 32 symbols
tsifs = 12 symbols
Unacknowledged transmission
Long frame
Short frame
tlifs = 40 symbols
tsifs = 12 symbols
Figure 88: Interframe spacing examples
6.14.14 EasyDMA
The RADIO uses EasyDMA to read and write packets to RAM without CPU involvement.
As illustrated in RADIO block diagram on page 184, the RADIO's EasyDMA utilizes the same PACKETPTR
for receiving and transmitting packets. This pointer should be reconfigured by the CPU each time before
RADIO is started by the START task. The PACKETPTR register is double-buffered, meaning that it can be
updated and prepared for the next transmission.
The END event indicates that the last bit has been processed by the RADIO. The DISABLED event is issued
to acknowledge that a DISABLE task is done.
The structure of a packet is described in detail in Packet configuration on page 184. The data that is
stored in Data RAM and transported by EasyDMA consists of the following fields:
•
•
•
•
S0
LENGTH
S1
PAYLOAD
In addition, a static add-on is sent immediately after the payload.
The size of each of the above fields in the frame is configurable (see Packet configuration on page 184),
and the space occupied in RAM depends on these settings. The size of the field can be zero, as long as the
resulting frame complies with the chosen RF protocol.
All fields are extended in size to align with a byte boundary in RAM. For instance, a 3-bit long field on air
will occupy 1 byte in RAM while a 9-bit long field will be extended to 2 bytes.
The packet's elements can be configured as follows:
•
•
•
•
•
•
CI, TERM1, and TERM2 fields are only present in Bluetooth® Low Energy Long Range mode
S0 is configured through the PCNF0.S0LEN field
LENGTH is configured through the PCNF0.LFLEN field
S1 is configured through the PCNF0.S1LEN field
Payload size is configured through the value in RAM corresponding to the LENGTH field
Static add-on size is configured through the PCNF1.STATLEN field
The PCNF1.MAXLEN field configures the maximum packet payload plus add-on size in number of bytes
that can be transmitted or received by the RADIO. This feature can be used to ensure that the RADIO does
not overwrite, or read beyond, the RAM assigned to the packet payload. This means that if the LENGTH
field of the packet payload exceedes PCNF1.STATLEN, and the LENGTH field in the packet specifies a
packet larger than configured in PCNF1.MAXLEN, the payload will be truncated to the length specified in
PCNF1.MAXLEN.
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Note: The PCNF1.MAXLEN field includes the payload and the add-on, but excludes the size
occupied by the S0, LENGTH, and S1 fields. This has to be taken into account when allocating RAM.
If the payload and add-on length is specified larger than PCNF1.MAXLEN, the RADIO will still transmit or
receive in the same way as before, except the payload is now truncated to PCNF1.MAXLEN. The packet's
LENGTH field will not be altered when the payload is truncated. The RADIO will calculate CRC as if the
packet length is equal to PCNF1.MAXLEN.
Note: If PACKETPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a
HardFault or RAM corruption. See Memory on page 16 for more information about the different
memory regions.
The END event indicates that the last bit has been processed by the RADIO. The DISABLED event is issued
to acknowledge that an DISABLE task is done.
6.14.15 Registers
Base address
Peripheral
Instance
Description
0x40001000
RADIO
RADIO
2.4 GHz radio
Configuration
Table 71: Instances
Register
Offset
Description
TASKS_TXEN
0x000
Enable RADIO in TX mode
TASKS_RXEN
0x004
Enable RADIO in RX mode
TASKS_START
0x008
Start RADIO
TASKS_STOP
0x00C
Stop RADIO
TASKS_DISABLE
0x010
Disable RADIO
TASKS_RSSISTART
0x014
Start the RSSI and take one single sample of the receive signal strength
TASKS_RSSISTOP
0x018
Stop the RSSI measurement
TASKS_BCSTART
0x01C
Start the bit counter
TASKS_BCSTOP
0x020
Stop the bit counter
TASKS_EDSTART
0x024
Start the energy detect measurement used in IEEE 802.15.4 mode
TASKS_EDSTOP
0x028
Stop the energy detect measurement
TASKS_CCASTART
0x02C
Start the clear channel assessment used in IEEE 802.15.4 mode
TASKS_CCASTOP
0x030
Stop the clear channel assessment
EVENTS_READY
0x100
RADIO has ramped up and is ready to be started
EVENTS_ADDRESS
0x104
Address sent or received
EVENTS_PAYLOAD
0x108
Packet payload sent or received
EVENTS_END
0x10C
Packet sent or received
EVENTS_DISABLED
0x110
RADIO has been disabled
EVENTS_DEVMATCH
0x114
A device address match occurred on the last received packet
EVENTS_DEVMISS
0x118
No device address match occurred on the last received packet
EVENTS_RSSIEND
0x11C
Sampling of receive signal strength complete
EVENTS_BCMATCH
0x128
Bit counter reached bit count value
EVENTS_CRCOK
0x130
Packet received with CRC ok
EVENTS_CRCERROR
0x134
Packet received with CRC error
EVENTS_FRAMESTART
0x138
IEEE 802.15.4 length field received
EVENTS_EDEND
0x13C
Sampling of energy detection complete. A new ED sample is ready for readout from the
EVENTS_EDSTOPPED
0x140
The sampling of energy detection has stopped
EVENTS_CCAIDLE
0x144
Wireless medium in idle - clear to send
EVENTS_CCABUSY
0x148
Wireless medium busy - do not send
RADIO.EDSAMPLE register.
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Register
Offset
Description
EVENTS_CCASTOPPED
0x14C
The CCA has stopped
EVENTS_RATEBOOST
0x150
Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.
EVENTS_TXREADY
0x154
RADIO has ramped up and is ready to be started TX path
EVENTS_RXREADY
0x158
RADIO has ramped up and is ready to be started RX path
EVENTS_MHRMATCH
0x15C
MAC header match found
EVENTS_SYNC
0x168
Preamble indicator
EVENTS_PHYEND
0x16C
Generated when last bit is sent on air, or received from air
EVENTS_CTEPRESENT
0x170
CTE is present (early warning right after receiving CTEInfo byte)
SHORTS
0x200
Shortcuts between local events and tasks
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
CRCSTATUS
0x400
CRC status
RXMATCH
0x408
Received address
RXCRC
0x40C
CRC field of previously received packet
DAI
0x410
Device address match index
PDUSTAT
0x414
Payload status
CTESTATUS
0x44C
CTEInfo parsed from received packet
DFESTATUS
0x458
DFE status information
PACKETPTR
0x504
Packet pointer
FREQUENCY
0x508
Frequency
TXPOWER
0x50C
Output power
MODE
0x510
Data rate and modulation
PCNF0
0x514
Packet configuration register 0
PCNF1
0x518
Packet configuration register 1
BASE0
0x51C
Base address 0
BASE1
0x520
Base address 1
PREFIX0
0x524
Prefixes bytes for logical addresses 0-3
PREFIX1
0x528
Prefixes bytes for logical addresses 4-7
TXADDRESS
0x52C
Transmit address select
RXADDRESSES
0x530
Receive address select
CRCCNF
0x534
CRC configuration
CRCPOLY
0x538
CRC polynomial
CRCINIT
0x53C
CRC initial value
TIFS
0x544
Interframe spacing in µs
RSSISAMPLE
0x548
RSSI sample
STATE
0x550
Current radio state
DATAWHITEIV
0x554
Data whitening initial value
BCC
0x560
Bit counter compare
DAB[n]
0x600
Device address base segment n
DAP[n]
0x620
Device address prefix n
DACNF
0x640
Device address match configuration
MHRMATCHCONF
0x644
Search pattern configuration
MHRMATCHMAS
0x648
Pattern mask
MODECNF0
0x650
Radio mode configuration register 0
SFD
0x660
IEEE 802.15.4 start of frame delimiter
EDCNT
0x664
IEEE 802.15.4 energy detect loop count
EDSAMPLE
0x668
IEEE 802.15.4 energy detect level
CCACTRL
0x66C
IEEE 802.15.4 clear channel assessment control
DFEMODE
0x900
Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)
CTEINLINECONF
0x904
Configuration for CTE inline mode
DFECTRL1
0x910
Various configuration for Direction finding
DFECTRL2
0x914
Start offset for Direction finding
SWITCHPATTERN
0x928
GPIO patterns to be used for each antenna
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Register
Offset
Description
CLEARPATTERN
0x92C
Clear the GPIO pattern array for antenna control
PSEL.DFEGPIO[0]
0x930
Pin select for DFE pin 0
PSEL.DFEGPIO[1]
0x934
Pin select for DFE pin 1
PSEL.DFEGPIO[2]
0x938
Pin select for DFE pin 2
PSEL.DFEGPIO[3]
0x93C
Pin select for DFE pin 3
PSEL.DFEGPIO[4]
0x940
Pin select for DFE pin 4
PSEL.DFEGPIO[5]
0x944
Pin select for DFE pin 5
PSEL.DFEGPIO[6]
0x948
Pin select for DFE pin 6
PSEL.DFEGPIO[7]
0x94C
Pin select for DFE pin 7
DFEPACKET.PTR
0x950
Data pointer
DFEPACKET.MAXCNT
0x954
Maximum number of buffer words to transfer
DFEPACKET.AMOUNT
0x958
Number of samples transferred in the last transaction
POWER
0xFFC
Peripheral power control
Table 72: Register overview
6.14.15.1 TASKS_TXEN
Address offset: 0x000
Enable RADIO in TX mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_TXEN
Enable RADIO in TX mode
Trigger task
6.14.15.2 TASKS_RXEN
Address offset: 0x004
Enable RADIO in RX mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_RXEN
Enable RADIO in RX mode
Trigger task
6.14.15.3 TASKS_START
Address offset: 0x008
Start RADIO
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_START
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Peripherals
6.14.15.4 TASKS_STOP
Address offset: 0x00C
Stop RADIO
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_STOP
Stop RADIO
Trigger task
6.14.15.5 TASKS_DISABLE
Address offset: 0x010
Disable RADIO
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_DISABLE
Disable RADIO
Trigger task
6.14.15.6 TASKS_RSSISTART
Address offset: 0x014
Start the RSSI and take one single sample of the receive signal strength
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_RSSISTART
Start the RSSI and take one single sample of the receive
signal strength
Trigger
1
Trigger task
6.14.15.7 TASKS_RSSISTOP
Address offset: 0x018
Stop the RSSI measurement
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_RSSISTOP
Stop the RSSI measurement
Trigger
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210
Peripherals
6.14.15.8 TASKS_BCSTART
Address offset: 0x01C
Start the bit counter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_BCSTART
Start the bit counter
Trigger task
6.14.15.9 TASKS_BCSTOP
Address offset: 0x020
Stop the bit counter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_BCSTOP
Stop the bit counter
Trigger task
6.14.15.10 TASKS_EDSTART
Address offset: 0x024
Start the energy detect measurement used in IEEE 802.15.4 mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_EDSTART
Start the energy detect measurement used in IEEE 802.15.4
mode
Trigger
1
Trigger task
6.14.15.11 TASKS_EDSTOP
Address offset: 0x028
Stop the energy detect measurement
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_EDSTOP
Stop the energy detect measurement
Trigger
4454_140 v1.1
1
Trigger task
211
Peripherals
6.14.15.12 TASKS_CCASTART
Address offset: 0x02C
Start the clear channel assessment used in IEEE 802.15.4 mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_CCASTART
Start the clear channel assessment used in IEEE 802.15.4
mode
Trigger
1
Trigger task
6.14.15.13 TASKS_CCASTOP
Address offset: 0x030
Stop the clear channel assessment
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_CCASTOP
Stop the clear channel assessment
Trigger task
6.14.15.14 EVENTS_READY
Address offset: 0x100
RADIO has ramped up and is ready to be started
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_READY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
RADIO has ramped up and is ready to be started
6.14.15.15 EVENTS_ADDRESS
Address offset: 0x104
Address sent or received
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_ADDRESS
4454_140 v1.1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Address sent or received
212
Peripherals
6.14.15.16 EVENTS_PAYLOAD
Address offset: 0x108
Packet payload sent or received
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_PAYLOAD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Packet payload sent or received
6.14.15.17 EVENTS_END
Address offset: 0x10C
Packet sent or received
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_END
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Packet sent or received
6.14.15.18 EVENTS_DISABLED
Address offset: 0x110
RADIO has been disabled
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_DISABLED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
RADIO has been disabled
6.14.15.19 EVENTS_DEVMATCH
Address offset: 0x114
A device address match occurred on the last received packet
4454_140 v1.1
213
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_DEVMATCH
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
A device address match occurred on the last received
packet
NotGenerated
0
Event not generated
Generated
1
Event generated
6.14.15.20 EVENTS_DEVMISS
Address offset: 0x118
No device address match occurred on the last received packet
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_DEVMISS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
No device address match occurred on the last received
packet
NotGenerated
0
Event not generated
Generated
1
Event generated
6.14.15.21 EVENTS_RSSIEND
Address offset: 0x11C
Sampling of receive signal strength complete
A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_RSSIEND
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Sampling of receive signal strength complete
A new RSSI sample is ready for readout from the
RADIO.RSSISAMPLE register
NotGenerated
0
Event not generated
Generated
1
Event generated
6.14.15.22 EVENTS_BCMATCH
Address offset: 0x128
Bit counter reached bit count value
Bit counter value is specified in the RADIO.BCC register
4454_140 v1.1
214
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_BCMATCH
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Bit counter reached bit count value
Bit counter value is specified in the RADIO.BCC register
NotGenerated
0
Event not generated
Generated
1
Event generated
6.14.15.23 EVENTS_CRCOK
Address offset: 0x130
Packet received with CRC ok
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_CRCOK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Packet received with CRC ok
NotGenerated
0
Event not generated
Generated
1
Event generated
6.14.15.24 EVENTS_CRCERROR
Address offset: 0x134
Packet received with CRC error
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_CRCERROR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Packet received with CRC error
NotGenerated
0
Event not generated
Generated
1
Event generated
6.14.15.25 EVENTS_FRAMESTART
Address offset: 0x138
IEEE 802.15.4 length field received
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_FRAMESTART
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
IEEE 802.15.4 length field received
NotGenerated
0
Event not generated
Generated
1
Event generated
6.14.15.26 EVENTS_EDEND
Address offset: 0x13C
4454_140 v1.1
215
Peripherals
Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE
register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_EDEND
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Sampling of energy detection complete. A new ED sample is
ready for readout from the RADIO.EDSAMPLE register.
NotGenerated
0
Event not generated
Generated
1
Event generated
6.14.15.27 EVENTS_EDSTOPPED
Address offset: 0x140
The sampling of energy detection has stopped
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_EDSTOPPED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
The sampling of energy detection has stopped
6.14.15.28 EVENTS_CCAIDLE
Address offset: 0x144
Wireless medium in idle - clear to send
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_CCAIDLE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Wireless medium in idle - clear to send
6.14.15.29 EVENTS_CCABUSY
Address offset: 0x148
Wireless medium busy - do not send
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_CCABUSY
4454_140 v1.1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Wireless medium busy - do not send
216
Peripherals
6.14.15.30 EVENTS_CCASTOPPED
Address offset: 0x14C
The CCA has stopped
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_CCASTOPPED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
The CCA has stopped
6.14.15.31 EVENTS_RATEBOOST
Address offset: 0x150
Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_RATEBOOST
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Ble_LR CI field received, receive mode is changed from
Ble_LR125Kbit to Ble_LR500Kbit.
NotGenerated
0
Event not generated
Generated
1
Event generated
6.14.15.32 EVENTS_TXREADY
Address offset: 0x154
RADIO has ramped up and is ready to be started TX path
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_TXREADY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
RADIO has ramped up and is ready to be started TX path
6.14.15.33 EVENTS_RXREADY
Address offset: 0x158
RADIO has ramped up and is ready to be started RX path
4454_140 v1.1
217
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_RXREADY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
RADIO has ramped up and is ready to be started RX path
6.14.15.34 EVENTS_MHRMATCH
Address offset: 0x15C
MAC header match found
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_MHRMATCH
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
MAC header match found
6.14.15.35 EVENTS_SYNC
Address offset: 0x168
Preamble indicator
A possible preamble has been received in Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit modes
during an RX transaction. False triggering of the event is possible.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_SYNC
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Preamble indicator
A possible preamble has been received in Ble_LR125Kbit,
Ble_LR500Kbit, or Ieee802154_250Kbit modes during an RX
transaction. False triggering of the event is possible.
NotGenerated
0
Event not generated
Generated
1
Event generated
6.14.15.36 EVENTS_PHYEND
Address offset: 0x16C
Generated when last bit is sent on air, or received from air
4454_140 v1.1
218
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_PHYEND
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Generated when last bit is sent on air, or received from air
6.14.15.37 EVENTS_CTEPRESENT
Address offset: 0x170
CTE is present (early warning right after receiving CTEInfo byte)
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_CTEPRESENT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
CTE is present (early warning right after receiving CTEInfo
byte)
NotGenerated
0
Event not generated
Generated
1
Event generated
6.14.15.38 SHORTS
Address offset: 0x200
Shortcuts between local events and tasks
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
U T S R Q P O N M L K
Reset 0x00000000
ID
Access
Field
A
RW READY_START
B
C
D
E
F
G
H
G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Shortcut between event READY and task START
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW END_DISABLE
Shortcut between event END and task DISABLE
RW DISABLED_TXEN
Shortcut between event DISABLED and task TXEN
RW DISABLED_RXEN
Shortcut between event DISABLED and task RXEN
RW ADDRESS_RSSISTART
Shortcut between event ADDRESS and task RSSISTART
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW END_START
Shortcut between event END and task START
RW ADDRESS_BCSTART
Shortcut between event ADDRESS and task BCSTART
RW DISABLED_RSSISTOP
4454_140 v1.1
H
Shortcut between event DISABLED and task RSSISTOP
219
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
U T S R Q P O N M L K
Reset 0x00000000
ID
K
L
M
N
O
P
Q
R
S
T
U
Access
Field
H
G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW RXREADY_CCASTART
Shortcut between event RXREADY and task CCASTART
RW CCAIDLE_TXEN
Shortcut between event CCAIDLE and task TXEN
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW CCABUSY_DISABLE
Shortcut between event CCABUSY and task DISABLE
RW FRAMESTART_BCSTART
Shortcut between event FRAMESTART and task BCSTART
RW READY_EDSTART
Shortcut between event READY and task EDSTART
RW EDEND_DISABLE
Shortcut between event EDEND and task DISABLE
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW CCAIDLE_STOP
Shortcut between event CCAIDLE and task STOP
RW TXREADY_START
Shortcut between event TXREADY and task START
RW RXREADY_START
Shortcut between event RXREADY and task START
RW PHYEND_DISABLE
Shortcut between event PHYEND and task DISABLE
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW PHYEND_START
Shortcut between event PHYEND and task START
6.14.15.39 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
a Z Y
Reset 0x00000000
ID
Access
Field
A
RW READY
4454_140 v1.1
V U T S R Q P O N M L K
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to enable interrupt for event READY
220
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
a Z Y
Reset 0x00000000
ID
Access
Field
B
RW ADDRESS
C
D
E
F
G
H
V U T S R Q P O N M L K
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to enable interrupt for event ADDRESS
RW PAYLOAD
Write '1' to enable interrupt for event PAYLOAD
RW END
Write '1' to enable interrupt for event END
RW DISABLED
Write '1' to enable interrupt for event DISABLED
RW DEVMATCH
Write '1' to enable interrupt for event DEVMATCH
RW DEVMISS
Write '1' to enable interrupt for event DEVMISS
RW RSSIEND
Write '1' to enable interrupt for event RSSIEND
A new RSSI sample is ready for readout from the
RADIO.RSSISAMPLE register
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW BCMATCH
Write '1' to enable interrupt for event BCMATCH
Bit counter value is specified in the RADIO.BCC register
K
L
M
N
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
RW CRCOK
Write '1' to enable interrupt for event CRCOK
RW CRCERROR
Write '1' to enable interrupt for event CRCERROR
RW FRAMESTART
Write '1' to enable interrupt for event FRAMESTART
RW EDEND
4454_140 v1.1
Write '1' to enable interrupt for event EDEND
221
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
a Z Y
Reset 0x00000000
ID
O
P
Q
R
S
T
U
V
Y
Access
Field
V U T S R Q P O N M L K
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Enabled
1
Read: Enabled
RW EDSTOPPED
Write '1' to enable interrupt for event EDSTOPPED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CCAIDLE
Write '1' to enable interrupt for event CCAIDLE
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CCABUSY
Write '1' to enable interrupt for event CCABUSY
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CCASTOPPED
Write '1' to enable interrupt for event CCASTOPPED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RATEBOOST
Write '1' to enable interrupt for event RATEBOOST
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXREADY
Write '1' to enable interrupt for event TXREADY
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXREADY
Write '1' to enable interrupt for event RXREADY
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW MHRMATCH
Write '1' to enable interrupt for event MHRMATCH
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SYNC
Write '1' to enable interrupt for event SYNC
A possible preamble has been received in Ble_LR125Kbit,
Ble_LR500Kbit, or Ieee802154_250Kbit modes during an RX
transaction. False triggering of the event is possible.
Z
a
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PHYEND
Write '1' to enable interrupt for event PHYEND
RW CTEPRESENT
4454_140 v1.1
Write '1' to enable interrupt for event CTEPRESENT
222
Peripherals
6.14.15.40 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
a Z Y
Reset 0x00000000
ID
Access
Field
A
RW READY
B
C
D
E
F
G
H
V U T S R Q P O N M L K
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event READY
RW ADDRESS
Write '1' to disable interrupt for event ADDRESS
RW PAYLOAD
Write '1' to disable interrupt for event PAYLOAD
RW END
Write '1' to disable interrupt for event END
RW DISABLED
Write '1' to disable interrupt for event DISABLED
RW DEVMATCH
Write '1' to disable interrupt for event DEVMATCH
RW DEVMISS
Write '1' to disable interrupt for event DEVMISS
RW RSSIEND
Write '1' to disable interrupt for event RSSIEND
A new RSSI sample is ready for readout from the
RADIO.RSSISAMPLE register
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW BCMATCH
Write '1' to disable interrupt for event BCMATCH
Bit counter value is specified in the RADIO.BCC register
K
L
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CRCOK
Write '1' to disable interrupt for event CRCOK
RW CRCERROR
4454_140 v1.1
Write '1' to disable interrupt for event CRCERROR
223
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
a Z Y
Reset 0x00000000
ID
M
N
O
P
Q
R
S
T
U
V
Y
Access
Field
V U T S R Q P O N M L K
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW FRAMESTART
Write '1' to disable interrupt for event FRAMESTART
RW EDEND
Write '1' to disable interrupt for event EDEND
RW EDSTOPPED
Write '1' to disable interrupt for event EDSTOPPED
RW CCAIDLE
Write '1' to disable interrupt for event CCAIDLE
RW CCABUSY
Write '1' to disable interrupt for event CCABUSY
RW CCASTOPPED
Write '1' to disable interrupt for event CCASTOPPED
RW RATEBOOST
Write '1' to disable interrupt for event RATEBOOST
RW TXREADY
Write '1' to disable interrupt for event TXREADY
RW RXREADY
Write '1' to disable interrupt for event RXREADY
RW MHRMATCH
Write '1' to disable interrupt for event MHRMATCH
RW SYNC
Write '1' to disable interrupt for event SYNC
A possible preamble has been received in Ble_LR125Kbit,
Ble_LR500Kbit, or Ieee802154_250Kbit modes during an RX
transaction. False triggering of the event is possible.
4454_140 v1.1
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
224
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
a Z Y
Reset 0x00000000
ID
Access
Field
Z
RW PHYEND
a
V U T S R Q P O N M L K
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event PHYEND
RW CTEPRESENT
Write '1' to disable interrupt for event CTEPRESENT
6.14.15.41 CRCSTATUS
Address offset: 0x400
CRC status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
CRCSTATUS
CRC status of packet received
CRCError
0
Packet received with CRC error
CRCOk
1
Packet received with CRC ok
6.14.15.42 RXMATCH
Address offset: 0x408
Received address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
RXMATCH
Received address
Logical address of which previous packet was received
6.14.15.43 RXCRC
Address offset: 0x40C
CRC field of previously received packet
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
RXCRC
CRC field of previously received packet
CRC field of previously received packet
4454_140 v1.1
225
Peripherals
6.14.15.44 DAI
Address offset: 0x410
Device address match index
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
DAI
Device address match index
Index (n) of device address, see DAB[n] and DAP[n], that got
an address match
6.14.15.45 PDUSTAT
Address offset: 0x414
Payload status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B B A
Reset 0x00000000
ID
Access
Field
A
R
B
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
LessThan
0
Payload less than PCNF1.MAXLEN
GreaterThan
1
Payload greater than PCNF1.MAXLEN
LR125kbit
0
Frame is received at 125 kbps
LR500kbit
1
Frame is received at 500 kbps
PDUSTAT
Status on payload length vs. PCNF1.MAXLEN
CISTAT
Status on what rate packet is received with in Long Range
6.14.15.46 CTESTATUS
Address offset: 0x44C
CTEInfo parsed from received packet
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C C B A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
Value ID
Value
Description
A
R
CTETIME
CTETime parsed from packet
B
R
RFU
RFU parsed from packet
C
R
CTETYPE
CTEType parsed from packet
6.14.15.47 DFESTATUS
Address offset: 0x458
DFE status information
4454_140 v1.1
226
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B
Reset 0x00000000
ID
Access
Field
A
R
B
R
A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Idle
0
Switching state Idle
Offset
1
Switching state Offset
Guard
2
Switching state Guard
Ref
3
Switching state Ref
Switching
4
Switching state Switching
Ending
5
Switching state Ending
Idle
0
Sampling state Idle
Sampling
1
Sampling state Sampling
SWITCHINGSTATE
Internal state of switching state machine
SAMPLINGSTATE
Internal state of sampling state machine
6.14.15.48 PACKETPTR
Address offset: 0x504
Packet pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW PACKETPTR
Value ID
Value
Description
Packet pointer
Packet address to be used for the next transmission or
reception. When transmitting, the packet pointed to by
this address will be transmitted and when receiving, the
received packet will be written to this address. This address
is a byte aligned RAM address. See the memory chapter for
details about which memories are avilable for EasyDMA.
6.14.15.49 FREQUENCY
Address offset: 0x508
Frequency
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B
Reset 0x00000002
ID
Access
Field
A
RW FREQUENCY
B
RW MAP
Value ID
Value
Description
[0..100]
Radio channel frequency
Frequency = 2400 + FREQUENCY (MHz)
Channel map selection
Default
0
Low
1
Channel map between 2400 MHZ .. 2500 MHz
Frequency = 2400 + FREQUENCY (MHz)
Channel map between 2360 MHZ .. 2460 MHz
Frequency = 2360 + FREQUENCY (MHz)
6.14.15.50 TXPOWER
Address offset: 0x50C
4454_140 v1.1
A A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
227
Peripherals
Output power
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW TXPOWER
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
RADIO output power
Output power in number of dBm, i.e. if the value -20 is
specified the output power will be set to -20 dBm.
Pos4dBm
0x4
+4 dBm
Pos3dBm
0x3
+3 dBm
0dBm
0x0
0 dBm
Neg4dBm
0xFC
-4 dBm
Neg8dBm
0xF8
-8 dBm
Neg12dBm
0xF4
-12 dBm
Neg16dBm
0xF0
-16 dBm
Neg20dBm
0xEC
-20 dBm
Neg30dBm
0xE2
-40 dBm
Neg40dBm
0xD8
-40 dBm
Deprecated
6.14.15.51 MODE
Address offset: 0x510
Data rate and modulation
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A
Reset 0x00000000
ID
Access
Field
A
RW MODE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Radio data rate and modulation setting. The radio supports
frequency-shift keying (FSK) modulation.
Nrf_1Mbit
0
1 Mbps Nordic proprietary radio mode
Nrf_2Mbit
1
2 Mbps Nordic proprietary radio mode
Ble_1Mbit
3
1 Mbps BLE
Ble_2Mbit
4
2 Mbps BLE
Ble_LR125Kbit
5
Long range 125 kbps TX, 125 kbps and 500 kbps RX
Ble_LR500Kbit
6
Long range 500 kbps TX, 125 kbps and 500 kbps RX
Ieee802154_250Kbit
15
IEEE 802.15.4-2006 250 kbps
6.14.15.52 PCNF0
Address offset: 0x514
Packet configuration register 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
J J
Reset 0x00000000
I H H G G
F E E E E
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW LFLEN
Length on air of LENGTH field in number of bits
C
RW S0LEN
Length on air of S0 field in number of bytes
E
RW S1LEN
Length on air of S1 field in number of bits
F
RW S1INCL
Include or exclude S1 field in RAM
4454_140 v1.1
A A A A
Value ID
Value
Description
228
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
J J
Reset 0x00000000
ID
Access
Field
G
RW CILEN
H
RW PLEN
I
J
I H H G G
F E E E E
C
A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Automatic
0
Include S1 field in RAM only if S1LEN > 0
Include
1
Always include S1 field in RAM independent of S1LEN
Length of code indicator - long range
Length of preamble on air. Decision point: TASKS_START task
8bit
0
8-bit preamble
16bit
1
16-bit preamble
32bitZero
2
32-bit zero preamble - used for IEEE 802.15.4
LongRange
3
Preamble - used for BLE long range
Exclude
0
LENGTH does not contain CRC
Include
1
LENGTH includes CRC
RW CRCINC
Indicates if LENGTH field contains CRC or not
RW TERMLEN
Length of TERM field in Long Range operation
6.14.15.53 PCNF1
Address offset: 0x518
Packet configuration register 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
E D
Reset 0x00000000
ID
Access
Field
A
RW MAXLEN
C C C B B B B B B B B A A A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
[0..255]
Maximum length of packet payload. If the packet payload is
larger than MAXLEN, the radio will truncate the payload to
MAXLEN.
B
RW STATLEN
[0..255]
Static length in number of bytes
The static length parameter is added to the total length
of the payload when sending and receiving packets, e.g. if
the static length is set to N the radio will receive or send N
bytes more than what is defined in the LENGTH field of the
packet.
C
RW BALEN
[2..4]
Base address length in number of bytes
The address field is composed of the base address and the
one byte long address prefix, e.g. set BALEN=2 to get a total
address of 3 bytes.
D
RW ENDIAN
On-air endianness of packet, this applies to the S0, LENGTH,
S1, and the PAYLOAD fields.
E
Little
0
Least significant bit on air first
Big
1
Most significant bit on air first
Disabled
0
Disable
Enabled
1
Enable
RW WHITEEN
Enable or disable packet whitening
6.14.15.54 BASE0
Address offset: 0x51C
Base address 0
4454_140 v1.1
229
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW BASE0
Value ID
Value
Description
Base address 0
6.14.15.55 BASE1
Address offset: 0x520
Base address 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW BASE1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Base address 1
6.14.15.56 PREFIX0
Address offset: 0x524
Prefixes bytes for logical addresses 0-3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A-D
RW AP[i] (i=0..3)
Value ID
Value
Description
Address prefix i.
6.14.15.57 PREFIX1
Address offset: 0x528
Prefixes bytes for logical addresses 4-7
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00000000
ID
Access
Field
A-D
RW AP[i] (i=4..7)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Address prefix i.
6.14.15.58 TXADDRESS
Address offset: 0x52C
Transmit address select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A
Reset 0x00000000
ID
Access
Field
A
RW TXADDRESS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Transmit address select
Logical address to be used when transmitting a packet
4454_140 v1.1
230
Peripherals
6.14.15.59 RXADDRESSES
Address offset: 0x530
Receive address select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
H G F E D C B A
Reset 0x00000000
ID
Access
Field
A-H
RW ADDR[i] (i=0..7)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Enable or disable reception on logical address i.
6.14.15.60 CRCCNF
Address offset: 0x534
CRC configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B B
Reset 0x00000000
ID
Access
Field
A
RW LEN
Value ID
Value
Description
[1..3]
CRC length in number of bytes
For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set
to 3 is supported
B
Disabled
0
CRC length is zero and CRC calculation is disabled
One
1
CRC length is one byte and CRC calculation is enabled
Two
2
CRC length is two bytes and CRC calculation is enabled
Three
3
CRC length is three bytes and CRC calculation is enabled
RW SKIPADDR
Include or exclude packet address field out of CRC
calculation.
Include
0
CRC calculation includes address field
Skip
1
CRC calculation does not include address field. The CRC
Ieee802154
2
calculation will start at the first byte after the address.
CRC calculation as per 802.15.4 standard. Starting at first
byte after length field.
6.14.15.61 CRCPOLY
Address offset: 0x538
CRC polynomial
4454_140 v1.1
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
231
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW CRCPOLY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
CRC polynomial
Each term in the CRC polynomial is mapped to a bit in this
register which index corresponds to the term's exponent.
The least significant term/bit is hardwired internally to
1, and bit number 0 of the register content is ignored by
the hardware. The following example is for an 8 bit CRC
polynomial: x8 + x7 + x3 + x2 + 1 = 1 1000 1101 .
6.14.15.62 CRCINIT
Address offset: 0x53C
CRC initial value
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW CRCINIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
CRC initial value
Initial value for CRC calculation
6.14.15.63 TIFS
Address offset: 0x544
Interframe spacing in µs
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW TIFS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Interframe spacing in µs.
Interframe space is the time interval between two
consecutive packets. It is defined as the time, in
microseconds, from the end of the last bit of the previous
packet to the start of the first bit of the subsequent packet.
6.14.15.64 RSSISAMPLE
Address offset: 0x548
RSSI sample
4454_140 v1.1
232
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
RSSISAMPLE
Value
Description
[0..127]
RSSI sample.
RSSI sample result. The value of this register is read as a
positive value while the actual received signal strength is a
negative value. Actual received signal strength is therefore
as follows: received signal strength = -A dBm.
6.14.15.65 STATE
Address offset: 0x550
Current radio state
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
RADIO is in the Disabled state
RxRu
1
RADIO is in the RXRU state
RxIdle
2
RADIO is in the RXIDLE state
Rx
3
RADIO is in the RX state
RxDisable
4
RADIO is in the RXDISABLED state
TxRu
9
RADIO is in the TXRU state
TxIdle
10
RADIO is in the TXIDLE state
Tx
11
RADIO is in the TX state
TxDisable
12
RADIO is in the TXDISABLED state
STATE
Current radio state
6.14.15.66 DATAWHITEIV
Address offset: 0x554
Data whitening initial value
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A
Reset 0x00000040
ID
Access
Field
A
RW DATAWHITEIV
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Value ID
Value
Description
Data whitening initial value. Bit 6 is hardwired to '1', writing
'0' to it has no effect, and it will always be read back and
used by the device as '1'.
Bit 0 corresponds to Position 6 of the LSFR, Bit 1 to Position
5, etc.
6.14.15.67 BCC
Address offset: 0x560
Bit counter compare
4454_140 v1.1
233
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW BCC
Value ID
Value
Description
Bit counter compare
Bit counter compare register
6.14.15.68 DAB[n] (n=0..7)
Address offset: 0x600 + (n × 0x4)
Device address base segment n
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW DAB
Value ID
Value
Description
Device address base segment n
6.14.15.69 DAP[n] (n=0..7)
Address offset: 0x620 + (n × 0x4)
Device address prefix n
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW DAP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Device address prefix n
6.14.15.70 DACNF
Address offset: 0x640
Device address match configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
P O N M L K J I H G F E D C B A
Reset 0x00000000
ID
Access
Field
A-H
RW ENA[i] (i=0..7)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Enable or disable device address matching using device
address i
I-P
Disabled
0
Disabled
Enabled
1
Enabled
RW TXADD[i] (i=0..7)
TxAdd for device address i
6.14.15.71 MHRMATCHCONF
Address offset: 0x644
Search pattern configuration
4454_140 v1.1
234
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW MHRMATCHCONF
Value ID
Value
Description
Search pattern configuration
6.14.15.72 MHRMATCHMAS
Address offset: 0x648
Pattern mask
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW MHRMATCHMAS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Pattern mask
6.14.15.73 MODECNF0
Address offset: 0x650
Radio mode configuration register 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C C
Reset 0x00000200
ID
Access
Field
A
RW RU
Value ID
Value
Default
0
Fast
1
Description
Radio ramp-up time
Default ramp-up time (tRXEN and tTXEN), compatible with
firmware written for nRF51
Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical
specifications for more information
When enabled, TIFS is not enforced by hardware and
software needs to control when to turn on the Radio
C
RW DTX
Default TX value
Specifies what the RADIO will transmit when it is not
started, i.e. between:
RADIO.EVENTS_READY and RADIO.TASKS_START
RADIO.EVENTS_END and RADIO.TASKS_START
RADIO.EVENTS_END and RADIO.EVENTS_DISABLED
For IEEE 802.15.4 250 kbps mode only Center is a valid
setting
For Bluetooth Low Energy Long Range mode only Center is
a valid setting
B1
0
Transmit '1'
B0
1
Transmit '0'
Center
2
Transmit center frequency
When tuning the crystal for center frequency, the RADIO
must be set in DTX = Center mode to be able to achieve the
expected accuracy
4454_140 v1.1
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
235
Peripherals
6.14.15.74 SFD
Address offset: 0x660
IEEE 802.15.4 start of frame delimiter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x000000A7
ID
Access
Field
A
RW SFD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1
Value ID
Value
Description
IEEE 802.15.4 start of frame delimiter
6.14.15.75 EDCNT
Address offset: 0x664
IEEE 802.15.4 energy detect loop count
Number of iterations to perform an ED scan. If set to 0 one scan is performed, otherwise the specified
number + 1 of ED scans will be performed and the max ED value tracked in EDSAMPLE.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW EDCNT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
IEEE 802.15.4 energy detect loop count
6.14.15.76 EDSAMPLE
Address offset: 0x668
IEEE 802.15.4 energy detect level
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
EDLVL
Value
Description
[0..127]
IEEE 802.15.4 energy detect level
Register value must be converted to IEEE 802.15.4 range by
an 8-bit saturating multiplication by factor ED_RSSISCALE, as
shown in the code example for ED sampling
6.14.15.77 CCACTRL
Address offset: 0x66C
IEEE 802.15.4 clear channel assessment control
4454_140 v1.1
236
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D D D D D D D D C C C C C C C C B B B B B B B B
Reset 0x052D0000
0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW CCAMODE
Value ID
Value
EdMode
0
A A A
Description
CCA mode of operation
Energy above threshold
Will report busy whenever energy is detected above
CCAEDTHRES
CarrierMode
1
Carrier seen
Will report busy whenever compliant IEEE 802.15.4 signal is
seen
CarrierAndEdMode
2
Energy above threshold AND carrier seen
CarrierOrEdMode
3
Energy above threshold OR carrier seen
EdModeTest1
4
Energy above threshold test mode that will abort when first
ED measurement over threshold is seen. No averaging.
B
RW CCAEDTHRES
CCA energy busy threshold. Used in all the CCA modes
except CarrierMode.
Must be converted from IEEE 802.15.4 range by dividing by
factor ED_RSSISCALE - similar to EDSAMPLE register
C
RW CCACORRTHRES
CCA correlator busy threshold. Only relevant to
CarrierMode, CarrierAndEdMode, and CarrierOrEdMode.
D
RW CCACORRCNT
Limit for occurances above CCACORRTHRES. When not
equal to zero the corrolator based signal detect is enabled.
6.14.15.78 DFEMODE
Address offset: 0x900
Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A
Reset 0x00000000
ID
Access
Field
A
RW DFEOPMODE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Direction finding operation mode
Disabled
0
Direction finding mode disabled
AoD
2
Direction finding mode set to AoD
AoA
3
Direction finding mode set to AoA
6.14.15.79 CTEINLINECONF
Address offset: 0x904
Configuration for CTE inline mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
I
Reset 0x00002800
ID
Access
Field
A
RW CTEINLINECTRLEN
I I I I I I I H H H H H H H H G G G F F F
Value
Description
Enable parsing of CTEInfo from received packet in BLE
Enabled
1
Parsing of CTEInfo is enabled
Disabled
0
Parsing of CTEInfo is disabled
RW CTEINFOINS1
4454_140 v1.1
C B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
Value ID
modes
B
E E
CTEInfo is S1 byte or not
237
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
I
Reset 0x00002800
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
ID
C
E
Access
Field
I I I I I I I H H H H H H H H G G G F F F
E E
Value ID
Value
Description
InS1
1
CTEInfo is in S1 byte (data PDU)
NotInS1
0
CTEInfo is NOT in S1 byte (advertising PDU)
Yes
1
Sampling and antenna switching also when CRC is not OK
No
0
No sampling and antenna switching when CRC is not OK
RW CTEERRORHANDLING
C B
Sampling/switching if CRC is not OK
RW CTETIMEVALIDRANGE
Max range of CTETime
Valid range is 2-20 in BLE core spec. If larger than 20, it can
be an indication of an error in the received packet.
20
0
20 in 8 µs unit (default)
Set to 20 if parsed CTETime is larger than 20
F
31
1
31 in 8 µs unit
63
2
63 in 8 µs unit
RW CTEINLINERXMODE1US
Spacing between samples for the samples in the
SWITCHING period when CTEINLINEMODE is set.
When the device is in AoD mode, this is used when the
received CTEType is "AoD 1 µs". When in AoA mode, this is
used when TSWITCHSPACING is 2 µs.
G
4us
1
4 µs
2us
2
2 µs
1us
3
1 µs
500ns
4
0.5 µs
250ns
5
0.25 µs
125ns
6
0.125 µs
RW CTEINLINERXMODE2US
Spacing between samples for the samples in the
SWITCHING period when CTEINLINEMODE is set.
When the device is in AoD mode, this is used when the
received CTEType is "AoD 2 µs". When in AoA mode, this is
used when TSWITCHSPACING is 4 µs.
H
4us
1
4 µs
2us
2
2 µs
1us
3
1 µs
500ns
4
0.5 µs
250ns
5
0.25 µs
125ns
6
0.125 µs
RW S0CONF
S0 bit pattern to match
The least significant bit always corresponds to the first bit of
S0 received.
I
RW S0MASK
S0 bit mask to set which bit to match
The least significant bit always corresponds to the first bit of
S0 received.
6.14.15.80 DFECTRL1
Address offset: 0x910
Various configuration for Direction finding
4454_140 v1.1
238
A
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
I I I I
Reset 0x00023282
ID
Access
Field
A
RW NUMBEROF8US
G G G F E E E
C C C B
A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 0
Value ID
Value
Description
Length of the AoA/AoD procedure in number of 8 µs units
Always used in TX mode, but in RX mode only when
CTEINLINECTRLEN is 0
B
RW DFEINEXTENSION
Add CTE extension and do antenna switching/sampling in
this extension
C
CRC
1
AoA/AoD procedure triggered at end of CRC
Payload
0
Antenna switching/sampling is done in the packet payload
RW TSWITCHSPACING
Interval between every time the antenna is changed in the
SWITCHING state
E
F
G
4us
1
4 µs
2us
2
2 µs
1us
3
1 µs
4us
1
4 µs
2us
2
2 µs
1us
3
1 µs
500ns
4
0.5 µs
250ns
5
0.25 µs
125ns
6
0.125 µs
IQ
0
Complex samples in I and Q
MagPhase
1
Complex samples as magnitude and phase
RW TSAMPLESPACINGREF
Interval between samples in the REFERENCE period
RW SAMPLETYPE
Whether to sample I/Q or magnitude/phase
RW TSAMPLESPACING
Interval between samples in the SWITCHING period when
CTEINLINECTRLEN is 0
Not used when CTEINLINECTRLEN is set. Then either
CTEINLINERXMODE1US or CTEINLINERXMODE2US are used.
I
4us
1
4 µs
2us
2
2 µs
1us
3
1 µs
500ns
4
0.5 µs
250ns
5
0.25 µs
125ns
6
0.125 µs
RW AGCBACKOFFGAIN
Gain will be lowered by the specified number of gain steps
at the start of CTE
First LNAGAIN gain drops, then MIXGAIN, then AAFGAIN
6.14.15.81 DFECTRL2
Address offset: 0x914
Start offset for Direction finding
4454_140 v1.1
239
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B B B B B B B B B B B B
Reset 0x00000000
ID
Access
Field
A
RW TSWITCHOFFSET
A A A A A A A A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Signed value offset after the end of the CRC before starting
switching in number of 16M cycles
Decreasing TSWITCHOFFSET beyond the trigger of the AoA/
AoD procedure will have no effect
B
RW TSAMPLEOFFSET
Signed value offset before starting sampling in number of
16M cycles relative to the beginning of the REFERENCE state
- 12 µs after switching start
Decreasing TSAMPLEOFFSET beyond the trigger of the AoA/
AoD procedure will have no effect
6.14.15.82 SWITCHPATTERN
Address offset: 0x928
GPIO patterns to be used for each antenna
Maximum 8 GPIOs can be controlled. To secure correct signal levels on the pins, the pins must be
configured in the GPIO peripheral as described in Pin configuration.
If, during switching, the total number of antenna slots is bigger than the number of written patterns, the
RADIO loops back to the pattern used after the reference pattern.
A minimum number of three patterns must be written.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW SWITCHPATTERN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Fill array of GPIO patterns for antenna control.
The GPIO pattern array size is 40 entries.
When written, bit n corresponds to the GPIO configured in
PSEL.DFEGPIO[n].
When read, returns the number of GPIO patterns
written since the last time the array was cleared. Use
CLEARPATTERN to clear the array.
6.14.15.83 CLEARPATTERN
Address offset: 0x92C
Clear the GPIO pattern array for antenna control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW CLEARPATTERN
4454_140 v1.1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Clear
1
Description
Clears GPIO pattern array for antenna control
Clear the GPIO pattern
240
Peripherals
6.14.15.84 PSEL.DFEGPIO[n] (n=0..7)
Address offset: 0x930 + (n × 0x4)
Pin select for DFE pin n
Must be set before enabling the radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
RW PIN
C
RW CONNECT
Value ID
A A A A A
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
6.14.15.85 DFEPACKET.PTR
Address offset: 0x950
Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW PTR
Value ID
Value
Description
Data pointer
See the memory chapter for details about which memories
are available for EasyDMA.
6.14.15.86 DFEPACKET.MAXCNT
Address offset: 0x954
Maximum number of buffer words to transfer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A
Reset 0x00001000
ID
Access
Field
A
RW MAXCNT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Maximum number of buffer words to transfer
6.14.15.87 DFEPACKET.AMOUNT
Address offset: 0x958
Number of samples transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
AMOUNT
4454_140 v1.1
Number of samples transferred in the last transaction
241
Peripherals
6.14.15.88 POWER
Address offset: 0xFFC
Peripheral power control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000001
ID
Access
Field
A
RW POWER
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value ID
Value
Description
Peripheral power control. The peripheral and its registers
will be reset to its initial state by switching the peripheral
off and then back on again.
Disabled
0
Peripheral is powered off
Enabled
1
Peripheral is powered on
6.14.16 Electrical specification
6.14.16.1 General radio characteristics
Symbol
Description
Min.
fOP
Operating frequencies
2360
Typ.
Max.
Units
2500
MHz
fPLL,CH,SP
PLL channel spacing
1
MHz
fDELTA,1M
Frequency deviation @ 1 Mbps
±170
kHz
fDELTA,BLE,1M
Frequency deviation @ BLE 1 Mbps
±250
kHz
fDELTA,2M
Frequency deviation @ 2 Mbps
±320
kHz
fDELTA,BLE,2M
Frequency deviation @ BLE 2 Mbps
fskBPS
On-the-air data rate
fchip, IEEE 802.15.4
Chip rate in IEEE 802.15.4 mode
±500
125
kHz
2000
2000
kbps
kchip/
s
6.14.16.2 Radio current consumption (transmitter)
Symbol
Description
ITX,PLUS4dBM,DCDC
TX only run current (DC/DC, 3 V) PRF = +4 dBm
7.0
mA
ITX,PLUS4dBM
TX only run current PRF = +4 dBm
15.4
mA
ITX,0dBM,DCDC
TX only run current (DC/DC, 3 V)PRF = 0 dBm
4.6
mA
ITX,0dBM
TX only run current PRF = 0 dBm
10.1
mA
ITX,MINUS4dBM,DCDC
TX only run current DC/DC, 3 V PRF = -4 dBm
3.6
mA
ITX,MINUS4dBM
TX only run current PRF = -4 dBm
7.8
mA
ITX,MINUS8dBM,DCDC
TX only run current DC/DC, 3 V PRF = -8 dBm
3.2
mA
ITX,MINUS8dBM
TX only run current PRF = -8 dBm
6.8
mA
ITX,MINUS12dBM,DCDC TX only run current DC/DC, 3 V PRF = -12 dBm
2.9
mA
ITX,MINUS12dBM
6.2
mA
ITX,MINUS16dBM,DCDC TX only run current DC/DC, 3 V PRF = -16 dBm
2.7
mA
ITX,MINUS16dBM
5.7
mA
ITX,MINUS20dBM,DCDC TX only run current DC/DC, 3 V PRF = -20 dBm
2.5
mA
ITX,MINUS20dBM
5.4
mA
ITX,MINUS40dBM,DCDC TX only run current DC/DC, 3 V PRF = -40 dBm
2.1
mA
ITX,MINUS40dBM
TX only run current PRF = -40 dBm
4.3
mA
ISTART,TX,DCDC
TX start-up current DC/DC, 3 V, PRF = 4 dBm
..
..
..
mA
ISTART,TX
TX start-up current, PRF = 4 dBm
..
..
..
mA
4454_140 v1.1
Min.
TX only run current PRF = -12 dBm
TX only run current PRF = -16 dBm
TX only run current PRF = -20 dBm
242
Typ.
Max.
Units
Peripherals
6.14.16.3 Radio current consumption (Receiver)
Symbol
Description
IRX,1M,DCDC
RX only run current (DC/DC, 3 V) 1 Mbps/1 Mbps BLE
Min.
Typ.
4.6
Max.
Units
mA
IRX,1M
RX only run current (LDO, 3 V) 1 Mbps/1 Mbps BLE
10.0
mA
IRX,2M,DCDC
RX only run current (DC/DC, 3 V) 2 Mbps/2 Mbps BLE
5.2
mA
IRX,2M
RX only run current (LDO, 3 V) 2 Mbps/2 Mbps BLE
11.2
mA
ISTART,RX,1M,DCDC
RX start-up current (DC/DC, 3 V) 1 Mbps/1 Mbps BLE
3.5
mA
ISTART,RX,1M
RX start-up current 1 Mbps/1 Mbps BLE
6.7
mA
6.14.16.4 Transmitter specification
Symbol
Description
Min.
Typ.
Max.
PRF
Maximum output power
4.0
PRFC
RF power control range
24
PRFCR
RF power accuracy
PRF1,1
1st Adjacent Channel Transmit Power 1 MHz (1 Mbps)
-25
dBc
PRF2,1
2nd Adjacent Channel Transmit Power 2 MHz (1 Mbps)
-50
dBc
PRF1,2
1st Adjacent Channel Transmit Power 2 MHz (2 Mbps)
-25
dBc
PRF2,2
2nd Adjacent Channel Transmit Power 4 MHz (2 Mbps)
-50
dBc
Evm
Error vector magnitude in IEEE 802.15.4 mode
12
%rms
-45
dBm
dBm
dB
±4
Pharm2nd, IEEE 802.15.4 2nd harmonics in IEEE 802.15.4 mode
Pharm3rd, IEEE 802.15.4 3rd harmonics in IEEE 802.15.4 mode
Output power [dBm]
5
4.5
4
3.5
-20
0
20
40
60
Temperature Range [°C]
1.7 V
3V
3.6 V
Figure 89: Output power, 1 Mbps Bluetooth low energy
mode, at maximum TXPOWER setting (typical values)
4454_140 v1.1
dB
dBm
5.5
3
-40
Units
243
80
100
Peripherals
2.5
2
Output power [dBm]
1.5
1
0.5
0
-0.5
-1
-40
-20
0
20
40
60
80
100
Temperature Range [°C]
1.7 V
3V
3.6 V
Figure 90: Output power, 1 Mbps Bluetooth low energy mode, at 0 dBm TXPOWER setting (typical values)
6.14.16.5 Receiver operation
Symbol
Description
PRX,MAX
Maximum received signal strength at < 0.1% PER
Min.
Typ.
Max.
Units
0
dBm
PSENS,IT,1M
Sensitivity, 1 Mbps nRF mode ideal transmitter
13
-94
dBm
PSENS,IT,2M
Sensitivity, 2 Mbps nRF mode ideal transmitter 13
-91
dBm
PSENS,IT,SP,1M,BLE
Sensitivity, 1 Mbps BLE ideal transmitter, packet length ≤ 37
-97
dBm
-96
dBm
-94
dBm
14
bytes BER=1E-3
PSENS,IT,LP,1M,BLE
Sensitivity, 1 Mbps BLE ideal transmitter, packet length ≥ 128
bytes BER=1E-4
PSENS,IT,SP,2M,BLE
15
Sensitivity, 2 Mbps BLE ideal transmitter, packet length ≤ 37
bytes
PSENS,IT,BLE LE125k
Sensitivity, 125 kbps BLE mode
-104
dBm
PSENS,IT,BLE LE500k
Sensitivity, 500 kbps BLE mode
-100
dBm
PSENS,IEEE 802.15.4
Sensitivity in IEEE 802.15.4 mode
-101
dBm
13
14
15
Typical sensitivity applies when ADDR0 is used for receiver address correlation. When ADDR[1...7]
are used for receiver address correlation, the typical sensitivity for this mode is degraded by 3 dB.
As defined in the Bluetooth Core Specification v4.0 Volume 6: Core System Package (Low Energy
Controller Volume).
Equivalent BER limit < 10E-04.
4454_140 v1.1
244
Peripherals
-95.5
-96
Sensitivity [dBm]
-96.5
-97
-97.5
-98
-98.5
-99
-40
-20
0
20
40
60
80
100
Temperature Range [°C]
1.7 V
3V
3.6 V
Figure 91: Sensitivity, 1 Mbps Bluetooth low energy mode, Regulator = LDO (typical values)
6.14.16.6 RX selectivity
RX selectivity with equal modulation on interfering signal16
Symbol
Description
C/I1M,co-channel
1Mbps mode, co-channel interference
9
dB
C/I1M,-1MHz
1 Mbps mode, Adjacent (-1 MHz) interference
-2
dB
C/I1M,+1MHz
1 Mbps mode, Adjacent (+1 MHz) interference
-10
dB
C/I1M,-2MHz
1 Mbps mode, Adjacent (-2 MHz) interference
-19
dB
C/I1M,+2MHz
1 Mbps mode, Adjacent (+2 MHz) interference
-42
dB
C/I1M,-3MHz
1 Mbps mode, Adjacent (-3 MHz) interference
-38
dB
C/I1M,+3MHz
1 Mbps mode, Adjacent (+3 MHz) interference
-48
dB
C/I1M,±6MHz
1 Mbps mode, Adjacent (≥6 MHz) interference
-50
dB
C/I1MBLE,co-channel
1 Mbps BLE mode, co-channel interference
6
dB
C/I1MBLE,-1MHz
1 Mbps BLE mode, Adjacent (-1 MHz) interference
-2
dB
C/I1MBLE,+1MHz
1 Mbps BLE mode, Adjacent (+1 MHz) interference
-9
dB
C/I1MBLE,-2MHz
1 Mbps BLE mode, Adjacent (-2 MHz) interference
-22
dB
C/I1MBLE,+2MHz
1 Mbps BLE mode, Adjacent (+2 MHz) interference
-46
dB
C/I1MBLE,>3MHz
1 Mbps BLE mode, Adjacent (≥3 MHz) interference
-50
dB
C/I1MBLE,image
Image frequency interference
-22
dB
C/I1MBLE,image,1MHz
Adjacent (1 MHz) interference to in-band image frequency
-35
dB
C/I2M,co-channel
2 Mbps mode, co-channel interference
10
dB
C/I2M,-2MHz
2 Mbps mode, Adjacent (-2 MHz) interference
6
dB
C/I2M,+2MHz
2 Mbps mode, Adjacent (+2 MHz) interference
-14
dB
C/I2M,-4MHz
2 Mbps mode, Adjacent (-4 MHz) interference
-20
dB
C/I2M,+4MHz
2 Mbps mode, Adjacent (+4 MHz) interference
-44
dB
16
Min.
Typ.
Max.
Units
Desired signal level at PIN = -67 dBm. One interferer is used, having equal modulation as the desired
signal. The input power of the interferer where the sensitivity equals BER = 0.1% is presented.
4454_140 v1.1
245
Peripherals
Symbol
Description
Min.
Typ.
Max.
Units
C/I2M,-6MHz
2 Mbps mode, Adjacent (-6 MHz) interference
-42
dB
C/I2M,+6MHz
2 Mbps mode, Adjacent (+6 MHz) interference
-47
dB
C/I2M,≥12MHz
2 Mbps mode, Adjacent (≥12 MHz) interference
-52
dB
C/I2MBLE,co-channel
2 Mbps BLE mode, co-channel interference
6
dB
C/I2MBLE,-2MHz
2 Mbps BLE mode, Adjacent (-2 MHz) interference
-2
dB
C/I2MBLE,+2MHz
2 Mbps BLE mode, Adjacent (+2 MHz) interference
-13
dB
C/I2MBLE,-4MHz
2 Mbps BLE mode, Adjacent (-4 MHz) interference
-28
dB
C/I2MBLE,+4MHz
2 Mbps BLE mode, Adjacent (+4 MHz) interference
-48
dB
C/I2MBLE,≥6MHz
2 Mbps BLE mode, Adjacent (≥6 MHz) interference
-50
dB
C/I2MBLE,image
Image frequency interference
-28
dB
C/I2MBLE,image, 2MHz Adjacent (2 MHz) interference to in-band image frequency
-44
dB
C/I125k BLE LR,co-
125 kbps BLE LR mode, co-channel interference
4
dB
C/I125k BLE LR,-1MHz
125 kbps BLE LR mode, Adjacent (-1 MHz) interference
-9
dB
C/I125k BLE LR,+1MHz
125 kbps BLE LR mode, Adjacent (+1 MHz) interference
-16
dB
C/I125k BLE LR,-2MHz
125 kbps BLE LR mode, Adjacent (-2 MHz) interference
-30
dB
C/I125k BLE LR,+2MHz
125 kbps BLE LR mode, Adjacent (+2 MHz) interference
-50
dB
C/I125k BLE LR,>3MHz
125 kbps BLE LR mode, Adjacent (≥3 MHz) interference
-55
dB
C/I125k BLE LR,image
Image frequency interference
-30
dB
C/IIEEE 802.15.4,-5MHz IEEE 802.15.4 mode, Adjacent (-5 MHz) rejection
-33
dB
C/IIEEE 802.15.4,+5MHz IEEE 802.15.4 mode, Adjacent (+5 MHz) rejection
-38
dB
C/IIEEE 802.15.4,±10MHz IEEE 802.15.4 mode, Alternate (±10 MHz) rejection
-48
dB
channel
6.14.16.7 RX intermodulation
RX intermodulation. Desired signal level at PIN = -64 dBm. Two interferers with equal input power are
used. The interferer closest in frequency is not modulated, the other interferer is modulated equal with
the desired signal. The input power of the interferers where the sensitivity equals BER = 0.1% is presented.
Symbol
Description
Min.
PIMD,5TH,1M
IMD performance, 1 Mbps, 5th offset channel, packet length
Typ.
Max.
Units
-33
dBm
-30
dBm
-33
dBm
-31
dBm
≤ 37 bytes
PIMD,5TH,1M,BLE
IMD performance, BLE 1 Mbps, 5th offset channel, packet
length ≤ 37 bytes
PIMD,5TH,2M
IMD performance, 2 Mbps, 5th offset channel, packet length
≤ 37 bytes
PIMD,5TH,2M,BLE
IMD performance, BLE 2 Mbps, 5th offset channel, packet
length ≤ 37 bytes
6.14.16.8 Radio timing
Symbol
Description
Min.
Max.
Units
tTXEN,BLE,1M
Time between TXEN task and READY event after channel
140
Typ.
140
µs
40
40
µs
6
6
µs
140
140
µs
40
40
µs
FREQUENCY configured (1 Mbps BLE and 150 µs TIFS)
tTXEN,FAST,BLE,1M
Time between TXEN task and READY event after channel
FREQUENCY configured (1 Mbps BLE with fast ramp-up and
150 µs TIFS)
tTXDIS,BLE,1M
When in TX, delay between DISABLE task and DISABLED
event for MODE = Nrf_1Mbit and MODE = Ble_1Mbit
tRXEN,BLE,1M
Time between the RXEN task and READY event after channel
FREQUENCY configured (1 Mbps BLE)
tRXEN,FAST,BLE,1M
Time between the RXEN task and READY event after channel
FREQUENCY configured (1 Mbps BLE with fast ramp-up)
4454_140 v1.1
246
Peripherals
Symbol
Description
Min.
tRXDIS,BLE,1M
When in RX, delay between DISABLE task and DISABLED
Typ.
Max.
Units
0
0
µs
4
4
µs
0
0
µs
130
130
µs
40
40
µs
21
21
µs
130
130
µs
40
40
µs
0.5
0.5
µs
event for MODE = Nrf_1Mbit and MODE = Ble_1Mbit
tTXDIS,BLE,2M
When in TX, delay between DISABLE task and DISABLED
event for MODE = Nrf_2Mbit and MODE = Ble_2Mbit
tRXDIS,BLE,2M
When in RX, delay between DISABLE task and DISABLED
event for MODE = Nrf_2Mbit and MODE = Ble_2Mbit
tTXEN,IEEE 802.15.4
Time between TXEN task and READY event after channel
FREQUENCY configured (IEEE 802.15.4 mode)
tTXEN,FAST,IEEE 802.15.4 Time between TXEN task and READY event after channel
FREQUENCY configured (IEEE 802.15.4 mode with fast rampup)
tTXDIS,IEEE 802.15.4
When in TX, delay between DISABLE task and DISABLED
event (IEEE 802.15.4 mode)
tRXEN,IEEE 802.15.4
Time between the RXEN task and READY event after channel
FREQUENCY configured (IEEE 802.15.4 mode)
tRXEN,FAST,IEEE 802.15.4 Time between the RXEN task and READY event after channel
FREQUENCY configured (IEEE 802.15.4 mode with fast rampup)
tRXDIS,IEEE 802.15.4
When in RX, delay between DISABLE task and DISABLED
event (IEEE 802.15.4 mode)
tRX-to-TX turnaround
Maximum TX-to-RX or RX-to-TX turnaround time in IEEE
40
µs
802.15.4 mode
6.14.16.9 Received signal strength indicator (RSSI) specifications
Symbol
Description
RSSIACC
RSSI accuracy
RSSIRESOLUTION
RSSIPERIOD
RSSISETTLE
Min.
Typ.
Max.
Units
±2
dB
RSSI resolution
1
dB
RSSI sampling time from RSSI_START task
0.25
µs
RSSI settling time after signal level change
15
µs
17
6.14.16.10 Jitter
Symbol
Description
tDISABLEDJITTER
Jitter on DISABLED event relative to END event when
Min.
Typ.
Max.
Units
0.25
µs
0.25
µs
shortcut between END and DISABLE is enabled
tREADYJITTER
Jitter on READY event relative to TXEN and RXEN task
6.14.16.11 IEEE 802.15.4 mode energy detection constants
Symbol
Description
Min.
Typ.
Max.
ED_RSSISCALE
Scaling value when converting between hardware-reported
4
4
4
-92
-92
-92
value and dBm
ED_RSSIOFFS
Offset value when converting between hardware-reported
value and dBm
17
Valid range -90 to -30 dBm
4454_140 v1.1
247
Units
Peripherals
6.15 RNG — Random number generator
The Random number generator (RNG) generates true non-deterministic random numbers based on
internal thermal noise that are suitable for cryptographic purposes. The RNG does not require a seed
value.
START
Random number
generator
STOP
VALRDY
VALUE
Figure 92: Random number generator
The RNG is started by triggering the START task and stopped by triggering the STOP task. When started,
new random numbers are generated continuously and written to the VALUE register when ready. A
VALRDY event is generated for every new random number that is written to the VALUE register. This means
that after a VALRDY event is generated the CPU has the time until the next VALRDY event to read out the
random number from the VALUE register before it is overwritten by a new random number.
6.15.1 Bias correction
A bias correction algorithm is employed on the internal bit stream to remove any bias toward '1' or '0'. The
bits are then queued into an eight-bit register for parallel readout from the VALUE register.
It is possible to enable bias correction in the CONFIG register. This will result in slower value generation,
but will ensure a statistically uniform distribution of the random values.
6.15.2 Speed
The time needed to generate one random byte of data is unpredictable, and may vary from one byte to
the next. This is especially true when bias correction is enabled.
6.15.3 Registers
Base address
Peripheral
Instance
Description
Configuration
0x4000D000
RNG
RNG
Random number generator
Table 73: Instances
Register
Offset
Description
TASKS_START
0x000
Task starting the random number generator
TASKS_STOP
0x004
Task stopping the random number generator
EVENTS_VALRDY
0x100
Event being generated for every new random number written to the VALUE register
SHORTS
0x200
Shortcuts between local events and tasks
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
CONFIG
0x504
Configuration register
VALUE
0x508
Output random number
Table 74: Register overview
6.15.3.1 TASKS_START
Address offset: 0x000
4454_140 v1.1
248
Peripherals
Task starting the random number generator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_START
Task starting the random number generator
Trigger
1
Trigger task
6.15.3.2 TASKS_STOP
Address offset: 0x004
Task stopping the random number generator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_STOP
Task stopping the random number generator
Trigger task
6.15.3.3 EVENTS_VALRDY
Address offset: 0x100
Event being generated for every new random number written to the VALUE register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_VALRDY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Event being generated for every new random number
written to the VALUE register
NotGenerated
0
Event not generated
Generated
1
Event generated
6.15.3.4 SHORTS
Address offset: 0x200
Shortcuts between local events and tasks
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW VALRDY_STOP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Shortcut between event VALRDY and task STOP
6.15.3.5 INTENSET
Address offset: 0x304
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Peripherals
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW VALRDY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Write '1' to enable interrupt for event VALRDY
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
6.15.3.6 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW VALRDY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event VALRDY
6.15.3.7 CONFIG
Address offset: 0x504
Configuration register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW DERCEN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disabled
Enabled
1
Enabled
Bias correction
6.15.3.8 VALUE
Address offset: 0x508
Output random number
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
R
VALUE
4454_140 v1.1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
[0..255]
Generated random number
250
Peripherals
6.15.4 Electrical specification
6.15.4.1 RNG Electrical Specification
Symbol
Description
tRNG,START
Time from setting the START task to generation begins.
Min.
Typ.
Max.
Units
128
µs
30
µs
120
µs
This is a one-time delay on START signal and does not apply
between samples.
tRNG,RAW
Run time per byte without bias correction. Uniform
distribution of 0 and 1 is not guaranteed.
tRNG,BC
Run time per byte with bias correction. Uniform distribution
of 0 and 1 is guaranteed. Time to generate a byte cannot be
guaranteed.
6.16 RTC — Real-time counter
The Real-time counter (RTC) module provides a generic, low power timer on the low-frequency clock
source (LFCLK).
32.768 kHz
START
STOP
CLEAR
TRIGOVRFLW
task
PRESCALER
event
TICK
event
OVRFLW
event
COMPARE[0..N]
COUNTER
task
RTC
task
task
CC[0:3]
Figure 93: RTC block schematic
The RTC module features a 24-bit COUNTER, a 12-bit (1/X) prescaler, capture/compare registers, and a tick
event generator for low power, tickless RTOS implementation.
6.16.1 Clock source
The RTC will run off the LFCLK.
The COUNTER resolution will therefore be 30.517 μs. Depending on the source, the RTC is able to run
while the HFCLK is OFF and PCLK16M is not available.
The software has to explicitely start LFCLK before using the RTC.
See CLOCK — Clock control on page 64 for more information about clock sources.
6.16.2 Resolution versus overflow and the PRESCALER
4454_140 v1.1
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Peripherals
Counter increment frequency:
fRTC [kHz] = 32.768 / (PRESCALER + 1 )
The PRESCALER register is read/write when the RTC is stopped. The PRESCALER register is read-only once
the RTC is STARTed. Writing to the PRESCALER register when the RTC is started has no effect.
The PRESCALER is restarted on START, CLEAR and TRIGOVRFLW, that is, the prescaler value is latched to an
internal register () on these tasks.
Examples:
1. Desired COUNTER frequency 100 Hz (10 ms counter period)
PRESCALER = round(32.768 kHz / 100 Hz) - 1 = 327
fRTC = 99.9 Hz
10009.576 μs counter period
2. Desired COUNTER frequency 8 Hz (125 ms counter period)
PRESCALER = round(32.768 kHz / 8 Hz) – 1 = 4095
fRTC = 8 Hz
125 ms counter period
Prescaler
Counter resolution
Overflow
0
30.517 μs
512 seconds
28-1
7812.5 μs
131072 seconds
212-1
125 ms
582.542 hours
Table 75: RTC resolution versus overflow
6.16.3 COUNTER register
The COUNTER increments on LFCLK when the internal PRESCALER register () is 0x00.
is reloaded from the PRESCALER register. If enabled, the TICK event occurs on each increment
of the COUNTER. The TICK event is disabled by default.
SysClk
LFClk
TICK
PRESC
COUNTER
0x000
0x000
0x000
0x000
0x000
0x000000
0x000001
0x000002
0x000003
Figure 94: Timing diagram - COUNTER_PRESCALER_0
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Peripherals
SysClk
LFClk
TICK
PRESC
0x001
0x000
COUNTER
0x001
0x000000
0x000
0x001
0x000001
Figure 95: Timing diagram - COUNTER_PRESCALER_1
6.16.4 Overflow features
The TRIGOVRFLW task sets the COUNTER value to 0xFFFFF0 to allow SW test of the overflow condition.
OVRFLW occurs when COUNTER overflows from 0xFFFFFF to 0.
Important: The OVRFLW event is disabled by default.
6.16.5 TICK event
The TICK event enables low power "tick-less" RTOS implementation as it optionally provides a regular
interrupt source for a RTOS without the need to use the ARM® SysTick feature.
Using the RTC TICK event rather than the SysTick allows the CPU to be powered down while still keeping
RTOS scheduling active.
Important: The TICK event is disabled by default.
6.16.6 Event control feature
To optimize RTC power consumption, events in the RTC can be individually disabled to prevent PCLK16M
and HFCLK being requested when those events are triggered. This is managed using the EVTEN register.
For example, if the TICK event is not required for an application, this event should be disabled as it is
frequently occurring and may increase power consumption if HFCLK otherwise could be powered down for
long durations.
This means that the RTC implements a slightly different task and event system compared to the standard
system described in Peripheral interface on page 77. The RTC task and event system is illustrated in
Tasks, events and interrupts in the RTC on page 254.
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Peripherals
Task signal from PPI
RTC
write
TASK
OR
task
RTC
core
event
EVTEN
m
INTEN
m
EVENT m
IRQ signal to NVIC
Event signal to PPI
Figure 96: Tasks, events and interrupts in the RTC
6.16.7 Compare feature
There are a number of Compare registers.
For more information, see Registers on page 259.
When setting a compare register, the following behavior of the RTC compare event should be noted:
• If a CC register value is 0 when a CLEAR task is set, this will not trigger a COMPARE event.
SysClk
LFClk
PRESC
COUNTER
0x000
X
0x000000
CLEAR
CC[0]
0x000000
COMPARE[0]
0
Figure 97: Timing diagram - COMPARE_CLEAR
• If a CC register is N and the COUNTER value is N when the START task is set, this will not trigger a
COMPARE event.
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Peripherals
SysClk
LFClk
PRESC
0x000
COUNTER
N-1
N
N+1
START
CC[0]
N
COMPARE[0]
0
Figure 98: Timing diagram - COMPARE_START
• COMPARE occurs when a CC register is N and the COUNTER value transitions from N-1 to N.
SysClk
LFClk
PRESC
COUNTER
0x000
N-2
N-1
CC[0]
N
N+1
N
COMPARE[0]
0
1
Figure 99: Timing diagram - COMPARE
• If the COUNTER is N, writing N+2 to a CC register is guaranteed to trigger a COMPARE event at N+2.
SysClk
LFClk
PRESC
COUNTER
0x000
N-1
N
N+1
N+2
> 62.5 ns
CC[0]
COMPARE[0]
X
N+2
0
1
Figure 100: Timing diagram - COMPARE_N+2
• If the COUNTER is N, writing N or N+1 to a CC register may not trigger a COMPARE event.
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Peripherals
SysClk
LFClk
PRESC
COUNTER
0x000
N-2
N-1
N
N+1
>= 0
CC[0]
X
N+1
COMPARE[0]
0
Figure 101: Timing diagram - COMPARE_N+1
• If the COUNTER is N and the current CC register value is N+1 or N+2 when a new CC value is written, a
match may trigger on the previous CC value before the new value takes effect. If the current CC value
greater than N+2 when the new value is written, there will be no event due to the old value.
SysClk
LFClk
PRESC
COUNTER
CC[0]
0x000
N-2
N-1
N
N+1
>= 0
N
X
COMPARE[0]
0
1
Figure 102: Timing diagram - COMPARE_N-1
6.16.8 TASK and EVENT jitter/delay
Jitter or delay in the RTC is due to the peripheral clock being a low frequency clock (LFCLK) which is not
synchronous to the faster PCLK16M.
Registers in the peripheral interface, part of the PCLK16M domain, have a set of mirrored registers in the
LFCLK domain. For example, the COUNTER value accessible from the CPU is in the PCLK16M domain and
is latched on read from an internal register called COUNTER in the LFCLK domain. COUNTER is the register
which is actually modified each time the RTC ticks. These registers must be synchronised between clock
domains (PCLK16M and LFCLK).
The following is a summary of the jitter introduced on tasks and events. Figures illustrating jitter follow.
Task
Delay
CLEAR, STOP, START, TRIGOVRFLOW
+15 to 46 μs
Table 76: RTC jitter magnitudes on tasks
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Peripherals
Operation/Function
Jitter
START to COUNTER increment
COMPARE to COMPARE
+/- 15 μs
+/- 62.5 ns
18
Table 77: RTC jitter magnitudes on events
1. CLEAR and STOP (and TRIGOVRFLW; not shown) will be delayed as long as it takes for the peripheral to
clock a falling edge and rising of the LFCLK. This is between 15.2585 μs and 45.7755 μs – rounded to 15
μs and 46 μs for the remainder of the section.
SysClk
CLEAR
LFClk
PRESC
COUNTER
CLEARa
0x000
X
X+1
0x000000
0x000001
0 or more SysClk after
= ~15 us
1 or more SysClk before
CLEARb
Figure 103: Timing diagram - DELAY_CLEAR
SysClk
STOP
LFClk
PRESC
COUNTER
STOPa
STOPb
0x000
X
X+1
0 or more SysClk after
= ~15 us
1 or more SysClk before
Figure 104: Timing diagram - DELAY_STOP
2. The START task will start the RTC. Assuming that the LFCLK was previously running and stable, the
first increment of COUNTER (and instance of TICK event) will be typically after 30.5 μs +/-15 μs. In
some cases, in particular if the RTC is STARTed before the LFCLK is running, that timing can be up to
~250 μs. The software should therefore wait for the first TICK if it has to make sure the RTC is running.
Sending a TRIGOVRFLW task sets the COUNTER to a value close to overflow. However, since the update
of COUNTER relies on a stable LFCLK, sending this task while LFCLK is not running will start LFCLK,
but the update will then be delayed by the same amount of time of up to ~250 us. The figures show
the smallest and largest delays to on the START task which appears as a +/-15 μs jitter on the first
COUNTER increment.
18
Assumes RTC runs continuously between these events.
Note: 32.768 kHz clock jitter is additional to the numbers provided above.
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Peripherals
SysClk
First tick
LFClk
PRESC
0x000
COUNTER
X
X+1
X+2
X+3
>= ~15 us
0 or more SysClk before
START
Figure 105: Timing diagram - JITTER_STARTSysClk
First tick
LFClk
PRESC
0x000
COUNTER
X
X+1
X+2
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