IP804A
Preliminary Datasheet
4-Port PSE Controller for PoE Systems
Features
IEEE 802.3AF-2003 and 802.3AT-2009
compliant
Single DC power supply voltage input (45~57V)
Wide temperature range: -40℃~+85℃
Supplies 4 independent power ports
Built-in power FETs
I2C Bus to access up to 8 x IP804A devices
Continuous system monitoring for every port
Independent system parameters setting for
every port
Thermal monitoring and protection
Built-in 3.3V regulators for external devices
Built-in Power on Reset
Configurations: (1) 30W x 4 ports
Total Current Limit
Built-in LEDs control
Built-in EEPROM interface for dumb application
Package and operation temperature
48 Pin(7mmx7mm) MQFN, -40~85℃
Application
General Description
4 port PSE Switch
8 port PSE Switch
IP804A is an 4-port PSE (Power Sourcing
Equipment) controller IC for PoE (Power over
Ethernet) systems. It integrates power, analog and
logic circuits into a single chip, and can be used for
Midcap and Endpoint PSE applications.
IP804A meets all IEEE 802.3AF-2003
requirements, such as multi-point resistor
detection, PD classification, DC Disconnect, and
Back-off for Midcap. It also meets all IEEE
802.3AT-2009 requirements, such as two-event
classification and supply maximum 36W per port.
IP804A comprises internal temperature
monitoring and thermal protection to protect
against junction overheating. The 3.3V regulator
is built-in to support external devices. Multiple
IP804As can integrate to build an 4 x N ports PSE
system, and I2C bus uses to collect PD power
status from each IP804A to support global power
managements.
Multiple IP804As can build a cost effective PHY
level PSE system to support PD classification and
power management without a host. With a
management host, a networked LLDP (Link Layer
Discovery Protocol) based multiple IP804As PSE
system can be built. Based on LLDP (part of IEEE
Std 802.3AT-2009), dynamic power management
between PSE and PD can be maintained in real
time for power efficiency.
Management switch host has options to
communicate IP804As via I2C bus for PSE
management activities. Opt couplers can be
implemented to provide electrical isolations
between the host and IP804As for signal
communication.
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May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
Table of Contents
Features ................................................................................................................................................................................. 1
General Description .............................................................................................................................................................. 1
Table of Contents .................................................................................................................................................................. 2
List of Figures ........................................................................................................................................................................ 3
List of Tables .......................................................................................................................................................................... 3
Revision History..................................................................................................................................................................... 4
1 Pin diagram ..................................................................................................................................................................... 5
1.1 IP804A Pin diagram (MQFN48) ................................................................................................ 5
2 IP804A application diagram .......................................................................................................................................... 6
2.1 Dumb & Smart device application ............................................................................................. 6
3 Block diagram ................................................................................................................................................................. 7
3.1 Blocks Description ..................................................................................................................... 8
3.1.1 Global Blocks ................................................................................................................. 9
3.1.2 Per Port Block .............................................................................................................. 10
4 Pin description ............................................................................................................................................................... 11
5 Functional Description..................................................................................................................................................13
5.1 System Reset .......................................................................................................................... 13
5.2 Operation Modes & System Configuration ............................................................................. 14
5.3 I2C Slave Interface .................................................................................................................. 16
5.4 EEPROM controller ................................................................................................................. 18
5.5 PSE State Machine ................................................................................................................. 19
5.6 Power Manager ....................................................................................................................... 22
5.6.1 Power Trunks ............................................................................................................... 22
5.6.2 Power Configuration .................................................................................................... 22
5.6.3 Port Polling................................................................................................................... 25
5.6.4 Power Event Handling ................................................................................................. 26
5.7 Real time Monitor Power Event .............................................................................................. 27
5.8 Port Status and Interrupt ......................................................................................................... 28
5.9 Total Current Limit ................................................................................................................... 30
5.10 LED Interface .......................................................................................................................... 31
6 IP804A Register descriptions ......................................................................................................................................34
7 Electrical Characteristics..............................................................................................................................................38
7.1 Absolute Maximum Ratings .................................................................................................... 38
7.2 Operating Conditions .............................................................................................................. 38
7.3 Electrical Characteristics for Analog I/O Pins ......................................................................... 38
7.4 IEEE802.3 AF/AT Mode Parameters ...................................................................................... 39
7.5 Digital Electrical Characteristics.............................................................................................. 42
7.6 AC Timing ................................................................................................................................ 43
7.6.1 Power On Sequence and Reset Timing ...................................................................... 43
7.6.2 EEPROM Timing .......................................................................................................... 44
7.6.2.1 Data read cycle .................................................................................................. 44
7.6.2.2 Command cycle ................................................................................................. 44
7.6.3 I2C Timing .................................................................................................................... 45
7.6.3.1 Data read cycle .................................................................................................. 45
7.6.3.2 Command cycle ................................................................................................. 45
7.7 Thermal Data ........................................................................................................................... 45
8 Order Information..........................................................................................................................................................46
9 Package Detail ..............................................................................................................................................................47
9.1 48 MQFN Outline Dimensions (in mm) ................................................................................... 47
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IP804A-DS-R01
IP804A
Preliminary Datasheet
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Pin Diagram ............................................................................................................... 5
Application Diagram .................................................................................................. 6
Block Diagram ........................................................................................................... 7
I2C bus read/write cycles diagram ........................................................................... 16
EEPROM Format ..................................................................................................... 18
LED behavior and system diagram of multiple IP804A application ........................ 33
Typical Power up Sequence .................................................................................... 40
Power on Sequence and Reset Timing Diagram .................................................... 43
EEPROM Read Cycle Timing Diagram ................................................................... 44
EEPROM Command Cycle Timing Diagram........................................................... 44
I2C Read Cycle Timing Diagram .............................................................................. 45
I2C Command Cycle Timing Diagram ..................................................................... 45
Package Outline Dimensions .................................................................................. 47
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Pin description ............................................................................................................. 11
Mode Setting ............................................................................................................... 15
Available functions in Operation modes...................................................................... 15
Port power off conditions ............................................................................................. 27
Register Page 0 description ........................................................................................ 34
Register Page 1 description ........................................................................................ 36
Electrical Characteristics ............................................................................................. 38
IEEE802.3 AF/AT Mode Parameters ........................................................................... 39
Digital Electrical Characteristics .................................................................................. 42
Order Information ...................................................................................................... 46
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IP804A-DS-R01
IP804A
Preliminary Datasheet
Revision History
Revision #
IP804A-DS-R01
Date
2017/05/02
Change Description
Initial release
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May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
1
Pin diagram
1.1
IP804A Pin diagram (MQFN48)
AD0
AD1
AD2
RstN
DV3P3
DGND
INITB
SDAI/EE_DAT
SDAO
SCL/EE_CLK
LED_DAT
LED_CLK
48
47
46
45
44
43
42
41
40
39
38
37
(7mm X 7mm Top view)
AGND
1
36
AGND
RS0
2
35
AGND
PortN0
3
34
AGND
RS1
4
33
AGND
PortN1
AGND
5
32
AGND
31
AGND
RS2
7
30
AGND
PortN2
8
29
AGND
RS3
9
28
AGND
PortN3
10
27
AGND
AGND
AGND
11
26
AGND
12
25
AGND
6
Exposed PAD
(Ground)
17
18
19
20
21
22
23
24
RGND
V54
AGND
V5
V3P3
V2P5
VPP
In_Top
EnB_Reg
SCAN1
VRext
SCAN0
16
14
15
13
Exposed pad is system GND, must be soldered to PCB ground plane
Figure 1
Pin Diagram
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IP804A-DS-R01
IP804A
Preliminary Datasheet
2
IP804A application diagram
2.1
Dumb & Smart device application
Switch
PA0+~PA3+
Diode
V54
C
PA0-
Port N0
SCAN1
Operation
Mode
Transformer
Transformer
44~57V Power input
FUSE
SCAN0
0.5 ohm
IP804A
TVS
RS0
LED_CLK
LED
LED_DAT
PA3-
Port N3
SCL/EE_CLK
SDAI/EE_DAT
EEPROM
SDAO
RJ45
RS3
TP cable
RJ45
TP cable
MCU
Power Device
2
I C Bus
Power Device
Options for Smart Application
Figure 2
Application
Smart
MCU
V
Dumb
X
Application Diagram
EEPROM
X
V: update default value
X: use default value
IP804A Mode setting
Manual mode
Reference
Section 5.3
Auto mode
Section 5.4
V: necessary; X: unnecessary
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IP804A-DS-R01
IP804A
Preliminary Datasheet
3
Block diagram
RGND Vrext EnB_Reg V3P3 V5
AD0
AD1
AD2
SCL/EE_CLK
SDAI/EE_DAT
SDAO
INTB
VPP
AGND
V54
Port3
Port1
Reference & Regulator
Port0
2
IC
Interface
Registers
Detection
Amp
AGND
RstN
SCAN0
SCAN1
DV3P3
V2P5
DGND
Control Management
& State Machine
Classification
T Sensor
&
Thermal
Shutdown
PortN0
︴
Power
Management
10 Bits
ADC
Bias
PortN3
I/V Control
DC Disconnect
LED_DAT
LED_CLK
LED Control
POR & OSC
AGND
RS3
RS0
AGND
Figure 3
Block Diagram
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IP804A-DS-R01
IP804A
Preliminary Datasheet
3.1
Blocks Description
The blocks of IP804A include global blocks for and per port blocks as below:
Global blocks for 4 ports:
Reference & Regulator
2
I C Interface
Registers
Control Management & State Machine
Power Management
10 Bits ADC
POR & OSC
Per port blocks for individual port:
Detection
Classification
I/V Control & Fold-back
Amp
DC Disconnect
T sensor & Thermal Shutdown
Bias
Power MOSFET
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IP804A-DS-R01
IP804A
Preliminary Datasheet
3.1.1 Global Blocks
¾
Reference & Regulator:
The Reference & Regulator generates 2.5V, 3.3V and 5V power for internal use and 3.3V power
also can supply typical 6mA current on V3P3 pin for external devices if EnB_Reg pin is connected to
GND. If EnB_Reg is conncted to 3.3V, the internal 3.3V regulator is disabled and V3P3 pin should be
connected to an external 3.3V power source.
It also generates 1.25V voltage on VREXT pin, which is connected to ground through an external
62KΩ resistor, to generate internal bias current.
¾
Registers:
The “Registers” provides the 8 bits data for Ilim, Icut programming registers, and all other needing
registers per port
¾
Control Management & State Machine:
This block provides all the control procedures to perform PoE function. The “State Machine”
implements as specified in the IEEE802.3AF/AT.
¾
Power Management:
The “Power Management” provides power management method to meet PD power requirement, or
not to power PD if power is not enough.
¾
10 Bits ADC:
The 10 Bits ADC used to convert analog signals into digital bus for Control Management, State
Machine, and Power Management for request.
¾
POR & OSC:
The POR generates an internal power on reset signal when V54 is power on. The POR also
monitors V3P3, DV3P3, V5, & V54 voltage level. If these voltages level are below specific thresholds, a
reset signal generates and resets IP804A.
The OSC is an internal oscillator to generate 8MHz clock for IP804A timing source.
¾
I2C Interface:
A host (master) can communicates with multiple IP804A (slave) via I2C Interface (SCL/EE_CLK,
SDAO, SDAI/EE_DAT) to collect PD power status to support global power managements and all
control requirements.
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IP804A
Preliminary Datasheet
3.1.2 Per Port Block
¾
Detection:
The IP804A uses 4 points detection method to discover PD. It shall accepted resistance as a valid
“AF/AT PD” between 19KΩand 26.5KΩ, with a paralleled capacitance small than 0.15uF.
It shall rejects resistance with paralleled capacitance as an invalid “AF/AT PD” small than 15KΩ,
larger than 33KΩ, or capacitance larger than 10uF.
The specification is as specified in the IEEE802.3AF/AT.
¾
Classification:
The “Classification” is to distinguish the requested power of PD as specified in the IEEE802.3AF/AT.
In IEEE 802.3AF, classification is 1-event method.
In IEEE 802.3AT, classification is 2-event method.
¾
I/V Control:
The “I/V Control” is to control the slew rate during “detection, classification, inrush, short circuit,
power off … and so on”, as specified in IEEE802.3AF/AT
When short circuit event occurs, the “I/V control” will reduce the port current instantaneously to
protect the power MOSFET from damages.
¾
Amp:
The “AMP” is used to convert the differential voltage between V54 and PortNx into single end
voltage. This voltage will be fed into the “Detection, Classification, I/V Control” blocks to perform the
IEEE8023AF/AT specifications.
¾
DC Disconnect:
The IP804A supports DC Disconnect function according to IEEE 802.3AF-2003 & IEEE
802.3AT-2009 requirement.
This DC Disconnect continuously monitors port current after port inrush time, and disconnects port
current when port current is below 7.5mA (typical) for more than 360ms (typical) .Please refer to
Tmpdo in table 8 for detail information.
¾
T sensor & Thermal Shutdown:
The “T sensor” senses the temperature of each port, and will shutdown the port current as
temperature beyond 150℃. When temperature goes down to 129℃, the port will start again.
¾
Bias:
The “Bias” provides the current & voltage bias for all ports according to control signals.
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IP804A-DS-R01
IP804A
Preliminary Datasheet
4
Pin description
Type
Description
Type
Description
P
Power or Ground
O
Output
I
Input
OD
Open drain
IL
Input
reset
NC
No connection in internal
latched
upon
Table 1 Pin description
Pin
no.
Label
Type
Description
Exposed pad, it should be connected to AGND.
Analog ground
Port0 current sensing voltage input
It should be connected to AGND through a 0.5Ω±1% resistor.
Port0 negative feeding voltage input.
Port1 current sensing voltage input
It should be connected to AGND through a 0.5Ω±1% resistor.
Port1 negative feeding voltage input.
Analog ground
Port2 current sensing voltage input
It should be connected to AGND through a 0.5Ω±1% resistor.
Port2 negative feeding voltage input.
Port0 current sensing voltage input
It should be connected to AGND through a 0.5Ω±1% resistor.
Port0 negative feeding voltage input.
Analog ground
Analog ground
Operation mode, please refer to section 5.2 table 2 for more detail
information.
Operation mode, please refer to section 5.2 table 2 for more detail
information. It should be connected to AGND for normal operation.
Connecting to RGND through a 62KΩ±1% resistor, it is for internal bias only.
Low noise analog reference ground, it should be connected to AGND.
Main power supply input for chip
A 4.7uF capacitor should be added between V54 and AGND.
Analog ground
Internal 5V generation for internal use only.
A 4.7uF capacitor should be added between V5 and AGND.
When EnB_Reg is connected to AGND, the built-in 3.3v regulator is active,
and besides IP804A itself, V3P3 can provide 3.3v (6mA) for external device.
When EnB_Reg is connected to 3.3v, V3P3 should be connected to an
external power 3.3V (6mA minimum) for IP804A.
A 4.7uF capacitor should be added between V3P3 and AGND.
Enable/Disable the internal 3.3V regulator
Please refer to pin description of V3P3.
Internal 2.5V for internal use only
Adding an 1uF capacitor between V2P5 and AGND
Connecting to V5 for EFuse power
1
EPAD
AGND
P
P
2
RS0
I
3
PortN0
I
4
RS1
I
5
6
PortN1
AGND
I
P
7
RS2
I
8
PortN2
I
9
RS3
I
10 PortN3
11 AGND
12 AGND
I
P
P
13 SCAN0
I
14 SCAN1
I
15 Vrext
16 RGND
O
P
17 V54
P
18 AGND
P
19 V5
P
20 V3P3
P
24 EnB_Reg
I
21 V2P5
P
22 VPP
P
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IP804A-DS-R01
IP804A
Preliminary Datasheet
(Continued)
Pin
Label
no.
23 In_Top
25 AGND
26 AGND
27 AGND
Type
P
P
Description
P
It should be connected to RGND for normal operation.
Analog ground
Analog ground
P
Analog ground
28 AGND
29 AGND
P
P
Analog ground
30 AGND
P
Analog ground
31 AGND
32 AGND
33 AGND
34 AGND
P
P
Analog ground
Analog ground
P
P
Analog ground
35 AGND
36 AGND
P
Analog ground
P
Analog ground
Analog ground
Analog ground
37 LED_CLK
OD
Serial LED clock output, please refer to section 5.10 LED interface.
38 LED_DAT
OD
Serial LED data output
39 SCL/EE_CLK
I/OD
In manual mode, this pin is I2C clock input.
In auto mode, this pin is clock out to EEPROM.
I2C serial data output
In manual mode, this pin is I2C serial data input.
41 SDAI/EE_DAT I/OD
In auto mode, this pin is data input from EEPROM.
40 SDAO
OD
42 INTB
OD
Interrupt output and low active
43 DGND
P
Digital ground, it should be connected to AGND.
Digital power 3.3V
A 4.7uF capacitor should be added between DV3P3 and DGND and
DV3P3 should be connected to V3P3.
44 DV3P3
P
45 RstN
46 AD2
I
IL
It is a low active signal to reset IP804A.
I2C device address bus AD2, please refer to section 5.3&5.10
47 AD1
IL
I2C device address bus AD1
48 AD0
IL
I2C device address bus AD0
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IP804A
Preliminary Datasheet
5
Functional Description
5.1
System Reset
System reset occurs in either of the following conditions:
1. Reset triggered by the built-in power-on-reset circuit
IP804A generates an internal power on reset signal when V54 is power on. It didn’t leave reset state
until V54 reaching V54_UVL. After reset, IP804A still keeps on monitoring voltage level of V3P3, DV3P3,
and V54. If the voltage level of V54 (V3P3) is below V54_UVL(V3P3_UVL),or over V54_OVL
(V3P3_OVL), IP804A enters reset state. Please refer to section 7.3 for detail specification of V54_UVL,
and V3P3_UVL. It is note that there are two values for one parameter because of hysteresis.
2. Reset triggered by the reset pin (RstN)
3. Reset triggered by the Software
¾
System Control Register @ 0x02 of Page 1
Bit #
7:1
R/W
R
0
R/W
Default Description
0
Reserved.
Software Reset.
Writing 1 to this bit initiates a system reset. After system reset, this bit is
0
automatically cleared. Writing 0 has no effects. Reading this bit always
returns 0.
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IP804A-DS-R01
IP804A
Preliminary Datasheet
5.2
Operation Modes & System Configuration
IP804A operates in four possible modes, namely the Auto Mode, Manual Mode, Diagnostic Mode, and
Scan Mode. The mode in which the chip operates in is determined by the two pins SCAN at
system reset.
¾ Auto Mode means the chip is operating in a stand alone fashion, i.e. without the need for software
intervention. The state machine does the detection, classification, power configuration, and system
event monitoring automatically. The system events and status will be recorded in the corresponding
registers, however, no interrupt will be generated and I2C bus in this mode could not be used.
IP804A detects voltage of power supply automatically to determine whether it should support AF or
AT standard. If V54 is greater than 50 volts, IP804A supports AT standard (PSE type 2), otherwise
IP804A supports AF standard (PSE type 1). The detection result is stored in the AF/AT Mode
Register.
Avoid setting the wrong AF/AT mode, IP808 reset time must be 0.5S or more waiting power supply
voltage to stable.
If there is an EEPROM, the contents of the EEPROM are loaded into the register file as initial values.
Please refer to the section 5.4 for the description of the syntax of the contents of the EEPROM.
¾ Manual Mode means the chip will not be working, that is all ports are disabled, until the software has
(1) enabled the port by writing 0x01 to the Port Power Control Register, and (2) written 1 to the
Start bit of the System Control Register; at that time, the state machine start doing the detection,
classification, power configuration, and system event monitoring as does in auto mode. The interrupt
output pin will be active if the interrupt masks are turned off by software and predefined events occur.
The ports can be disabled (power turned off and no further detection activity) by writing 0x00 to the
Port Power Control Register. If the operation mode is either in manual mode or diagnostic mode,
the host CPU can read register 0 (I2C LSB Device Address Register) to make sure that IP804A has
done the system start up procedure
¾ Diagnostic Mode, as its name suggests, is not for normal operation. It is used in field diagnosis and
mass production test. In this mode, the state machine will be working in a step-by-step fashion, in
which the state machine will stop at each detection, classification, and power configuration step and
can be controlled by software to advance to the next step. The port current, voltage, or temperature
measured by the ADC can be read in each steps. Another use of diagnostic mode is to program the
E-Fuse during mass production.
¾ Scan Mode is also not for normal operation. It is used to execute the scan test through the scan in,
scan out, and scan enable pins. The state machine will not be working in this mode.
Mode
Pin setting
SCAN0
SCAN1
AD2
LED_CLK
LED_DAT
Auto Mode
LED
Master
0
0
1
1
1
LED
Slave
0
0
0
1
1
LED
Disable
0
0
X
0
0
Manual Mode
LED
Master
1
0
1
1
1
LED
Slave
1
0
0
1
1
LED
Disable
1
0
X
0
0
Diagnostic
Mode
Scan
Mode
0
1
X
0
X
1
1
X
X
X
Please refer to Section 5.11 for LED mode setting.
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IP804A-DS-R01
IP804A
Preliminary Datasheet
Table 2 Mode Setting
A summary of available functions in different modes
Function
Auto start detection,classfiction, and power up
Program to detection, classfiction, and power up
Stepbystepdetection classfiction, and power up
Access register through I2C
Load EEPROM
LED master & slave
Auto
mode
V
V
V
Manual
mode
V
V
V
V
Diagnostic
mode
V
V
V
-
Reference
Section 5.2
Section 5.2
Section 5.2
Section 5.3
Section 5.4
Section 5.10
Table 3 Available functions in Operation modes
¾ System Configuration Register @ 0x01 of Page 1
Bit #
R/W
Default
7:6
R
N/A
5
R
0
4
R/W
0
3:0
R
0
Description
Operation Modes.
At system reset, these bits latch the input pins SCAN to
determine the operation mode.
00b: Auto Mode.
01b: Manual Mode.
10b: Diagnostic Mode.
11b: Scan Mode.
Reserved.
Alternative Indicator.
0: Alternative A.
1: Alternative B.
Reserved.
AF/AT Mode Register @ 0x25 of Page 0
Bit #
R/W
Default
3:0
R/W
0x00
Description
AF/AT Mode.
The 4 bits represent the AF/AT mode of the 4 ports, where bit 0
corresponds to port 0, and bit 1 corresponds to port 1, etc.
0 = AF mode.
1 = AT mode.
In auto mode, IP804A will detect the supply voltage to determine
AF/AT mode and automatically update this register.
In manual mode or diagnostic mode, this register should be written
by host CPU.
Note: When Host Defined Power Limit (HDPL) is used, please refer
to Host Defined Power Limit (HDPL) application note.
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IP804A-DS-R01
IP804A
Preliminary Datasheet
I2C Slave Interface
5.3
Through the I2C slave interface of IP804A, host CPU can access the register file in IP804A. It consists of
SCL, SDAO and SDAI pins, where SCL is Clock, SDAO is Serial Data Output and SDAI is Serial Data
Input. It should be note that SDAO and SDAI could be connected to implement a bidirectional data pin.
This I2C interface supports the 7-bit addressing mode of the I2C standard. The clock speed can be up to
1 Mbit/sec.
There can be up to eight IP804A chips on one I2C bus, the LSB 3 bits of the I2C address can be assigned
with the address pin AD2~AD0. The MSB 4 bits of the I2C address are fixed at 1010b.
The following diagram is the register read/write cycles of the I2C bus.
I2C Register Write Cycle
S
7-bit SLAVE
address
R/W
A
Register
Address
A
A
1st Register
Address
A
A
1stRegisterData
A
Register Data
A
P
‘0’ = Write
I2C Register Read Cycle
S
7-bit SLAVE
address
R/W
P
‘0’ = Write
S
7-bit SLAVE
address
R/W
‘1’ =Read
the last
Register data
….
N (Data bytes+ ACK)
P
Data byte + NACK
= From host to IP804A
S = Start Bit = 1Æ0
P = Stop Bit = 0Æ1
= From IP804A to host
A = ACK Bit=0
A = NACK Bit=1
Figure 4
A
I2C bus read/write cycles diagram
Following the 7-bit slave address and read/write bit, the 1st data byte received by IP804A is always
interpreted as the register address to be accessed, thus named the address byte.
In a write cycle, following the address byte, there is only one byte, which contains the register data to
be written. IP804A replies an ACK to the host whenever it receives a data byte. After writing this byte, the
host should terminate the write cycle by sending a STOP bit.
In a read cycle, the host writes only one byte, which contains the initial address of registers to be read,
to the IP804A firstly. Then the host needs to start another I2C cycle with its read/write bit set to 1. IP804A
will continue to send out the next data and increase the address by one automatically whenever the host
acknowledges a data byte with an ACK, If the calculated register address is valid (within valid address
range). The host can terminates a read cycle by sending a NACK following by a STOP bit. If the address
of the data to be sent back falls out of valid register address range, IP804A always returns 00h.
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IP804A-DS-R01
IP804A
Preliminary Datasheet
¾ I2C Device Address Register @ 0x00 of Both Pages
Bit #
7
R/W
R
Default
0
6
R/W
0
5:3
R
0
2:0
R
000b
Description
Reserved.
Register Page.
This bit specifies the page number of the register to be accessed
through the I2C interface.
0: page 0, 1: page 1
Reserved.
I2C Device LSB Address.
Unique device address to identify this chip on the I2C bus. This address
is latched in from the input pins AD2~AD0.
The highest I2C clock speed supported is 1MHz. However, in order to prevent abnormal activity on the
I C bus from hanging IP804A, the I2C interface implements a time out mechanism. Host CPU can stop
the I2C clock when it’s low and resume the clock within 7 mini-seconds. If the clock does not resume
within 7 mini-seconds, the I2C interface will abort the current I2C cycle and wait for the next START
condition.
2
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IP804A-DS-R01
IP804A
Preliminary Datasheet
5.4
EEPROM controller
When IP804A operates in auto mode, the register file can be loaded with some initial value from external
EEPROM (24xx series EEPROM, Maximum support to 24C16). IP804A reads the EEPROM starting
from address 0, parses the contents of the EEPROM command blocks, checks for integrity of the
contents, and then writes the designated registers. This process continues until there is either no more
data or the integrity check fails. EEPROM is necessary only if user wants to modify the default value of
registers in auto mode.
The format of the EEPROM follows:
BYTE
0
1
2
3
…
1+N
2+N
3+N
Bit 7
Bit 6
Command
Bit 5
Bit 3
Bit 2
# of Data Bytes
Starting Register Address
Data Byte 1
Data Byte 2
…
Data Byte N
Checksum Byte
Next command block
Figure 5
Bit 4
Bit 1
Bit 0
X
EEPROM Format
Where:
¾ Command: 10b = valid command, other values are invalid command and will stop the EEPROM
loading process.
¾
# Of Data Bytes: the number of data bytes in this command block. 0 = 1 byte, 1 = 2 bytes, etc.
¾
Starting Register Address: the starting register address to be loaded by the following data bytes.
¾
Data Bytes: the data bytes to be loaded in to specified registers.
¾ Checksum Byte: the checksum byte is the checksum of all previous bytes in the command block.
The checksum is calculated by adding all the previous bytes with the carry bit (if any) adding back to the
sum. If the checksum fails, the system start up procedure fails and the system halt.
18 / 47
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IP804A-DS-R01
IP804A
Preliminary Datasheet
5.5
PSE State Machine
IP804A has four ports and each port is mainly controlled by a state machine to perform the detection,
classification, and powering up procedures. As the eight state machines run in parallel, they contend for
ADC 1 in the detection and classification procedures. Thus an arbiter is needed to grant the access
rights among the eight state machines.
Furthermore, to limit the chip inrush current, a maximum of two ports are allowed to start their
classification procedures simultaneously. And only one port is allowed to turn on power at a time. After
successful detection, classification, and power configuration, the port power is turned on.
The state machine is also designed to respond to abnormal power events, such as overload, short
circuit, and overheat (thermal shutdown); basically port power will be turned off when such event
happens. It takes time to cool off the device after power is turned off, so the state machine will delay a
certain amount of time before starting next detection procedure for the port.
¾ Port 0~3 Power Control Registers @ 0x98~0x9B of Page 1
Bit #
7:2
1:0
R/W Default Description
R
0x00 Reserved.
PSE Enable.
00b = PSE port disabled.
The port is disabled, port power is turned off, and the PSE state machine
returns to the IDLE state.
01b = PSE port enabled.
The port is enabled, and the PSE state machine starts the detection
process if the port is not in error condition and the Start State Machine
bit in the State Machine Control Register is set to be 1.
R/W
0x0
10b = PSE port force power on.
The port is forced to turn power on without going through the normal
detection, classification, and power configuration processes. This is used
for testing purpose, not for normal operation.
11b = PSE port enabled (skip detection process).
The port is enabled, and the PSE state machine skips the detection
process and starts the classification process directly. This is only used for
testing purpose and not for normal operation.
¾ Port 0~3 State Machine Control Registers @ 0x90~0x93 of Page 1
Bit #
R/W Default
7
R/W
0
6
R/W
0
5
R
0
4:0
R
0
Description
Start State Machine.
When in manual mode or diagnostic mode, writing 1 to this bit will start the
state machine (from IDLE state) if the port is enabled.
Step State Machine.
When in diagnostic mode, writing 1 to this bit will advance the state machine
to the next state, after which this bit will be cleared by hardware. Writing 0 has
no effect.
Note that not every state can be stepped; Basically, only those states directly
related to the detection and classification procedures can be stepped.
Reserved.
Current State of the State Machine.
Current state of the state machine.
0 = DISABLED
1 = TEST_MODE
2 = TEST_ERROR
3 = IDLE
4 = START_DETECTION
5 = DETECT_EVAL
6 = SINATURE_INVALID
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IP804A-DS-R01
IP804A
Preliminary Datasheet
Bit #
R/W Default
Description
7 = BACKOFF
8 = START_CLASSIFICATION (AF Mode)
1-EVENT_CLASS (AT Mode)
9 = CLASS_EV1 (AT Mode)
10 = MARK_EV1 (AT Mode)
11 = CLASS_EV2 (AT Mode)
12 = MARK_EV2 (AT Mode)
13 = CLASSIFICATION_EVAL
14 = POWER_DENIED
15 = POWER_UP
16 = POWER_ON
17 = SET_PARAMETERS (AT Mode)
18 = DLL_ENABLE (AT Mode)
19 = ERROR_DELAY (AT Mode)
ERROR_DELAY_SHORT (AF Mode)
20 = ERROR_DELAY_OVER (AF Mode)
¾ Port 0~3 Detected Signature Registers @ 0x68~0x6B of Page 0
Bit #
7:3
R/W
R
1:0
R
Default Description
0x0 Reserved.
Detected Signature.
00b = RBAD.
0
01b = RGOOD.
10b = ROPEN.
¾ Port 0~3 Invalid Signature Counter Registers @ 0xB0~0xB3 of Page 1
Bit #
R/W
Default
3:0
R
0
Description
Invalid Signature Counter.
When an invalid signature is detected in the detection process, this counter is
increased by 1.
¾ Port 0~3 Classification Event Number Registers @ 0xA0 of Page 1
Bit #
R/W
Default
7:6
R/W
2
5:4
3:2
1:0
R/W
R/W
R/W
2
2
2
Description
Number of Classification Events for Port 3.
Valid value range is from 0 to 2. The value 3 will be regarded as 2. If the value
is 0, no classification is executed, and the PD is always deemed class 0
device.
This register can be written to by host CPU. However, according to
IEEE802.3 standard, if the port is in AF mode, only one classification event is
executed, and in AT mode, there will be two classification events. So, this
register will be automatically updated when the AF/AT Mode Register is
updated.
Number of Classification Events for Port 2.
Number of Classification Events for Port 1.
Number of Classification Events for Port 0.
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IP804A-DS-R01
IP804A
Preliminary Datasheet
¾
PSE Skip Event 2 Register @ 0xA2 of Page 1
Bit #
R/W
Default
3:0
R/W
0xFF
Description
Skip the Second Classification Event.
Bit 0 corresponds to port 0, bit 1 corresponds to port 1, etc.
0 = do not skip event 2,
1 = skip event 2.
¾ Port 0~1 Detected PD Class Registers @ 0x88 of Page 0
Bit #
7
R/W
R
6:4
R
3
2:0
R
R
Default Description
0
Reserved.
Detected PD Class of Port 1.
0 = Class 0
1 = Class 1
2 = Class 2
5
3 = Class 3
4 = Class 4
5 = Unknown
0
Reserved.
5
Detected PD Class of Port 0.
¾ Port 2~3 Detected PD Class Registers @ 0x89 of Page 0
Bit #
7
6:4
3
2:0
R/W
R
R
R
R
Default
0
5
0
5
Description
Reserved.
Detected PD Class of Port 3.
Reserved.
Detected PD Class of Port 2.
¾ Port ICLASS Registers @ 0x78~0x7F of Page 0
¾
Bit #
7:5
R/W
R
4:0
R
Bit #
7:0
R/W
R
Default Description
0
Reserved.
Port ICLASS MSB.
The current detected in classification.
5
The MSB 10 bits are integer and the LSB 4 bits are fractional. Unit is in
mAmp.
Default Description
0x00 Port ICLASS LSB.
Port PD Requested Power Registers @ 0x90~0x93 of Page 0
Bit #
R/W
Default
7:0
R
0x00
Description
PD Requested Power of Port.
The power requested by a PD that passes detection and classification.
The MSB 6 bits are the integer part, and the LSB 2 bits are the fractional part.
Unit is in Watts.
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IP804A-DS-R01
IP804A
Preliminary Datasheet
5.6
Power Manager
Power manager is responsible for two tasks: power configuration and power monitoring. Power
configuration is the task to allocate power to the ports requesting for power. Power monitoring is the task
to monitor power conditions (current, voltage, and temperature). When invalid conditions occur, proper
actions will be taken to prevent hazardous consequences.
5.6.1 Power Trunks
Before doing power configuration, the total available power must be determined first. IP804A supports
two trunks of power, where each power trunk has its own set of parameters to facilitate the calculation of
total available power.
¾ Trunk Power Limit is the maximum power supply capacity allocated to the power trunk.
¾ Trunk 0 Power Limit Register @ 0x40~0x41 of Page 1
Bit # R/W Default Description
7:3
R
0
Reserved.
2:0 R/W
1
Trunk 0 Power Limit (MSB).
Bit # R/W Default Description
Trunk 0 Power Limit (LSB).
7:0 R/W 0x2C Trunk Power Limit specifies the upper limit of the power supply.
Default is 300 Watts.
¾ Trunk 1 Power Limit Register @ 0x42~0x43 of Page 1
Bit # R/W Default Description
7:3
R
0
Reserved. 0x42
2:0 R/W
1
Trunk 1 Power Limit (MSB). 0x42
Trunk 1 Power Limit (LSB). 0x43
7:0 R/W 0x2C
Default is 300 Watts.
¾ Trunk Select Register @ 0x69 of Page 1
Bit # R/W Default Description
7:3
R
0
Reserved.
Trunk Select.
Writing to this register will switch power trunk. Note that whenever the
parameters of the power trunk currently in use are updated, this Trunk Select
1:0 R/W
0
Register must also be written to make the newly updated parameters in
effect.
0 = Trunk 0, 1 = Trunk 1.
5.6.2 Power Configuration
Power manager is responsible to allocate powers to the ports that pass the detection and classification
process. To do so, several parameters must be specified or be calculated in advance:
1) Maximun Trunk Power (specified in register 0x40~0x43, page1).
2) Power configuration Mode (specified in register 0x10, page1).
¾ Power configuration Mode specifies the way to determine the requested port power of the power
device (RPP of Power configuration Mode Register) in the power configuration process.
¾ Requested Port Power is determined in the power configuration process according to RPP of power
configuration mode.
.
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IP804A-DS-R01
IP804A
Preliminary Datasheet
¾ Power configuration Mode Register 0 @ 0x10 of Page 1
Bit #
7:5
R/W
R/W
4:3
R/W
2:0
R
Default Description
0
Reserved
Requested port power (RPP) specifies ways to determine the port power
requested by the power device in the power configuration process
0 = Host Defined Power Limit (HDPL) specified in Host Defined Power
Limit registers
1
1 = Class defined power limit (CDPL) specified in Class Defined Power
Limit registers.
0
Note: When Host Defined Power Limit (HDPL) is used, please refer to Host
Defined Power Limit (HDPL) application note.
Reserved.
¾ Class 0 Defined Power Limit Registers @ 0x12 of Page 1
Bit #
R/W
Default
7:0
R/W
0x3e
Description
Class 0 Port Power Limit (C0DPL).
The maximum allowable port power for class 0 devices if RPP is set to be 1.
Bit 7~2 specifies the integral part of the power limit, whereas bit 1~0
specifies the fractional part of the power limit value.
Default is 0x3e = 15.5W.
¾ Class 1 Defined Power Limit Registers @ 0x13 of Page 1
Bit #
R/W
Default
7:0
R/W
0x10
Description
Class 1 Port Power Limit (C1DPL).
The maximum allowable port power for class 1 devices if RPP is set to be 1.
Bit 7~2 specifies the integral part of the power limit, whereas bit 1~0
specifies the fractional part of the power limit value.
Default is 0x10 = 4.0W.
¾ Class 2 Defined Power Limit Registers @ 0x14 of Page 1
Bit #
R/W
Default
7:0
R/W
0x1c
Description
Class 2 Port Power Limit (C2DPL).
The maximum allowable port power for class 2 devices if RPP is set to be 1.
Bit 7~2 specifies the integral part of the power limit, whereas bit 1~0
specifies the fractional part of the power limit value.
Default is 0x1c = 7.0W.
¾ Class 3 Defined Power Limit Registers @ 0x15 of Page 1
Bit #
R/W
Default
7:0
R/W
0x3e
Description
Class 3 Port Power Limit (C3DPL).
The maximum allowable port power for class 3 devices if RPP is set to be 1.
Bit 7~2 specifies the integral part of the power limit, whereas bit 1~0
specifies the fractional part of the power limit value.
Default is 0x3e = 15.5W.
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IP804A-DS-R01
IP804A
Preliminary Datasheet
¾ Class 4 Type 1 Power Limit Registers @ 0x16 of Page 1
Bit #
R/W
Default
7:0
R/W
0x3e
Description
Class 4 Port Power Limit Type 1 (C4DPL_TYPE1).
The maximum allowable port power for class 4 type 1 devices if RPP is set to
be 1.
Bit 7~2 specifies the integral part of the power limit, whereas bit 1~0
specifies the fractional part of the power limit value.
Default is 0x3e = 15.5W (i.e. Type 1 device, ICABLE = 0.35A, VPORT_PSE_MIN =
44V)
¾ Class 4 Type 2 Power Limit Registers @ 0x17 of Page 1
Bit #
R/W
Default
7:0
R/W
0x78
Description
Class 4 Port Power Limit Type 2 (C4DPL_TYPE2).
The maximum allowable port power for type 2 class 4 devices if RPP is set to
be 1.
Bit 7~2 specifies the integral part of the power limit, whereas bit 1~0
specifies the fractional part of the power limit value.
Default is 0x78 = 30.0W (i.e. Type 1 device, ICABLE = 0.60A, VPORT_PSE_MIN =
50V)
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May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
5.6.3 Port Polling
Besides power configuration, power manager is also responsible for the monitoring of port current (I),
port voltage (V), and port temperature (T). When either of IVT is out of its valid range, power manager will
take prompt actions to prevent the system from hazardous consequences.
Power manager do the monitoring by periodically polling the IVT of each port. The poll period can be
specified in the IVT Poll Register.
¾ Force Poll Register @ 0xE2 of Page 0
Bit #
R/W
Default
3:0
R/W
0
Description
Force Poll.
Writing 1 to a bit will force an IVT poll on the corresponding port.
Bit 0 corresponds to port 0, and bit 1 corresponds to port 1, etc.
When the polling completes, the bit will be cleared automatically.
¾ IVT Poll Register @ 0xE3 of Page 0
Bit #
3
R/W
R
6
R/W
5
R/W
4:0
R/W
Default Description
0
Reserved.
Check Port Voltage.
1
0 = do not check port voltage.
1= check port voltage after polling.
Auto Poll.
0
Enable automatically polling of IVT of powered ports. In auto mode, this bit
will be set to 1 automatically after system reset.
Poll Period.
10
Number of 8ms between each poll to the port IVT. Minimum value is 10.
Thus, by default, the poll period is 10 * 8 = 80 ms.
¾ Port 0~3 Current Registers @ 0xA0~0xA3 of Page 0
Bit #
7:4
3:0
Bit #
R/W
R
R
R/W
7:0
R
Default Description
0
Reserved.
0
Port Current.
Default Description
Port Current.
0
The port current. MSB 10 bits are the integer part and LSB 2 bits are the
fractional part. The unit is mA.
¾ Port 0~3 Voltage Registers @ 0xB0~0xB7
Bit #
7:4
3:0
Bit #
R/W
R
R
R/W
7:0
R
Default Description
0
Reserved.
0
Port Voltage.
Default Description
Port Voltage.
The MSB 8 bits are the integer part and the LSB 4 bits are the fractional part.
0
The unit is Volts. This value is updated every time the port is polled.
Note that the true port voltage is (Supply Voltage - Port Voltage). Please
refer to Supply Voltage Registers.
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IP804A
Preliminary Datasheet
¾ Port 0~3 Temperature Registers @ 0xC0~0xC7 of Page 0
Bit #
7:5
4:0
Bit #
R/W
R
R
R/W
7:0
R
Default Description
0
Reserved.
0
Port Temperature.
Default Description
Port Temperature.
0
The MSB 9 bits are the integer part and the LSB 4 bits are the fractional part.
The unit is Celsius. This value is updated every time the port is polled.
¾ Supply Voltage Registers @ 0xE0~0xE1 of Page 0
Bit #
7:4
3:0
Bit #
R/W
R
R
R/W
7:0
R
Default Description
0
Reserved.
0
Supply Voltage.
Default Description
Supply Voltage.
The supply voltage in Volts.
0
The MSB 8 bits are the integer part, where the LSB 4 bits are the fractional
part.
5.6.4 Power Event Handling
After the IVTs are polled and recorded, the power manager checks the polled values against
predefined valid ranges. If the polled values drop out of the predefined valid range, power events are
recorded and handled. The power events triggered by power manager Port Temperature Limit Event.
When a power event occurs, if its corresponding power event handle bit is 1, the port power is turned
off. If IP804A is in manual mode or diagnostic mode, and the power event’s corresponding status mask
bit is 1, an interrupt will be issued to the host CPU.
¾ Port Temperature Limit Event (Bit 7). After the port is polled and if the port temperature is above
the value specified in Port Temperature Limit Register, a Port Temperature Limit Event occurs.
¾ Port Temperature Limit Registers @ 0x24~0x25 of Page 1
Bit #
7:5
4:0
Bit #
R/W
R
R
R/W
7:0
R
Default Description
0
Reserved.
0x9 Port Temperature Limit.
Default Description
Port Temperature Limit.
The port temperature limit in Celsius, over which a port temperature limit
0x60 event will be reported.
The 9 MSB bits are the integer part, and the 4 LSB bits are the fraction part.
Default 0x960 = 150°C.
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IP804A-DS-R01
IP804A
Preliminary Datasheet
5.7
Real time Monitor Power Event
Power events described in previous sections are discovered only when the ports are polled. The
analog monitor can continuously watch over and report time-critical power events so that the power
manager can take prompt actions. Power events from analog monitor include thermal shutdown event,
severe short circuit event (I > 1Amp), MPS error event (DC Disconnect), overload event (I > ICUT), and
short circuit event (I > ILIM).
¾ Thermal Shutdown Event is the event where the port temperature is over the pre-defined thermal
shutdown threshold. The port power is turned off and the port is eligible for detection only after the port
is cooled off (temperature drops below the threshold).
¾ Severe Short Circuit Event is the event where the port current is over 1 Amp. Immediate action
must be taken to eliminate such event. The power manager responds to this event by temporarily turn
off port power.
¾ DC Disconnect Event is the event the port cannot maintain its power signature (MPS). If the event
lasts for specified period of time (Event High Count Register), this will be considered an MPS error
event and the port power will be turned off. After the power is turned off the port start another detection
process after about 1.6 seconds.
¾ Overload (ICUT) Event is the event where port current is greater than ICUT. If the event lasts for
specified period of time (Event High Count Register), this will be considered an overload event.
When an overload condition is determined, the port power will be turned off. After the power is turned
off the port start another detection process after about 1.6 seconds.
¾ Short Circuit (ILIM) Event is the event where port current is greater than ILIM. This event should be
sampled by the power manager to determine if a short circuit event has occurred either during the
power up process or after the port being powered up. When a short circuit condition is determined, the
port power will be turned off. After the power is turned off the port start another detection process after
about 1.6 seconds.
A summary of power off conditions
Condition
Power Trunk< budget
Port temp > limit
Port temp > thermal
Port I > 1A
Port unplug UTP
Port I > Ilim
Port I > Icut
description
Power Trunk not enough power to
port used
Port temperature Event
Thermal Shutdown Event
Severe Short Circuit Event
DC Disconnect Event
short circuit event
Overload (ICUT) Event
Power off moment
Reference
Section
Power up sequence
5.6.1
IVT polling
Real-time monitor
Real-time monitor
Real-time monitor
Real-time monitor
Real-time monitor
5.6.4
5.7
5.7
5.7
5.7
5.7
Table 4 Port power off conditions
27 / 47
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IP804A-DS-R01
IP804A
Preliminary Datasheet
5.8
Port Status and Interrupt
Port state and power events are recorded in the registers. In manual mode and diagnostic mode,
these statuses can generate interrupts to host CPU for further processing.
¾ Port Power Event Handle Register @ 0x81 of Page 1
Bit #
7
R/W
R/W
6:0
R/W
Default
Description
1
Port Temperature Limit Event Handle.
0 = Do not turn off power when the event occurs.
1 = Turn off power when the event occurs.
0x1F Not used.
¾ Port 0~3 Power Event Register @ 0x70~0x73 of Page 1
Bit #
R/W
Default
7
W1C
0
6:5
W1C
0
4
W1C
0
3
W1C
0
2
W1C
0
1
W1C
0
0
W1C
0
Description
Port Temperature Limit Event.
In manual or diagnostic mode, write 1 to clear the bit. Writing 0 to this bit has
no effect.
Not used.
Port Thermal Shutdown Event.
In manual or diagnostic mode, write 1 to clear the bit. Writing 0 to this bit has
no effect.
Port Severe Short Circuit Event.
In manual or diagnostic mode, write 1 to clear the bit. Writing 0 to this bit has
no effect.
Port MPS Error (DC Disconnect) Event.
In manual or diagnostic mode, write 1 to clear the bit. Writing 0 to this bit has
no effect.
Port Short Circuit Limit (ILIM) Event.
In manual or diagnostic mode, write 1 to clear the bit. Writing 0 to this bit has
no effect.
Port Overload (ICUT) Event.
In manual or diagnostic mode, write 1 to clear the bit. Writing 0 to this bit has
no effect.
¾ Port 0~3 Power Event Mask Register @ 0x78~0x7B of Page 1
Bit #
R/W
Default
7
R/W
1
6:5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
Description
Port Temperature Limit Event Mask.
In manual mode or diagnostic mode, when mask bit is 0, no interrupt will be
issued for this event.
Not used.
Port Thermal Shutdown Event Mask.
Port Severe Short Circuit Event Mask.
Port MPS Error (DC Disconnect) Event Mask.
Port Short Circuit (ILIM) Event Mask.
Port Overload (ICUT) Event Mask.
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IP804A
Preliminary Datasheet
¾ Port Interrupt Register @ 0x80 of Page 1
Bit #
7:4
R/W
R
3
R
2
R
1
R
0
R
Default
Description
0
Not used.
Port 3 Interrupt.
0
Port 3 has interrupt.
Port 2 Interrupt.
0
Port 2 has interrupt.
Port 1 Interrupt.
0
Port 1 has interrupt.
Port 0 Interrupt.
0
Port 0 has interrupt.
¾ Port Power Status Register @ 0x82 of Page 1
Bit #
R/W
Default
3:0
R
0x00
Description
Power Status of the Ports.
0 = power off.
1 = power on.
Bit 0 corresponds to port 0, and bit 1 corresponds to port 1, etc.
¾ Port MPS Present Status Register @ 0x83 of Page 1
Bit #
R/W
Default
3:0
R
0x00
Description
MPS Status of the Ports.
0 = MPS not present.
1 = MPS present
Bit 0 corresponds to port 0, and bit 1 corresponds to port 1, etc.
¾ Port 0~3 Invalid Signature Counter Registers @ 0xB0~0xB3 of Page 1
Bit #
R/W
Default
3:0
R
0
Description
Invalid Signature Counter.
Number of times the port encounters an “Invalid Signature” in detection
process.
¾ Port 0~3 Power Denied Counter Registers @ 0xB8~0xBB of Page 1
Bit #
R/W
Default
3:0
R
0
Description
Power Denied Counter.
Number of times the port encounters a “Power Denied” in classification
process.
29 / 47
Copyright © 2017, IC Plus Corp.
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
5.9
Total Current Limit
When the IVT is polled, the port currents are summed up to get the total current consumption.
Total current limit Register can be specified and checked against the total current consumption. When
this total current limit is exceeded, the last port powered on would be turned off. The total current limit is
by default disabled and can be enabled by using the Total Current Limit Control Register. The total
current limit is specified in the PSE Available Current Registers.
¾ Total Current Limit Control Registers @ 0xC0 of Page 1
Bit #
R/W
Default
7
R/W
0
6:0
R
0
Description
Enable Total Current Limit
0= Disable
1= Enable
Reserved.
¾ PSE Available Current Registers @ 0xC1~0xC2 of Page 1
Bit #
7:6
5:0
Bit #
R/W
R
R/W
R/W
7:0
R/W
Default Description
0
Reserved.
0
PSE Available Current MSB
Default Description
PSE Available Current LSB
Total available current is the maximum current that the power supply can
0
provide to the ports.
The MSB 12 bits are the integer part and LSB 2 bits are the fractional part.
The unit is mA.
30 / 47
Copyright © 2017, IC Plus Corp.
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
5.10
LED Interface
In auto mode or manual mode, the LED interface can hook up with an IP403 (Serial-to-Parallel LED
driver) to display the port status. A port status LED is lit up when IP804A allocates power to the port
LED interface is enabled by pulling up LED_DAT pin with a resister. One IP804A can handle 4 LEDs
and up to three IP804As can share one IP403, where one IP804A serves as the master to drive
LED_CLK and the others are slaves. AD2 pin defines IP804A to be a master or a slave. The index
counter in all IP804As counts from 0 to 55 repeatly with LED_CLK after reset and the value of index
counter in all IP804A are identical. An IP804A will send out 4-bit LED information on LED_DAT when its
index counter reaches start index defined in start index register (0x0B). The detail is illustrated in the
LED start index register (0x0B) and figure 7.
If there is only one IP804A, user can replace IP403 with a 74LV164 to display port status for cost
saving. IP804A should be configured as a master.
LED Configuration Register @ 0x08 of Page 1
Bit #
R/W
7
R/W
6:5
R
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
Default Description
LED Interface Enable.
Enable the LED interface.
0/1
0 = disable, 1 = enable.
The default value of this bit is latched from LED_DAT pin.
0
Reserved.
LED Order.
The order in which 4-bit LED information is shifted out.
1
0 = Port 0, Port1, .… Port3.
1 = Port3, Port1, …. Port 0.
LED Active Level.
0
0 = light up a LED by driving logic low
1 = light up a LED by driving logic high
LED Initial Level.
1
The initial level of the LED. After reset, the LED will be driven to this initial
value.
LED Clock Rate.
Clock rate of the LED clock.
1
0 = LED clock is 512k Hz
1 = LED clock is 1M Hz
LED Master.
0 = slave. IP804A receives LED clock on LED_CLK pin.
0/1
1 = master. IP804A drives LED_CLK pin.
The default value of this bit is latched from AD2 pin.
31 / 47
Copyright © 2017, IC Plus Corp.
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
¾
LED Start Index Register @ 0x0B of Page 1
Bit #
7:6
5:0
R/W
R
R/W
Default Description
0
Reserved.
LED Start Index.
There are 3 default values can be selected with I2C address pin AD2 ~ AD0.
It is benefit to implement a multiple (no more than 3) IP804A LED display
without software programming.
AD2~AD0
default value of bit [5:0]
1,x,x (master)
0x30h (48d)
0,0,0(slave)
0x28h (40d)
0,0,1(slave)
0x20h (32d)
0,1,0(slave)
0x18h (24d)
0,1,1(slave)
0x10h (16d)
The following table demostrates the LED applications for 1~3 IP804A.
3 x IP804A
Master
Slave1
Slave2
Start index
0x30h
0x28h
0x20h
AD2~AD0
1,x,x
0,0,0
0,0,1
2 x IP804A
Master
Slave1
Start index
0x30h
0x28h
-AD2~AD0
1,x,x
0,0,0
-1 x IP804A
Master
Start index
0x30h
--AD2~AD0
1,x,x
--In manual mode, because AD0~AD2 is used for I2C address at the same
time, the default setting of LED start index may be incorrect. User has to
correct the LED start index by writing this register to make sure that IP804A
can send out LED status correctly.
There is an alternative for LED implementation if there is a MCU in the
system. The MCU reads the port status of IP804A through I2C and write the
LED information to IP403, where IP403 works as a GPIO controller not a
serial-to-parallel LED driver. Because LED is handled by MCU itself, the start
index in IP804A can be ignored.
32 / 47
Copyright © 2017, IC Plus Corp.
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
LED_DAT
…
…
…
…
LED Order = 0
P0 P1
…
P3
P0 P1
…
P3
P0 P1
…
P3
LED Order = 1 (default)
P3 P2
…
P0
P3 P2
…
P0
P3 P2
…
P0
Index conter
32
33
…
35
40
41
…
43
48 49
…
51
AD2, AD0
LED_CLK
01: 10 bit LED data sent out by
00 : 10 bit LED data sent out by
Slave2 with Start Index = 32
Slave1 with Start Index = 40
…
…
0
1
32
33
IP804A-3
(Slave2)
AD0
AD2
LED_CLK
34
35
…
36
40
41
42
IP804A-2
(Slave1)
LED_DAT
1x: 10 bit LED data sent out by
Master with Start Index = 48
LED_CLK
43
44
…
48
49
50
54
IP804A-1
(Master)
AD0
AD2
LED_CLK
LED_DAT
55
AD2
LED_DAT
LED_CLK
LED_DAT
IP403 (Serial to parallel mode, Mode[2:0]=100)
Q
1
……
Q …
3
3
Case 1:
LED Order = 0
Q
3
5
Q
3
6
Q
4
1
…
Q
4
3
Q
4
4
Q
4
9
…
Q
5
1
Port 3 ~ Port 0
power LED
Port 3~ Port 0
power LED
Port 3 ~ Port 0
power LED
Port 0 ~ Port 3
power LED
Port 0 ~ Port 3
power LED
Port 0 ~ Port 3
power LED
Slave2: Start Index = 32
Slave1: Start Index = 40
Master: Start Index = 48
Q
5
2
Case 2:
LED Order = 1
Figure 6
LED behavior and system diagram of multiple IP804A application
33 / 47
Copyright © 2017, IC Plus Corp.
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
6
IP804A Register descriptions
Table 5 Register Page 0 description
Page
Register Address
Register Name
#
and Attribute
2
I C Interface Registers
0
0x00
R/W
Register Page & I2C LSB Device Address (I2C Addr)
Analog Configure and Control Registers
0
0x01~0x24
R
Reserved (write prohibited)
0
0x25
R/W
AF/AT Mode
0
0x26
R
Reserved (write prohibited)
0
0x27
R/W
Power Down HV Analog Driver
0
0x28~0x5E
R
Reserved (write prohibited)
0
0x5F
R/W
Inrush Time
0
0x60~0x67
R
Reserved (write prohibited)
Detection Result
0
0x68
R
RDET for Port 0
0
0x69
R
RDET for Port 1
0
0x6A
R
RDET for Port 2
0
0x6B
R
RDET for Port 3
0
0x6C~0x77
R
Reserved (write prohibited)
Classification Currents
0
0x78
R
ICLASS for Port 0 MSB
0
0x79
R
ICLASS for Port 0 LSB
0
0x7A
R
ICLASS for Port 1 MSB
0
0x7B
R
ICLASS for Port 1 LSB
0
0x7C
R
ICLASS for Port 2 MSB
0
0x7D
R
ICLASS for Port 2 LSB
0
0x7E
R
ICLASS for Port 3 MSB
0
0x7F
R
ICLASS for Port 3 LSB
0
0x80~0x87
R
Reserved (write prohibited)
Classification Results (Detected PD Classes)
0
0x88
R
Detected PD Class Port 1 & 0
0
0x89
R
Detected PD Class Port 3 & 2
0
0x8A~0x8F
R
Reserved (write prohibited)
PD Requested Powers
0
0x90
R
PD 0 Requested Power
0
0x91
R
PD 1 Requested Power
0
0x92
R
PD 2 Requested Power
0
0x93
R
PD 3 Requested Power
0
0x94~0x9F
R
Reserved (write prohibited)
Port Currents
0
0xA0
R
Port 0 Current MSB
0
0xA1
R
Port 0 Current LSB
0
0xA2
R
Port 1 Current MSB
0
0xA3
R
Port 1 Current LSB
0
0xA4
R
Port 2 Current MSB
0
0xA5
R
Port 2 Current LSB
0
0xA6
R
Port 3 Current MSB
0
0xA7
R
Port 3 Current LSB
0
0xA8~0xAF
R
Reserved (write prohibited)
34 / 47
Copyright © 2017, IC Plus Corp.
Default Value
(x0xx,xPPP)
P: pin setting
(0000,0000)
(0000,0000)
(0111,1110)
(xxxx,xx00)
(xxxx,xx00)
(xxxx,xx00)
(xxxx,xx00)
(xx00,0000)
(0000,0000)
(xx00,0000)
(0000,0000)
(xx00,0000)
(0000,0000)
(xx00,0000)
(0000,0000)
(x101,x101)
(x101,x101)
(0000,0000)
(0000,0000)
(0000,0000)
(0000,0000)
(xxxx,0000)
(0000,0000)
(xxxx,0000)
(0000,0000)
(xxxx,0000)
(0000,0000)
(xxxx,0000)
(0000,0000)
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
Page
Register Address
#
and Attribute
Port Voltages
0
0xB0
R
0
0xB1
R
0
0xB2
R
0
0xB3
R
0
0xB4
R
0
0xB5
R
0
0xB6
R
0
0xB7
R
0
0xB8~0xBF
R
Port Temperatures
0
0xC0
R
0
0xC1
R
0
0xC2
R
0
0xC3
R
0
0xC4
R
0
0xC5
R
0
0xC6
R
0
0xC7
R
0
0xC8~0xDF
R
Supply Voltage
0
0xE0
R
0
0xE1
R
IVT Poll Control
0
0xE2
R/W
0
0xE3
R/W
0
0xE4 ~ 0xFF
R
Register Name
Port 0 Voltage MSB
Port 0 Voltage LSB
Port 1 Voltage MSB
Port 1 Voltage LSB
Port 2 Voltage MSB
Port 2 Voltage LSB
Port 3 Voltage MSB
Port 3 Voltage LSB
Reserved (write prohibited)
(xxxx,0000)
(0000,0000)
(xxxx,0000)
(0000,0000)
(xxxx,0000)
(0000,0000)
(xxxx,0000)
(0000,0000)
-
Port 0 Temp. MSB
Port 0 Temp. LSB
Port 1 Temp. MSB
Port 1 Temp. LSB
Port 2 Temp. MSB
Port 2 Temp. LSB
Port 3 Temp. MSB
Port 3 Temp. LSB
Reserved (write prohibited)
(xxx0,0000)
(0000,0000)
(xxx0,0000)
(0000,0000)
(xxx0,0000)
(0000,0000)
(xxx0,0000)
(0000,0000)
-
Supply Voltage MSB
Supply Voltage LSB
(xxxx,0000)
(0000,0000)
Force IVT Poll
IVT Poll Control
Reserved (write prohibited)
(0000,0000)
(x101,1110)
-
35 / 47
Copyright © 2017, IC Plus Corp.
Default Value
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
Table 6 Register Page 1 description
Page
Register Address
#
and Attribute
Register Page & I2C Interface Registers
1
0x00
R/W
Register Name
Default Value
(Binary)
Register Page & I2C LSB Device Address (I2C Addr)
(x0xx,xPPP)
P:pin setting
System Configuration & Control Registers
1
0x01
R/W
1
0x02
R/W
1
0x03~0x07
R
LED Control & Configuration
1
0x08
R/W
1
0x09~0x0A
R
1
0x0B
R/W
System Configuration
System Control
Reserved (write prohibited)
LED Control
Reserved (write prohibited)
LED Start Index
1
0x0C~0x0F
R
Reserved (write prohibited)
Power Configuration
1
0x10
R/W
Power Configuration Mode (PAM)
1
0x11
R
Reserved (write prohibited)
1
0x12
R/W
Class 0 Port Power Limit
1
0x13
R/W
Class 1 Port Power Limit
1
0x14
R/W
Class 2 Port Power Limit
1
0x15
R/W
Class 3 Port Power Limit
1
0x16
R/W
Class 4 Port Power Limit Type 1
1
0x17
R/W
Class 4 Port Power Limit Type 2
1
0x18~0x23
R
Reserved (write prohibited)
1
0x24
R/W
Port Temp. Limit MSB
1
0x25
R/W
Port Temp. Limit LSB
1
0x26~0x3F
R
Reserved (write prohibited)
Power Trunk Control & Configuration
1
0x40
R/W
Trunk 0 Power Limit MSB
1
0x41
R/W
Trunk 0 Power Limit LSB
1
0x42
R/W
Trunk 1 Power Limit MSB
1
0x43
R/W
Trunk 1 Power Limit LSB
1
0x44~0x68
R
Reserved (write prohibited)
1
0x69
R/W
Trunk Select
1
0x6A~0x6F
R
Reserved (write prohibited)
Port Status
1
0x70
R/W1C Port 0 Status
1
0x71
R/W1C Port 1 Status
1
0x72
R/W1C Port 2 Status
1
0x73
R/W1C Port 3 Status
1
0x74~0x77
R
Reserved (write prohibited)
1
0x78
R/W
Port 0 Status Mask
1
0x79
R/W
Port 1 Status Mask
1
0x7A
R/W
Port 2 Status Mask
1
0x7B
R/W
Port 3 Status Mask
1
0x7C~0x7F
R
Reserved (write prohibited)
1
0x80
R
Port Interrupt Status
36 / 47
Copyright © 2017, IC Plus Corp.
(PPx0,xxxx)
P:pin setting
(xxxx,xxx0)
(Pxx1,011P)
P:PinSetting
(PPPP,PPPP)
P:PinSetting
(0000,1000)
(0011,1110)
(0001,0000)
(0001,1100)
(0011,1110)
(0011,1110)
(0111,1000)
(xxx0,1001)
(0110,0000)
(xxxx,x000)
(1111,1010)
(xxxx,x000)
(1111,1010)
(xxxx,xx00)
(0000,0000)
(0000,0000)
(0000,0000)
(0000,0000)
(1111,1111)
(1111,1111)
(1111,1111)
(1111,1111)
(0000,0000)
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
Page
Register Address
#
and Attribute
1
0x81
R/W
1
0x82
R
1
0x83
R
1
0x84~0x8F
R
State Machine Control & Status
1
0x90
R/W
1
0x91
R/W
1
0x92
R/W
1
0x93
R/W
1
0x94~0x97
R
1
0x98
R/W
1
0x99
R/W
1
0x9A
R/W
1
0x9B
R/W
1
0x9C~0x9F
R
1
0xA0
R/W
1
0xA1
R
1
0xA2
R/W
1
0XA3~0xAF
R
Counter Registers
1
0xB0
R
1
0xB1
R
1
0xB2
R
1
0xB3
R
1
0XB3~0xB7
R
1
0xB8
R
1
0xB9
R
1
0xBA
R
1
0xBB
R
1
0xBC~0xFF
R
Total Current Limit Registers
1
0xC0
R/W
1
0xC1
R/W
1
0xC2
R/W
Register Name
Power Event Handle
Port Power Status
MPS Present Status
Reserved (write prohibited)
Port 0 State Machine State
Port 1 State Machine State
Port 2 State Machine State
Port 3 State Machine State
Reserved (write prohibited)
Port 0 Power Control
Port 1 Power Control
Port 2 Power Control
Port 3 Power Control
Reserved (write prohibited)
Port 3-0 Classification Event Number
Reserved (write prohibited)
PSE Skip Event 2
Reserved (write prohibited)
(00x0,0000)
(00x0,0000)
(00x0,0000)
(00x0,0000)
(xxxx,xx00)
(xxxx,xx00)
(xxxx,xx00)
(xxxx,xx00)
(1010,1010)
(1111,1111)
-
Port 0 Invalid Signature Count
Port 1 Invalid Signature Count
Port 2 Invalid Signature Count
Port 3 Invalid Signature Count
Reserved (write prohibited)
Port 0 Power Denied Count
Port 1 Power Denied Count
Port 2 Power Denied Count
Port 3 Power Denied Count
Reserved (write prohibited)
(0000,0000)
(0000,0000)
(0000,0000)
(0000,0000)
(0000,0000)
(0000,0000)
(0000,0000)
(0000,0000)
-
Total Current Limit Control
PSE Available Current MSB
PSE Available Current LSB
(0xxx,xxxx)
(xx00,0000)
(0000,0000)
37 / 47
Copyright © 2017, IC Plus Corp.
Default Value
(Binary)
(111x,xxxx)
(0000,0000)
(0000,0000)
-
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
7
Electrical Characteristics
7.1
Absolute Maximum Ratings
(Note: Beyond these ratings can cause damage to the device)
Table 7 Electrical Characteristics
Parameter
Supply Voltage
PortN0~PortN3
RS0~RS3
V5
All other Pins
RGND, AGND
Maximum Junction
Temperature
Storage Temperature
Range
Lead Temperature
ESD at all Pins
7.2
Description
V54 – AGND
PortNn– AGND @n=0~3
RSn – AGND @n=0~3
V5 – AGND
All other Pin – (AGND, or DGND)
DGND – AGND
Typ.
-65
Soldering 10 seconds
HBM
Max.
+80
+80
+5.5
+5.5
+3.6
+0.3
Unit
V
V
V
V
V
V
150
℃
150
℃
300
℃
KV
Max.
+85
57
57
Units
℃
V
V
±2
Operating Conditions
Parameter Description
Ta
Ambient temperature
V54
V54 – AGND @ AF
V54 – AGND @ AT
7.3
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Min.
-40
45
51
Typ.
48
54
Electrical Characteristics for Analog I/O Pins
Parameter Description
Conditions
Min.
45V~57V @AF
V54
51V~57V @AT
All ports on @w/o peripheral load
I54
current & port load current
External Capacitance=4.7uF
V3P3
V3P3 voltage
@short V3P3 and DV3P3
V3P3 providing to peripheral device
Iout_v3p3 EnB_Reg=low
@short V3P3 and DV3P3
External 3.3V provides to V3P3 @short
Iin_v3p3
EnB_Reg=high
V3P3 and DV3P3
V5
Internal use only External Capacitance=4.7uF
V2P5
Internal use only External Capacitance=1uF
Increasing V54 – AGND
V54 under
V54_UVL
voltage lockout
Decreasing V54 – AGND
V54 overvoltage Increasing V54 – AGND
V54_OVL
lockout
Decreasing V54 – AGND
V3P3 under
Increasing V3P3 – AGND
V3P3_UVL
voltage lockout
V3P3 – AGND @short V3P3 and DV3P3
V3P3 overvoltage Decreasing V3P3 – AGND
V3P3_OVL
lockout
V3P3 – AGND @short V3P3 and DV3P3
Power Supply
voltage
V54 operating
current
38 / 47
Copyright © 2017, IC Plus Corp.
Typ.
Max.
Unit
57
57
V
V
12
18
mA
3.30
3.46
V
6
mA
45
51
3.10
6
5
2.37
mA
5.25
2.5
30
27
63
60
5.5
2.62
V
V
V
V
V
V
2.8
V
1.9.
V
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
7.4
IEEE802.3 AF/AT Mode Parameters
Table 8 IEEE802.3 AF/AT Mode Parameters
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Tovlrec
Auto-recovery time
From overload shutdown to next detection
1.6
s
Tudlrec
Auto-recovery time
From Imin_off shutdown to next detection
1.6
s
Tbackoff
Back-off time
Midspan mode detection back-off time
2.5
s
Iinrush
Inrush current
For t=50ms Cload=180uF max.
400
Iport
Port output current
Continuous port output current after AF
startup period
AT
Pport
Port output power
425
450
mA
10
375
mA
10
640
mA
Continuous port output power after startup
period @ AF
0.57
15.4
W
Continuous port output power after startup
period @ AT
0.57
30
W
5
mA
Imin_off
Port off
Must disconnect for t greater than Tmpdo
0
Imin_onoff
Port off or on
May or may not disconnect for greater than
Tmpdo
5
7.5
10
mA
Tmpdo
PD Maintenance
power signature
dropout time limit
AF/AT
300
350
400
ms
Tmps
PD Maintenance
Port current pulse width to reset
power signature time
disconnect timer
for validity
Icut
Over load current
(default)
AF
350
375
400
mA
AT
600
640
664
mA
Tcut
Over load time
Iport > Icut, AF/AT
50
62.5
75
ms
Ilim
Current limit
AF
400
425
450
mA
AT
800
860
920
mA
Tlim
Current limit time
Iport = Ilim, AF/AT
50
62.5
75
ms
Toff
Turn off time
From VportN to V54-2.8V
500
ms
Ron
Port on resistance
Iport≦640mA, & Ta=25℃
Ioff_port
PortN leakage
current
V54=54V , Ta=25℃, Port off
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Copyright © 2017, IC Plus Corp.
49
ms
0.3
Ω
10
uA
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
Typical: PortN0~3 (Detection, 2-event Classification, Port On, Port Off) sequence
Time specification show in table 8
Tpon
Tdet
0V
-4V
-8V
-9V
Time
Port Off
Port Off
-Vdet1
-Vdet2
-Vdet2
-Vdet1
-Vmark
-18V
-54V
-Vclass
Port On
(PortNn-V54, n=0~3)
Figure 7
Typical Power up Sequence
IEEE802.3 AF/AT Mode Parameters: (continued)
Parameter Description
Detection
Vdet1
Detection voltage
@first point
Detection voltage
@second point
Idetlim
Detection current limit
Time to complete
Tdet
detection of a PD
Detection port open
Vdet_oc
circuit voltage
Minimum Rdet
Rdet_min
detection resistance
Maximum Rdet
Rdet_max
detection resistance
Rdet_open Open circuit resistance
Valid Cdet detection
Cdet_good
capacitance
Invalid Cdet detection
Cdet_bad
capacitance
Vdet2
Conditions
V54 – PortNn, (n=0~3)
@Rdet=25ΚΩ
V54 – PortNn, (n=0~3)
@Rdet=25KΩ
V54=PortNn, (n=0~3)
Typ.
Max.
Unit
2.8
8
10
V
2.8
4
10
V
5
mA
500
ms
30
V
AF/AT
326
V54 – PortNn, (n=0~3)
@Port open circuit
@Cdet=0.15uF
15
17
19
KΩ
@Cdet=0.15uF
26.5
30
33
KΩ
Rdet @Cdet=0.15uF
500
@Rdet=25KΩ
0
@Rdet=25KΩ
10
40 / 47
Copyright © 2017, IC Plus Corp.
Min.
KΩ
0.15
uF
uF
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
Parameter Description
Classification
Conditions
Min.
Typ.
Max.
Unit
15.5
18.0
20.5
V
Vclass
Classification voltage
V54 – PortNn, (n=0~3)
@0mA≦Iclass≦50mA
Iclasslim
Classification current
limitation
V54=PortNn, (n=0~3)
51
100
mA
Iclass
Classification current
Class 0
Class 1
Class 2
Class 3
Class 4
Invalid class
0
8
16
25
35
51
5
13
21
31
45
mA
mA
mA
mA
mA
Vmark
Mark voltage
V54 – PortNn, (n=0~3)
@0mA≦Imark≦10mA
7
10
V
Imarklim
Mark current
limitation
V54=PortNn, (n=0~3)
5
100
mA
Tme1
Tme2
Classification event
time
Mark event 1 time
Mark event 2 time
Tpon
Power turn on time
Tcle
Width for classification event 1 or
event 2
Width for mark event 1
Width for mark event 2
From end of valid detect to
application of power to port
9
6
12
30
ms
6
16
9
22
12
ms
ms
55
400
ms
Temperature Sensor
Tsd
Thermal shutdown
Thy
Thermal shutdown
hysteresis
Internal temperature for thermal
shutdown
Internal temperature for release
thermal shutdown
41 / 47
Copyright © 2017, IC Plus Corp.
150
℃
129
℃
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
7.5
Digital Electrical Characteristics
Table 9 Digital Electrical Characteristics
Parameter Description
2
I C & EEPROM interface
VIL
Input low voltage
VIH
VOL
VOL
Tscl
Tee
TSDAO
TSDAOH
TSDAI
TSDAIH
Others
VIL
VIH
Conditions
Min.
Max.
Unit
0.8
V
2
SCL/EE_CLK,SDAI/EE_DAT@ I C mode,
SCAN0, SCAN1
2
Input high voltage
SCL/EE_CLK,SDAI/EE_DAT@I C mode,
SCAN0, SCAN1
Open drain output
SCL/EE_CLK,SDAI/EE_DAT@auto
low voltage
mode
@ Isink =5mA
Open drain output
SDAO,INTB,LED_CLK,LED_DAT
low voltage
@ Isink =5mA
2
SCL/EE_CLK input
I C input clock
SCL/EE_CLK output Output clock for EEPROM
SDAO output Delay
SDAO output Hold
SDAI Input Setup
SDAI Input Hold
350
125
50
50
Input low voltage
Input high voltage
2.2
AD0~AD2
AD0~AD2
42 / 47
Copyright © 2017, IC Plus Corp.
Typ.
2.2
V
0.7
V
0.7
V
1
1
MHz
MHz
ns
ns
ns
ns
0.8
V
V
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
7.6
AC Timing
7.6.1 Power On Sequence and Reset Timing
Description
Min.
V54_Power on time@ V54 rising time from 0v to 57v
V54 stable to RstN release
Reset to System up time
Typ.
Max.
Unit
100
-
ms
ms
ms
200
150
V54_Power on time
V54
RstN
V54 stable to RstN release
I2C
Reset to System up time
2
I C Access
Figure 8
Power on Sequence and Reset Timing Diagram
43 / 47
Copyright © 2017, IC Plus Corp.
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
7.6.2 EEPROM Timing
7.6.2.1 Data read cycle
Symbol
Description
TSCL
TsSCL
ThSCL
Receive clock period
SDA to SCL setup time
SDA to SCL hold time
Min.
Typ.
Max.
Unit
2
0.5
20480
-
-
ns
ns
ns
Min.
Typ.
Max.
Unit
-
20480
-
5200
ns
ns
T SCL
SCL
T hS C L
SDA
T sSCL
R ead data cycle
Figure 9 EEPROM Read Cycle Timing Diagram
7.6.2.2 Command cycle
Symbol
Description
TSCL
TdSCL
Transmit clock period
SCL falling edge to SDA
T SCL
SCL
T dSCL
SDA
Comand cycle
Figure 10 EEPROM Command Cycle Timing Diagram
44 / 47
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May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
7.6.3 I2C Timing
7.6.3.1 Data read cycle
Symbol
Description
2
TSCL
TSDAO
TSDAOH
I C clock period
SDAO output delay
SDAO output hold time of the last data bit
Min.
Typ.
Max.
Unit
1000
125
-
350
-
ns
ns
ns
Min.
Typ.
Max.
Unit
1000
50
50
-
-
ns
ns
ns
T SCL
SCL
T SDAOH
T SDAO
SDAO
R ead data cycle
Figure 11 I2C Read Cycle Timing Diagram
7.6.3.2 Command cycle
Symbol
Description
I2C clock period
SDAI setup time
SDAI hold time
TSCL
TSDAI
TSDAIH
T SCL
SCL
T SDAI
T SDAIH
SDAI
Comand cycle
Figure 12 I2C Command Cycle Timing Diagram
7.7
Thermal Data
θJA
θJC
ΨJT
Conditions
21
9.6
0.47
4 Layer PCB
45 / 47
Copyright © 2017, IC Plus Corp.
Units
o
C/W
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
8
Order Information
Table 10 Order Information
Part No.
IP804A
Package
48-Lead MQFN
Operating Temperature
-40°C to 85°C
46 / 47
Copyright © 2017, IC Plus Corp.
Notice
May 2, 2017
IP804A-DS-R01
IP804A
Preliminary Datasheet
9
Package Detail
9.1
48 MQFN Outline Dimensions (in mm)
Figure 13 Package Outline Dimensions
IC Plus Corp.
Headquarters
10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2,
Hsin-Chu City, Taiwan 300, R.O.C.
TEL: 886-3-575-0275
FAX: 886-3-575-0475
Website: www.icplus.com.tw
Sales Office
4F, No. 106, Hsin-Tai-Wu Road, Sec.1,
Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C.
TEL: 886-2-2696-1669
FAX: 886-2-2696-2220
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May 2, 2017
IP804A-DS-R01
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