nRF52832 Product Specification v1.8
Key features
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2.4 GHz transceiver
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-96 dBm sensitivity in Bluetooth® low energy mode
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Supported data rates: 1 Mbps, 2 Mbps Bluetooth® low energy mode
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-20 to +4 dBm TX power, configurable in 4 dB steps
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On-chip balun (single-ended RF)
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5.3 mA peak current in TX (0 dBm)
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5.4 mA peak current in RX
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RSSI (1 dB resolution)
Arm® Cortex®-M4 32-bit processor with FPU, 64 MHz
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Applications
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Internet of Things (IoT)
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Home automation
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Sensor networks
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Building automation
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Industrial
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Retail
Personal area networks
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215 EEMBC CoreMark® score running from flash memory
58 μA/MHz running from flash memory
51.6 μA/MHz running from RAM
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Data watchpoint and trace (DWT), embedded trace macrocell (ETM), and
instrumentation trace macrocell (ITM)
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Serial wire debug (SWD)
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Trace port
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Flexible power management
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1.7 V–3.6 V supply voltage range
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Fully automatic LDO and DC/DC regulator system
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Fast wake-up using 64 MHz internal oscillator
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0.3 μA at 3 V in System OFF mode
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0.7 μA at 3 V in System OFF mode with full 64 kB RAM retention
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1.9 μA at 3 V in System ON mode, no RAM retention, wake on RTC
Memory
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Health/fitness sensor and monitor devices
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Medical devices
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Key fobs and wrist watches
Interactive entertainment devices
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Remote controls
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Gaming controllers
Beacons
A4WP wireless chargers and devices
Remote control toys
Computer peripherals and I/O devices
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Mouse
Keyboard
Multi-touch trackpad
Gaming
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512 kB flash/64 kB RAM
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256 kB flash/32 kB RAM
Nordic SoftDevice ready
Support for concurrent multi-protocol
Type 2 near field communication (NFC-A) tag with wakeup-on-field and touchto-pair capabilities
12-bit, 200 ksps ADC - 8 configurable channels with programmable gain
64 level comparator
15 level low power comparator with wakeup from System OFF mode
Temperature sensor
32 general purpose I/O pins
3x 4-channel pulse width modulator (PWM) unit with EasyDMA
Digital microphone interface (PDM)
5x 32-bit timer with counter mode
Up to 3x SPI master/slave with EasyDMA
Up to 2x I2C compatible 2-wire master/slave
I2S with EasyDMA
UART (CTS/RTS) with EasyDMA
Programmable peripheral interconnect (PPI)
Quadrature decoder (QDEC)
AES HW encryption with EasyDMA
Autonomous peripheral operation without CPU intervention using PPI and
EasyDMA
3x real-time counter (RTC)
Single crystal operation
Package variants
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QFN48 package, 6 × 6 mm
WLCSP package, 3.0 × 3.2 mm
All rights reserved.
Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
2021-11-01
Contents
Contents
1 Revision history................................................................................... 9
2 About this document............................................................................................ 11
2.1
2.2
2.3
2.4
Document naming and status............................................................................................... 11
Peripheral naming and abbreviations................................................................................... 11
Register tables...................................................................................................................... 11
Registers............................................................................................................................... 12
3 Block diagram........................................................................................................13
4 Pin assignments.................................................................................................... 14
4.1 QFN48 pin assignments....................................................................................................... 14
4.2 WLCSP ball assignments..................................................................................................... 16
4.3 GPIO usage restrictions........................................................................................................18
5 Absolute maximum ratings.................................................................................. 20
6 Recommended operating conditions.................................................................. 21
6.1 WLCSP light sensitivity......................................................................................................... 21
7 CPU......................................................................................................................... 22
7.1 Floating point interrupt.......................................................................................................... 22
7.2 Electrical specification........................................................................................................... 22
7.3 CPU and support module configuration................................................................................23
8 Memory................................................................................................................... 24
8.1
8.2
8.3
8.4
RAM - Random access memory...........................................................................................24
Flash - Non-volatile memory.................................................................................................25
Memory map......................................................................................................................... 25
Instantiation........................................................................................................................... 25
9 AHB multilayer.......................................................................................................27
9.1 AHB multilayer priorities........................................................................................................27
10 EasyDMA.............................................................................................................. 28
10.1 EasyDMA array list............................................................................................................. 29
11 NVMC — Non-volatile memory controller......................................................... 30
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Writing to Flash...................................................................................................................30
Erasing a page in Flash..................................................................................................... 30
Writing to user information configuration registers (UICR)................................................. 30
Erasing user information configuration registers (UICR).................................................... 30
Erase all.............................................................................................................................. 31
Cache.................................................................................................................................. 31
Registers............................................................................................................................. 31
Electrical specification......................................................................................................... 34
12 BPROT — Block protection................................................................................35
12.1 Registers............................................................................................................................. 35
13 FICR — Factory information configuration registers.......................................44
13.1 Registers............................................................................................................................. 44
14 UICR — User information configuration registers........................................... 55
14.1 Registers............................................................................................................................. 55
15 Peripheral interface............................................................................................. 69
15.1
15.2
15.3
15.4
15.5
15.6
Peripheral ID....................................................................................................................... 69
Peripherals with shared ID..................................................................................................69
Peripheral registers............................................................................................................. 70
Bit set and clear..................................................................................................................70
Tasks................................................................................................................................... 70
Events..................................................................................................................................71
Page 2
Contents
15.7 Shortcuts............................................................................................................................. 71
15.8 Interrupts............................................................................................................................. 71
16 Debug and trace.................................................................................................. 73
16.1
16.2
16.3
16.4
16.5
16.6
DAP - Debug access port...................................................................................................73
Access port protection........................................................................................................ 73
CTRL-AP - Control access port.......................................................................................... 76
Debug Interface mode........................................................................................................ 77
Real-time debug.................................................................................................................. 78
Trace................................................................................................................................... 78
17 Power and clock management...........................................................................79
17.1 Current consumption scenarios.......................................................................................... 79
18 POWER — Power supply....................................................................................81
18.1 Regulators........................................................................................................................... 81
18.2 System OFF mode..............................................................................................................82
18.3 System ON mode............................................................................................................... 83
18.4 Power supply supervisor.....................................................................................................83
18.5 RAM sections...................................................................................................................... 85
18.6 Reset................................................................................................................................... 85
18.7 Retained registers............................................................................................................... 86
18.8 Reset behavior.................................................................................................................... 86
18.9 Registers............................................................................................................................. 86
18.10 Electrical specification..................................................................................................... 102
19 CLOCK — Clock control...................................................................................104
19.1
19.2
19.3
19.4
HFCLK clock controller..................................................................................................... 104
LFCLK clock controller......................................................................................................106
Registers........................................................................................................................... 108
Electrical specification....................................................................................................... 112
20 GPIO — General purpose input/output........................................................... 114
20.1
20.2
20.3
20.4
Pin configuration............................................................................................................... 114
GPIO located near the RADIO......................................................................................... 116
Registers........................................................................................................................... 116
Electrical specification....................................................................................................... 157
21 GPIOTE — GPIO tasks and events..................................................................161
21.1
21.2
21.3
21.4
21.5
Pin events and tasks........................................................................................................ 161
Port event..........................................................................................................................162
Tasks and events pin configuration.................................................................................. 162
Registers........................................................................................................................... 162
Electrical specification....................................................................................................... 171
22 PPI — Programmable peripheral interconnect............................................... 172
22.1 Pre-programmed channels................................................................................................173
22.2 Registers........................................................................................................................... 173
23 RADIO — 2.4 GHz Radio.................................................................................. 209
23.1 EasyDMA...........................................................................................................................209
23.2 Packet configuration..........................................................................................................210
23.3 Maximum packet length.................................................................................................... 211
23.4 Address configuration........................................................................................................211
23.5 Data whitening.................................................................................................................. 211
23.6 CRC...................................................................................................................................212
23.7 Radio states...................................................................................................................... 213
23.8 Transmit sequence............................................................................................................213
23.9 Receive sequence.............................................................................................................215
23.10 Received Signal Strength Indicator (RSSI).....................................................................216
23.11 Interframe spacing...........................................................................................................216
23.12 Device address match.................................................................................................... 217
23.13 Bit counter....................................................................................................................... 217
23.14 Registers......................................................................................................................... 218
23.15 Electrical specification..................................................................................................... 234
Page 3
Contents
24 TIMER — Timer/counter....................................................................................238
24.1
24.2
24.3
24.4
24.5
24.6
Capture..............................................................................................................................239
Compare............................................................................................................................239
Task delays....................................................................................................................... 239
Task priority.......................................................................................................................239
Registers........................................................................................................................... 239
Electrical specification....................................................................................................... 245
25 RTC — Real-time counter.................................................................................246
25.1 Clock source..................................................................................................................... 246
25.2 Resolution versus overflow and the PRESCALER........................................................... 246
25.3 COUNTER register............................................................................................................247
25.4 Overflow features.............................................................................................................. 247
25.5 TICK event........................................................................................................................ 247
25.6 Event control feature.........................................................................................................248
25.7 Compare feature............................................................................................................... 248
25.8 TASK and EVENT jitter/delay........................................................................................... 250
25.9 Reading the COUNTER register.......................................................................................252
25.10 Registers......................................................................................................................... 252
25.11 Electrical specification..................................................................................................... 258
26 RNG — Random number generator................................................................ 259
26.1
26.2
26.3
26.4
Bias correction.................................................................................................................. 259
Speed................................................................................................................................ 259
Registers........................................................................................................................... 259
Electrical specification....................................................................................................... 261
27 TEMP — Temperature sensor.......................................................................... 262
27.1 Registers........................................................................................................................... 262
27.2 Electrical specification....................................................................................................... 267
28 ECB — AES electronic codebook mode encryption...................................... 268
28.1
28.2
28.3
28.4
28.5
Shared resources.............................................................................................................. 268
EasyDMA...........................................................................................................................268
ECB data structure............................................................................................................268
Registers........................................................................................................................... 269
Electrical specification....................................................................................................... 270
29 CCM — AES CCM mode encryption................................................................271
29.1
29.2
29.3
29.4
29.5
29.6
29.7
29.8
29.9
Shared resources.............................................................................................................. 272
Encryption..........................................................................................................................272
Decryption......................................................................................................................... 272
AES CCM and RADIO concurrent operation.................................................................... 273
Encrypting packets on-the-fly in radio transmit mode.......................................................273
Decrypting packets on-the-fly in radio receive mode........................................................274
CCM data structure...........................................................................................................275
EasyDMA and ERROR event........................................................................................... 276
Registers........................................................................................................................... 276
30 AAR — Accelerated address resolver.............................................................280
30.1 Shared resources.............................................................................................................. 280
30.2 EasyDMA...........................................................................................................................280
30.3 Resolving a resolvable address........................................................................................280
30.4 Use case example for chaining RADIO packet reception with address resolution using
AAR.......................................................................................................................................281
30.5 IRK data structure............................................................................................................. 281
30.6 Registers........................................................................................................................... 282
30.7 Electrical specification....................................................................................................... 284
31 SPIM — Serial peripheral interface master with EasyDMA............................285
31.1
31.2
31.3
31.4
Shared resources.............................................................................................................. 285
EasyDMA...........................................................................................................................286
SPI master transaction sequence..................................................................................... 287
Low power.........................................................................................................................288
Page 4
Contents
31.5 Master mode pin configuration......................................................................................... 288
31.6 Registers........................................................................................................................... 289
31.7 Electrical specification....................................................................................................... 294
32 SPIS — Serial peripheral interface slave with EasyDMA...............................296
32.1
32.2
32.3
32.4
32.5
32.6
Shared resources.............................................................................................................. 296
EasyDMA...........................................................................................................................296
SPI slave operation...........................................................................................................297
Pin configuration............................................................................................................... 298
Registers........................................................................................................................... 299
Electrical specification....................................................................................................... 307
2
33 TWIM — I C compatible two-wire interface master with EasyDMA...............309
33.1
33.2
33.3
33.4
33.5
33.6
33.7
33.8
33.9
Shared resources.............................................................................................................. 310
EasyDMA...........................................................................................................................310
Master write sequence......................................................................................................311
Master read sequence...................................................................................................... 312
Master repeated start sequence....................................................................................... 313
Low power.........................................................................................................................314
Master mode pin configuration......................................................................................... 314
Registers........................................................................................................................... 314
Electrical specification....................................................................................................... 321
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34 TWIS — I C compatible two-wire interface slave with EasyDMA.................. 323
34.1 Shared resources.............................................................................................................. 325
34.2 EasyDMA...........................................................................................................................325
34.3 TWI slave responding to a read command.......................................................................325
34.4 TWI slave responding to a write command...................................................................... 326
34.5 Master repeated start sequence....................................................................................... 327
34.6 Terminating an ongoing TWI transaction..........................................................................328
34.7 Low power.........................................................................................................................328
34.8 Slave mode pin configuration........................................................................................... 328
34.9 Registers........................................................................................................................... 329
34.10 Electrical specification..................................................................................................... 335
35 UARTE — Universal asynchronous receiver/transmitter with EasyDMA.... 337
35.1 Shared resources.............................................................................................................. 337
35.2 EasyDMA...........................................................................................................................337
35.3 Transmission..................................................................................................................... 338
35.4 Reception.......................................................................................................................... 338
35.5 Error conditions................................................................................................................. 340
35.6 Using the UARTE without flow control............................................................................. 340
35.7 Parity configuration............................................................................................................340
35.8 Low power.........................................................................................................................340
35.9 Pin configuration............................................................................................................... 341
35.10 Registers......................................................................................................................... 341
35.11 Electrical specification..................................................................................................... 349
36 QDEC — Quadrature decoder.......................................................................... 351
36.1
36.2
36.3
36.4
36.5
36.6
36.7
36.8
Sampling and decoding.................................................................................................... 351
LED output........................................................................................................................ 352
Debounce filters................................................................................................................ 352
Accumulators.....................................................................................................................353
Output/input pins............................................................................................................... 353
Pin configuration............................................................................................................... 353
Registers........................................................................................................................... 354
Electrical specification....................................................................................................... 360
37 SAADC — Successive approximation analog-to-digital converter............... 361
37.1
37.2
37.3
37.4
Shared resources.............................................................................................................. 361
Overview............................................................................................................................361
Digital output..................................................................................................................... 362
Analog inputs and channels..............................................................................................363
Page 5
Contents
37.5 Operation modes...............................................................................................................363
37.6 EasyDMA...........................................................................................................................365
37.7 Resistor ladder.................................................................................................................. 366
37.8 Reference.......................................................................................................................... 367
37.9 Acquisition time................................................................................................................. 367
37.10 Limits event monitoring................................................................................................... 368
37.11 Registers......................................................................................................................... 369
37.12 Electrical specification..................................................................................................... 393
37.13 Performance factors........................................................................................................ 395
38 COMP — Comparator........................................................................................396
38.1
38.2
38.3
38.4
Differential mode............................................................................................................... 397
Single-ended mode........................................................................................................... 398
Registers........................................................................................................................... 400
Electrical specification....................................................................................................... 405
39 LPCOMP — Low power comparator................................................................406
39.1
39.2
39.3
39.4
Shared resources.............................................................................................................. 407
Pin configuration............................................................................................................... 407
Registers........................................................................................................................... 408
Electrical specification....................................................................................................... 412
40 WDT — Watchdog timer................................................................................... 413
40.1
40.2
40.3
40.4
40.5
Reload criteria................................................................................................................... 413
Temporarily pausing the watchdog................................................................................... 413
Watchdog reset................................................................................................................. 413
Registers........................................................................................................................... 414
Electrical specification....................................................................................................... 418
41 SWI — Software interrupts...............................................................................419
41.1 Registers........................................................................................................................... 419
42 NFCT — Near field communication tag...........................................................420
42.1 Overview............................................................................................................................420
42.2 Pin configuration............................................................................................................... 422
42.3 EasyDMA...........................................................................................................................422
42.4 Collision resolution............................................................................................................ 423
42.5 Frame timing controller..................................................................................................... 424
42.6 Frame assembler.............................................................................................................. 425
42.7 Frame disassembler..........................................................................................................426
42.8 Antenna interface.............................................................................................................. 427
42.9 NFCT antenna recommendations..................................................................................... 427
42.10 Battery protection............................................................................................................ 427
42.11 References...................................................................................................................... 428
42.12 Registers......................................................................................................................... 428
42.13 Electrical specification..................................................................................................... 439
43 PDM — Pulse density modulation interface................................................... 440
2
43.1
43.2
43.3
43.4
43.5
43.6
43.7
43.8
Master clock generator..................................................................................................... 440
Module operation.............................................................................................................. 440
Decimation filter................................................................................................................ 441
EasyDMA...........................................................................................................................441
Hardware example............................................................................................................ 442
Pin configuration............................................................................................................... 442
Registers........................................................................................................................... 443
Electrical specification....................................................................................................... 447
44 I S — Inter-IC sound interface......................................................................... 449
44.1
44.2
44.3
44.4
44.5
44.6
Mode..................................................................................................................................449
Transmitting and receiving................................................................................................ 449
Left right clock (LRCK)..................................................................................................... 450
Serial clock (SCK).............................................................................................................450
Master clock (MCK).......................................................................................................... 451
Width, alignment and format.............................................................................................451
Page 6
Contents
44.7 EasyDMA...........................................................................................................................453
44.8 Module operation.............................................................................................................. 455
44.9 Pin configuration............................................................................................................... 456
44.10 Registers......................................................................................................................... 457
44.11 Electrical specification..................................................................................................... 464
45 MWU — Memory watch unit.............................................................................465
45.1 Registers........................................................................................................................... 465
46 EGU — Event generator unit............................................................................492
46.1 Registers........................................................................................................................... 492
46.2 Electrical specification....................................................................................................... 498
47 PWM — Pulse width modulation..................................................................... 499
47.1
47.2
47.3
47.4
47.5
47.6
Wave counter.................................................................................................................... 499
Decoder with EasyDMA.................................................................................................... 502
Limitations......................................................................................................................... 507
Pin configuration............................................................................................................... 507
Registers........................................................................................................................... 508
Electrical specification....................................................................................................... 516
48 SPI — Serial peripheral interface master........................................................517
48.1 Functional description....................................................................................................... 517
48.2 Registers........................................................................................................................... 520
48.3 Electrical specification....................................................................................................... 523
2
49 TWI — I C compatible two-wire interface....................................................... 525
49.1
49.2
49.3
49.4
49.5
49.6
49.7
49.8
49.9
Functional description....................................................................................................... 525
Master mode pin configuration......................................................................................... 525
Shared resources.............................................................................................................. 526
Master write sequence......................................................................................................526
Master read sequence...................................................................................................... 527
Master repeated start sequence....................................................................................... 528
Low power.........................................................................................................................529
Registers........................................................................................................................... 529
Electrical specification....................................................................................................... 533
50 UART — Universal asynchronous receiver/transmitter................................. 535
50.1 Functional description....................................................................................................... 535
50.2 Pin configuration............................................................................................................... 535
50.3 Shared resources.............................................................................................................. 536
50.4 Transmission..................................................................................................................... 536
50.5 Reception.......................................................................................................................... 536
50.6 Suspending the UART...................................................................................................... 537
50.7 Error conditions................................................................................................................. 537
50.8 Using the UART without flow control................................................................................538
50.9 Parity configuration............................................................................................................538
50.10 Registers......................................................................................................................... 538
50.11 Electrical specification..................................................................................................... 543
51 Mechanical specifications................................................................................ 544
51.1 QFN48 6 x 6 mm package............................................................................................... 544
51.2 WLCSP package............................................................................................................... 545
52 Ordering information.........................................................................................546
52.1
52.2
52.3
52.4
52.5
IC marking.........................................................................................................................546
Box labels..........................................................................................................................546
Order code........................................................................................................................ 547
Code ranges and values...................................................................................................547
Product options................................................................................................................. 548
53 Reference circuitry............................................................................................ 550
53.1 Schematic QFAA and QFAB QFN48 with internal LDO setup......................................... 550
53.2 Schematic QFAA and QFAB QFN48 with DC/DC regulator setup................................... 551
53.3 Schematic QFAA and QFAB QFN48 with DC/DC regulator and NFC setup.................... 552
53.4 Schematic CIAA WLCSP with internal LDO setup........................................................... 553
Page 7
Contents
53.5
53.6
53.7
53.8
Schematic CIAA WLCSP with DC/DC regulator setup..................................................... 554
Schematic CIAA WLCSP with DC/DC regulator and NFC setup......................................555
PCB guidelines..................................................................................................................555
PCB layout example......................................................................................................... 556
54 Legal notices......................................................................................................558
Page 8
1 Revision history
1 Revision history
Date
November 2021
Version
1.8
Description
The following content has been added or updated:
Ordering information on page 546 - Build codes
Fxx not recommended for new designs.
The following content has been added or updated:
•
August 2021
1.7
Pin assignments on page 14 - Added
description of standard drive and low frequency I/
O
•
FICR — Factory information configuration registers
on page 44 - Updated INFO.VARIANT register
The following content has been added or updated:
•
April 2021
1.6
Debug and trace on page 73 - Updated
disabling access port protection description.
•
FICR — Factory information configuration registers
on page 44 - Updated INFO.VARIANT register.
•
GPIO — General purpose input/output on page
114 - Updated electrical specification.
•
SPIS — Serial peripheral interface slave with
EasyDMA on page 296 - Updated SPIS electrical
parameters tSPIS,VSO, tSPIS,HSO, tSPIS,SUSI, and tSPIS,HSI.
The following content has been added or updated:
•
March 2021
1.5
Absolute maximum ratings on page 20 Increased Flash memory retention to 10 years at
85 °C.
•
UICR — User information configuration registers
on page 55 - Added value HwDisabled to
APPROTECT register.
•
Debug and trace on page 73 - Added
description of APPROTECT functionality for devices
where APPROTECT is controlled by hardware
and software. Added peripheral APPROTECT
with necessary registers to control APPROTECT
for devices where APPROTECT is controlled by
hardware and software.
•
Ordering information on page 546 - Added new
product options.
The following content has been added or updated:
•
October 2017
1.4
Recommended operating conditions on page
21 - Added WLCSP light sensitivity information.
•
FICR — Factory information configuration registers
on page 44 - Added registers PARTNO,
HWREVISION and PRODUCTIONREVISION.
•
UICR — User information configuration registers
on page 55 - Changed width of PSELRESETn
port fields.
•
SPIM - Polarity in SPI mode table corrected.
•
COMP — Comparator on page 396 Documentation structure improvements/changes.
•
Liability disclaimer updated - Directive 2011/65/
EU (RoHS 2).
The following content has been added or updated:
•
February 2017
1.3
RADIO — 2.4 GHz Radio on page 209 Introduced 2 Mbps Bluetooth® low energy mode.
•
FICR — Factory information configuration registers
on page 44 - Updated INFO.PACKAGE register
(new package added).
•
UARTE - Corrected the pin configuration table.
•
PPI — Programmable peripheral interconnect on
page 172 - Timing information corrected.
•
Updated the liability disclaimer.
Updated the following:
•
September 2016
1.2
Power and clock management, Current
consumption: Ultra-low power on page 80.
•
Power, Current consumption, sleep on page
102
Added documentation for nRF52832 CIAA WLCSP.
•
July 2016
1.1
Added or updated the following content:
•
Page 9
Cover - Added Key features.
1 Revision history
Date
Version
February 2016
1.0
Description
•
Pin assignments on page 14 - Added WLCSP
ball assignments. Moved GPIO usage restrictions
here from GPIO/Notes on usage and restrictions.
•
Absolute maximum ratings on page 20 - Added
environmental information for WLCSP to the
table.
•
Memory on page 24 - Added QFAB and CIAA
information to the table.
•
FICR — Factory information configuration registers
on page 44 - Updated INFO.PACKAGE register.
•
UICR — User information configuration registers
on page 55 - Updated APPROTECT register.
•
Debug and trace on page 73 - Updated DAP Debug access port.
•
POWER — Power supply on page 81 - Updated
Pin reset.
•
CLOCK — Clock control on page 104 - Updated
information on external 32 kHz clock support.
•
GPIO — General purpose input/output on page
114 - Added GPIO located near the RADIO.
•
RADIO — 2.4 GHz Radio on page 209 - Updated
Figure 29 and Interframe spacing.
•
CCM - Updated SCRATCHPTR register.
•
SPIM - Updated Master mode pin configuration.
•
UARTE - Added RXDRDY and TXDRDY events.
•
NFCT - Updated Electrical specifications.
•
PWM — Pulse width modulation on page 499 Updated SEQ[1].REFRESH register.
•
Mechanical specifications on page 544 - Added
WLCSP package.
•
Ordering information on page 546 - Updated
with CIAA and QFAB information.
•
Reference circuitry on page 550 - QFAB
information added. CIAA WLCSP schematics
added.
First release.
Page 10
2 About this document
2 About this document
This product specification is organized into chapters based on the modules and peripherals that are available
in this IC.
The peripheral descriptions are divided into separate sections that include the following information:
•
•
•
A detailed functional description of the peripheral
Register configuration for the peripheral
Electrical specification tables, containing performance data which apply for the operating conditions
described in Recommended operating conditions on page 21.
2.1 Document naming and status
Nordic uses three distinct names for this document, which are reflecting the maturity and the status of the
document and its content.
Table 1: Defined document names
Document name
Objective Product Specification (OPS)
Description
Applies to document versions up to 0.7.
Preliminary Product Specification (PPS)
This product specification contains target specifications for product development.
Applies to document versions 0.7 and up to 1.0.
Product Specification (PS)
This product specification contains preliminary data. Supplementary data may be
published from Nordic Semiconductor ASA later.
Applies to document versions 1.0 and higher.
This product specification contains final product specifications. Nordic
Semiconductor ASA reserves the right to make changes at any time without notice
in order to improve design and supply the best possible product.
2.2 Peripheral naming and abbreviations
Every peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used for
identification and reference. This name is used in chapter headings and references, and it will appear in the
ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer to identify
the peripheral.
The peripheral instance name, which is different from the peripheral name, is constructed using the
peripheral name followed by a numbered postfix, starting with 0, for example, TIMER0. A postfix is normally
only used if a peripheral can be instantiated more than once. The peripheral instance name is also used in
the CMSIS to identify the peripheral instance.
2.3 Register tables
Individual registers are described using register tables. These tables are built up of two sections. The first
three colored rows describe the position and size of the different fields in the register. The following rows
describe the fields in more detail.
2.3.1 Fields and values
The Id (Field Id) row specifies the bits that belong to the different fields in the register. If a field has
enumerated values, then every value will be identified with a unique value id in the Value Id column.
A blank space means that the field is reserved and read as undefined, and it also must be written as 0 to
secure forward compatibility. If a register is divided into more than one field, a unique field name is specified
for each field in the Field column. The Value Id may be omitted in the single-bit bit fields when values can be
substituted with a Boolean type enumerator range, e.g. true/false, disable(d)/enable(d), on/off, and so on.
Page 11
2 About this document
Values are usually provided as decimal or hexadecimal. Hexadecimal values have a 0x prefix, decimal
values have no prefix.
The Value column can be populated in the following ways:
•
•
•
Individual enumerated values, for example 1, 3, 9.
Range of values, e.g. [0..4], indicating all values from and including 0 and 4.
Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or
alternatively the field's translation and limitations are described in the text instead.
If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all but the
first field. Subsequent fields will indicate inheritance with '..'.
A feature marked Deprecated should not be used for new designs.
2.4 Registers
Table 2: Register Overview
Register
Offset
Description
DUMMY
0x514
Example of a register controlling a dummy feature
2.4.1 DUMMY
Address offset: 0x514
Example of a register controlling a dummy feature
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D
Reset 0x00050002
Id
RW Field
A
RW FIELD_A
B
C
D
0
C C C
B
A A
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value Id
Value
Description
Disabled
0
The example feature is disabled
NormalMode
1
The example feature is enabled in normal mode
ExtendedMode
2
The example feature is enabled along with extra functionality
Disabled
0
The override feature is disabled
Enabled
1
The override feature is enabled
ValidRange
[2..7]
Example of a field with several enumerated values
RW FIELD_B
Example of a deprecated field
RW FIELD_C
Example of a field with a valid range of values
Example of allowed values for this field
RW FIELD_D
Example of a field with no restriction on the values
Page 12
Deprecated
3 Block diagram
3 Block diagram
This block diagram illustrates the overall system. Arrows with white heads indicate signals that share
physical pins with other signals.
SWCLK
RAM7
GPIO
P0
(P0.0 – P0.31)
slave
RAM6
slave
RAM5
slave
slave
RAM4
slave
RAM3
slave
RAM2
slave
TPIU
RAM1
slave
TP
RAM0
slave
nRF52832
SW-DP
ETM
slave
slave
slave
master
AHB-AP
slave
AHB
Multi-Layer
CTRL-AP
slave
SWDIO
I-Cache
AHB TO APB
BRIDGE
CPU
FICR
UICR
Flash
ARM
CORTEX-M4
NVIC
nRESET
NVMC
SysTick
RNG
POWER
RTC [0..2]
TIMER [0..4]
WDT
TEMP
PPI
XC1
XC2
XL1
ECB
CLOCK
EasyDMA
master
XL2
CCM
ANT2
EasyDMA
NFC2
NFC1
NFCT
EasyDMA
master
ma s
master
master
OUT0 – OUT3
PWM[0..3]
SDA
SCL
SDA
EasyDMA
RTS
CTS
TXD
RXD
master
master
EasyDMA
CSN
I2S
SPIS [0..2]
MISO
MOSI
SCK
EasyDMA
CLK
DIN
TWIM [0..1]
master
SCL
EasyDMA
UARTE [0]
EasyDMA
MCK
LRCK
SCL
SDOUT
SDIN
master
SAADC
QDEC
EasyDMA
TWIS [0..1]
master
MOSI
MISO
master
LPCOMP
LED
A
B
AAR
EasyDMA
SCK
COMP
EasyDMA
ter
SPIM [0..2]
GPIOTE
AIN0 – AIN7
EasyDMA
master
RADIO
APB0
ANT1
master
PDM
EasyDMA
master
Figure 1: Block diagram
Page 13
master
EasyDMA
4 Pin assignments
4 Pin assignments
Here we cover the pin assignments for each variant of the chip.
4.1 QFN48 pin assignments
P0.25
P0.26
P0.27
P0.28/AIN4
P0.29/AIN5
P0.30/AIN6
P0.31/AIN7
NC
VSS
DEC4
DCC
VDD
37
38
39
40
41
42
43
44
46
45
48
47
DEC1
P0.00/XL1
P0.01/XL2
P0.02/AIN0
P0.03/AIN1
P0.04/AIN2
P0.05/AIN3
P0.06
P0.07
P0.08
NFC1/P0.09
NFC2/P0.10
1
36
2
35
3
34
4
33
5
32
nRF5102
N52832
QFN48
QFN48
6
7
8
31
30
29
9
28
10
27
exposed die pad
11
26
12
25
VDD
XC2
XC1
DEC3
DEC2
VSS
ANT
P0.24
P0.23
P0.22
SWDIO
SWDCLK
24
23
22
21
20
19
18
17
16
15
14
13
P0.21/nRESET
P0.20/TRACECLK
P0.19
P0.18/TRACEDATA[0]/SWO
P0.17
P0.16/TRACEDATA[1]
P0.15/TRACEDATA[2]
P0.14/TRACEDATA[3]
P0.13
P0.12
P0.11
VDD
Figure 2: QFN48 pin assignments, top view
Table 3: QFN48 pin assignments
Pin
Name
Type
Description
1
DEC1
Power
0.9 V regulator digital supply decoupling
2
P0.00
Digital I/O
General purpose I/O
XL1
Analog input
Connection for 32.768 kHz crystal (LFXO)
P0.01
Digital I/O
General purpose I/O
XL2
Analog input
Connection for 32.768 kHz crystal (LFXO)
P0.02
Digital I/O
General purpose I/O
AIN0
Analog input
SAADC/COMP/LPCOMP input
P0.03
Digital I/O
General purpose I/O
AIN1
Analog input
SAADC/COMP/LPCOMP input
P0.04
Digital I/O
General purpose I/O
AIN2
Analog input
SAADC/COMP/LPCOMP input
P0.05
Digital I/O
General purpose I/O
Left Side of chip
3
4
5
6
7
AIN3
Analog input
SAADC/COMP/LPCOMP input
8
P0.06
Digital I/O
General purpose I/O
9
P0.07
Digital I/O
General purpose I/O
Page 14
4 Pin assignments
Pin
Name
Type
Description
10
P0.08
Digital I/O
General purpose I/O
11
NFC1
NFC input
NFC antenna connection
P0.09
Digital I/O
General purpose I/O1
NFC2
NFC input
NFC antenna connection
P0.10
Digital I/O
General purpose I/O1
13
VDD
Power
Power supply
14
P0.11
Digital I/O
General purpose I/O
15
P0.12
Digital I/O
General purpose I/O
16
P0.13
Digital I/O
General purpose I/O
17
P0.14
Digital I/O
General purpose I/O
12
Bottom side of chip
TRACEDATA[3]
18
P0.15
Trace port output
Digital I/O
TRACEDATA[2]
19
P0.16
General purpose I/O
Trace port output
Digital I/O
TRACEDATA[1]
General purpose I/O
Trace port output
20
P0.17
Digital I/O
General purpose I/O
21
P0.18
Digital I/O
General purpose I/O
TRACEDATA[0] / SWO
Single wire output
Trace port output
22
P0.19
Digital I/O
General purpose I/O
23
P0.20
Digital I/O
General purpose I/O
TRACECLK
24
P0.21
Trace port clock output
Digital I/O
nRESET
General purpose I/O
Configurable as pin reset
Right Side of chip
25
SWDCLK
Digital input
Serial wire debug clock input for debug
26
SWDIO
Digital I/O
27
P0.22
Digital I/O
General purpose I/O2
28
P0.23
Digital I/O
General purpose I/O2
29
P0.24
Digital I/O
General purpose I/O2
30
ANT
RF
Single-ended radio antenna connection
31
VSS
Power
Ground (Radio supply)
32
DEC2
Power
1.3 V regulator supply decoupling (Radio
33
DEC3
Power
Power supply decoupling
34
XC1
Analog input
Connection for 32 MHz crystal
35
XC2
Analog input
Connection for 32 MHz crystal
36
VDD
Power
Power supply
37
P0.25
Digital I/O
General purpose I/O2
38
P0.26
Digital I/O
General purpose I/O2
39
P0.27
Digital I/O
General purpose I/O2
40
P0.28
Digital I/O
General purpose I/O2
AIN4
Analog input
SAADC/COMP/LPCOMP input
P0.29
Digital I/O
General purpose I/O2
AIN5
Analog input
SAADC/COMP/LPCOMP input
P0.30
Digital I/O
General purpose I/O2
AIN6
Analog input
SAADC/COMP/LPCOMP input
P0.31
Digital I/O
General purpose I/O pin2
AIN7
Analog input
SAADC/COMP/LPCOMP input
and programming
Serial wire debug I/O for debug and
programming
supply)
Top side of chip
41
42
43
Page 15
4 Pin assignments
Pin
Name
44
NC
Type
Description
45
VSS
Power
Ground
46
DEC4
Power
1.3 V regulator supply decoupling
No connect
Leave unconnected
Input from DC/DC regulator
Output from 1.3 V LDO
47
DCC
Power
DC/DC regulator output
48
VDD
Power
Power supply
VSS
Power
Ground pad
Bottom of chip
Die pad
Exposed die pad must be connected
to ground (VSS) for proper device
operation.
4.2 WLCSP ball assignments
1
2
3
4
5
6
7
A
B
C
D
E
F
N52832
CIAAHP
YYWWLL
G
H
Figure 3: WLCSP ball assignments, top view
Table 4: WLCSP ball assignments
Ball
Name
A1
XC2
Analog input
Description
Connection for 32 MHz crystal
A2
DEC2
Power
1.3 V regulator supply decoupling (Radio
A3
P0.28
Digital I/O
General purpose I/O3
AIN4
Analog input
SAADC/COMP/LPCOMP input
P0.29
Digital I/O
General purpose I/O3
AIN5
Analog input
SAADC/COMP/LPCOMP input
P0.30
Digital I/O
General purpose I/O3
AIN6
Analog input
SAADC/COMP/LPCOMP input
DEC4
Power
1.3 V regulator supply decoupling
supply)
A4
A5
A6
Input from DC/DC converter. Output
from 1.3 V LDO
A7
VDD
Power
Power supply
B2
XC1
Analog input
Connection for 32 MHz crystal
B3
P0.25
Digital I/O
General purpose I/O3
1
2
See GPIO located near the radio on page 18 for more information.
See NFC antenna pins on page 18 for more information.
Page 16
4 Pin assignments
Ball
Name
B4
P0.27
Digital I/O
Description
General purpose I/O3
B5
P0.31
Digital I/O
General purpose I/O3
AIN7
Analog input
SAADC/COMP/LPCOMP input
B6
DCC
Power
DC/DC converter output
B7
DEC1
Power
0.9 V regulator digital supply decoupling
C2
DEC3
Power
Power supply decoupling
C3
NC
N/A
Not connected
C4
VSS
Power
Ground
C5
VSS
Power
Ground
C6
P0.02
Digital I/O
General purpose I/O
AIN0
Analog input
SAADC/COMP/LPCOMP input
P0.01
Digital I/O
General purpose I/O
C7
XL2
Analog input
Connection for 32.768 kHz crystal (LFXO)
D1
ANT
RF
Single-ended radio antenna connection
D2
VSS_PA
Power
Ground (Radio supply)
D3
P0.26
Digital I/O
General purpose I/O 3
D6
P0.03
Digital I/O
General purpose I/O
AIN1
Analog input
SAADC/COMP/LPCOMP input
P0.00
Digital I/O
General purpose I/O
D7
XL1
Analog input
Connection for 32.768 kHz crystal (LFXO)
E1
P0.24
Digital I/O
General purpose I/O3
E2
P0.23
Digital I/O
General purpose I/O3
E3
VSS
Power
Ground
E6
P0.04
Digital I/O
General purpose I/O
AIN2
Analog input
SAADC/COMP/LPCOMP input
P0.05
Digital I/O
General purpose I/O
E7
AIN3
Analog input
SAADC/COMP/LPCOMP input
F1
SWDCLK
Digital input
Serial wire debug clock input for debug
F2
P0.22
Digital I/O
General purpose I/O3
F3
P0.19
Digital I/O
General purpose I/O
F4
P0.11
Digital I/O
General purpose I/O
F5
VSS
Power
Ground
F6
P0.07
Digital I/O
General purpose I/O
F7
P0.06
Digital I/O
General purpose I/O
G1
SWDIO
Digital I/O
Serial wire debug I/O for debug and
G2
P0.20
Digital I/O
and programming
programming
TRACECLK
General purpose I/O
Trace port clock output
G3
P0.17
Digital I/O
General purpose I/O
G4
P0.13
Digital I/O
General purpose I/O
G5
NFC2
NFC input
NFC antenna connection
P0.10
Digital I/O
General purpose I/O4
NFC1
NFC input
NFC antenna connection
P0.09
Digital I/O
General purpose I/O4
G7
P0.08
Digital I/O
General purpose I/O
H1
P0.21
Digital I/O
General purpose I/O
G6
nRESET
H2
P0.18
Configurable as pin reset
Digital I/O
TRACEDATA[0]
H3
P0.16
Trace port output
Digital I/O
TRACEDATA[1]
H4
P0.15
General purpose I/O
General purpose I/O
Trace port output
Digital I/O
Page 17
General purpose I/O
4 Pin assignments
Ball
Name
Description
TRACEDATA[2]
H5
P0.14
Trace port output
Digital I/O
TRACEDATA[3]
General purpose I/O
Trace port output
H6
P0.12
Digital I/O
General purpose I/O
H7
VDD
Power
Power supply
4.3 GPIO usage restrictions
For more information on standard drive, see GPIO — General purpose input/output on page 114. Low
frequency I/O is a signal with a frequency up to 10 kHz.
4.3.1 GPIO located near the radio
Radio performance parameters, such as sensitivity, may be affected by high frequency digital I/O with large
sink/source current close to the Radio power supply and antenna pins.
Table 5: GPIO recommended usage for QFN48 package on page 18 and Table 6: GPIO recommended
usage for WLCSP package on page 18 identify some GPIO that have recommended usage guidelines to
maximize radio performance in an application.
Table 5: GPIO recommended usage for QFN48 package
Pin
27
28
29
37
38
39
40
41
42
43
GPIO
P0.22
P0.23
P0.24
P0.25
P0.26
P0.27
P0.28
P0.29
P0.30
P0.31
Recommended usage
Low drive, low frequency I/O only.
Table 6: GPIO recommended usage for WLCSP package
Pin
F2
E2
E1
B3
D3
B4
A3
A4
A5
B5
GPIO
P0.22
P0.23
P0.24
P0.25
P0.26
P0.27
P0.28
P0.29
P0.30
P0.31
Recommended usage
Low drive, low frequency I/O only.
4.3.2 NFC antenna pins
Two physical pins can be configured either as NFC antenna pins (factory default), or as GPIOs, as shown
below.
Table 7: GPIO pins used by NFC
NFC pad name
NFC1
NFC2
GPIO
P0.09
P0.10
When configured as NFC antenna pins, the GPIOs on those pins will automatically be set to DISABLE state
and a protection circuit will be enabled preventing the chip from being damaged in the presence of a strong
3
4
See GPIO located near the radio on page 18 for more information.
See NFC antenna pins on page 18 for more information.
Page 18
4 Pin assignments
NFC field. The protection circuit will short the two pins together if voltage difference exceeds approximately 2
V.
For information on how to configure these pins as normal GPIOs, see NFCT — Near field communication tag
on page 420 and UICR — User information configuration registers on page 55. Note that the device will
not be protected against strong NFC field damage if the pins are configured as GPIO and an NFC antenna
is connected to the device. The pins will always be configured as NFC pins during power-on reset until the
configuration is set according to the UICR register.
These two pins will have some limitations when configured as GPIO. The pin capacitance will be higher on
these pins, and there is some current leakage between the two pins if they are driven to different logical
values. To avoid leakage between the pins when configured as GPIO, these GPIOs should always be at the
same logical value whenever entering one of the device power saving modes. See Electrical specification.
Page 19
5 Absolute maximum ratings
5 Absolute maximum ratings
Maximum ratings are the extreme limits to which the chip can be exposed for a limited amount of time
without permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time may
affect the reliability of the device.
Table 8: Absolute maximum ratings
Supply voltages
VDD
VSS
I/O pin voltage
VI/O, VDD ≤3.6 V
VI/O, VDD >3.6 V
NFC antenna pin current
INFC1/2
Radio
RF input level
Environmental QFN48, 6×6 mm package
Storage temperature
MSL (moisture sensitivity level)
ESD HBM (human body model)
ESD CDM (charged device model)
Environmental WLCSP, 3.0×3.2 mm package
Storage temperature
MSL
ESD HBM
ESD CDM
Flash memory
Endurance
Retention
Min.
Max.
Unit
-0.3
+3.9
0
V
V
-0.3
-0.3
VDD + 0.3 V
3.9 V
V
V
80
mA
10
dBm
+125
2
4
1000
°C
+125
1
2
500
°C
-40
-40
10 000
10 years at 85°C
Page 20
kV
V
kV
V
Write/erase cycles
6 Recommended operating conditions
6 Recommended operating conditions
The operating conditions are the physical parameters that the chip can operate within.
Table 9: Recommended operating conditions
Symbol
VDD
tR_VDD
TA
Parameter
Supply voltage, independent of DCDC enable
Supply rise time (0 V to 1.7 V)
Operating temperature
Notes
Min.
1.7
Nom.
3.0
-40
25
Max.
3.6
60
85
Units
V
ms
°C
Important: The on-chip power-on reset circuitry may not function properly for rise times longer than
the specified maximum.
6.1 WLCSP light sensitivity
All WLCSP package variants are sensitive to visible and close-range infrared light. This means that a final
product design must shield the chip properly, either by final product encapsulation or by shielding/coating of
the WLCSP device.
Page 21
7 CPU
7 CPU
The ARM® Cortex®-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb®-2
technology) that implements a superset of 16 and 32-bit instructions to maximize code density and
performance.
This processor implements several features that enable energy-efficient arithmetic and high-performance
signal processing including:
•
•
•
•
•
Digital signal processing (DSP) instructions
Single-cycle multiply and accumulate (MAC) instructions
Hardware divide
8 and 16-bit single instruction multiple data (SIMD) instructions
Single-precision floating-point unit (FPU)
The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the
ARM Cortex processor series is implemented and available for the M4 CPU.
Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling
events at configurable priority levels via the Nested Vectored Interrupt Controller (NVIC).
Executing code from flash will have a wait state penalty on the nRF52 Series. An instruction cache can be
enabled to minimize flash wait states when fetching instructions. For more information on cache, see Cache
on page 31. The section Electrical specification on page 22 shows CPU performance parameters
including wait states in different modes, CPU current and efficiency, and processing power and efficiency
based on the CoreMark® benchmark.
7.1 Floating point interrupt
The floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow. These
exceptions will trigger the FPU interrupt (see Instantiation on page 25). To clear the IRQ line when an
exception has occurred, the relevant exception bit within the FPSCR register needs to be cleared. For more
information about the FPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide.
7.2 Electrical specification
7.2.1 CPU performance
The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is
executing the CoreMark™ benchmark. It includes power regulator and clock base currents. All other blocks
are IDLE.
Symbol
Description
Min.
WFLASH
CPU wait states, running from flash, cache disabled
0
Typ.
Max.
2
Units
WFLASHCACHE
CPU wait states, running from flash, cache enabled
0
3
WRAM
CPU wait states, running from RAM
IDDFLASHCACHE
CPU current, running from flash, cache enabled, LDO
7.4
mA
IDDFLASHCACHEDCDC
CPU current, running from flash, cache enabled, DCDC 3V
3.7
mA
IDDFLASH
CPU current, running from flash, cache disabled, LDO
8.0
mA
IDDFLASHDCDC
CPU current, running from flash, cache disabled, DCDC 3V
3.9
mA
IDDRAM
CPU current, running from RAM, LDO
6.7
mA
IDDRAMDCDC
CPU current, running from RAM, DCDC 3V
3.3
mA
IDDFLASH/MHz
CPU efficiency, running from flash, cache enabled, LDO
125
µA/
IDDFLASHDCDC/MHz
CPU efficiency, running from flash, cache enabled, DCDC 3V
58
0
MHz
µA/
MHz
Page 22
7 CPU
Symbol
Description
CMFLASH
CoreMark5, running from flash, cache enabled
Min.
Typ.
215
Max.
Units
CoreMark
CMFLASH/MHz
CoreMark per MHz, running from flash, cache enabled
3.36
CoreMark/
CMFLASH/mA
CoreMark per mA, running from flash, cache enabled, DCDC 3V
58
MHz
CoreMark/
mA
7.3 CPU and support module configuration
The ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on the
device.
Option / Module
Core options
NVIC
PRIORITIES
WIC
Endianness
Bit Banding
DWT
SysTick
Modules
MPU
FPU
DAP
ETM
ITM
TPIU
ETB
FPB
HTM
5
Description
Implemented
Nested Vector Interrupt Controller
Priority bits
Wakeup Interrupt Controller
Memory system endianness
Bit banded memory
Data Watchpoint and Trace
System tick timer
37 vectors
3
NO
Little endian
NO
YES
YES
Memory protection unit
Floating point unit
Debug Access Port
Embedded Trace Macrocell
Instrumentation Trace Macrocell
Trace Port Interface Unit
Embedded Trace Buffer
Flash Patch and Breakpoint Unit
AHB Trace Macrocell
YES
YES
YES
YES
YES
YES
NO
YES
NO
Using IAR v6.50.1.4452 with flags --endian=little --cpu=Cortex-M4 -e --fpu=VFPv4_sp –Ohs --no_size_constraints
Page 23
8 Memory
8 Memory
The nRF52832 contains flash and RAM that can be used for code and data storage.
The amount of RAM and flash will vary depending on variant, see Table 10: Memory variants on page 24.
Table 10: Memory variants
Device name
nRF52832-QFAA
nRF52832-QFAB
nRF52832-CIAA
RAM
64 kB
32 kB
64 kB
Flash
512 kB
256 kB
512 kB
Comments
The CPU and the EasyDMA can access memory via the AHB multilayer interconnect. The CPU is also able
to access peripherals via the AHB multilayer interconnect, as illustrated in Figure 4: Memory layout on page
24.
Data RAM
System
APB
ICODE
AHB
DCODE
AHB multilayer interconnect
Section 0
0x0080 F000
0x2000 E000
0x0080 E000
RAM6
AHB slave
Section 1
0x2000 D000
0x0080 D000
Section 0
0x2000 C000
0x0080 C000
RAM5
AHB slave
Section 1
0x2000 B000
0x0080 B000
Section 0
0x2000 A000
0x0080 A000
RAM4
AHB slave
Section 1
0x2000 9000
0x0080 9000
Section 0
0x2000 8000
0x0080 8000
RAM3
AHB slave
Section 1
0x2000 7000
0x0080 7000
0x2000 6000
0x0080 6000
RAM2
AHB slave
Section 1
0x2000 5000
0x0080 5000
Section 0
0x2000 4000
0x0080 4000
RAM1
AHB slave
Section 1
0x2000 3000
0x0080 3000
Section 0
0x2000 2000
0x0080 2000
RAM0
AHB slave
Section 1
0x2100 1000
0x0080 1000
Section 0
0x2000 0000
0x0080 0000
I-Cache
System bus
ICODE
DCODE
EasyDMA
DMA bus
DMA bus
EasyDMA
Peripheral
Code RAM
ICODE/DCODE
0x2000 F000
Section 0
Page 127
NVMC
ARM Cortex-M4
Peripheral
Section 1
AHB
slave
CPU
RAM7
AHB slave
AHB
slave
AHB2APB
Flash
ICODE/DCODE
0x0007 F000
Page 3..126
0x0000 3000
Page 2
Page 1
Page 0
0x0000 2000
0x0000 1000
Block 7
0x0000 0E00
Block 2..6
0x0000 0400
Block 1
0x0000 0200
Block 0
0x0000 0000
Figure 4: Memory layout
See AHB multilayer on page 27 and EasyDMA on page 28 for more information about the AHB
multilayer interconnect and the EasyDMA.
The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to the
application to partition the RAM within these regions so that one does not corrupt the other.
8.1 RAM - Random access memory
The RAM interface is divided into multiple RAM AHB slaves.
Each RAM AHB slave is connected to two 4-kilobyte RAM sections, see Section 0 and Section 1 in Figure 4:
Memory layout on page 24.
Each of the RAM sections have separate power control for System ON and System OFF mode operation,
which is configured via RAM register (see the POWER — Power supply on page 81).
Page 24
8 Memory
8.2 Flash - Non-volatile memory
The Flash can be read an unlimited number of times by the CPU, but it has restrictions on the number of
times it can be written and erased and also on how it can be written.
Writing to Flash is managed by the Non-volatile memory controller (NVMC), see NVMC — Non-volatile
memory controller on page 30.
The Flash is divided into multiple pages that can be accessed by the CPU via both the ICODE and DCODE
buses as shown in, Figure 4: Memory layout on page 24. Each page is divided into 8 blocks.
8.3 Memory map
The complete memory map is shown in Figure 5: Memory map on page 25. As described in Memory on
page 24, Code RAM and the Data RAM are the same physical RAM.
nRF52832 Address Map
0xE010 0000
0xE0FF 0000
0xE004 2000
0xE004 1000
0xE004 0000
ROM Table
External PPB
ETM
TPIU
0xE004 0000
0xE000 F000
0xE000 E000
0xE000 3000
0xE000 2000
0xE000 1000
0xE000 0000
Reserved
SCS
Reserved
FPB
DWT
ITM
0x2000 0000
0x1000 1000
0x1000 0000
0xFFFF FFFF
Cortex M4 System Address Map
Private Peripheral Bus - External
Private Peripheral Bus - Internal
0x6000 0000
External device
1.0GB
Reserved
AHB peripherals
Reserved
0xA000 0000
0x5000 0000
APB peripherals
Reserved
UICR
Reserved
FICR
External RAM
1.0GB
Peripheral
0.5GB
SRAM
0.5GB
Reserved
0x0081 0000
nRF52832 Address Map
System
Code RAM
0x0080 0000
0x4000 0000
0x4000 0000
Reserved
Reserved
0x0008 0000
Data RAM
Flash
Code
0.5GB
0x2001 0000
0x2000 0000
0x0000 0000
Figure 5: Memory map
8.4 Instantiation
Table 11: Instantiation table
ID
Base Address
Peripheral
Instance
Description
0
0x40000000
POWER
POWER
Power control
0
0x40000000
CLOCK
CLOCK
Clock control
0
0x40000000
APPROTECT
APPROTECT
APPROTECT control
0
0x40000000
BPROT
BPROT
Block Protect
1
0x40001000
RADIO
RADIO
2.4 GHz radio
2
0x40002000
UARTE
UARTE0
Universal Asynchronous Receiver/Transmitter with EasyDMA
2
0x40002000
UART
UART0
Universal Asynchronous Receiver/Transmitter
3
0x40003000
SPIM
SPIM0
SPI master 0
3
0x40003000
SPIS
SPIS0
SPI slave 0
3
0x40003000
SPI
SPI0
SPI master 0
3
0x40003000
TWIM
TWIM0
Two-wire interface master 0
Page 25
Deprecated
Deprecated
8 Memory
ID
Base Address
Peripheral
Instance
Description
3
0x40003000
TWIS
TWIS0
Two-wire interface slave 0
3
0x40003000
TWI
TWI0
Two-wire interface master 0
Deprecated
4
0x40004000
TWI
TWI1
Two-wire interface master 1
Deprecated
4
0x40004000
TWIM
TWIM1
Two-wire interface master 1
4
0x40004000
TWIS
TWIS1
Two-wire interface slave 1
4
0x40004000
SPI
SPI1
SPI master 1
4
0x40004000
SPIM
SPIM1
SPI master 1
4
0x40004000
SPIS
SPIS1
SPI slave 1
5
0x40005000
NFCT
NFCT
Near Field Communication Tag
6
0x40006000
GPIOTE
GPIOTE
GPIO Tasks and Events
7
0x40007000
SAADC
SAADC
Analog to digital converter
8
0x40008000
TIMER
TIMER0
Timer 0
9
0x40009000
TIMER
TIMER1
Timer 1
10
0x4000A000
TIMER
TIMER2
Timer 2
11
0x4000B000
RTC
RTC0
Real-time counter 0
12
0x4000C000
TEMP
TEMP
Temperature sensor
13
0x4000D000
RNG
RNG
Random number generator
14
0x4000E000
ECB
ECB
AES Electronic Code Book (ECB) mode block encryption
15
0x4000F000
CCM
CCM
AES CCM Mode Encryption
15
0x4000F000
AAR
AAR
Acelerated Address Resolver
16
0x40010000
WDT
WDT
Watchdog timer
17
0x40011000
RTC
RTC1
Real-time counter 1
18
0x40012000
QDEC
QDEC
Quadrature decoder
19
0x40013000
LPCOMP
LPCOMP
Low power comparator
19
0x40013000
COMP
COMP
General purpose comparator
20
0x40014000
EGU
EGU0
Event Generator Unit 0
20
0x40014000
SWI
SWI0
Software interrupt 0
21
0x40015000
EGU
EGU1
Event Generator Unit 1
21
0x40015000
SWI
SWI1
Software interrupt 1
22
0x40016000
SWI
SWI2
Software interrupt 2
22
0x40016000
EGU
EGU2
Event Generator Unit 2
23
0x40017000
SWI
SWI3
Software interrupt 3
23
0x40017000
EGU
EGU3
Event Generator Unit 3
24
0x40018000
SWI
SWI4
Software interrupt 4
24
0x40018000
EGU
EGU4
Event Generator Unit 4
25
0x40019000
SWI
SWI5
Software interrupt 5
25
0x40019000
EGU
EGU5
Event Generator Unit 5
26
0x4001A000
TIMER
TIMER3
Timer 3
27
0x4001B000
TIMER
TIMER4
Timer 4
28
0x4001C000
PWM
PWM0
Pulse Width Modulation Unit 0
29
0x4001D000
PDM
PDM
Pulse Density Modulation (Digital Microphone Interface)
30
0x4001E000
NVMC
NVMC
Non-Volatile Memory Controller
31
0x4001F000
PPI
PPI
Programmable Peripheral Interconnect
32
0x40020000
MWU
MWU
Memory Watch Unit
33
0x40021000
PWM
PWM1
Pulse Width Modulation Unit 1
34
0x40022000
PWM
PWM2
Pulse Width Modulation Unit 2
35
0x40023000
SPIS
SPIS2
SPI slave 2
35
0x40023000
SPI
SPI2
SPI master 2
35
0x40023000
SPIM
SPIM2
SPI master 2
36
0x40024000
RTC
RTC2
Real-time counter 2
37
0x40025000
I2S
I2S
Inter-IC Sound Interface
38
0x40026000
FPU
FPU
FPU interrupt
0
0x50000000
GPIO
GPIO
General purpose input and output
0
0x50000000
GPIO
P0
General purpose input and output
N/A
0x10000000
FICR
FICR
Factory Information Configuration
N/A
0x10001000
UICR
UICR
User Information Configuration
Page 26
Deprecated
Deprecated
Deprecated
9 AHB multilayer
9 AHB multilayer
The CPU and all of the EasyDMAs are AHB bus masters on the AHB multilayer, while the RAM and various
other modules are AHB slaves.
See Block diagram on page 13 for an overview of which peripherals implement EasyDMA.
The CPU has exclusive access to all AHB slaves except for the RAM that can also be accessed by the
EasyDMA.
Access rights to each of the RAM AHB slaves are resolved using the priority of the different bus masters in
the system
See AHB multilayer priorities on page 27 for information about the priority of the different AHB bus
masters in the system. It is possible for two or more bus masters to have the same priority in cases where
it is guaranteed by design that the related masters will never be able to access the same slave at the same
time.
9.1 AHB multilayer priorities
Each master connected to the AHB multilayer is assigned a priority.
Table 12: AHB bus masters
Bus master name
CPU
SPIS1
RADIO
CCM/ECB/AAR
SAADC
UARTE
SERIAL0
SERIAL2
NFCT
I2S
PDM
PWM
Priority
Highest priority
Description
Applies to SPIM1, SPIS1, TWIM1, TWIS1
Applies to SPIM0, SPIS0, TWIM0, TWIS0
Applies to SPIM2, SPIS2
I2S
PDM
Applies to PWM0, PWM1, PWM2
Lowest priority
Page 27
10 EasyDMA
10 EasyDMA
EasyDMA is an easy-to-use direct memory access module that some peripherals implement to gain direct
access to Data RAM.
The EasyDMA is an AHB bus master similar to the CPU and it is connected to the AHB multilayer
interconnect for direct access to the Data RAM. The EasyDMA is not able to access the Flash.
A peripheral can implement multiple EasyDMA instances, for example to provide a dedicated channel for
reading data from RAM into the peripheral at the same time as a second channel is dedicated for writing data
to the RAM from the peripheral. This concept is illustrated in Figure 6: EasyDMA example on page 28
RAM
AHB Multilayer
Peripheral
READER
RAM
RAM
AHB
EasyDMA
WRITER
AHB
Peripheral
Core
EasyDMA
Figure 6: EasyDMA example
An EasyDMA channel is usually exposed to the user in the form illustrated below, but some variations may
occur:
READERBUFFER_SIZE 5
WRITERBUFFER_SIZE 6
uint8_t readerBuffer[READERBUFFER_SIZE]
uint8_t writerBuffer[WRITERBUFFER_SIZE]
__at__ 0x20000000;
__at__ 0x20000005;
// Configuring the READER channel
MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE;
MYPERIPHERAL->READER.PTR = &readerBuffer;
// Configure the WRITER channel
MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE;
MYPERIPHERAL->WRITER.PTR = &writerBuffer;
This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels, one
for reading, called READER, and one for writing, called WRITER. When the peripheral is started, it is here
assumed that the peripheral will read 5 bytes from the readerBuffer located in RAM at address 0x20000000,
process the data and then write no more than 6 bytes back to the writerBuffer located in RAM at address
0x20000005. The memory layout of these buffers is illustrated in Figure 7: EasyDMA memory layout on page
29.
Page 28
10 EasyDMA
0x20000000
readerBuffer[0]
readerBuffer[1]
readerBuffer[2]
readerBuffer[3]
0x20000004
readerBuffer[4]
writerBuffer[0]
writerBuffer[1]
writerBuffer[2]
0x20000008
writerBuffer[3]
writerBuffer[4]
writerBuffer[5]
Figure 7: EasyDMA memory layout
The EasyDMA channel's MAXCNT register cannot be specified larger than the actual size of the buffer. If,
for example, the WRITER.MAXCNT register is specified larger than the size of the writerBuffer, the WRITER
EasyDMA channel may overflow the writerBuffer.
After the peripheral has completed the EasyDMA transfer, the CPU can read the EasyDMA channel's
AMOUNT register to see how many bytes that were transferred, e.g. it is possible for the CPU to read the
MYPERIPHERAL->WRITER.AMOUNT register to see how many bytes the WRITER wrote to RAM.
10.1 EasyDMA array list
The EasyDMA is able to operate in a mode called array list.
The EasyDMA array list can be represented by the data structure ArrayList_type illustrated in the code
example below.
This data structure includes only a buffer with size equal to READER.MAXCNT. EasyDMA will use the
READER.MAXCNT register to determine when the buffer is full.
This array list does not provide a mechanism to explicitly specify where the next item in the list is located.
Instead, it assumes that the list is organized as a linear array where items are located one after the other in
RAM.
#define BUFFER_SIZE
4
typedef struct ArrayList
{
uint8_t buffer[BUFFER_SIZE];
} ArrayList_type;
ArrayList_type ReaderList[3];
READER.MAXCNT = BUFFER_SIZE;
READER.PTR = &ReaderList;
READER.PTR = &ReaderList
0x20000000 : ReaderList[0]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000004 : ReaderList[1]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000008 : ReaderList[2]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
Figure 8: EasyDMA array list
Page 29
11 NVMC — Non-volatile memory controller
11 NVMC — Non-volatile memory controller
The Non-volatile memory controller (NVMC) is used for writing and erasing the internal Flash memory and
the UICR.
Before a write can be performed, the NVMC must be enabled for writing in CONFIG.WEN. Similarly, before
an erase can be performed, the NVMC must be enabled for erasing in CONFIG.EEN, see CONFIG on page
32. The user must make sure that writing and erasing are not enabled at the same time. Failing to do so
may result in unpredictable behavior.
11.1 Writing to Flash
When writing is enabled, the Flash is written by writing a full 32-bit word to a word-aligned address in the
Flash.
The NVMC is only able to write '0' to bits in the Flash that are erased, that is, set to '1'. It cannot write back a
bit to '1'.
As illustrated in Memory on page 24, the Flash is divided into multiple pages that are further divided into
multiple blocks. The same block in the Flash can only be written nWRITE number of times before an erase
must be performed using ERASEPAGE or ERASEALL. See the memory size and organization in Memory on
page 24 for block size.
Only full 32-bit words can be written to Flash using the NVMC interface. To write less than 32 bits to Flash,
write the data as a word, and set all the bits that should remain unchanged in the word to '1'. Note that the
restriction about the number of writes (see above) still applies in this case.
The time it takes to write a word to the Flash is specified by tWRITE. The CPU is halted while the NVMC is
writing to the Flash.
Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.
11.2 Erasing a page in Flash
When erase is enabled, the Flash can be erased page by page using the ERASEPAGE register.
After erasing a Flash page, all bits in the page are set to '1'. The time it takes to erase a page is specified by
tERASEPAGE. The CPU is halted while the NVMC performs the erase operation.
11.3 Writing to user information configuration registers (UICR)
User information configuration registers (UICR) are written in the same way as Flash. After UICR has been
written, the new UICR configuration will only take effect after a reset.
UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR or
ERASEALL.
The time it takes to write a word to the UICR is specified by tWRITE. The CPU is halted while the NVMC is
writing to the UICR.
11.4 Erasing user information configuration registers (UICR)
When erase is enabled, UICR can be erased using the ERASEUICR register.
After erasing UICR all bits in UICR are set to '1'. The time it takes to erase UICR is specified by tERASEPAGE.
The CPU is halted while the NVMC performs the erase operation.
Page 30
11 NVMC — Non-volatile memory controller
11.5 Erase all
When erase is enabled, the whole Flash and UICR can be erased in one operation by using the ERASEALL
register. ERASEALL will not erase the factory information configuration registers (FICR).
The time it takes to perform an ERASEALL command is specified by tERASEALL The CPU is halted while the
NVMC performs the erase operation.
11.6 Cache
An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.
See the Memory map in Memory map on page 25 for the location of Flash.
A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of wait-states
for a cache miss, where the instruction is not available in the cache and needs to be fetched from Flash,
depends on the processor frequency and is shown in CPU on page 22
Enabling the cache can increase CPU performance and reduce power consumption by reducing the number
of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache will use some
current when enabled. If the reduction in average current due to reduced flash accesses is larger than the
cache power requirement, the average current to execute the program code will reduce.
When disabled, the cache does not use current and does not retain its content.
It is possible to enable cache profiling to analyze the performance of the cache for your program using the
ICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for every
instruction cache hit or miss respectively. The hit and miss profiling registers do not wrap around after
reaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to get
correct numbers.
11.7 Registers
Table 13: Instances
Base address
Peripheral
Instance
Description
0x4001E000
NVMC
NVMC
Non-Volatile Memory Controller
Configuration
Table 14: Register Overview
Register
Offset
Description
READY
0x400
Ready flag
CONFIG
0x504
Configuration register
ERASEPAGE
0x508
Register for erasing a page in Code area
ERASEPCR1
0x508
Register for erasing a page in Code area. Equivalent to ERASEPAGE.
ERASEALL
0x50C
Register for erasing all non-volatile user memory
ERASEPCR0
0x510
Register for erasing a page in Code area. Equivalent to ERASEPAGE.
ERASEUICR
0x514
Register for erasing User Information Configuration Registers
ICACHECNF
0x540
I-Code cache configuration register.
IHIT
0x548
I-Code cache hit counter.
IMISS
0x54C
I-Code cache miss counter.
11.7.1 READY
Address offset: 0x400
Ready flag
Page 31
Deprecated
Deprecated
11 NVMC — Non-volatile memory controller
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Busy
0
NVMC is busy (on-going write or erase operation)
Ready
1
NVMC is ready
READY
NVMC is ready or busy
11.7.2 CONFIG
Address offset: 0x504
Configuration register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW WEN
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Program memory access mode. It is strongly recommended
to only activate erase and write modes when they are actively
used. Enabling write or erase will invalidate the cache and keep
it invalidated.
Ren
0
Read only access
Wen
1
Write Enabled
Een
2
Erase enabled
11.7.3 ERASEPAGE
Address offset: 0x508
Register for erasing a page in Code area
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ERASEPAGE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Register for starting erase of a page in Code area
The value is the address to the page to be erased. (Addresses of
first word in page). Note that code erase has to be enabled by
CONFIG.EEN before the page can be erased. Attempts to erase
pages that are outside the code area may result in undesirable
behaviour, e.g. the wrong page may be erased.
11.7.4 ERASEPCR1 ( Deprecated )
Address offset: 0x508
Register for erasing a page in Code area. Equivalent to ERASEPAGE.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ERASEPCR1
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Register for erasing a page in Code area. Equivalent to
ERASEPAGE.
11.7.5 ERASEALL
Address offset: 0x50C
Register for erasing all non-volatile user memory
Page 32
11 NVMC — Non-volatile memory controller
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ERASEALL
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Erase all non-volatile memory including UICR registers. Note
that code erase has to be enabled by CONFIG.EEN before the
UICR can be erased.
NoOperation
0
No operation
Erase
1
Start chip erase
11.7.6 ERASEPCR0 ( Deprecated )
Address offset: 0x510
Register for erasing a page in Code area. Equivalent to ERASEPAGE.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ERASEPCR0
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Register for starting erase of a page in Code area. Equivalent to
ERASEPAGE.
11.7.7 ERASEUICR
Address offset: 0x514
Register for erasing User Information Configuration Registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ERASEUICR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Register starting erase of all User Information Configuration
Registers. Note that code erase has to be enabled by
CONFIG.EEN before the UICR can be erased.
NoOperation
0
No operation
Erase
1
Start erase of UICR
11.7.8 ICACHECNF
Address offset: 0x540
I-Code cache configuration register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
Reset 0x00000000
Id
RW Field
A
RW CACHEEN
B
0
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable cache. Invalidates all cache entries.
Enabled
1
Enable cache
Disabled
0
Disable cache profiling
Enabled
1
Enable cache profiling
Cache enable
RW CACHEPROFEN
Cache profiling enable
11.7.9 IHIT
Address offset: 0x548
I-Code cache hit counter.
Page 33
11 NVMC — Non-volatile memory controller
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW HITS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Number of cache hits
11.7.10 IMISS
Address offset: 0x54C
I-Code cache miss counter.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MISSES
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Number of cache misses
11.8 Electrical specification
11.8.1 Flash programming
Symbol
Description
nWRITE,BLOCK
Amount of writes allowed in a block between erase
Min.
Typ.
Max.
Units
tWRITE
Time to write one word
67.5
338
µs
tERASEPAGE
Time to erase one page
2.05
89.7
ms
tERASEALL
Time to erase all flash
6.72
295.3
ms
Max.
Units
181
11.8.2 Cache size
Symbol
Description
SizeICODE
I-Code cache size
Min.
Typ.
2048
Page 34
Bytes
12 BPROT — Block protection
12 BPROT — Block protection
The mechanism for protecting non-volatile memory can be used to prevent application code from erasing or
writing to protected blocks.
Non-volatile memory can be protected from erases and writes depending on the settings in the CONFIG
registers. One bit in a CONFIG register represents one protected block of 4 kB. There are four CONFIG
registers of 32 bits, which means there are 128 protectable blocks in total.
Important: If an erase or write to a protected block is detected, the CPU will hard fault. If an
ERASEALL operation is attempted from the CPU while any block is protected, it will be blocked and
the CPU will hard fault.
On reset, all the protection bits are cleared. To ensure safe operation, the first task after reset must be to set
the protection bits. The only way of clearing protection bits is by resetting the device from any reset source.
The protection mechanism is turned off when in debug interface mode (a debugger is connected) and the
DISABLEINDEBUG register is set to disable. For more information, see Debug and trace on page 73.
Program Memory
127
126
125
l
31
CONFIG[3]
0
...
2
1
0
0x00000000
l
31
CONFIG[0]
0
Figure 9: Protected regions of program memory
12.1 Registers
Table 15: Instances
Base address
Peripheral
Instance
Description
0x40000000
BPROT
BPROT
Block Protect
Configuration
Table 16: Register Overview
Register
Offset
Description
CONFIG0
0x600
Block protect configuration register 0
CONFIG1
0x604
Block protect configuration register 1
DISABLEINDEBUG
0x608
Disable protection mechanism in debug interface mode
0x60C
Reserved
CONFIG2
0x610
Block protect configuration register 2
CONFIG3
0x614
Block protect configuration register 3
Page 35
12 BPROT — Block protection
12.1.1 CONFIG0
Address offset: 0x600
Block protect configuration register 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW REGION0
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
Value Id
Value
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
I H G F E D C B A
Description
Enable protection for region 0. Write '0' has no effect.
RW REGION1
Enable protection for region 1. Write '0' has no effect.
RW REGION2
Enable protection for region 2. Write '0' has no effect.
RW REGION3
Enable protection for region 3. Write '0' has no effect.
RW REGION4
Enable protection for region 4. Write '0' has no effect.
RW REGION5
Enable protection for region 5. Write '0' has no effect.
RW REGION6
Enable protection for region 6. Write '0' has no effect.
RW REGION7
Enable protection for region 7. Write '0' has no effect.
RW REGION8
Enable protection for region 8. Write '0' has no effect.
RW REGION9
Enable protection for region 9. Write '0' has no effect.
RW REGION10
Enable protection for region 10. Write '0' has no effect.
RW REGION11
Enable protection for region 11. Write '0' has no effect.
RW REGION12
Enable protection for region 12. Write '0' has no effect.
RW REGION13
Enable protection for region 13. Write '0' has no effect.
RW REGION14
Enable protection for region 14. Write '0' has no effect.
RW REGION15
Enable protection for region 15. Write '0' has no effect.
RW REGION16
Enable protection for region 16. Write '0' has no effect.
Protection disabled
Page 36
12 BPROT — Block protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
R
S
T
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
Disabled
0
Protection disabled
Enabled
1
Protection enable
RW REGION17
I H G F E D C B A
Enable protection for region 17. Write '0' has no effect.
RW REGION18
Enable protection for region 18. Write '0' has no effect.
RW REGION19
Enable protection for region 19. Write '0' has no effect.
RW REGION20
Enable protection for region 20. Write '0' has no effect.
RW REGION21
Enable protection for region 21. Write '0' has no effect.
RW REGION22
Enable protection for region 22. Write '0' has no effect.
RW REGION23
Enable protection for region 23. Write '0' has no effect.
RW REGION24
Enable protection for region 24. Write '0' has no effect.
RW REGION25
Enable protection for region 25. Write '0' has no effect.
RW REGION26
Enable protection for region 26. Write '0' has no effect.
RW REGION27
Enable protection for region 27. Write '0' has no effect.
RW REGION28
Enable protection for region 28. Write '0' has no effect.
RW REGION29
Enable protection for region 29. Write '0' has no effect.
RW REGION30
Enable protection for region 30. Write '0' has no effect.
RW REGION31
Enable protection for region 31. Write '0' has no effect.
12.1.2 CONFIG1
Address offset: 0x604
Block protect configuration register 1
Page 37
12 BPROT — Block protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW REGION32
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
Value Id
Value
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
I H G F E D C B A
Description
Enable protection for region 32. Write '0' has no effect.
RW REGION33
Enable protection for region 33. Write '0' has no effect.
RW REGION34
Enable protection for region 34. Write '0' has no effect.
RW REGION35
Enable protection for region 35. Write '0' has no effect.
RW REGION36
Enable protection for region 36. Write '0' has no effect.
RW REGION37
Enable protection for region 37. Write '0' has no effect.
RW REGION38
Enable protection for region 38. Write '0' has no effect.
RW REGION39
Enable protection for region 39. Write '0' has no effect.
RW REGION40
Enable protection for region 40. Write '0' has no effect.
RW REGION41
Enable protection for region 41. Write '0' has no effect.
RW REGION42
Enable protection for region 42. Write '0' has no effect.
RW REGION43
Enable protection for region 43. Write '0' has no effect.
RW REGION44
Enable protection for region 44. Write '0' has no effect.
RW REGION45
Enable protection for region 45. Write '0' has no effect.
RW REGION46
Enable protection for region 46. Write '0' has no effect.
RW REGION47
Enable protection for region 47. Write '0' has no effect.
RW REGION48
Enable protection for region 48. Write '0' has no effect.
RW REGION49
Enable protection for region 49. Write '0' has no effect.
RW REGION50
Enable protection for region 50. Write '0' has no effect.
Page 38
12 BPROT — Block protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
T
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
RW REGION51
I H G F E D C B A
Enable protection for region 51. Write '0' has no effect.
RW REGION52
Enable protection for region 52. Write '0' has no effect.
RW REGION53
Enable protection for region 53. Write '0' has no effect.
RW REGION54
Enable protection for region 54. Write '0' has no effect.
RW REGION55
Enable protection for region 55. Write '0' has no effect.
RW REGION56
Enable protection for region 56. Write '0' has no effect.
RW REGION57
Enable protection for region 57. Write '0' has no effect.
RW REGION58
Enable protection for region 58. Write '0' has no effect.
RW REGION59
Enable protection for region 59. Write '0' has no effect.
RW REGION60
Enable protection for region 60. Write '0' has no effect.
RW REGION61
Enable protection for region 61. Write '0' has no effect.
RW REGION62
Enable protection for region 62. Write '0' has no effect.
RW REGION63
Enable protection for region 63. Write '0' has no effect.
12.1.3 DISABLEINDEBUG
Address offset: 0x608
Disable protection mechanism in debug interface mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000001
Id
RW Field
A
RW DISABLEINDEBUG
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value
Description
Disable the protection mechanism for NVM regions while
in debug interface mode. This register will only disable the
protection mechanism if the device is in debug interface mode.
Disabled
1
Disable in debug
Page 39
12 BPROT — Block protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000001
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Description
Enabled
0
Enable in debug
12.1.4 CONFIG2
Address offset: 0x610
Block protect configuration register 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW REGION64
B
C
D
E
F
G
H
I
J
K
L
M
N
O
Value Id
Value
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
I H G F E D C B A
Description
Enable protection for region 64. Write '0' has no effect.
RW REGION65
Enable protection for region 65. Write '0' has no effect.
RW REGION66
Enable protection for region 66. Write '0' has no effect.
RW REGION67
Enable protection for region 67. Write '0' has no effect.
RW REGION68
Enable protection for region 68. Write '0' has no effect.
RW REGION69
Enable protection for region 69. Write '0' has no effect.
RW REGION70
Enable protection for region 70. Write '0' has no effect.
RW REGION71
Enable protection for region 71. Write '0' has no effect.
RW REGION72
Enable protection for region 72. Write '0' has no effect.
RW REGION73
Enable protection for region 73. Write '0' has no effect.
RW REGION74
Enable protection for region 74. Write '0' has no effect.
RW REGION75
Enable protection for region 75. Write '0' has no effect.
RW REGION76
Enable protection for region 76. Write '0' has no effect.
RW REGION77
Enable protection for region 77. Write '0' has no effect.
RW REGION78
Enable protection for region 78. Write '0' has no effect.
Protection disabled
Page 40
12 BPROT — Block protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
P
Q
R
S
T
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
RW REGION79
I H G F E D C B A
Enable protection for region 79. Write '0' has no effect.
RW REGION80
Enable protection for region 80. Write '0' has no effect.
RW REGION81
Enable protection for region 81. Write '0' has no effect.
RW REGION82
Enable protection for region 82. Write '0' has no effect.
RW REGION83
Enable protection for region 83. Write '0' has no effect.
RW REGION84
Enable protection for region 84. Write '0' has no effect.
RW REGION85
Enable protection for region 85. Write '0' has no effect.
RW REGION86
Enable protection for region 86. Write '0' has no effect.
RW REGION87
Enable protection for region 87. Write '0' has no effect.
RW REGION88
Enable protection for region 88. Write '0' has no effect.
RW REGION89
Enable protection for region 89. Write '0' has no effect.
RW REGION90
Enable protection for region 90. Write '0' has no effect.
RW REGION91
Enable protection for region 91. Write '0' has no effect.
RW REGION92
Enable protection for region 92. Write '0' has no effect.
RW REGION93
Enable protection for region 93. Write '0' has no effect.
RW REGION94
Enable protection for region 94. Write '0' has no effect.
RW REGION95
Enable protection for region 95. Write '0' has no effect.
Page 41
12 BPROT — Block protection
12.1.5 CONFIG3
Address offset: 0x614
Block protect configuration register 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW REGION96
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
Value Id
Value
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
I H G F E D C B A
Description
Enable protection for region 96. Write '0' has no effect.
RW REGION97
Enable protection for region 97. Write '0' has no effect.
RW REGION98
Enable protection for region 98. Write '0' has no effect.
RW REGION99
Enable protection for region 99. Write '0' has no effect.
RW REGION100
Enable protection for region 100. Write '0' has no effect.
RW REGION101
Enable protection for region 101. Write '0' has no effect.
RW REGION102
Enable protection for region 102. Write '0' has no effect.
RW REGION103
Enable protection for region 103. Write '0' has no effect.
RW REGION104
Enable protection for region 104. Write '0' has no effect.
RW REGION105
Enable protection for region 105. Write '0' has no effect.
RW REGION106
Enable protection for region 106. Write '0' has no effect.
RW REGION107
Enable protection for region 107. Write '0' has no effect.
RW REGION108
Enable protection for region 108. Write '0' has no effect.
RW REGION109
Enable protection for region 109. Write '0' has no effect.
RW REGION110
Enable protection for region 110. Write '0' has no effect.
RW REGION111
Enable protection for region 111. Write '0' has no effect.
RW REGION112
Enable protection for region 112. Write '0' has no effect.
Protection disabled
Page 42
12 BPROT — Block protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
R
S
T
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
Disabled
0
Protection disabled
Enabled
1
Protection enabled
RW REGION113
I H G F E D C B A
Enable protection for region 113. Write '0' has no effect.
RW REGION114
Enable protection for region 114. Write '0' has no effect.
RW REGION115
Enable protection for region 115. Write '0' has no effect.
RW REGION116
Enable protection for region 116. Write '0' has no effect.
RW REGION117
Enable protection for region 117. Write '0' has no effect.
RW REGION118
Enable protection for region 118. Write '0' has no effect.
RW REGION119
Enable protection for region 119. Write '0' has no effect.
RW REGION120
Enable protection for region 120. Write '0' has no effect.
RW REGION121
Enable protection for region 121. Write '0' has no effect.
RW REGION122
Enable protection for region 122. Write '0' has no effect.
RW REGION123
Enable protection for region 123. Write '0' has no effect.
RW REGION124
Enable protection for region 124. Write '0' has no effect.
RW REGION125
Enable protection for region 125. Write '0' has no effect.
RW REGION126
Enable protection for region 126. Write '0' has no effect.
RW REGION127
Enable protection for region 127. Write '0' has no effect.
Page 43
13 FICR — Factory information configuration
registers
13 FICR — Factory information configuration registers
Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by
the user. These registers contain chip-specific information and configuration.
13.1 Registers
Table 17: Instances
Base address
Peripheral
Instance
Description
0x10000000
FICR
FICR
Factory Information Configuration
Configuration
Table 18: Register Overview
Register
Offset
Description
CODEPAGESIZE
0x010
Code memory page size
CODESIZE
0x014
Code memory size
DEVICEID[0]
0x060
Device identifier
DEVICEID[1]
0x064
Device identifier
ER[0]
0x080
Encryption Root, word 0
ER[1]
0x084
Encryption Root, word 1
ER[2]
0x088
Encryption Root, word 2
ER[3]
0x08C
Encryption Root, word 3
IR[0]
0x090
Identity Root, word 0
IR[1]
0x094
Identity Root, word 1
IR[2]
0x098
Identity Root, word 2
IR[3]
0x09C
Identity Root, word 3
DEVICEADDRTYPE
0x0A0
Device address type
DEVICEADDR[0]
0x0A4
Device address 0
DEVICEADDR[1]
0x0A8
Device address 1
INFO.PART
0x100
Part code
INFO.VARIANT
0x104
Part Variant, Hardware version and Production configuration
INFO.PACKAGE
0x108
Package option
INFO.RAM
0x10C
RAM variant
INFO.FLASH
0x110
Flash variant
0x114
Reserved
0x118
Reserved
0x11C
Reserved
TEMP.A0
0x404
Slope definition A0.
TEMP.A1
0x408
Slope definition A1.
TEMP.A2
0x40C
Slope definition A2.
TEMP.A3
0x410
Slope definition A3.
TEMP.A4
0x414
Slope definition A4.
TEMP.A5
0x418
Slope definition A5.
TEMP.B0
0x41C
y-intercept B0.
TEMP.B1
0x420
y-intercept B1.
TEMP.B2
0x424
y-intercept B2.
TEMP.B3
0x428
y-intercept B3.
TEMP.B4
0x42C
y-intercept B4.
TEMP.B5
0x430
y-intercept B5.
TEMP.T0
0x434
Segment end T0.
TEMP.T1
0x438
Segment end T1.
TEMP.T2
0x43C
Segment end T2.
TEMP.T3
0x440
Segment end T3.
TEMP.T4
0x444
Segment end T4.
Page 44
13 FICR — Factory information configuration
registers
Register
Offset
Description
NFC.TAGHEADER0
0x450
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFC.TAGHEADER1
0x454
NFC.TAGHEADER2
0x458
NFC.TAGHEADER3
0x45C
NFCID1_2ND_LAST and NFCID1_LAST.
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
13.1.1 CODEPAGESIZE
Address offset: 0x010
Code memory page size
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
CODEPAGESIZE
Code memory page size
13.1.2 CODESIZE
Address offset: 0x014
Code memory size
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
CODESIZE
Code memory size in number of pages
Total code space is: CODEPAGESIZE * CODESIZE
13.1.3 DEVICEID[0]
Address offset: 0x060
Device identifier
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
DEVICEID
64 bit unique device identifier
DEVICEID[0] contains the least significant bits of the device
identifier. DEVICEID[1] contains the most significant bits of the
device identifier.
13.1.4 DEVICEID[1]
Address offset: 0x064
Device identifier
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
DEVICEID
64 bit unique device identifier
Page 45
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
DEVICEID[0] contains the least significant bits of the device
identifier. DEVICEID[1] contains the most significant bits of the
device identifier.
13.1.5 ER[0]
Address offset: 0x080
Encryption Root, word 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
ER
Encryption Root, word n
13.1.6 ER[1]
Address offset: 0x084
Encryption Root, word 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
ER
Encryption Root, word n
13.1.7 ER[2]
Address offset: 0x088
Encryption Root, word 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
ER
Encryption Root, word n
13.1.8 ER[3]
Address offset: 0x08C
Encryption Root, word 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
ER
Encryption Root, word n
13.1.9 IR[0]
Address offset: 0x090
Identity Root, word 0
Page 46
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
IR
Identity Root, word n
13.1.10 IR[1]
Address offset: 0x094
Identity Root, word 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
IR
Identity Root, word n
13.1.11 IR[2]
Address offset: 0x098
Identity Root, word 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
IR
Identity Root, word n
13.1.12 IR[3]
Address offset: 0x09C
Identity Root, word 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
IR
Identity Root, word n
13.1.13 DEVICEADDRTYPE
Address offset: 0x0A0
Device address type
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Description
Public
0
Public address
Random
1
Random address
DEVICEADDRTYPE
Device address type
13.1.14 DEVICEADDR[0]
Address offset: 0x0A4
Device address 0
Page 47
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
DEVICEADDR
48 bit device address
DEVICEADDR[0] contains the least significant bits of the device
address. DEVICEADDR[1] contains the most significant bits of
the device address. Only bits [15:0] of DEVICEADDR[1] are used.
13.1.15 DEVICEADDR[1]
Address offset: 0x0A8
Device address 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
DEVICEADDR
48 bit device address
DEVICEADDR[0] contains the least significant bits of the device
address. DEVICEADDR[1] contains the most significant bits of
the device address. Only bits [15:0] of DEVICEADDR[1] are used.
13.1.16 INFO.PART
Address offset: 0x100
Part code
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00052832
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 1 0 0 1 0
Value Id
Value
Description
N52832
0x52832
nRF52832
Unspecified
0xFFFFFFFF
Unspecified
PART
Part code
13.1.17 INFO.VARIANT
Address offset: 0x104
Part Variant, Hardware version and Production configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x41414142
Id
RW Field
A
R
0
Value Id
1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0
Value
Description
VARIANT
Part Variant, Hardware version and Production configuration,
encoded as ASCII
AAAA
0x41414141
AAAA
AAAC
0x41414143
AAAC
AABA
0x41414241
AABA
AABB
0x41414242
AABB
AAB0
0x41414230
AAB0
ABB0
0x41424230
ABB0
AAE0
0x41414530
AAE0
ABE0
0x41424530
ABE0
AAGB
0x41414742
AAGB
ABGB
0x41424742
ABGB
AAG0
0x41414730
AAG0
ABG0
0x41424730
ABG0
Page 48
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x41414142
Id
RW Field
0
1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0
Value Id
Value
Description
Unspecified
0xFFFFFFFF
Unspecified
13.1.18 INFO.PACKAGE
Address offset: 0x108
Package option
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00002000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
QF
0x2000
QFxx - 48-pin QFN
CH
0x2001
CHxx - 7x8 WLCSP 56 balls
CI
0x2002
CIxx - 7x8 WLCSP 56 balls
CK
0x2005
CKxx - 7x8 WLCSP 56 balls with backside coating for light
Unspecified
0xFFFFFFFF
PACKAGE
Package option
protection
Unspecified
13.1.19 INFO.RAM
Address offset: 0x10C
RAM variant
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000040
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Value Id
Value
Description
K16
0x10
16 kByte RAM
K32
0x20
32 kByte RAM
K64
0x40
64 kByte RAM
Unspecified
0xFFFFFFFF
Unspecified
RAM
RAM variant
13.1.20 INFO.FLASH
Address offset: 0x110
Flash variant
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000200
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
K128
0x80
128 kByte FLASH
K256
0x100
256 kByte FLASH
K512
0x200
512 kByte FLASH
Unspecified
0xFFFFFFFF
Unspecified
FLASH
Flash variant
13.1.21 TEMP.A0
Address offset: 0x404
Slope definition A0.
Page 49
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x00000320
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0
Value
Description
A
A (slope definition) register.
13.1.22 TEMP.A1
Address offset: 0x408
Slope definition A1.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x00000343
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1
Value
Description
A
A (slope definition) register.
13.1.23 TEMP.A2
Address offset: 0x40C
Slope definition A2.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x0000035D
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 1
Value
Description
A
A (slope definition) register.
13.1.24 TEMP.A3
Address offset: 0x410
Slope definition A3.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x00000400
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Value
Description
A
A (slope definition) register.
13.1.25 TEMP.A4
Address offset: 0x414
Slope definition A4.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x00000452
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0
Value
Description
A
A (slope definition) register.
13.1.26 TEMP.A5
Address offset: 0x418
Slope definition A5.
Page 50
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A
Reset 0x0000037B
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 1 1
Value
Description
A
A (slope definition) register.
13.1.27 TEMP.B0
Address offset: 0x41C
y-intercept B0.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00003FCC
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0
Value
Description
B
B (y-intercept)
13.1.28 TEMP.B1
Address offset: 0x420
y-intercept B1.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00003F98
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0
Value
Description
B
B (y-intercept)
13.1.29 TEMP.B2
Address offset: 0x424
y-intercept B2.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00003F98
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0
Value
Description
B
B (y-intercept)
13.1.30 TEMP.B3
Address offset: 0x428
y-intercept B3.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00000012
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Value
Description
B
B (y-intercept)
13.1.31 TEMP.B4
Address offset: 0x42C
y-intercept B4.
Page 51
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x0000004D
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1
Value
Description
B
B (y-intercept)
13.1.32 TEMP.B5
Address offset: 0x430
y-intercept B5.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00003E10
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0
Value
Description
B
B (y-intercept)
13.1.33 TEMP.T0
Address offset: 0x434
Segment end T0.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x000000E2
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0
Value
Description
T
T (segment end)register.
13.1.34 TEMP.T1
Address offset: 0x438
Segment end T1.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
T
T (segment end)register.
13.1.35 TEMP.T2
Address offset: 0x43C
Segment end T2.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000014
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0
Value
Description
T
T (segment end)register.
13.1.36 TEMP.T3
Address offset: 0x440
Segment end T3.
Page 52
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000019
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1
Value
Description
T
T (segment end)register.
13.1.37 TEMP.T4
Address offset: 0x444
Segment end T4.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000050
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0
Value
Description
T
T (segment end)register.
13.1.38 NFC.TAGHEADER0
Address offset: 0x450
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFF5F
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1
Id
RW Field
Value
A
R
MFGID
Description
B
R
UD1
Unique identifier byte 1
C
R
UD2
Unique identifier byte 2
D
R
UD3
Unique identifier byte 3
Default Manufacturer ID: Nordic Semiconductor ASA has ICM
0x5F
13.1.39 NFC.TAGHEADER1
Address offset: 0x454
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
Value
A
R
UD4
Description
Unique identifier byte 4
B
R
UD5
Unique identifier byte 5
C
R
UD6
Unique identifier byte 6
D
R
UD7
Unique identifier byte 7
13.1.40 NFC.TAGHEADER2
Address offset: 0x458
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
R
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
UD8
Unique identifier byte 8
Page 53
13 FICR — Factory information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
Value
B
R
UD9
Description
Unique identifier byte 9
C
R
UD10
Unique identifier byte 10
D
R
UD11
Unique identifier byte 11
13.1.41 NFC.TAGHEADER3
Address offset: 0x45C
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
Value
A
R
UD12
Description
Unique identifier byte 12
B
R
UD13
Unique identifier byte 13
C
R
UD14
Unique identifier byte 14
D
R
UD15
Unique identifier byte 15
Page 54
14 UICR — User information configuration
registers
14 UICR — User information configuration registers
The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for configuring
user specific settings.
For information on writing UICR registers, see the NVMC — Non-volatile memory controller on page 30 and
Memory on page 24 chapters.
14.1 Registers
Table 19: Instances
Base address
Peripheral
Instance
Description
0x10001000
UICR
UICR
User Information Configuration
Configuration
Table 20: Register Overview
Register
Offset
Description
0x000
Reserved
0x004
Reserved
0x008
Reserved
0x010
Reserved
NRFFW[0]
0x014
Reserved for Nordic firmware design
NRFFW[1]
0x018
Reserved for Nordic firmware design
NRFFW[2]
0x01C
Reserved for Nordic firmware design
NRFFW[3]
0x020
Reserved for Nordic firmware design
NRFFW[4]
0x024
Reserved for Nordic firmware design
NRFFW[5]
0x028
Reserved for Nordic firmware design
NRFFW[6]
0x02C
Reserved for Nordic firmware design
NRFFW[7]
0x030
Reserved for Nordic firmware design
NRFFW[8]
0x034
Reserved for Nordic firmware design
NRFFW[9]
0x038
Reserved for Nordic firmware design
NRFFW[10]
0x03C
Reserved for Nordic firmware design
NRFFW[11]
0x040
Reserved for Nordic firmware design
NRFFW[12]
0x044
Reserved for Nordic firmware design
NRFFW[13]
0x048
Reserved for Nordic firmware design
NRFFW[14]
0x04C
Reserved for Nordic firmware design
NRFHW[0]
0x050
Reserved for Nordic hardware design
NRFHW[1]
0x054
Reserved for Nordic hardware design
NRFHW[2]
0x058
Reserved for Nordic hardware design
NRFHW[3]
0x05C
Reserved for Nordic hardware design
NRFHW[4]
0x060
Reserved for Nordic hardware design
NRFHW[5]
0x064
Reserved for Nordic hardware design
NRFHW[6]
0x068
Reserved for Nordic hardware design
NRFHW[7]
0x06C
Reserved for Nordic hardware design
NRFHW[8]
0x070
Reserved for Nordic hardware design
NRFHW[9]
0x074
Reserved for Nordic hardware design
NRFHW[10]
0x078
Reserved for Nordic hardware design
NRFHW[11]
0x07C
Reserved for Nordic hardware design
CUSTOMER[0]
0x080
Reserved for customer
CUSTOMER[1]
0x084
Reserved for customer
CUSTOMER[2]
0x088
Reserved for customer
CUSTOMER[3]
0x08C
Reserved for customer
CUSTOMER[4]
0x090
Reserved for customer
CUSTOMER[5]
0x094
Reserved for customer
CUSTOMER[6]
0x098
Reserved for customer
Page 55
14 UICR — User information configuration
registers
Register
Offset
Description
CUSTOMER[7]
0x09C
Reserved for customer
CUSTOMER[8]
0x0A0
Reserved for customer
CUSTOMER[9]
0x0A4
Reserved for customer
CUSTOMER[10]
0x0A8
Reserved for customer
CUSTOMER[11]
0x0AC
Reserved for customer
CUSTOMER[12]
0x0B0
Reserved for customer
CUSTOMER[13]
0x0B4
Reserved for customer
CUSTOMER[14]
0x0B8
Reserved for customer
CUSTOMER[15]
0x0BC
Reserved for customer
CUSTOMER[16]
0x0C0
Reserved for customer
CUSTOMER[17]
0x0C4
Reserved for customer
CUSTOMER[18]
0x0C8
Reserved for customer
CUSTOMER[19]
0x0CC
Reserved for customer
CUSTOMER[20]
0x0D0
Reserved for customer
CUSTOMER[21]
0x0D4
Reserved for customer
CUSTOMER[22]
0x0D8
Reserved for customer
CUSTOMER[23]
0x0DC
Reserved for customer
CUSTOMER[24]
0x0E0
Reserved for customer
CUSTOMER[25]
0x0E4
Reserved for customer
CUSTOMER[26]
0x0E8
Reserved for customer
CUSTOMER[27]
0x0EC
Reserved for customer
CUSTOMER[28]
0x0F0
Reserved for customer
CUSTOMER[29]
0x0F4
Reserved for customer
CUSTOMER[30]
0x0F8
Reserved for customer
CUSTOMER[31]
0x0FC
Reserved for customer
PSELRESET[0]
0x200
Mapping of the nRESET function (see POWER chapter for details)
PSELRESET[1]
0x204
Mapping of the nRESET function (see POWER chapter for details)
APPROTECT
0x208
Access port protection
NFCPINS
0x20C
Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
14.1.1 NRFFW[0]
Address offset: 0x014
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.2 NRFFW[1]
Address offset: 0x018
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.3 NRFFW[2]
Address offset: 0x01C
Reserved for Nordic firmware design
Page 56
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.4 NRFFW[3]
Address offset: 0x020
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.5 NRFFW[4]
Address offset: 0x024
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.6 NRFFW[5]
Address offset: 0x028
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.7 NRFFW[6]
Address offset: 0x02C
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.8 NRFFW[7]
Address offset: 0x030
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
Page 57
14 UICR — User information configuration
registers
14.1.9 NRFFW[8]
Address offset: 0x034
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.10 NRFFW[9]
Address offset: 0x038
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.11 NRFFW[10]
Address offset: 0x03C
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.12 NRFFW[11]
Address offset: 0x040
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.13 NRFFW[12]
Address offset: 0x044
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.14 NRFFW[13]
Address offset: 0x048
Reserved for Nordic firmware design
Page 58
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.15 NRFFW[14]
Address offset: 0x04C
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFFW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic firmware design
14.1.16 NRFHW[0]
Address offset: 0x050
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.17 NRFHW[1]
Address offset: 0x054
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.18 NRFHW[2]
Address offset: 0x058
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.19 NRFHW[3]
Address offset: 0x05C
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
Page 59
14 UICR — User information configuration
registers
14.1.20 NRFHW[4]
Address offset: 0x060
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.21 NRFHW[5]
Address offset: 0x064
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.22 NRFHW[6]
Address offset: 0x068
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.23 NRFHW[7]
Address offset: 0x06C
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.24 NRFHW[8]
Address offset: 0x070
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.25 NRFHW[9]
Address offset: 0x074
Reserved for Nordic hardware design
Page 60
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.26 NRFHW[10]
Address offset: 0x078
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.27 NRFHW[11]
Address offset: 0x07C
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW NRFHW
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for Nordic hardware design
14.1.28 CUSTOMER[0]
Address offset: 0x080
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.29 CUSTOMER[1]
Address offset: 0x084
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.30 CUSTOMER[2]
Address offset: 0x088
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
Page 61
14 UICR — User information configuration
registers
14.1.31 CUSTOMER[3]
Address offset: 0x08C
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.32 CUSTOMER[4]
Address offset: 0x090
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.33 CUSTOMER[5]
Address offset: 0x094
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.34 CUSTOMER[6]
Address offset: 0x098
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.35 CUSTOMER[7]
Address offset: 0x09C
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.36 CUSTOMER[8]
Address offset: 0x0A0
Reserved for customer
Page 62
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.37 CUSTOMER[9]
Address offset: 0x0A4
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.38 CUSTOMER[10]
Address offset: 0x0A8
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.39 CUSTOMER[11]
Address offset: 0x0AC
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.40 CUSTOMER[12]
Address offset: 0x0B0
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.41 CUSTOMER[13]
Address offset: 0x0B4
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
Page 63
14 UICR — User information configuration
registers
14.1.42 CUSTOMER[14]
Address offset: 0x0B8
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.43 CUSTOMER[15]
Address offset: 0x0BC
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.44 CUSTOMER[16]
Address offset: 0x0C0
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.45 CUSTOMER[17]
Address offset: 0x0C4
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.46 CUSTOMER[18]
Address offset: 0x0C8
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.47 CUSTOMER[19]
Address offset: 0x0CC
Reserved for customer
Page 64
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.48 CUSTOMER[20]
Address offset: 0x0D0
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.49 CUSTOMER[21]
Address offset: 0x0D4
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.50 CUSTOMER[22]
Address offset: 0x0D8
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.51 CUSTOMER[23]
Address offset: 0x0DC
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.52 CUSTOMER[24]
Address offset: 0x0E0
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
Page 65
14 UICR — User information configuration
registers
14.1.53 CUSTOMER[25]
Address offset: 0x0E4
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.54 CUSTOMER[26]
Address offset: 0x0E8
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.55 CUSTOMER[27]
Address offset: 0x0EC
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.56 CUSTOMER[28]
Address offset: 0x0F0
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.57 CUSTOMER[29]
Address offset: 0x0F4
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.58 CUSTOMER[30]
Address offset: 0x0F8
Reserved for customer
Page 66
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.59 CUSTOMER[31]
Address offset: 0x0FC
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW CUSTOMER
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Reserved for customer
14.1.60 PSELRESET[0]
Address offset: 0x200
Mapping of the nRESET function (see POWER chapter for details)
All PSELRESET registers have to contain the same value for a pin mapping to be valid. If values are not
the same, there will be no nRESET function exposed on a GPIO. As a result, the device will always start
independently of the levels present on any of the GPIOs.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
21
GPIO number P0.n onto which Reset is exposed
Connection
Disconnected
1
Disconnect
Connected
0
Connect
14.1.61 PSELRESET[1]
Address offset: 0x204
Mapping of the nRESET function (see POWER chapter for details)
All PSELRESET registers have to contain the same value for a pin mapping to be valid. If values are not
the same, there will be no nRESET function exposed on a GPIO. As a result, the device will always start
independently of the levels present on any of the GPIOs.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
21
GPIO number P0.n onto which Reset is exposed
Connection
Disconnected
1
Disconnect
Connected
0
Connect
14.1.62 APPROTECT
Address offset: 0x208
Access port protection
Page 67
14 UICR — User information configuration
registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PALL
1
Value Id
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Enable or disable access port protection.
See Debug and trace on page 73 for more information.
Disabled
0xFF
HwDisabled
0x5A
Enabled
0x00
Hardware disable of access port protection for devices where
access port protection is controlled by hardware
Hardware disable of access port protection for devices where
access port protection is controlled by hardware and software
Enable
14.1.63 NFCPINS
Address offset: 0x20C
Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PROTECT
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Description
Disabled
0
Operation as GPIO pins. Same protection as normal GPIO pins.
NFC
1
Operation as NFC antenna pins. Configures the protection for
Setting of pins dedicated to NFC functionality
NFC operation.
Page 68
15 Peripheral interface
15 Peripheral interface
Peripherals are controlled by the CPU by writing to configuration registers and task registers. Peripheral
events are indicated to the CPU by event registers and interrupts if they are configured for a given event.
Task signal from PPI
Peripheral
TASK
write
k
OR
SHORTS
task
Peripheral
core
event
INTEN
m
EVENT m
IRQ signal to NVIC
Event signal to PPI
Figure 10: Tasks, events, shortcuts, and interrupts
15.1 Peripheral ID
Every peripheral is assigned a fixed block of 0x1000 bytes of address space, which is equal to 1024 x 32 bit
registers.
See Instantiation on page 25 for more information about which peripherals are available and where they are
located in the address map.
There is a direct relationship between the peripheral ID and base address. For example, a peripheral with
base address 0x40000000 is assigned ID=0, a peripheral with base address 0x40001000 is assigned ID=1,
and a peripheral with base address 0x4001F000 is assigned ID=31.
Peripherals may share the same ID, which may impose one or more of the following limitations:
•
•
•
Some peripherals share some registers or other common resources.
Operation is mutually exclusive. Only one of the peripherals can be used at a time.
Switching from one peripheral to another must follow a specific pattern (disable the first, then enable the
second peripheral).
15.2 Peripherals with shared ID
In general, and with the exception of ID 0, peripherals sharing an ID and base address may not be used
simultaneously. The user can only enable one at the time on this specific ID.
When switching between two peripherals that share an ID, the user should do the following to prevent
unwanted behavior:
•
Disable the previously used peripheral
Page 69
15 Peripheral interface
•
•
•
•
Remove any PPI connections set up for the peripheral that is being disabled
Clear all bits in the INTEN register, i.e. INTENCLR = 0xFFFFFFFF.
Explicitly configure the peripheral that you enable and do not rely on configuration values that may be
inherited from the peripheral that was disabled.
Enable the now configured peripheral.
For each of the rows in the following table, the instance ID listed is shared by the peripherals in the same
row.
Table 21: Peripherals sharing an ID
Instance
ID 2 (0x40002000)
ID 3 (0x40003000)
ID 4 (0x40004000)
ID 35 (0x40023000)
ID 15 (0x4000F000)
ID 19 (0x40013000)
ID 20 (0x40014000)
ID 21 (0x40015000)
ID 22 (0x40016000)
ID 23 (0x40017000)
ID 24 (0x40018000)
ID 25 (0x40019000)
UARTE
UART
SPIM
SPIM
SPIM
SPIS
SPIS
SPIS
AAR
CCM
COMP
LPCOMP
SWI
SWI
SWI
SWI
SWI
SWI
EGU
EGU
EGU
EGU
EGU
EGU
SPI
SPI
SPI
TWIM
TWIM
TWIS
TWIS
TWI
TWI
15.3 Peripheral registers
Most peripherals feature an ENABLE register. Unless otherwise specified in the relevant chapter, the
peripheral registers (in particular the PSEL registers) must be configured before enabling the peripheral.
Note that the peripheral must be enabled before tasks and events can be used.
15.4 Bit set and clear
Registers with multiple single-bit bit fields may implement the "set-and-clear" pattern. This pattern enables
firmware to set and clear individual bits in a register without having to perform a read-modify-write operation
on the main register.
This pattern is implemented using three consecutive addresses in the register map where the main register
is followed by a dedicated SET and CLR register in that order.
The SET register is used to set individual bits in the main register while the CLR register is used to clear
individual bits in the main register. Writing a '1' to a bit in the SET or CLR register will set or clear the same
bit in the main register respectively. Writing a '0' to a bit in the SET or CLR register has no effect. Reading
the SET or CLR registers returns the value of the main register.
Restriction: The main register may not be visible and hence not directly accessible in all cases.
15.5 Tasks
Tasks are used to trigger actions in a peripheral, for example, to start a particular behavior. A peripheral can
implement multiple tasks with each task having a separate register in that peripheral's task register group.
A task is triggered when firmware writes a '1' to the task register or when the peripheral itself or another
peripheral toggles the corresponding task signal. See Figure 10: Tasks, events, shortcuts, and interrupts on
page 69.
Page 70
15 Peripheral interface
15.6 Events
Events are used to notify peripherals and the CPU about events that have happened, for example, a state
change in a peripheral. A peripheral may generate multiple events with each event having a separate
register in that peripheral’s event register group.
An event is generated when the peripheral itself toggles the corresponding event signal, and the event
register is updated to reflect that the event has been generated. See Figure 10: Tasks, events, shortcuts,
and interrupts on page 69. An event register is only cleared when firmware writes a '0' to it.
Events can be generated by the peripheral even when the event register is set to '1'.
15.7 Shortcuts
A shortcut is a direct connection between an event and a task within the same peripheral. If a shortcut is
enabled, its associated task is automatically triggered when its associated event is generated.
Using a shortcut is the equivalent to making the same connection outside the peripheral and through the
PPI. However, the propagation delay through the shortcut is usually shorter than the propagation delay
through the PPI.
Shortcuts are predefined, which means their connections cannot be configured by firmware. Each shortcut
can be individually enabled or disabled through the shortcut register, one bit per shortcut, giving a maximum
of 32 shortcuts for each peripheral.
15.8 Interrupts
All peripherals support interrupts. Interrupts are generated by events.
A peripheral only occupies one interrupt, and the interrupt number follows the peripheral ID. For example, the
peripheral with ID=4 is connected to interrupt number 4 in the Nested Vectored Interrupt Controller (NVIC).
Using the INTEN, INTENSET and INTENCLR registers, every event generated by a peripheral can be
configured to generate that peripheral’s interrupt. Multiple events can be enabled to generate interrupts
simultaneously. To resolve the correct interrupt source, the event registers in the event group of peripheral
registers will indicate the source.
Some peripherals implement only INTENSET and INTENCLR, and the INTEN register is not available
on those peripherals. Refer to the individual chapters for details. In all cases, however, reading back the
INTENSET or INTENCLR register returns the same information as in INTEN.
Each event implemented in the peripheral is associated with a specific bit position in the INTEN, INTENSET
and INTENCLR registers.
The relationship between tasks, events, shortcuts, and interrupts is shown in Figure 10: Tasks, events,
shortcuts, and interrupts on page 69.
15.8.1 Interrupt clearing
When clearing an interrupt by writing "0" to an event register, or disabling an interrupt using the INTENCLR
register, it can take up to four CPU clock cycles to take effect. This means that an interrupt may reoccur
immediatelly even if a new event has not come, if the program exits an interrupt handler after the interrupt is
cleared or disabled, but before four clock cycles have passed.
Important: To avoid an interrupt reoccurring before a new event has come, the program should
perform a read from one of the peripheral registers, for example, the event register that has been
cleared, or the INTENCLR register that has been used to disable the interrupt.
This will cause a one to three-cycle delay and ensure the interrupt is cleared before exiting the interrupt
handler. Care should be taken to ensure the compiler does not remove the read operation as an
optimization. If the program can guarantee a four-cycle delay after event clear or interrupt disable another
way, then a read of a register is not required.
Page 71
15 Peripheral interface
Page 72
16 Debug and trace
16 Debug and trace
The debug and trace system offers a flexible and powerful mechanism for non-intrusive debugging.
DAP
SWDCLK
External
debugger
CTRL-AP
SW-DP
SWDIO
NVMC
Access Port Protection Enable
DAP bus
interconnect
&
UICR
APPROTECT
AHB-AP
AHB
CxxxPWRUPREQ
CxxxPWRUPRACK
POWER
RAM & flash
CPU
Power
ARM Cortex-M4
TRACECLK
Trace
TRACEDATA[0] / SWO
APB/AHB
ETM
Peripherals
TRACEDATA[1]
TRACEDATA[2]
TPIU
TRACEDATA[3]
Trace
ITM
Figure 11: Debug and trace overview
The main features of the debug and trace system are the following:
•
•
Two-pin serial wire debug (SWD) interface
Flash patch and breakpoint (FPB) unit that supports the following comparators:
•
•
•
•
• Two literal comparators
• Six instruction comparators
Data watchpoint and trace (DWT) unit with four comparators
Instrumentation trace macrocell (ITM)
Embedded trace macrocell (ETM)
Trace port interface unit (TPIU)
•
•
4-bit parallel trace of ITM and ETM trace data
Serial wire output (SWO) trace of ITM data
16.1 DAP - Debug access port
An external debugger can access the device via the DAP.
The debug access port (DAP) implements a standard ARM® CoreSight™ serial wire debug port (SW-DP),
which implements the serial wire debug protocol (SWD). SWD is a two-pin serial interface, see SWDCLK
and SWDIO in Figure 11: Debug and trace overview on page 73.
In addition to the default access port in CPU (AHB-AP), the DAP includes a custom control access port
(CTRL-AP). The CTRL-AP is described in more detail in CTRL-AP - Control access port on page 76.
Note:
•
•
The SWDIO line has an internal pull-up resistor.
The SWDCLK line has an internal pull-down resistor.
16.2 Access port protection
Access port protection blocks the debugger from read and write access to all CPU registers and memorymapped addresses when enabled.
Page 73
16 Debug and trace
Access port protection is enabled and disabled differently depending on the build code of the device.
16.2 Access port protection controlled by hardware
This information refers to build codes Fxx and earlier.
By default, access port protection is disabled.
Access port protection is enabled by writing UICR.APPROTECT to Enabled and performing any reset. See
Reset on page 85 for more information.
Access port protection is disabled by issuing an ERASEALL command via CTRL-AP. This command will
erase the flash, UICR, and RAM, including UICR.APPROTECT. Erasing UICR will set UICR.APPROTECT
value to Disabled. CTRL-AP is described in more detail in CTRL-AP - Control access port on page 76.
16.2 Access port protection controlled by hardware and software
This information refers to build codes Gxx and later.
By default, access port protection is enabled.
Access port protection is disabled by issuing an ERASEALL command via CTRL-AP. Read CTRLAP.APPROTECTSTATUS to ensure that access port protection is disabled, and repeat the ERASEALL
command if needed. This command will erase the flash, UICR, and RAM. CTRL-AP is described in more
detail in CTRL-AP - Control access port on page 76. Access port protection will remain disabled until one
of the following occurs:
•
•
•
•
Pin reset
Power or brownout reset
Watchdog reset if not in Debug Interface Mode, see Debug Interface mode on page 77
Wake from System OFF if not in Emulated System OFF
To keep access port protection disabled, the following actions must be performed:
•
•
Program UICR.APPROTECT to HwDisabled. This disables the hardware part of the access port
protection scheme after the first reset of any type. The hardware part of the access port protection will
stay disabled as long as UICR.APPROTECT is not overwritten.
Firmware must write APPROTECT.DISABLE to SwDisable. This disables the software part of the
access port protection scheme.
Note: Register APPROTECT.DISABLE is reset after pin reset, power or brownout reset, watchdog
reset, or wake from System OFF as mentioned above.
The following figure is an example on how a device with access port protection enabled can be erased,
programmed, and configured to allow debugging. Operations sent from debugger as well as registers written
by firmware will affect the access port state.
Debugger
Pi
CR =
U I CT
e
d
r i t TE l e
W P R O i s ab
AP D
Hw
m
ra e
o g ar
Pr m w
fi r
re
se
t
Open
n
P
-A L
R L AL
CT A S E
ER
Closed
Closed Open
Access port state
Write APPROTECT.DISABLE =
SwDisable
Firmware
Figure 12: Access port unlocking
Page 74
16 Debug and trace
Access port protection is enabled when the disabling conditions are not present. For additional security,
it is recommended to write Enabled to UICR.APPROTECT, and have firmware write Force to
APPROTECT.FORCEPROTECT. This is illustrated in the following figure.
Note: Register APPROTECT.FORCEPROTECT is reset after any reset.
Debugger
Pi
CR =
U I CT
e
r i t TE d
W P R O ble
a
A P En
n
re
se
t
m
ra e
o g ar
Pr m w
fi r
P
-A L
R L AL
CT A S E
ER
Closed
Open
Closed
Access port state
Write APPROTECT.FORCEPROTECT =
Force
Firmware
Figure 13: Force access port protection
16.2.1 Registers
Table 22: Instances
Base address
Peripheral
Instance
Description
0x40000000
APPROTECT
APPROTECT
APPROTECT control
Configuration
Table 23: Register Overview
Register
Offset
Description
FORCEPROTECT
0x550
Software force enable APPROTECT mechanism until next reset.
DISABLE
0x558
This register can only be written once.
Software disable APPROTECT mechanism
FORCEPROTECT
Address offset: 0x550
Software force enable APPROTECT mechanism until next reset.
This register can only be written once.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW FORCEPROTECT
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Force
0x0
Description
Write 0x0 to force enable APPROTECT mechanism
Software force enable APPROTECT mechanism
DISABLE
Address offset: 0x558
Software disable APPROTECT mechanism
Page 75
16 Debug and trace
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DISABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
SwDisable
0x5A
Description
Software disable APPROTECT mechanism
Software disable APPROTECT mechanism
16.3 CTRL-AP - Control access port
The control access port (CTRL-AP) is a custom access port that enables control of the device when other
access ports in the DAP are disabled by the access port protection.
Access port protection is described in more detail in Access port protection on page 73.
Control access port has the following features:
•
•
Soft reset - see Reset on page 85 for more information
Disabling of access port protection - device control is allowed through CTRL-AP even when all other
access ports in DAP are disabled by access port protection
16.3.1 Registers
Table 24: Register Overview
Register
Offset
Description
RESET
0x000
Soft reset triggered through CTRL-AP
ERASEALL
0x004
Erase all
ERASEALLSTATUS
0x008
Status register for the ERASEALL operation
APPROTECTSTATUS
0x00C
Status register for access port protection
IDR
0x0FC
CTRL-AP identification register, IDR
RESET
Address offset: 0x000
Soft reset triggered through CTRL-AP
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW RESET
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Soft reset triggered through CTRL-AP. See Reset behavior in
POWER chapter for more details.
NoReset
0
Reset is not active
Reset
1
Reset is active. Device is held in reset.
ERASEALL
Address offset: 0x004
Erase all
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
W
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NoOperation
0
No operation
Erase
1
Erase all flash and RAM
ERASEALL
Erase all flash and RAM
ERASEALLSTATUS
Address offset: 0x008
Page 76
16 Debug and trace
Status register for the ERASEALL operation
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Ready
0
ERASEALL is ready
Busy
1
ERASEALL is busy (on-going)
ERASEALLSTATUS
Status register for the ERASEALL operation
APPROTECTSTATUS
Address offset: 0x00C
Status register for access port protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
0
Access port protection enabled
Disabled
1
Access port protection not enabled
APPROTECTSTATUS
Status register for access port protection
IDR
Address offset: 0x0FC
CTRL-AP identification register, IDR
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E
E E E D D D D C C C C C C C B B B B
Reset 0x02880000
0
0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
R
APID
B
R
CLASS
Value Id
Value
A A A A A A A A
Description
AP identification
Access port (AP) class
NotDefined
0x0
No defined class
MEMAP
0x8
Memory access port
C
R
JEP106ID
JEDEC JEP106 identity code
D
R
JEP106CONT
JEDEC JEP106 continuation code
E
R
REVISION
Revision
16.3.2 Electrical specification
Control access port
Symbol
Description
Min.
Typ.
Max.
Units
Rpull
Internal SWDIO and SWDCLK pull up/down resistance
..
..
..
kΩ
fSWDCLK
SWDCLK frequency
..
..
..
MHz
16.4 Debug Interface mode
Before an external debugger can access either CPU's access port (AHB-AP) or the control access port
(CTRL-AP), the debugger must first request the device to power up via CxxxPWRUPREQ in the SWJ-DP.
If the device is in System OFF when power is requested via CxxxPWRUPREQ, the system will wake up and
the DIF flag in RESETREAS on page 88 will be set. The device is in the Debug Interface mode as long
as the debugger is requesting power via CxxxPWRUPREQ. Once the debugger stops requesting power
via CxxxPWRUPREQ, the device is back in normal mode. Some peripherals behave differently in Debug
Interface mode compared to normal mode. These differences are described in more detail in the chapters of
the peripherals that are affected.
Page 77
16 Debug and trace
When a debug session is over, the external debugger must make sure to put the device back into normal
mode since the overall power consumption is higher in Debug Interface mode than in normal mode.
For details on how to use the debug capabilities, read the debug documentation of your IDE.
16.5 Real-time debug
The nRF52832 supports real-time debugging.
Real-time debugging allows interrupts to execute to completion in real time when breakpoints are set in
Thread mode or lower priority interrupts. This enables developers to set breakpoints and single-step through
the code without the risk of real-time event-driven threads running at higher priority failing. For example,
this enables the device to continue to service the high-priority interrupts of an external controller or sensor
without failure or loss of state synchronization while the developer steps through code in a low-priority
thread.
16.6 Trace
The device supports ETM and ITM trace.
Trace data from the ETM and the ITM is sent to an external debugger via a 4-bit wide parallel trace port
interface unit (TPIU), see TRACEDATA[0] through TRACEDATA[3] and TRACECLK in Figure 11: Debug
and trace overview on page 73.
In addition to parallel trace, the TPIU supports serial trace via the serial wire output (SWO) trace protocol.
Parallel and serial trace cannot be used at the same time. ETM trace is only supported in Parallel Trace
mode, while ITM trace is supported in both Parallel and Serial Trace modes.
For details on how to use the trace capabilities, read the debug documentation of your IDE.
TPIU's trace pins are multiplexed with GPIOs. SWO and TRACEDATA[0] use the same GPIO. See Pin
assignments on page 14 for more information.
Trace speed is configured in register TRACECONFIG on page 111. The speed of the trace pins depends
on the DRIVE setting of the GPIOs that the trace pins are multiplexed with. Only S0S1 and H0H1 drives are
suitable for debugging. S0S1 is the default DRIVE setting at reset. If parallel or serial trace port signals are
not fast enough with the default settings, all GPIOs in use for tracing should be set to high drive (H0H1). The
DRIVE setting for these GPIOs should not be overwritten by firmware during the debugging session.
16.6.1 Electrical specification
Trace port
Symbol
Description
Min.
Tcyc
Clock period as defined by Arm in the Timing specifications for
62.5
Trace Port Physical Interface of the Embedded Trace Macrocell
Architecture Specification
Page 78
Typ.
Max.
Units
500
ns
17 Power and clock management
17 Power and clock management
Power and clock management in nRF52832 is optimized for ultra-low power applications.
The core of the power and clock management system is the Power Management Unit (PMU) illustrated in
Figure 14: Power Management Unit on page 79.
MCU
CPU
External
Power sources
Internal
voltage
regulators
PMU
Memory
External
crystals
Internal
oscillators
Peripheral
Figure 14: Power Management Unit
The user application is not required to actively control power and clock, since the PMU is able to
automatically detect which resources are required by the different components in the system at any given
time. The PMU will continuously optimize the system based on this information to achieve the lowest power
consumption possible without user interaction.
17.1 Current consumption scenarios
As the system is being constantly tuned by the PMU, estimating the energy consumption of an application
can be challenging if the designer is not able to do measurements on the hardware directly. See Electrical
specification on page 79 for application scenarios showing average current drawn from the VDD supply.
Each scenario specifies a set of active operations and conditions applying to the given scenario. Table 25:
Current consumption scenarios, common conditions on page 79 shows the conditions used for a scenario
unless otherwise is stated in the scenario description.
Table 25: Current consumption scenarios, common conditions
Condition
VDD
Temperature
CPU
Peripherals
Clock
Regulator
Value
3V
25°C
WFI/WFE sleep
All idle
Not running
DCDC
17.1.1 Electrical specification
Current consumption: Radio
Symbol
Description
IRADIO_TX0
0 dBm TX @ 1 Mb/s Bluetooth Low Energy mode, Clock = HFXO
Min.
Typ.
7.1
Max.
Units
mA
IRADIO_TX1
-40 dBm TX @ 1 Mb/s Bluetooth Low Energy mode, Clock =
4.1
mA
6.5
mA
HFXO
IRADIO_RX0
Radio RX @ 1 Mb/s Bluetooth Low Energy mode, Clock = HFXO
Page 79
17 Power and clock management
Current consumption: Radio protocol configurations
Symbol
Description
IS0
CPU running CoreMark from Flash, Radio 0 dBm TX @ 1 Mb/s
Min.
Typ.
Max.
Units
9.2
mA
9.2
mA
Bluetooth Low Energy mode, Clock = HFXO, Cache enabled
IS1
CPU running CoreMark from Flash, Radio RX @ 1 Mb/s
Bluetooth Low Energy mode, Clock = HFXO, Cache enabled
Current consumption: Ultra-low power
Symbol
Description
ION_RAMOFF_EVENT
System ON, No RAM retention, Wake on any event
Min.
1.2
µA
ION_RAMON_EVENT
System ON, Full RAM retention, Wake on any event
1.5
µA
ION_RAMOFF_RTC
System ON, No RAM retention, Wake on RTC
1.9
µA
IOFF_RAMOFF_RESET
System OFF, No RAM retention, Wake on reset
0.3
µA
IOFF_RAMOFF_GPIO
System OFF, No RAM retention, Wake on GPIO
0.3
µA
IOFF_RAMOFF_LPCOMP
System OFF, No RAM retention, Wake on LPCOMP
1.9
µA
IOFF_RAMOFF_NFC
System OFF, No RAM retention, Wake on NFC field
0.7
µA
IOFF_RAMON_RESET
System OFF, Full 64 kB RAM retention, Wake on reset
0.7
µA
Page 80
Typ.
Max.
Units
18 POWER — Power supply
18 POWER — Power supply
This device has the following power supply features:
•
•
•
•
•
•
•
On-chip LDO and DC/DC regulators
Global System ON/OFF modes
Individual RAM section power control for all system modes
Analog or digital pin wakeup from System OFF
Supervisor HW to manage power on reset, brownout, and power fail
Auto-controlled refresh modes for LDO and DC/DC regulators to maximize efficiency
Automatic switching between LDO and DC/DC regulator based on load to maximize efficiency
Note: Two additional external passive components are required to use the DC/DC regulator.
18.1 Regulators
The following internal power regulator alternatives are supported:
•
•
Internal LDO regulator
Internal DC/DC regulator
The LDO is the default regulator.
The DC/DC regulator can be used as an alternative to the LDO regulator and is enabled through the
DCDCEN on page 91 register. Using the DC/DC regulator will reduce current consumption compared to
when using the LDO regulator, but the DC/DC regulator requires an external LC filter to be connected, as
shown in Figure 16: DC/DC regulator setup on page 82.
POWER
DCDCEN
REG
Supply
LDO
1.3V System power
VDD
DC/DC
DCC
Figure 15: LDO regulator setup
Page 81
DEC4
GND
18 POWER — Power supply
POWER
DCDCEN
REG
Supply
LDO
1.3V System power
VDD
DC/DC
DCC
DEC4
GND
Figure 16: DC/DC regulator setup
18.2 System OFF mode
System OFF is the deepest power saving mode the system can enter. In this mode, the system’s core
functionality is powered down and all ongoing tasks are terminated.
The device can be put into System OFF mode using the POWER register interface. When in System OFF
mode, the device can be woken up through one of the following signals:
1.
2.
3.
4.
The DETECT signal, optionally generated by the GPIO peripheral
The ANADETECT signal, optionally generated by the LPCOMP module
The SENSE signal, optionally generated by the NFC module to “wake-on-field”
A reset
When the system wakes up from System OFF mode, it gets reset. For more details, see Reset behavior on
page 86.
One or more RAM sections can be retained in System OFF mode depending on the settings in the
RAM[n].POWER registers.
RAM[n].POWER are retained registers, see Reset behavior. Note that these registers are usually overwritten
by the startup code provided with the nRF application examples.
Before entering System OFF mode, the user must make sure that all on-going EasyDMA transactions have
been completed. This is usually accomplished by making sure that the EasyDMA enabled peripheral is not
active when entering System OFF.
18.2.1 Emulated System OFF mode
If the device is in debug interface mode, System OFF will be emulated to secure that all required resources
needed for debugging are available during System OFF.
See Debug and trace on page 73 for more information. Required resources needed for debugging include
the following key components: Debug and trace on page 73, CLOCK — Clock control on page 104,
POWER — Power supply on page 81, NVMC — Non-volatile memory controller on page 30, CPU, Flash,
and RAM. Since the CPU is kept on in an emulated System OFF mode, it is recommended to add an infinite
loop directly after entering System OFF, to prevent the CPU from executing code that normally should not be
executed.
Page 82
18 POWER — Power supply
18.3 System ON mode
System ON is the default state after power-on reset. In System ON, all functional blocks such as the CPU or
peripherals, can be in IDLE or RUN mode, depending on the configuration set by the software and the state
of the application executing.
Register RESETREAS on page 88 provides information about the source that caused the wakeup or
reset.
The system can switch on and off the appropriate internal power sources, depending on how much power is
needed at any given time. The power requirement of a peripheral is directly related to its activity level, and
the activity level of a peripheral is usually raised and lowered when specific tasks are triggered or events are
generated.
18.3.1 Sub power modes
In System ON mode, when both the CPU and all the peripherals are in IDLE mode, the system can reside in
one of the two sub power modes.
The sub power modes are:
•
•
Constant latency
Low power
In constant latency mode the CPU wakeup latency and the PPI task response will be constant and kept at
a minimum. This is secured by forcing a set of base resources on while in sleep. The advantage of having
a constant and predictable latency will be at the cost of having increased power consumption. The constant
latency mode is selected by triggering the CONSTLAT task.
In low power mode the automatic power management system, described in System ON mode on page
83, ensures the most efficient supply option is chosen to save the most power. The advantage of having
the lowest power possible will be at the cost of having varying CPU wakeup latency and PPI task response.
The low power mode is selected by triggering the LOWPWR task.
When the system enters System ON mode, it will, by default, reside in the low power sub-power mode.
18.4 Power supply supervisor
The power supply supervisor initializes the system at power-on and provides an early warning of impending
power failure.
In addition, the power supply supervisor puts the system in a reset state if the supply voltage is too low for
safe operation (brownout). The power supply supervisor is illustrated in Figure 17: Power supply supervisor
on page 84.
Page 83
18 POWER — Power supply
VDD
C
Power on reset
R
VBOR
POFCON
Brownout reset
1.7V
...........
MUX
POFWARN
Vpof
2.8V
Figure 17: Power supply supervisor
18.4.1 Power-fail comparator
The power-fail comparator (POF) can provide the CPU with an early warning of impending power failure. It
will not reset the system, but give the CPU time to prepare for an orderly power-down.
The comparator features a hysteresis of VHYST, as illustrated in Figure 18: Power-fail comparator (BOR =
Brownout reset) on page 84. The threshold VPOF is set in register POFCON on page 89. If the POF
is enabled and the supply voltage falls below VPOF, the POFWARN event will be generated. This event will
also be generated if the supply voltage is already below VPOF at the time the POF is enabled, or if VPOF is reconfigured to a level above the supply voltage.
If power-fail warning is enabled and the supply voltage is below VPOF the power-fail comparator will prevent
the NVMC from performing write operations to the NVM. See NVMC — Non-volatile memory controller on
page 30 for more information about the NVMC.
VDD
VPOF+VHYST
VPOF
1.7V
POFWARN
POFWARN
MCU
t
BOR
Figure 18: Power-fail comparator (BOR = Brownout reset)
To save power, the power-fail comparator is not active in System OFF or in System ON when HFCLK is not
running.
Page 84
18 POWER — Power supply
18.5 RAM sections
RAM section power control is used for retention in System OFF mode and for powering down unused
sections in System ON mode.
Each RAM section can power up and down independently in both System ON and System OFF mode. See
chapter Memory on page 24 for more information on RAM sections.
18.6 Reset
There are multiple sources that may trigger a reset.
After a reset has occurred, register RESETREAS can be read to determine which source generated the
reset.
18.6.1 Power-on reset
The power-on reset generator initializes the system at power-on.
The system is held in reset state until the supply has reached the minimum operating voltage and the internal
voltage regulators have started.
A step increase in supply voltage of 300 mV or more, with rise time of 300 ms or less, within the valid supply
range, may result in a system reset.
18.6.2 Pin reset
A pin reset is generated when the physical reset pin on the device is asserted.
Pin reset is configured via the PSELRESET[0] and PSELRESET[1] registers.
Note: Pin reset is not available on all pins.
18.6.3 Wakeup from System OFF mode reset
The device is reset when it wakes up from System OFF mode.
The DAP is not reset following a wake up from System OFF mode if the device is in debug interface mode.
Refer to chapter Debug and trace on page 73 for more information.
18.6.4 Soft reset
A soft reset is generated when the SYSRESETREQ bit of the Application Interrupt and Reset Control
Register (AIRCR register) in the ARM® core is set.
Refer to ARM documentation for more details.
A soft reset can also be generated via the RESET on page 76 register in the CTRL-AP.
18.6.5 Watchdog reset
A Watchdog reset is generated when the watchdog times out.
Refer to chapter WDT — Watchdog timer on page 413 for more information.
18.6.6 Brown-out reset
The brown-out reset generator puts the system in reset state if the supply voltage drops below the brownout
reset (BOR) threshold.
Refer to section Power fail comparator on page 102 for more information.
Page 85
18 POWER — Power supply
18.7 Retained registers
A retained register is a register that will retain its value in System OFF mode and through a reset, depending
on reset source. See individual peripheral chapters for information of which registers are retained for the
various peripherals.
18.8 Reset behavior
Reset source
6
CPU lockup
Soft reset
Wakeup from System OFF mode
reset
Watchdog reset 9
Pin reset
Brownout reset
Power on reset
Reset target
CPU
Peripherals
GPIO
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Debuga
SWJ-DP
RAM
x7
x8
x
x
x
x
x
x
x
x
x
x
WDT
Retained
registers
x
x
x
x
x
x
x
x
RESETREAS
x
x
Note: The RAM is never reset, but depending on reset source, RAM content may be corrupted.
18.9 Registers
Table 26: Instances
Base address
Peripheral
Instance
Description
0x40000000
POWER
POWER
Power control
Configuration
Table 27: Register Overview
Register
Offset
Description
TASKS_CONSTLAT
0x078
Enable constant latency mode
TASKS_LOWPWR
0x07C
Enable low power mode (variable latency)
EVENTS_POFWARN
0x108
Power failure warning
EVENTS_SLEEPENTER
0x114
CPU entered WFI/WFE sleep
EVENTS_SLEEPEXIT
0x118
CPU exited WFI/WFE sleep
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
RESETREAS
0x400
Reset reason
RAMSTATUS
0x428
RAM status register
SYSTEMOFF
0x500
System OFF register
POFCON
0x510
Power failure comparator configuration
GPREGRET
0x51C
General purpose retention register
GPREGRET2
0x520
General purpose retention register
RAMON
0x524
RAM on/off register (this register is retained)
Deprecated
RAMONB
0x554
RAM on/off register (this register is retained)
Deprecated
DCDCEN
0x578
DC/DC enable register
RAM[0].POWER
0x900
RAM0 power control register
a
6
7
8
9
Deprecated
All debug components excluding SWJ-DP. See Debug and trace on page 73 chapter for more
information about the different debug components in the system.
Reset from CPU lockup is disabled if the device is in debug interface mode. CPU lockup is not possible in System
OFF.
The Debug components will not be reset if the device is in debug interface mode.
RAM is not reset on wakeup from OFF mode, but depending on settings in the RAM register parts, or the whole
RAM, may not be retained after the device has entered System OFF mode.
Watchdog reset is not available in System OFF.
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18 POWER — Power supply
Register
Offset
Description
RAM[0].POWERSET
0x904
RAM0 power control set register
RAM[0].POWERCLR
0x908
RAM0 power control clear register
RAM[1].POWER
0x910
RAM1 power control register
RAM[1].POWERSET
0x914
RAM1 power control set register
RAM[1].POWERCLR
0x918
RAM1 power control clear register
RAM[2].POWER
0x920
RAM2 power control register
RAM[2].POWERSET
0x924
RAM2 power control set register
RAM[2].POWERCLR
0x928
RAM2 power control clear register
RAM[3].POWER
0x930
RAM3 power control register
RAM[3].POWERSET
0x934
RAM3 power control set register
RAM[3].POWERCLR
0x938
RAM3 power control clear register
RAM[4].POWER
0x940
RAM4 power control register
RAM[4].POWERSET
0x944
RAM4 power control set register
RAM[4].POWERCLR
0x948
RAM4 power control clear register
RAM[5].POWER
0x950
RAM5 power control register
RAM[5].POWERSET
0x954
RAM5 power control set register
RAM[5].POWERCLR
0x958
RAM5 power control clear register
RAM[6].POWER
0x960
RAM6 power control register
RAM[6].POWERSET
0x964
RAM6 power control set register
RAM[6].POWERCLR
0x968
RAM6 power control clear register
RAM[7].POWER
0x970
RAM7 power control register
RAM[7].POWERSET
0x974
RAM7 power control set register
RAM[7].POWERCLR
0x978
RAM7 power control clear register
18.9.1 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B
Reset 0x00000000
Id
RW Field
A
RW POFWARN
0
Value Id
Value
Description
Write '1' to Enable interrupt for POFWARN event
See EVENTS_POFWARN
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SLEEPENTER
Write '1' to Enable interrupt for SLEEPENTER event
See EVENTS_SLEEPENTER
C
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SLEEPEXIT
Write '1' to Enable interrupt for SLEEPEXIT event
See EVENTS_SLEEPEXIT
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
18.9.2 INTENCLR
Address offset: 0x308
Disable interrupt
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18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B
Reset 0x00000000
Id
RW Field
A
RW POFWARN
0
Value Id
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for POFWARN event
See EVENTS_POFWARN
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SLEEPENTER
Write '1' to Disable interrupt for SLEEPENTER event
See EVENTS_SLEEPENTER
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SLEEPEXIT
Write '1' to Disable interrupt for SLEEPEXIT event
See EVENTS_SLEEPEXIT
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
18.9.3 RESETREAS
Address offset: 0x400
Reset reason
Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing '1' to it. If none of
the reset sources are flagged, this indicates that the chip was reset from the on-chip reset generator, which
will indicate a power-on-reset or a brownout reset.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G F E
Reset 0x00000000
Id
RW Field
A
RW RESETPIN
B
C
D
E
0
Value Id
Value
Description
NotDetected
0
Not detected
Detected
1
Detected
NotDetected
0
Not detected
Detected
1
Detected
NotDetected
0
Not detected
Detected
1
Detected
NotDetected
0
Not detected
Detected
1
Detected
Reset from pin-reset detected
RW DOG
Reset from watchdog detected
RW SREQ
Reset from soft reset detected
RW LOCKUP
Reset from CPU lock-up detected
RW OFF
Reset due to wake up from System OFF mode when wakeup is
triggered from DETECT signal from GPIO
F
NotDetected
0
Not detected
Detected
1
Detected
RW LPCOMP
Reset due to wake up from System OFF mode when wakeup is
triggered from ANADETECT signal from LPCOMP
G
D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NotDetected
0
Not detected
Detected
1
Detected
RW DIF
Reset due to wake up from System OFF mode when wakeup is
triggered from entering into debug interface mode
NotDetected
0
Not detected
Detected
1
Detected
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18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G F E
Reset 0x00000000
Id
RW Field
H
RW NFC
0
Value Id
D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Reset due to wake up from System OFF mode by NFC field
detect
NotDetected
0
Not detected
Detected
1
Detected
18.9.4 RAMSTATUS ( Deprecated )
Address offset: 0x428
RAM status register
Since this register is deprecated the following substitutions have been made: RAM block 0 is equivalent to
a block comprising RAM0.S0 and RAM1.S0, RAM block 1 is equivalent to a block comprising RAM2.S0 and
RAM3.S0, RAM block 2 is equivalent to a block comprising RAM4.S0 and RAM5.S0 and RAM block 3 is
equivalent to a block comprising RAM6.S0 and RAM7.S0. A RAM block field will indicate ON as long as any
of the RAM sections associated with a block are on.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C B A
Reset 0x00000000
Id
RW Field
A
R
B
C
D
R
R
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RAMBLOCK0
RAM block 0 is on or off/powering up
RAMBLOCK1
RAM block 1 is on or off/powering up
RAMBLOCK2
RAM block 2 is on or off/powering up
RAMBLOCK3
RAM block 3 is on or off/powering up
18.9.5 SYSTEMOFF
Address offset: 0x500
System OFF register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
W
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Enter
1
Description
SYSTEMOFF
Enable System OFF mode
Enable System OFF mode
18.9.6 POFCON
Address offset: 0x510
Power failure comparator configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B B B B A
Reset 0x00000000
Id
RW Field
A
RW POF
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Disabled
0
Description
Enable or disable power failure comparator
Disable
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18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B B B B A
Reset 0x00000000
Id
B
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Enable
V17
4
Set threshold to 1.7 V
V18
5
Set threshold to 1.8 V
V19
6
Set threshold to 1.9 V
V20
7
Set threshold to 2.0 V
V21
8
Set threshold to 2.1 V
V22
9
Set threshold to 2.2 V
V23
10
Set threshold to 2.3 V
V24
11
Set threshold to 2.4 V
V25
12
Set threshold to 2.5 V
V26
13
Set threshold to 2.6 V
V27
14
Set threshold to 2.7 V
V28
15
Set threshold to 2.8 V
RW THRESHOLD
Power failure comparator threshold setting
18.9.7 GPREGRET
Address offset: 0x51C
General purpose retention register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW GPREGRET
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
General purpose retention register
This register is a retained register
18.9.8 GPREGRET2
Address offset: 0x520
General purpose retention register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW GPREGRET
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
General purpose retention register
This register is a retained register
18.9.9 RAMON ( Deprecated )
Address offset: 0x524
RAM on/off register (this register is retained)
Since this register is deprecated the following substitutions have been made: RAM block 0 is equivalent to
a block comprising RAM0.S0 and RAM0.S1 and RAM block 1 is equivalent to a block comprising RAM1.S0
and RAM1.S1. For new designs it is recommended to use the POWER.RAM-0.POWER and its sibling
registers instead.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x00000003
Id
RW Field
A
RW ONRAM0
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Value Id
Value
RAM0Off
0
Description
Keep RAM block 0 on or off in system ON Mode
Off
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18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x00000003
Id
B
C
D
RW Field
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Value Id
Value
Description
RAM0On
1
On
RAM1Off
0
Off
RAM1On
1
On
RAM0Off
0
Off
RAM0On
1
On
RAM1Off
0
Off
RAM1On
1
On
RW ONRAM1
Keep RAM block 1 on or off in system ON Mode
RW OFFRAM0
Keep retention on RAM block 0 when RAM block is switched off
RW OFFRAM1
Keep retention on RAM block 1 when RAM block is switched off
18.9.10 RAMONB ( Deprecated )
Address offset: 0x554
RAM on/off register (this register is retained)
Since this register is deprecated the following substitutions have been made: RAM block 2 is equivalent to
a block comprising RAM2.S0 and RAM2.S1 and RAM block 3 is equivalent to a block comprising RAM3.S0
and RAM3.S1. For new designs it is recommended to use the POWER.RAM-0.POWER and its sibling
registers instead.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x00000003
Id
RW Field
A
RW ONRAM2
B
C
D
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Value Id
Value
Description
RAM2Off
0
Off
RAM2On
1
On
RAM3Off
0
Off
RAM3On
1
On
RAM2Off
0
Off
RAM2On
1
On
RAM3Off
0
Off
RAM3On
1
On
Keep RAM block 2 on or off in system ON Mode
RW ONRAM3
Keep RAM block 3 on or off in system ON Mode
RW OFFRAM2
Keep retention on RAM block 2 when RAM block is switched off
RW OFFRAM3
Keep retention on RAM block 3 when RAM block is switched off
18.9.11 DCDCEN
Address offset: 0x578
DC/DC enable register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW DCDCEN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Enable or disable DC/DC converter
18.9.12 RAM[0].POWER
Address offset: 0x900
RAM0 power control register
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18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
18.9.13 RAM[0].POWERSET
Address offset: 0x904
RAM0 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM0 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM0 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.14 RAM[0].POWERCLR
Address offset: 0x908
RAM0 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Description
S0POWER
Keep RAM section S0 of RAM0 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM0 on or off in System ON mode
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18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
C
RW Field
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Description
Off
1
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.9.15 RAM[1].POWER
Address offset: 0x910
RAM1 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
18.9.16 RAM[1].POWERSET
Address offset: 0x914
RAM1 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM1 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM1 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
On
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18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
D
W
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.17 RAM[1].POWERCLR
Address offset: 0x918
RAM1 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM1 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM1 on or off in System ON mode
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.9.18 RAM[2].POWER
Address offset: 0x920
RAM2 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
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18 POWER — Power supply
18.9.19 RAM[2].POWERSET
Address offset: 0x924
RAM2 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM2 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM2 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.20 RAM[2].POWERCLR
Address offset: 0x928
RAM2 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM2 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM2 on or off in System ON mode
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.9.21 RAM[3].POWER
Address offset: 0x930
RAM3 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
Page 95
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
18.9.22 RAM[3].POWERSET
Address offset: 0x934
RAM3 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM3 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM3 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.23 RAM[3].POWERCLR
Address offset: 0x938
RAM3 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM3 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM3 on or off in System ON mode
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
Off
Page 96
18 POWER — Power supply
18.9.24 RAM[4].POWER
Address offset: 0x940
RAM4 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
18.9.25 RAM[4].POWERSET
Address offset: 0x944
RAM4 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM4 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM4 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
On
18.9.26 RAM[4].POWERCLR
Address offset: 0x948
RAM4 power control clear register
When read, this register will return the value of the POWER register.
Page 97
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM4 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM4 on or off in System ON mode
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.9.27 RAM[5].POWER
Address offset: 0x950
RAM5 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
18.9.28 RAM[5].POWERSET
Address offset: 0x954
RAM5 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM5 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM5 on or off in System ON mode
On
Page 98
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
C
W
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.29 RAM[5].POWERCLR
Address offset: 0x958
RAM5 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM5 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM5 on or off in System ON mode
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.9.30 RAM[6].POWER
Address offset: 0x960
RAM6 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
Off
Page 99
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Description
On
1
On
18.9.31 RAM[6].POWERSET
Address offset: 0x964
RAM6 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM6 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM6 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.32 RAM[6].POWERCLR
Address offset: 0x968
RAM6 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM6 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM6 on or off in System ON mode
Off
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.9.33 RAM[7].POWER
Address offset: 0x970
RAM7 power control register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
RW S0POWER
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
Keep RAM section S0 ON or OFF in System ON mode.
Page 100
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S0RETENTION.
All RAM sections will be OFF in System OFF mode.
B
Off
0
Off
On
1
On
RW S1POWER
Keep RAM section S1 ON or OFF in System ON mode.
RAM sections are always retained when ON, but can also be
retained when OFF dependent on the settings in S1RETENTION.
All RAM sections will be OFF in System OFF mode.
C
D
Off
0
Off
On
1
On
Off
0
Off
On
1
On
Off
0
Off
On
1
On
RW S0RETENTION
Keep retention on RAM section S0 when RAM section is in OFF
RW S1RETENTION
Keep retention on RAM section S1 when RAM section is in OFF
18.9.34 RAM[7].POWERSET
Address offset: 0x974
RAM7 power control set register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
C
W
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
On
1
On
1
Description
S0POWER
Keep RAM section S0 of RAM7 on or off in System ON mode
On
S1POWER
Keep RAM section S1 of RAM7 on or off in System ON mode
On
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
On
D
W
1
On
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
On
1
On
18.9.35 RAM[7].POWERCLR
Address offset: 0x978
RAM7 power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
A
W
B
W
0
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value Id
Value
Off
1
Off
1
Description
S0POWER
Keep RAM section S0 of RAM7 on or off in System ON mode
Off
S1POWER
Keep RAM section S1 of RAM7 on or off in System ON mode
Off
Page 101
18 POWER — Power supply
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x0000FFFF
Id
RW Field
C
W
0
Value Id
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
S0RETENTION
Keep retention on RAM section S0 when RAM section is
switched off
Off
D
W
1
Off
S1RETENTION
Keep retention on RAM section S1 when RAM section is
switched off
Off
1
Off
18.10 Electrical specification
18.10.1 Current consumption, sleep
Symbol
Description
IOFF
System OFF current, no RAM retention
Min.
Typ.
0.3
Max.
Units
µA
ION
System ON base current, no RAM retention
1.2
µA
IRAM
Additional RAM retention current per 4 KB RAM section
20
nA
18.10.2 Device startup times
Symbol
Description
tPOR
Time in Power on Reset after VDD reaches 1.7 V for all supply
Min.
Typ.
Max.
Units
voltages and temperatures. Dependent on supply rise time. 10
tPOR,10us
VDD rise time 10us
1
ms
tPOR,10ms
VDD rise time 10ms
9
ms
tPOR,60ms
VDD rise time 60ms
23
ms
tPINR
If a GPIO pin is configured as reset, the maximum time taken
to pull up the pin and release reset after power on reset.
Dependent on the pin capacitive load (C)11: t=5RC, R = 13kOhm
tPINR,500nF
C = 500nF
32.5
ms
tPINR,10uF
C = 10uF
650
ms
tR2ON
Time from reset to ON (CPU execute)
tR2ON,NOTCONF
If reset pin not configured
tPOR
ms
tR2ON,CONF
If reset pin configured
tPOR +
ms
tPINR
tOFF2ON
Time from OFF to CPU execute
16.5
µs
tIDLE2CPU
Time from IDLE to CPU execute
3.0
µs
tEVTSET,CL1
Time from HW event to PPI event in Constant Latency System
0.0625
µs
0.0625
µs
ON mode
tEVTSET,CL0
Time from HW event to PPI event in Low Power System ON
mode
18.10.3 Power fail comparator
Symbol
Description
IPOF
Current consumption when enabled12
Min.
VPOF
Nominal power level warning thresholds (falling supply voltage).
Typ.
Max.
=0]
/ PAYLOAD
DISABLED
/ DISABLED
RXDISABLE
RXEN
RXRU
Packet received / END
Ramp-up
complete
/ READY
Address received [Address match]
/ ADDRESS
START
RXIDLE
RX
STOP
Payload received [payload length >=0]
/ PAYLOAD
DISABLE
Figure 36: Radio states
23.8 Transmit sequence
Before the RADIO is able to transmit a packet, it must first ramp-up in TX mode.
See TXRU in Figure 36: Radio states on page 213 and Figure 37: Transmit sequence on page 214.
A TXRU ramp-up sequence is initiated when the TXEN task is triggered. After the radio has successfully
ramped up it will generate the READY event indicating that a packet transmission can be initiate. A packet
transmission is initiated by triggering the START task. As illustrated in Figure 36: Radio states on page 213
the START task can first be triggered after the RADIO has entered into the TXIDLE state.
Figure 37: Transmit sequence on page 214 illustrates a single packet transmission where the CPU
manually triggers the different tasks needed to control the flow of the RADIO, i.e. no shortcuts are used. If
shortcuts are not used, a certain amount of delay caused by CPU execution is expected between READY
and START, and between END and DISABLE. As illustrated in Figure 37: Transmit sequence on page 214
Page 213
23 RADIO — 2.4 GHz Radio
TX
PAYLOAD
CRC
ADDRESS
S0 L S1
(carrier)
2
DISABLE
3
START
1
TXEN
Lifeline
READY
A
TXDISABLE
END
P
(carrier)
TXIDLE
DISABLED
TXIDLE
Transmitter
TXRU
PAYLOAD
State
the RADIO will by default transmit '1's between READY and START, and between END and DISABLED.
What is transmitted can be programmed through the DTX field in the MODECNF0 register.
Figure 37: Transmit sequence
TX
S0 L S1
PAYLOAD
PAYLOAD
CRC
(carrier)
DISABLED
A
TXDISABLE
1
DISABLE
2
START
TXEN
Lifeline
READY
P
ADDRESS
Transmitter
TXRU
END
State
A slightly modified version of the transmit sequence from Figure 37: Transmit sequence on page 214 is
illustrated in Figure 38: Transmit sequence using shortcuts to avoid delays on page 214 where the RADIO
is configured to use shortcuts between READY and START, and between END and DISABLE, which means
that no delay is introduced.
Figure 38: Transmit sequence using shortcuts to avoid delays
The RADIO is able to send multiple packets one after the other without having to disable and re-enable the
RADIO between packets, this is illustrated in Figure 39: Transmission of multiple packets on page 215.
Page 214
PAYLOAD
CRC
(carrier)
P
A
S0 L S1
PAYLOAD
(carrier)
START
TXEN
3
DISABLE
2
START
1
CRC
DISABLED
PAYLOAD
PAYLOAD
S0 L S1
TXDISABLE
TX
ADDRESS
A
ADDRESS
Lifeline
READY
P
TXIDLE
END
TX
Transmitter
TXRU
END
State
23 RADIO — 2.4 GHz Radio
Figure 39: Transmission of multiple packets
23.9 Receive sequence
Before the RADIO is able to receive a packet, it must first ramp up in RX mode
See RXRU in Figure 36: Radio states on page 213 and Figure 40: Receive sequence on page 215.
An RXRU ramp-up sequence is initiated when the RXEN task is triggered. After the radio has successfully
ramped up it will generate the READY event indicating that a packet reception can be initiated. A packet
reception is initiated by triggering the START task. As illustrated in Figure 36: Radio states on page 213
the START task can, first be triggered after the RADIO has entered into the RXIDLE state.
RX
S0 L S1
2
PAYLOAD
RXDISABLE
CRC
DISABLED
A
ADDRESS
P
DISABLE
3
START
1
RXEN
Lifeline
READY
’X’
RXIDLE
END
RXIDLE
Reception
RXRU
PAYLOAD
State
Figure 40: Receive sequence on page 215 illustrates a single packet reception where the CPU manually
triggers the different tasks needed to control the flow of the RADIO, i.e. no shortcuts are used. If shortcuts
are not used, a certain amount of delay, caused by CPU execution, is expected between READY and
START, and between END and DISABLE. As illustrated Figure 40: Receive sequence on page 215 the
RADIO will be listening and possibly receiving undefined data, illustrated with an 'X', from START and until a
packet with valid preamble (P) is received.
Figure 40: Receive sequence
A slightly modified version of the receive sequence from Figure 40: Receive sequence on page 215 is
illustrated in Figure 41: Receive sequence using shortcuts to avoid delays on page 216 where the the
RADIO is configured to use shortcuts between READY and START, and between END and DISABLE, which
means that no delay is introduced.
Page 215
RX
A
PAYLOAD
ADDRESS
Lifeline
S0 L S1
CRC
DISABLED
P
READY
’X’
RXDISABLE
PAYLOAD
Reception
RXRU
END
State
23 RADIO — 2.4 GHz Radio
1
DISABLE
RXEN
START
2
Figure 41: Receive sequence using shortcuts to avoid delays
’X’ P
A
S0 L S1
PAYLOAD
CRC
DISABLED
CRC
END
PAYLOAD
ADDRESS
S0 L S1
RXDISABLE
RX
END
A
START
3
DISABLE
2
START
1
RXEN
Lifeline
READY
’X’ P
RXIDLE
PAYLOAD
RX
ADDRESS
Receiver
RXRU
PAYLOAD
State
The RADIO is able to receive multiple packets one after the other without having to disable and re-enable
the RADIO between packets, this is illustrated Figure 42: Reception of multiple packets on page 216.
Figure 42: Reception of multiple packets
23.10 Received Signal Strength Indicator (RSSI)
The radio implements a mechanism for measuring the power in the received radio signal. This feature is
called Received Signal Strength Indicator (RSSI).
Sampling of the received signal strength is started by using the RSSISTART task. The sample can be read
from the RSSISAMPLE register.
The sample period of the RSSI is defined by RSSIPERIOD, see the device product specification for details.
The RSSI sample will hold the average received signal strength during this sample period.
For the RSSI sample to be valid the radio has to be enabled in receive mode (RXEN task) and the reception
has to be started (READY event followed by START task).
23.11 Interframe spacing
Interframe spacing is the time interval between two consecutive packets.
It is defined as the time, in micro seconds, from the end of the last bit of the previous packet received and
to the start of the first bit of the subsequent packet that is transmitted. The RADIO is able to enforce this
Page 216
23 RADIO — 2.4 GHz Radio
interval as specified in the TIFS register as long as TIFS is not specified to be shorter than the RADIO’s turnaround time, i.e. the time needed to switch off the receiver, and switch back on the transmitter.
TIFS is only enforced if END_DISABLE and DISABLED_TXEN or END_DISABLE and DISABLED_RXEN
shortcuts are enabled. TIFS is only qualified for use in BLE_1MBIT mode, and default ramp-up mode.
23.12 Device address match
The device address match feature is tailored for address white listing in a Bluetooth Smart and similar
implementations.
This feature enables on-the-fly device address matching while receiving a packet on air. This feature only
works in receive mode and as long as RADIO is configured for little endian, see PCNF1.ENDIAN.
The Device Address match unit assumes that the 48 first bits of the payload is the device address and that
bit number 6 in S0 is the TxAdd bit. See the Bluetooth Core Specification for more information about device
addresses, TxAdd and whitelisting.
The RADIO is able to listen for eight different device addresses at the same time. These addresses are
specified in a DAB/DAP register pair, one pair per address, in addition to a TxAdd bit configured in the
DACNF register. The DAB register specifies the 32 least significant bits of the device address, while the DAP
register specifies the 16 most significant bits of the device address.
Each of the device addresses can be individually included or excluded from the matching mechanism. This is
configured in the DACNF register.
23.13 Bit counter
The RADIO implements a simple counter that can be configured to generate an event after a specific number
of bits have been transmitted or received.
By using shortcuts, this counter can be started from different events generated by the RADIO and hence
count relative to these.
The bit counter is started by triggering the BCSTART task, and stopped by triggering the BCSTOP task.
A BCMATCH event will be generated when the bit counter has counted the number of bits specified in the
BCC register. The bit counter will continue to count bits until the DISABLED event is generated or until the
BCSTOP task is triggered. The CPU can therefore, after a BCMATCH event, reconfigure the BCC value for
new BCMATCH events within the same packet.
The bit counter can only be started after the RADIO has received the ADDRESS event.
The bit counter will stop and reset on BCSTOP, STOP, END and DISABLE tasks.
The figure below illustrates how the bit counter can be used to generate a BCMATCH event in the beginning
of the packet payload, and again generate a second BCMATCH event after sending 2 bytes (16 bits) of the
payload.
Page 217
RX
DISABLED
CRC
3
DISABLE
BCC = 12 + 16
BCSTART
START
BCMATCH
BCMATCH
READY
2
BCC = 12
2
PAYLOAD
1
RXEN
1
S0 L S1
PAYLOAD
Lifeline
This example
assumes that the
combined length
of S0, Length (L)
and S1 is 12
bits.
A
ADDRESS
Reception
0
’X’ P
RXDISABLE
END
RXRU
BCSTOP
State
23 RADIO — 2.4 GHz Radio
Figure 43: Bit counter example
23.14 Registers
Table 43: Instances
Base address
Peripheral
Instance
Description
0x40001000
RADIO
RADIO
2.4 GHz radio
Configuration
Table 44: Register Overview
Register
Offset
Description
TASKS_TXEN
0x000
Enable RADIO in TX mode
TASKS_RXEN
0x004
Enable RADIO in RX mode
TASKS_START
0x008
Start RADIO
TASKS_STOP
0x00C
Stop RADIO
TASKS_DISABLE
0x010
Disable RADIO
TASKS_RSSISTART
0x014
Start the RSSI and take one single sample of the receive signal strength.
TASKS_RSSISTOP
0x018
Stop the RSSI measurement
TASKS_BCSTART
0x01C
Start the bit counter
TASKS_BCSTOP
0x020
Stop the bit counter
EVENTS_READY
0x100
RADIO has ramped up and is ready to be started
EVENTS_ADDRESS
0x104
Address sent or received
EVENTS_PAYLOAD
0x108
Packet payload sent or received
EVENTS_END
0x10C
Packet sent or received
EVENTS_DISABLED
0x110
RADIO has been disabled
EVENTS_DEVMATCH
0x114
A device address match occurred on the last received packet
EVENTS_DEVMISS
0x118
No device address match occurred on the last received packet
EVENTS_RSSIEND
0x11C
Sampling of receive signal strength complete.
EVENTS_BCMATCH
0x128
Bit counter reached bit count value.
EVENTS_CRCOK
0x130
Packet received with CRC ok
EVENTS_CRCERROR
0x134
Packet received with CRC error
SHORTS
0x200
Shortcut register
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
CRCSTATUS
0x400
CRC status
RXMATCH
0x408
Received address
RXCRC
0x40C
CRC field of previously received packet
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23 RADIO — 2.4 GHz Radio
Register
Offset
Description
DAI
0x410
Device address match index
PACKETPTR
0x504
Packet pointer
FREQUENCY
0x508
Frequency
TXPOWER
0x50C
Output power
MODE
0x510
Data rate and modulation
PCNF0
0x514
Packet configuration register 0
PCNF1
0x518
Packet configuration register 1
BASE0
0x51C
Base address 0
BASE1
0x520
Base address 1
PREFIX0
0x524
Prefixes bytes for logical addresses 0-3
PREFIX1
0x528
Prefixes bytes for logical addresses 4-7
TXADDRESS
0x52C
Transmit address select
RXADDRESSES
0x530
Receive address select
CRCCNF
0x534
CRC configuration
CRCPOLY
0x538
CRC polynomial
CRCINIT
0x53C
CRC initial value
0x540
Reserved
TIFS
0x544
Inter Frame Spacing in us
RSSISAMPLE
0x548
RSSI sample
STATE
0x550
Current radio state
DATAWHITEIV
0x554
Data whitening initial value
BCC
0x560
Bit counter compare
DAB[0]
0x600
Device address base segment 0
DAB[1]
0x604
Device address base segment 1
DAB[2]
0x608
Device address base segment 2
DAB[3]
0x60C
Device address base segment 3
DAB[4]
0x610
Device address base segment 4
DAB[5]
0x614
Device address base segment 5
DAB[6]
0x618
Device address base segment 6
DAB[7]
0x61C
Device address base segment 7
DAP[0]
0x620
Device address prefix 0
DAP[1]
0x624
Device address prefix 1
DAP[2]
0x628
Device address prefix 2
DAP[3]
0x62C
Device address prefix 3
DAP[4]
0x630
Device address prefix 4
DAP[5]
0x634
Device address prefix 5
DAP[6]
0x638
Device address prefix 6
DAP[7]
0x63C
Device address prefix 7
DACNF
0x640
Device address match configuration
MODECNF0
0x650
Radio mode configuration register 0
POWER
0xFFC
Peripheral power control
23.14.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H
Reset 0x00000000
Id
RW Field
A
RW READY_START
0
Value Id
Value
Description
Shortcut between READY event and START task
See EVENTS_READY and TASKS_START
B
G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW END_DISABLE
Shortcut between END event and DISABLE task
See EVENTS_END and TASKS_DISABLE
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23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H
Reset 0x00000000
Id
C
RW Field
0
G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW DISABLED_TXEN
Shortcut between DISABLED event and TXEN task
See EVENTS_DISABLED and TASKS_TXEN
D
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW DISABLED_RXEN
Shortcut between DISABLED event and RXEN task
See EVENTS_DISABLED and TASKS_RXEN
E
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW ADDRESS_RSSISTART
Shortcut between ADDRESS event and RSSISTART task
See EVENTS_ADDRESS and TASKS_RSSISTART
F
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW END_START
Shortcut between END event and START task
See EVENTS_END and TASKS_START
G
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW ADDRESS_BCSTART
Shortcut between ADDRESS event and BCSTART task
See EVENTS_ADDRESS and TASKS_BCSTART
H
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW DISABLED_RSSISTOP
Shortcut between DISABLED event and RSSISTOP task
See EVENTS_DISABLED and TASKS_RSSISTOP
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
23.14.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
I
Value
Description
Write '1' to Enable interrupt for READY event
See EVENTS_READY
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ADDRESS
Write '1' to Enable interrupt for ADDRESS event
See EVENTS_ADDRESS
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PAYLOAD
Write '1' to Enable interrupt for PAYLOAD event
See EVENTS_PAYLOAD
D
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Enable interrupt for END event
Page 220
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K
Reset 0x00000000
Id
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_END
E
RW DISABLED
Write '1' to Enable interrupt for DISABLED event
See EVENTS_DISABLED
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DEVMATCH
Write '1' to Enable interrupt for DEVMATCH event
See EVENTS_DEVMATCH
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DEVMISS
Write '1' to Enable interrupt for DEVMISS event
See EVENTS_DEVMISS
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RSSIEND
Write '1' to Enable interrupt for RSSIEND event
See EVENTS_RSSIEND
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW BCMATCH
Write '1' to Enable interrupt for BCMATCH event
See EVENTS_BCMATCH
K
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CRCOK
Write '1' to Enable interrupt for CRCOK event
See EVENTS_CRCOK
L
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CRCERROR
Write '1' to Enable interrupt for CRCERROR event
See EVENTS_CRCERROR
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
23.14.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
I
Value
Description
Write '1' to Disable interrupt for READY event
See EVENTS_READY
Clear
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Disable
Page 221
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K
Reset 0x00000000
Id
B
RW Field
0
I
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ADDRESS
Write '1' to Disable interrupt for ADDRESS event
See EVENTS_ADDRESS
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PAYLOAD
Write '1' to Disable interrupt for PAYLOAD event
See EVENTS_PAYLOAD
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Disable interrupt for END event
See EVENTS_END
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DISABLED
Write '1' to Disable interrupt for DISABLED event
See EVENTS_DISABLED
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DEVMATCH
Write '1' to Disable interrupt for DEVMATCH event
See EVENTS_DEVMATCH
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DEVMISS
Write '1' to Disable interrupt for DEVMISS event
See EVENTS_DEVMISS
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RSSIEND
Write '1' to Disable interrupt for RSSIEND event
See EVENTS_RSSIEND
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW BCMATCH
Write '1' to Disable interrupt for BCMATCH event
See EVENTS_BCMATCH
K
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CRCOK
Write '1' to Disable interrupt for CRCOK event
See EVENTS_CRCOK
L
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CRCERROR
Write '1' to Disable interrupt for CRCERROR event
See EVENTS_CRCERROR
Clear
1
Disable
Disabled
0
Read: Disabled
Page 222
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K
Reset 0x00000000
Id
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Read: Enabled
23.14.4 CRCSTATUS
Address offset: 0x400
CRC status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
CRCError
0
Packet received with CRC error
CRCOk
1
Packet received with CRC ok
CRCSTATUS
CRC status of packet received
23.14.5 RXMATCH
Address offset: 0x408
Received address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RXMATCH
Received address
Logical address of which previous packet was received
23.14.6 RXCRC
Address offset: 0x40C
CRC field of previously received packet
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RXCRC
CRC field of previously received packet
CRC field of previously received packet
23.14.7 DAI
Address offset: 0x410
Device address match index
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
DAI
Device address match index
Index (n) of device address, see DAB[n] and DAP[n], that got an
address match.
23.14.8 PACKETPTR
Address offset: 0x504
Page 223
23 RADIO — 2.4 GHz Radio
Packet pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PACKETPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Packet pointer
Packet address to be used for the next transmission or
reception. When transmitting, the packet pointed to by this
address will be transmitted and when receiving, the received
packet will be written to this address. This address is a byte
aligned ram address.
23.14.9 FREQUENCY
Address offset: 0x508
Frequency
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
Reset 0x00000002
Id
RW Field
A
RW FREQUENCY
B
RW MAP
0
Value Id
A A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Value
Description
[0..100]
Radio channel frequency
Frequency = 2400 + FREQUENCY (MHz).
Channel map selection.
Default
0
Low
1
Channel map between 2400 MHZ .. 2500 MHz
Frequency = 2400 + FREQUENCY (MHz)
Channel map between 2360 MHZ .. 2460 MHz
Frequency = 2360 + FREQUENCY (MHz)
23.14.10 TXPOWER
Address offset: 0x50C
Output power
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TXPOWER
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RADIO output power.
Output power in number of dBm, i.e. if the value -20 is specified
the output power will be set to -20dBm.
Pos4dBm
0x04
+4 dBm
Pos3dBm
0x03
+3 dBm
0dBm
0x00
0 dBm
Neg4dBm
0xFC
-4 dBm
Neg8dBm
0xF8
-8 dBm
Neg12dBm
0xF4
-12 dBm
Neg16dBm
0xF0
-16 dBm
Neg20dBm
0xEC
-20 dBm
Neg30dBm
0xD8
-40 dBm
Neg40dBm
0xD8
-40 dBm
23.14.11 MODE
Address offset: 0x510
Data rate and modulation
Page 224
Deprecated
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW MODE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Radio data rate and modulation setting. The radio supports
Frequency-shift Keying (FSK) modulation.
Nrf_1Mbit
0
1 Mbit/s Nordic proprietary radio mode
Nrf_2Mbit
1
2 Mbit/s Nordic proprietary radio mode
Nrf_250Kbit
2
250 kbit/s Nordic proprietary radio mode
Ble_1Mbit
3
1 Mbit/s Bluetooth Low Energy
Ble_2Mbit
4
2 Mbit/s Bluetooth Low Energy
Deprecated
23.14.12 PCNF0
Address offset: 0x514
Packet configuration register 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00000000
0
Id
RW Field
A
RW LFLEN
Length on air of LENGTH field in number of bits.
C
RW S0LEN
Length on air of S0 field in number of bytes.
E
RW S1LEN
Length on air of S1 field in number of bits.
F
RW S1INCL
G
Value Id
F E E E E
C
A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Include or exclude S1 field in RAM
Automatic
0
Include S1 field in RAM only if S1LEN > 0
Include
1
Always include S1 field in RAM independent of S1LEN
8bit
0
8-bit preamble
16bit
1
16-bit preamble
RW PLEN
Length of preamble on air. Decision point: TASKS_START task
23.14.13 PCNF1
Address offset: 0x518
Packet configuration register 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D
Reset 0x00000000
Id
RW Field
A
RW MAXLEN
0
Value Id
C C C B B B B B B B B A A A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..255]
Maximum length of packet payload. If the packet payload is
larger than MAXLEN, the radio will truncate the payload to
MAXLEN.
B
RW STATLEN
[0..255]
Static length in number of bytes
The static length parameter is added to the total length of the
payload when sending and receiving packets, e.g. if the static
length is set to N the radio will receive or send N bytes more
than what is defined in the LENGTH field of the packet.
C
RW BALEN
[2..4]
Base address length in number of bytes
The address field is composed of the base address and the one
byte long address prefix, e.g. set BALEN=2 to get a total address
of 3 bytes.
D
RW ENDIAN
On air endianness of packet, this applies to the S0, LENGTH, S1
and the PAYLOAD fields.
E
Little
0
Least Significant bit on air first
Big
1
Most significant bit on air first
Disabled
0
RW WHITEEN
Enable or disable packet whitening
Disable
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23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D
Reset 0x00000000
Id
RW Field
0
C C C B B B B B B B B A A A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Enable
23.14.14 BASE0
Address offset: 0x51C
Base address 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW BASE0
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Base address 0
Radio base address 0.
23.14.15 BASE1
Address offset: 0x520
Base address 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW BASE1
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Base address 1
Radio base address 1.
23.14.16 PREFIX0
Address offset: 0x524
Prefixes bytes for logical addresses 0-3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00000000
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
Value
A
RW AP0
Description
Address prefix 0.
B
RW AP1
Address prefix 1.
C
RW AP2
Address prefix 2.
D
RW AP3
Address prefix 3.
23.14.17 PREFIX1
Address offset: 0x528
Prefixes bytes for logical addresses 4-7
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00000000
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
Value
A
RW AP4
Description
Address prefix 4.
B
RW AP5
Address prefix 5.
C
RW AP6
Address prefix 6.
D
RW AP7
Address prefix 7.
Page 226
23 RADIO — 2.4 GHz Radio
23.14.18 TXADDRESS
Address offset: 0x52C
Transmit address select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
RW TXADDRESS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Transmit address select
Logical address to be used when transmitting a packet.
23.14.19 RXADDRESSES
Address offset: 0x530
Receive address select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G F E D C B A
Reset 0x00000000
Id
RW Field
A
RW ADDR0
B
C
D
E
F
G
H
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Enable or disable reception on logical address 0.
RW ADDR1
Enable or disable reception on logical address 1.
RW ADDR2
Enable or disable reception on logical address 2.
RW ADDR3
Enable or disable reception on logical address 3.
RW ADDR4
Enable or disable reception on logical address 4.
RW ADDR5
Enable or disable reception on logical address 5.
RW ADDR6
Enable or disable reception on logical address 6.
RW ADDR7
Enable or disable reception on logical address 7.
23.14.20 CRCCNF
Address offset: 0x534
CRC configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
Reset 0x00000000
Id
RW Field
A
RW LEN
0
Value Id
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[1..3]
CRC length in number of bytes.
Disabled
0
CRC length is zero and CRC calculation is disabled
One
1
CRC length is one byte and CRC calculation is enabled
Two
2
CRC length is two bytes and CRC calculation is enabled
Page 227
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
Reset 0x00000000
Id
B
RW Field
0
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Three
3
CRC length is three bytes and CRC calculation is enabled
Include
0
CRC calculation includes address field
Skip
1
CRC calculation does not include address field. The CRC
RW SKIPADDR
Include or exclude packet address field out of CRC calculation.
calculation will start at the first byte after the address.
23.14.21 CRCPOLY
Address offset: 0x538
CRC polynomial
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CRCPOLY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
CRC polynomial
Each term in the CRC polynomial is mapped to a bit in this
register which index corresponds to the term's exponent. The
least significant term/bit is hard-wired internally to 1, and bit
number 0 of the register content is ignored by the hardware.
The following example is for an 8 bit CRC polynomial: x8 + x7 +
x3 + x2 + 1 = 1 1000 1101 .
23.14.22 CRCINIT
Address offset: 0x53C
CRC initial value
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CRCINIT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
CRC initial value
Initial value for CRC calculation.
23.14.23 TIFS
Address offset: 0x544
Inter Frame Spacing in us
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TIFS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Inter Frame Spacing in us
Inter frame space is the time interval between two consecutive
packets. It is defined as the time, in micro seconds, from the
end of the last bit of the previous packet to the start of the first
bit of the subsequent packet.
23.14.24 RSSISAMPLE
Address offset: 0x548
RSSI sample
Page 228
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
RSSISAMPLE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..127]
RSSI sample
RSSI sample result. The value of this register is read as a positive
value while the actual received signal strength is a negative
value. Actual received signal strength is therefore as follows:
received signal strength = -A dBm
23.14.25 STATE
Address offset: 0x550
Current radio state
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
RADIO is in the Disabled state
RxRu
1
RADIO is in the RXRU state
RxIdle
2
RADIO is in the RXIDLE state
Rx
3
RADIO is in the RX state
RxDisable
4
RADIO is in the RXDISABLED state
TxRu
9
RADIO is in the TXRU state
TxIdle
10
RADIO is in the TXIDLE state
Tx
11
RADIO is in the TX state
TxDisable
12
RADIO is in the TXDISABLED state
STATE
Current radio state
23.14.26 DATAWHITEIV
Address offset: 0x554
Data whitening initial value
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A
Reset 0x00000040
Id
RW Field
A
RW DATAWHITEIV
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Value
Description
Data whitening initial value. Bit 6 is hard-wired to '1', writing '0'
to it has no effect, and it will always be read back and used by
the device as '1'.
Bit 0 corresponds to Position 6 of the LSFR, Bit 1 to Position 5,
etc.
23.14.27 BCC
Address offset: 0x560
Bit counter compare
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW BCC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Bit counter compare
Bit counter compare register
Page 229
23 RADIO — 2.4 GHz Radio
23.14.28 DAB[0]
Address offset: 0x600
Device address base segment 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 0
23.14.29 DAB[1]
Address offset: 0x604
Device address base segment 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 1
23.14.30 DAB[2]
Address offset: 0x608
Device address base segment 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 2
23.14.31 DAB[3]
Address offset: 0x60C
Device address base segment 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 3
23.14.32 DAB[4]
Address offset: 0x610
Device address base segment 4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 4
23.14.33 DAB[5]
Address offset: 0x614
Device address base segment 5
Page 230
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 5
23.14.34 DAB[6]
Address offset: 0x618
Device address base segment 6
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 6
23.14.35 DAB[7]
Address offset: 0x61C
Device address base segment 7
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAB
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address base segment 7
23.14.36 DAP[0]
Address offset: 0x620
Device address prefix 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 0
23.14.37 DAP[1]
Address offset: 0x624
Device address prefix 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 1
23.14.38 DAP[2]
Address offset: 0x628
Device address prefix 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 2
Page 231
23 RADIO — 2.4 GHz Radio
23.14.39 DAP[3]
Address offset: 0x62C
Device address prefix 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 3
23.14.40 DAP[4]
Address offset: 0x630
Device address prefix 4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 4
23.14.41 DAP[5]
Address offset: 0x634
Device address prefix 5
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 5
23.14.42 DAP[6]
Address offset: 0x638
Device address prefix 6
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 6
23.14.43 DAP[7]
Address offset: 0x63C
Device address prefix 7
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DAP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Device address prefix 7
23.14.44 DACNF
Address offset: 0x640
Device address match configuration
Page 232
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
P O N M L K J
Reset 0x00000000
Id
RW Field
A
RW ENA0
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable device address matching using device address
0
B
Disabled
0
Disabled
Enabled
1
Enabled
RW ENA1
Enable or disable device address matching using device address
1
C
Disabled
0
Disabled
Enabled
1
Enabled
RW ENA2
Enable or disable device address matching using device address
2
D
Disabled
0
Disabled
Enabled
1
Enabled
RW ENA3
Enable or disable device address matching using device address
3
E
Disabled
0
Disabled
Enabled
1
Enabled
RW ENA4
Enable or disable device address matching using device address
4
F
Disabled
0
Disabled
Enabled
1
Enabled
RW ENA5
Enable or disable device address matching using device address
5
G
Disabled
0
Disabled
Enabled
1
Enabled
RW ENA6
Enable or disable device address matching using device address
6
H
Disabled
0
Disabled
Enabled
1
Enabled
RW ENA7
Enable or disable device address matching using device address
7
Disabled
0
Disabled
Enabled
1
Enabled
I
RW TXADD0
TxAdd for device address 0
J
RW TXADD1
TxAdd for device address 1
K
RW TXADD2
TxAdd for device address 2
L
RW TXADD3
TxAdd for device address 3
M
RW TXADD4
TxAdd for device address 4
N
RW TXADD5
TxAdd for device address 5
O
RW TXADD6
TxAdd for device address 6
P
RW TXADD7
TxAdd for device address 7
23.14.45 MODECNF0
Address offset: 0x650
Radio mode configuration register 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C C
Reset 0x00000200
Id
RW Field
A
RW RU
0
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Value Id
Value
Default
0
Fast
1
Description
Radio ramp-up time
Default ramp-up time (tRXEN), compatible with firmware
written for nRF51
Fast ramp-up (tRXEN,FAST), see electrical specification for more
information
Page 233
23 RADIO — 2.4 GHz Radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C C
Reset 0x00000200
Id
RW Field
C
RW DTX
0
Value Id
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Value
Description
Default TX value
Specifies what the RADIO will transmit when it is not started, i.e.
between:
RADIO.EVENTS_READY and RADIO.TASKS_START
RADIO.EVENTS_END and RADIO.TASKS_START
RADIO.EVENTS_END and RADIO.EVENTS_DISABLED
B1
0
Transmit '1'
B0
1
Transmit '0'
Center
2
Transmit center frequency
When tuning the crystal for centre frequency, the RADIO must
be set in DTX = Center mode to be able to achieve the expected
accuracy.
23.14.46 POWER
Address offset: 0xFFC
Peripheral power control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000001
Id
RW Field
A
RW POWER
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value
Description
Peripheral power control. The peripheral and its registers will be
reset to its initial state by switching the peripheral off and then
back on again.
Disabled
0
Peripheral is powered off
Enabled
1
Peripheral is powered on
23.15 Electrical specification
23.15.1 General Radio Characteristics
Symbol
Description
Min.
fOP
Operating frequencies
2360
Typ.
fPLL,PROG,RES
PLL programming resolution
2
kHz
fPLL,CH,SP
PLL channel spacing
1
MHz
fDELTA,1M
Frequency deviation @ 1 Msps
±170
kHz
fDELTA,BLE,1M
Frequency deviation @ BLE 1Msps
±250
kHz
fDELTA,2M
Frequency deviation @ 2 Msps
±320
kHz
fDELTA,BLE,2M
Frequency deviation @ BLE 2 Msps
±500
fskSPS
On-the-air data rate
1
Max.
Units
2500
MHz
kHz
2
Msps
Max.
Units
23.15.2 Radio current consumption (Transmitter)
Symbol
Description
ITX,PLUS4dBM,DCDC
TX only run current (DCDC, 3V) PRF =+4 dBm
Min.
7.5
mA
ITX,PLUS4dBM
TX only run current PRF = +4 dBm
16.6
mA
ITX,0dBM,DCDC
TX only run current (DCDC, 3V)PRF = 0dBm
5.3
mA
ITX,0dBM
TX only run current PRF = 0dBm
11.6
mA
ITX,MINUS4dBM,DCDC
TX only run current DCDC, 3V PRF = -4dBm
4.2
mA
ITX,MINUS4dBM
TX only run current PRF = -4 dBm
9.3
mA
ITX,MINUS8dBM,DCDC
TX only run current DCDC, 3V PRF = -8 dBm
3.8
mA
Page 234
Typ.
23 RADIO — 2.4 GHz Radio
Symbol
Description
ITX,MINUS8dBM
TX only run current PRF = -8 dBm
Min.
Typ.
8.4
Max.
Units
mA
ITX,MINUS12dBM,DCDC
TX only run current DCDC, 3V PRF = -12 dBm
3.5
mA
ITX,MINUS12dBM
TX only run current PRF = -12 dBm
7.7
mA
ITX,MINUS16dBM,DCDC
TX only run current DCDC, 3V PRF = -16 dBm
3.3
mA
ITX,MINUS16dBM
TX only run current PRF = -16 dBm
7.3
mA
ITX,MINUS20dBM,DCDC
TX only run current DCDC, 3V PRF = -20 dBm
3.2
mA
ITX,MINUS20dBM
TX only run current PRF = -20 dBm
7.0
mA
ITX,MINUS40dBM,DCDC
TX only run current DCDC, 3V PRF = -40 dBm
2.7
mA
ITX,MINUS40dBM
TX only run current PRF = -40 dBm
5.9
mA
ISTART,TX,DCDC
TX start-up current DCDC, 3V, PRF = 4 dBm
4.0
mA
ISTART,TX
TX start-up current, PRF = 4 dBm
8.8
mA
23.15.3 Radio current consumption (Receiver)
Symbol
Description
IRX,1M,DCDC
RX only run current (DCDC, 3V) 1Msps / 1Msps BLE
Min.
Typ.
5.4
Max.
Units
mA
IRX,1M
RX only run current 1Msps / 1Msps BLE
11.7
mA
IRX,2M,DCDC
RX only run current (DCDC, 3V) 2Msps / 2Msps BLE
5.8
mA
IRX,2M
RX only run current 2Msps / 2Msps BLE
12.9
mA
ISTART,RX,DCDC
RX start-up current (DCDC 3V)
3.5
mA
ISTART,RX,LDO
RX start-up current (LDO 3V)
7.5
mA
23.15.4 Transmitter specification
Symbol
Description
Typ.
Max.
Units
PRF
Maximum output power
Min.
4
6
dBm
PRFC
RF power control range
24
PRFCR
RF power accuracy
PRF1,1
1st Adjacent Channel Transmit Power 1 MHz (1 Msps Nordic
dB
±4
dB
-25
dBc
-50
dBc
-25
dBc
-50
dBc
proprietary mode)
PRF2,1
2nd Adjacent Channel Transmit Power 2 MHz (1 Msps Nordic
proprietary mode)
PRF1,2
1st Adjacent Channel Transmit Power 2 MHz (2 Msps Nordic
proprietary mode)
PRF2,2
2nd Adjacent Channel Transmit Power 4 MHz (2 Msps Nordic
proprietary mode)
PRF1,2,BLE
1st Adjacent Channel Transmit Power 2 MHz (2 Msps BLE mode)
-20
dBc
PRF2,2,BLE
2nd Adjacent Channel Transmit Power 4 MHz (2 Msps BLE
-50
dBc
mode)
23.15.5 Receiver operation
Symbol
Description
PRX,MAX
Maximum received signal strength at < 0.1% BER
Min.
Typ.
0
Max.
Units
dBm
PSENS,IT,1M
Sensitivity, 1Msps nRF mode16
-93
dBm
PSENS,IT,SP,1M,BLE
Sensitivity, 1Msps BLE ideal transmitter, =128 bytes BER=1E-4
-95
dBm
-89
dBm
18
PSENS,IT,2M
16
17
18
19
Sensitivity, 2Msps nRF mode19
Typical sensitivity applies when ADDR0 is used for receiver address correlation. When ADDR[1...7] are used for
receiver address correlation, the typical sensitivity for this mode is degraded by 3dB.
As defined in the Bluetooth Core Specification v4.0 Volume 6: Core System Package (Low Energy Controller
Volume)
Equivalent BER limit < 10E-04
Typical sensitivity applies when ADDR0 is used for receiver address correlation. When ADDR[1...7] are used for
receiver address correlation, the typical sensitivity for this mode is degraded by 3dB.
Page 235
23 RADIO — 2.4 GHz Radio
Symbol
Description
PSENS,IT,SP,2M,BLE
Sensitivity, 2Msps BLE ideal transmitter, Packet length
Min.
Typ.
Max.
Units
-93
dBm
-93
dBm
=
-92
dBm
128bytes
23.15.6 RX selectivity
20
RX selectivity with equal modulation on interfering signal
Symbol
Description
C/I1M,co-channel
1Msps mode, Co-Channel interference
Min.
Typ.
9
Max.
Units
dB
C/I1M,-1MHz
1 Msps mode, Adjacent (-1 MHz) interference
-2
dB
C/I1M,+1MHz
1 Msps mode, Adjacent (+1 MHz) interference
-10
dB
C/I1M,-2MHz
1 Msps mode, Adjacent (-2 MHz) interference
-19
dB
C/I1M,+2MHz
1 Msps mode, Adjacent (+2 MHz) interference
-42
dB
C/I1M,-3MHz
1 Msps mode, Adjacent (-3 MHz) interference
-38
dB
C/I1M,+3MHz
1 Msps mode, Adjacent (+3 MHz) interference
-48
dB
C/I1M,±6MHz
1 Msps mode, Adjacent (≥6 MHz) interference
-50
dB
C/I1MBLE,co-channel
1 Msps BLE mode, Co-Channel interference
6
dB
C/I1MBLE,-1MHz
1 Msps BLE mode, Adjacent (-1 MHz) interference
-2
dB
C/I1MBLE,+1MHz
1 Msps BLE mode, Adjacent (+1 MHz) interference
-9
dB
C/I1MBLE,-2MHz
1 Msps BLE mode, Adjacent (-2 MHz) interference
-22
dB
C/I1MBLE,+2MHz
1 Msps BLE mode, Adjacent (+2 MHz) interference
-46
dB
C/I1MBLE,>3MHz
1 Msps BLE mode, Adjacent (≥3 MHz) interference
-50
dB
C/I1MBLE,image
Image frequency Interference
-22
dB
C/I1MBLE,image,1MHz
Adjacent (1 MHz) interference to in-band image frequency
-35
dB
C/I2M,co-channel
2Msps mode, Co-Channel interference
10
dB
C/I2M,-2MHz
2 Msps mode, Adjacent (-2 MHz) interference
6
dB
C/I2M,+2MHz
2 Msps mode, Adjacent (+2 MHz) interference
-14
dB
C/I2M,-4MHz
2 Msps mode, Adjacent (-4 MHz) interference
-20
dB
C/I2M,+4MHz
2 Msps mode, Adjacent (+4 MHz) interference
-44
dB
C/I2M,-6MHz
2 Msps mode, Adjacent (-6 MHz) interference
-42
dB
C/I2M,+6MHz
2 Msps mode, Adjacent (+6 MHz) interference
-47
dB
C/I2M,≥12MHz
2 Msps mode, Adjacent (≥12 MHz) interference
-52
dB
C/I2MBLE,co-channel
2 Msps BLE mode, Co-Channel interference
7
dB
C/I2MBLE,±2MHz
2 Msps BLE mode, Adjacent (±2 MHz) interference
0
dB
C/I2MBLE,±4MHz
2 Msps BLE mode, Adjacent (±4 MHz) interference
-47
dB
C/I2MBLE,≥6MHz
2 Msps BLE mode, Adjacent (≥6 MHz) interference
-49
dB
C/I2MBLE,image
Image frequency Interference
-21
dB
C/I2MBLE,image, 2MHz
Adjacent (2 MHz) interference to in-band image frequency
-36
dB
23.15.7 RX intermodulation
21
RX intermodulation
Symbol
Description
PIMD,1M
IMD performance, 1 Msps (3 MHz, 4 MHz, and 5 MHz offset)
Min.
Typ.
-33
Max.
Units
dBm
PIMD,1M,BLE
IMD performance, BLE 1 Msps (3 MHz, 4 MHz, and 5 MHz
-30
dBm
-33
dBm
offset)
PIMD,2M
20
21
IMD performance, 2 Msps (6 MHz, 8 MHz, and 10 MHz offset)
Wanted signal level at PIN = -67 dBm. One interferer is used, having equal modulation as the wanted
signal. The input power of the interferer where the sensitivity equals BER = 0.1% is presented
Wanted signal level at PIN = -64 dBm. Two interferers with equal input power are used. The interferer
closest in frequency is not modulated, the other interferer is modulated equal with the wanted signal.
The input power of the interferers where the sensitivity equals BER = 0.1% is presented.
Page 236
23 RADIO — 2.4 GHz Radio
Symbol
Description
PIMD,2M,BLE
IMD performance, BLE 2 Msps (6 MHz, 8 MHz, and 10 MHz
Min.
Typ.
Max.
-32
Units
dBm
offset)
23.15.8 Radio timing
Symbol
Description
tTXEN
Time between TXEN task and READY event after channel
Min.
Typ.
Max.
Units
140
us
40
us
6
us
4
us
140
us
40
us
20
us
0
us
FREQUENCY configured
tTXEN,FAST
Time between TXEN task and READY event after channel
FREQUENCY configured (Fast Mode)
tTXDISABLE
Time between DISABLE task and DISABLED event when the
radio was in TX and mode is set to 1Msps
tTXDISABLE,2M
Time between DISABLE task and DISABLED event when the
radio was in TX and mode is set to 2Msps
tRXEN
Time between the RXEN task and READY event after channel
FREQUENCY configured in default mode
tRXEN,FAST
Time between the RXEN task and READY event after channel
FREQUENCY configured in fast mode
tSWITCH
The minimum time taken to switch from RX to TX or TX to RX
(channel FREQUENCY unchanged)
tRXDISABLE
Time between DISABLE task and DISABLED event when the
radio was in RX
tTXCHAIN
TX chain delay
0.6
us
tRXCHAIN
RX chain delay
9.4
us
tRXCHAIN,2M
RX chain delay in 2Msps mode
5
us
23.15.9 Received Signal Strength Indicator (RSSI) specifications
Symbol
Description
RSSIACC
RSSI Accuracy Valid range -90 to -20 dBm
Min.
Typ.
±2
Max.
Units
dB
RSSIRESOLUTION
RSSI resolution
1
dB
RSSIPERIOD
Sample period
0.25
us
23.15.10 Jitter
Symbol
Description
tDISABLEDJITTER
Jitter on DISABLED event relative to END event when shortcut
Min.
Typ.
Max.
Units
0.25
us
0.25
us
between END and DISABLE is enabled.
tREADYJITTER
Jitter on READY event relative to TXEN and RXEN task.
23.15.11 Delay when disabling the RADIO
Symbol
Description
tTXDISABLE,1M
Disable delay from TX.
Min.
Typ.
Max.
Units
6
us
0
us
Delay between DISABLE and DISABLED for MODE = Nrf_1Mbit
and MODE = Ble_1Mbit
tRXDISABLE,1M
Disable delay from RX.
Delay between DISABLE and DISABLED for MODE = Nrf_1Mbit
and MODE = Ble_1Mbit
Page 237
24 TIMER — Timer/counter
24 TIMER — Timer/counter
The TIMER can operate in two modes: timer and counter.
CLEAR
CAPTURE[0..n]
STOP
START
COUNT
TIMER
TIMER Core
Increment
BITMODE
Counter
PCLK1M
Prescaler
PCLK16M
fTIMER
PRESCALER
CC[0..n]
MODE
COMPARE[0..n]
Figure 44: Block schematic for timer/counter
The timer/counter runs on the high-frequency clock source (HFCLK) and includes a four-bit (1/2X) prescaler
that can divide the timer input clock from the HFCLK controller. Clock source selection between PCLK16M
and PCLK1M is automatic according to TIMER base frequency set by the prescaler. The TIMER base
frequency is always given as 16 MHz divided by the prescaler value.
The PPI system allows a TIMER event to trigger a task of any other system peripheral of the device. The
PPI system also enables the TIMER task/event features to generate periodic output and PWM signals to any
GPIO. The number of input/outputs used at the same time is limited by the number of GPIOTE channels.
The TIMER can operate in two modes, Timer mode and Counter mode. In both modes, the TIMER is started
by triggering the START task, and stopped by triggering the STOP task. After the timer is stopped the timer
can resume timing/counting by triggering the START task again. When timing/counting is resumed, the timer
will continue from the value it had prior to being stopped.
In Timer mode, the TIMER's internal Counter register is incremented by one for every tick of the timer
frequency fTIMER as illustrated in Figure 44: Block schematic for timer/counter on page 238. The timer
frequency is derived from PCLK16M as shown below, using the values specified in the PRESCALER
register:
fTIMER = 16 MHz / (2PRESCALER)
When fTIMER 62.5 ns
CC[0]
X
N+2
COMPARE[0]
•
0
1
Figure 52: Timing diagram - COMPARE_N+2
If the COUNTER is N, writing N or N+1 to a CC register may not trigger a COMPARE event.
SysClk
LFClk
PRESC
COUNTER
0x000
N-2
N-1
N+1
>= 0
CC[0]
X
N+1
COMPARE[0]
•
N
0
Figure 53: Timing diagram - COMPARE_N+1
If the COUNTER is N and the current CC register value is N+1 or N+2 when a new CC value is written,
a match may trigger on the previous CC value before the new value takes effect. If the current CC value
greater than N+2 when the new value is written, there will be no event due to the old value.
SysClk
LFClk
PRESC
COUNTER
CC[0]
0x000
N-2
N-1
N
N+1
>= 0
N
COMPARE[0]
X
0
1
Figure 54: Timing diagram - COMPARE_N-1
25.8 TASK and EVENT jitter/delay
Jitter or delay in the RTC is due to the peripheral clock being a low frequency clock (LFCLK) which is not
synchronous to the faster PCLK16M.
Registers in the peripheral interface, part of the PCLK16M domain, have a set of mirrored registers in the
LFCLK domain. For example, the COUNTER value accessible from the CPU is in the PCLK16M domain
and is latched on read from an internal register called COUNTER in the LFCLK domain. COUNTER is the
register which is actually modified each time the RTC ticks. These registers must be synchronised between
clock domains (PCLK16M and LFCLK).
The following is a summary of the jitter introduced on tasks and events. Figures illustrating jitter follow.
Page 250
25 RTC — Real-time counter
Table 48: RTC jitter magnitudes on tasks
Task
CLEAR, STOP, START, TRIGOVRFLOW
Delay
+15 to 46 μs
Table 49: RTC jitter magnitudes on events
Operation/Function
START to COUNTER increment
COMPARE to COMPARE 22
Jitter
+/- 15 μs
+/- 62.5 ns
1. CLEAR and STOP (and TRIGOVRFLW; not shown) will be delayed as long as it takes for the peripheral
to clock a falling edge and rising of the LFCLK. This is between 15.2585 µs and 45.7755 µs – rounded to
15 µs and 46 µs for the remainder of the section.
SysClk
CLEAR
LFClk
PRESC
COUNTER
CLEARa
0x000
X
X+1
0x000000
0x000001
0 or more SysClk after
= ~15 us
1 or more SysClk before
CLEARb
Figure 55: Timing diagram - DELAY_CLEAR
SysClk
STOP
LFClk
PRESC
COUNTER
STOPa
STOPb
0x000
X
X+1
0 or more SysClk after
= ~15 us
1 or more SysClk before
Figure 56: Timing diagram - DELAY_STOP
2. The START task will start the RTC. Assuming that the LFCLK was previously running and stable, the
first increment of COUNTER (and instance of TICK event) will be typically after 30.5 µs +/-15 µs. In
some cases, in particular if the RTC is STARTed before the LFCLK is running, that timing can be up to
~250 µs. The software should therefore wait for the first TICK if it has to make sure the RTC is running.
Sending a TRIGOVRFLW task sets the COUNTER to a value close to overflow. However, since the
update of COUNTER relies on a stable LFCLK, sending this task while LFCLK is not running will start
LFCLK, but the update will then be delayed by the same amount of time of up to ~250 us. The figures
show the smallest and largest delays to on the START task which appears as a +/-15 µs jitter on the first
COUNTER increment.
22
Assumes RTC runs continuously between these events.
Note: 32.768 kHz clock jitter is additional to the numbers provided above.
Page 251
25 RTC — Real-time counter
SysClk
First tick
LFClk
PRESC
COUNTER
START
0x000
X
X+1
X+2
X+3
>= ~15 us
0 or more SysClk before
Figure 57: Timing diagram - JITTER_STARTSysClk
First tick
LFClk
PRESC
COUNTER
0x000
X
X+1
X+2
MODE.DATARATE
Length of address (32 bit)
Length of CRC (24 bit)
29.5 Encrypting packets on-the-fly in radio transmit mode
When the AES CCM is encrypting a packet on-the-fly at the same time as the RADIO is transmitting it, the
RADIO must read the encrypted packet from the same memory location as the AES CCM is writing to.
The OUTPTR pointer in the AES CCM must therefore point to the same memory location as the
PACKETPTR pointer in the RADIO, see Figure 64: Configuration of on-the-fly encryption on page 273.
SCRATCHPTR
INPTR
Unencrypted packet
OUTPTR
&
PACKETPTR
H
L
RFU
MODE = ENCRYPTION
Encrypted packet
H
L+4
RFU
Scratch area
PL
EPL
AES CCM
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
PL: unencrypted payload
EPL: encrypted payload
CCM data
structure
MIC
CNFPTR
To remote
receiver
RADIO
TXEN
Figure 64: Configuration of on-the-fly encryption
In order to match the RADIO’s timing, the KSGEN task must be triggered no later than when the START task
in the RADIO is triggered, in addition the shortcut between the ENDKSGEN event and the CRYPT task must
be enabled. This use-case is illustrated in Figure 65: On-the-fly encryption using a PPI connection on page
274 using a PPI connection between the READY event in the RADIO and the KSGEN task in the AES
CCM.
Page 273
29 CCM — AES CCM mode encryption
SHORTCUT
ENDKSGEN
CRYPT
key-stream
generation
AES CCM
encryption
KSGEN
ENDCRYPT
PPI
READY
RADIO
RU
P
A
H
L
RFU
EPL
MIC
CRC
TXEN
END
READY
RU: Ramp-up of RADIO
P: Preamble
A: Address
START
SHORTCUT
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
EPL: encrypted payload
Figure 65: On-the-fly encryption using a PPI connection
29.6 Decrypting packets on-the-fly in radio receive mode
When the AES CCM is decrypting a packet on-the-fly at the same time as the RADIO is receiving it, the AES
CCM must read the encrypted packet from the same memory location as the RADIO is writing to.
The INPTR pointer in the AES CCM must therefore point to the same memory location as the PACKETPTR
pointer in the RADIO, see Figure 66: Configuration of on-the-fly decryption on page 274.
SCRATCHPTR
OUTPTR
Unencrypted packet
INPTR
&
PACKETPTR
H
L
H
L+4
RFU
AES CCM
MODE = DECRYPTION
Encrypted packet
RFU
Scratch area
PL
EPL
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
PL: unencrypted payload
EPL: encrypted payload
CCM data
structure
MIC
CNFPTR
From remote
transmitter
RADIO
RXEN
Figure 66: Configuration of on-the-fly decryption
In order to match the RADIO’s timing, the KSGEN task must be triggered no later than when the START task
in the RADIO is triggered. In addition, the CRYPT task must be triggered no earlier than when the ADDRESS
event is generated by the RADIO.
If the CRYPT task is triggered exactly at the same time as the ADDRESS event is generated by the RADIO,
the AES CCM will guarantee that the decryption is completed no later than when the END event in the
RADIO is generated.
This use-case is illustrated in Figure 67: On-the-fly decryption using a PPI connection between the READY
event in the RADIO and the KSGEN task in the AES CCM on page 275 using a PPI connection between
the ADDRESS event in the RADIO and the CRYPT task in the AES CCM. The KSGEN task is triggered from
the READY event in the RADIO through a PPI connection.
Page 274
29 CCM — AES CCM mode encryption
key-stream
generation
AES CCM
KSGEN
decryption
CRYPT
ENDKSGEN
ENDCRYPT
PPI
PPI
READY
RADIO
ADDRESS
RU
P
A
H
L
RFU
EPL
MIC
RXEN
CRC
END
READY
RU: Ramp-up of RADIO
P: Preamble
A: Address
START
SHORTCUT
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
EPL: encrypted payload
: RADIO receiving noise
Figure 67: On-the-fly decryption using a PPI connection between the READY event in the RADIO and
the KSGEN task in the AES CCM
29.7 CCM data structure
The CCM data structure is located in Data RAM at the memory location specified by the CNFPTR pointer
register.
Table 60: CCM data structure overview
Property
Address offset
Description
KEY
0
16 byte AES key
PKTCTR
16
Octet0 (LSO) of packet counter
17
Octet1 of packet counter
18
Octet2 of packet counter
19
Octet3 of packet counter
20
Bit 6 – Bit 0: Octet4 (7 most significant bits of packet counter, with Bit 6 being the most significant
bit) Bit7: Ignored
IV
21
Ignored
22
Ignored
23
Ignored
24
Bit 0: Direction bit Bit 7 – Bit 1: Zero padded
25
8 byte initialization vector (IV) Octet0 (LSO) of IV, Octet1 of IV, … , Octet7 (MSO) of IV
The NONCE vector (as specified by the Bluetooth Core Specification) will be generated by hardware based
on the information specified in the CCM data structure from Table 60: CCM data structure overview on page
275 .
Table 61: Data structure for unencrypted packet
Property
Address offset
Description
HEADER
0
Packet Header
LENGTH
1
Number of bytes in unencrypted payload
RFU
2
Reserved Future Use
PAYLOAD
3
Unencrypted payload
Table 62: Data structure for encrypted packet
Property
Address offset
Description
HEADER
0
Packet Header
LENGTH
1
Number of bytes in encrypted payload including length of MIC
Important: LENGTH will be 0 for empty packets since the MIC is not added to empty
packets
RFU
2
Reserved Future Use
PAYLOAD
3
Encrypted payload
MIC
3 + payload length
ENCRYPT: 4 bytes encrypted MIC
Page 275
29 CCM — AES CCM mode encryption
Property
Address offset
Description
Important: MIC is not added to empty packets
29.8 EasyDMA and ERROR event
The CCM implements an EasyDMA mechanism for reading and writing to the RAM.
In some scenarios where the CPU and other DMA enabled peripherals are accessing the RAM at the same
time, the CCM DMA could experience some bus conflicts which may also result in an error during encryption.
If this happens, the ERROR event will be generated.
The EasyDMA will have finished accessing the RAM when the ENDKSGEN and ENDCRYPT events are
generated.
If the CNFPTR, SCRATCHPTR, INPTR and the OUTPTR are not pointing to the Data RAM region,
an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 24 for more
information about the different memory regions.
29.9 Registers
Table 63: Instances
Base address
Peripheral
Instance
Description
0x4000F000
CCM
CCM
AES CCM Mode Encryption
Configuration
Table 64: Register Overview
Register
Offset
Description
TASKS_KSGEN
0x000
Start generation of key-stream. This operation will stop by itself when completed.
TASKS_CRYPT
0x004
Start encryption/decryption. This operation will stop by itself when completed.
TASKS_STOP
0x008
Stop encryption/decryption
EVENTS_ENDKSGEN
0x100
Key-stream generation complete
EVENTS_ENDCRYPT
0x104
Encrypt/decrypt complete
EVENTS_ERROR
0x108
CCM error event
SHORTS
0x200
Shortcut register
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
MICSTATUS
0x400
MIC check result
ENABLE
0x500
Enable
MODE
0x504
Operation mode
CNFPTR
0x508
Pointer to data structure holding AES key and NONCE vector
INPTR
0x50C
Input pointer
OUTPTR
0x510
Output pointer
SCRATCHPTR
0x514
Pointer to data area used for temporary storage
29.9.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ENDKSGEN_CRYPT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between ENDKSGEN event and CRYPT task
See EVENTS_ENDKSGEN and TASKS_CRYPT
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Page 276
29 CCM — AES CCM mode encryption
29.9.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW ENDKSGEN
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for ENDKSGEN event
See EVENTS_ENDKSGEN
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDCRYPT
Write '1' to Enable interrupt for ENDCRYPT event
See EVENTS_ENDCRYPT
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Enable interrupt for ERROR event
See EVENTS_ERROR
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
29.9.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW ENDKSGEN
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for ENDKSGEN event
See EVENTS_ENDKSGEN
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDCRYPT
Write '1' to Disable interrupt for ENDCRYPT event
See EVENTS_ENDCRYPT
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Disable interrupt for ERROR event
See EVENTS_ERROR
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
29.9.4 MICSTATUS
Address offset: 0x400
MIC check result
Page 277
29 CCM — AES CCM mode encryption
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
MICSTATUS
The result of the MIC check performed during the previous
decryption operation
CheckFailed
0
MIC check failed
CheckPassed
1
MIC check passed
29.9.5 ENABLE
Address offset: 0x500
Enable
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
2
Enable
Enable or disable CCM
29.9.6 MODE
Address offset: 0x504
Operation mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
Reset 0x00000001
Id
RW Field
A
RW MODE
B
C
0
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Description
Encryption
0
AES CCM packet encryption mode
Decryption
1
AES CCM packet decryption mode
1Mbit
0
In synch with 1 Mbit data rate
2Mbit
1
In synch with 2 Mbit data rate
Default
0
Default length. Effective length of LENGTH field is 5-bit
Extended
1
Extended length. Effective length of LENGTH field is 8-bit
The mode of operation to be used
RW DATARATE
Data rate that the CCM shall run in synch with
RW LENGTH
Packet length configuration
29.9.7 CNFPTR
Address offset: 0x508
Pointer to data structure holding AES key and NONCE vector
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CNFPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to the data structure holding the AES key and the CCM
NONCE vector (see Table 1 CCM data structure overview)
29.9.8 INPTR
Address offset: 0x50C
Input pointer
Page 278
29 CCM — AES CCM mode encryption
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW INPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Input pointer
29.9.9 OUTPTR
Address offset: 0x510
Output pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW OUTPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Output pointer
29.9.10 SCRATCHPTR
Address offset: 0x514
Pointer to data area used for temporary storage
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW SCRATCHPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to a scratch data area used for temporary storage
during key-stream generation, MIC generation and encryption/
decryption.
The scratch area is used for temporary storage of data during
key-stream generation and encryption.
A space of 43 bytes, or (16 + MAXPACKETSIZE) bytes, whatever
is largest, must be reserved in RAM.
Page 279
30 AAR — Accelerated address resolver
30 AAR — Accelerated address resolver
Accelerated address resolver is a cryptographic support function for implementing the "Resolvable Private
Address Resolution Procedure" described in the Bluetooth Core specification v4.0. "Resolvable private
address generation" should be achieved using ECB and is not supported by AAR.
The procedure allows two devices that share a secret key to generate and resolve a hash based on their
device address. The AAR block enables real-time address resolution on incoming packets when configured
as described in this chapter. This allows real-time packet filtering (whitelisting) using a list of known shared
keys (Identity Resolving Keys (IRK) in Bluetooth).
30.1 Shared resources
The AAR shares registers and other resources with the peripherals that have the same ID as the AAR.
The user must therefore disable all peripherals that have the same ID as the AAR before the AAR can be
configured and used.
Disabling a peripheral that have the same ID as the AAR will not reset any of the registers that are shared
with the AAR. It is therefore important to configure all relevant AAR registers explicitly to secure that it
operates correctly.
See the Instantiation table in Instantiation on page 25 for details on peripherals and their IDs.
30.2 EasyDMA
The AAR implements EasyDMA for reading and writing to the RAM. The EasyDMA will have finished
accessing the RAM when the END, RESOLVED, and NOTRESOLVED events are generated.
If the IRKPTR, ADDRPTR and the SCRATCHPTR is not pointing to the Data RAM region, an EasyDMA
transfer may result in a HardFault or RAM corruption. See Memory on page 24 for more information about
the different memory regions.
30.3 Resolving a resolvable address
As per Bluetooth specification, a private resolvable address is composed of six bytes.
LSB
MSB
random
hash
(24-bit)
10
prand
(24-bit)
Figure 68: Resolvable address
To resolve an address the ADDRPTR register must point to the start of packet. The resolver is started by
triggering the START task. A RESOLVED event is generated when the AAR manages to resolve the address
using one of the Identity Resolving Keys (IRK) found in the IRK data structure. The AAR will use the IRK
specified in the register IRK0 to IRK15 starting from IRK0. How many to be used is specified by the NIRK
register. The AAR module will generate a NOTRESOLVED event if it is not able to resolve the address using
the specified list of IRKs.
The AAR will go through the list of available IRKs in the IRK data structure and for each IRK try to resolve
the address according to the Resolvable Private Address Resolution Procedure described in the Bluetooth
24
Specification . The time it takes to resolve an address may vary depending on where in the list the
24
Bluetooth Specification Version 4.0 [Vol 3] chapter 10.8.2.3.
Page 280
30 AAR — Accelerated address resolver
resolvable address is located. The resolution time will also be affected by RAM accesses performed by other
peripherals and the CPU. See the Electrical specifications for more information about resolution time.
The AAR will only do a comparison of the received address to those programmed in the module. And not
check what type of address it actually is.
The AAR will stop as soon as it has managed to resolve the address, or after trying to resolve the address
using NIRK number of IRKs from the IRK data structure. The AAR will generate an END event after it has
stopped.
SCRATCHPTR
ADDR: resolvable address
START
Scratch area
ADDRPTR
RESOLVED
AAR
S0
L
S1
IRK data
structure
ADDR
IRKPTR
Figure 69: Address resolution with packet preloaded into RAM
30.4 Use case example for chaining RADIO packet reception with
address resolution using AAR
The AAR may be started as soon as the 6 bytes required by the AAR have been received by the RADIO and
stored in RAM. The ADDRPTR pointer must point to the start of packet.
SCRATCHPTR
S0: S0 field of RADIO (optional)
L: Length field of RADIO (optional)
S1: S1 field of RADIO (optional)
ADDR: resolvable address
START
PACKETPTR
ADDRPTR
Scratch area
RESOLVED
AAR
S0
L
S1
IRK data
structure
ADDR
IRKPTR
From remote
transmitter
RADIO
RXEN
Figure 70: Address resolution with packet loaded into RAM by the RADIO
30.5 IRK data structure
The IRK data structure is located in RAM at the memory location specified by the CNFPTR pointer register.
Table 65: IRK data structure overview
Property
IRK0
IRK1
..
IRK15
Address offset
0
16
..
240
Description
IRK number 0 (16 - byte)
IRK number 1 (16 - byte)
..
IRK number 15 (16 - byte)
Page 281
30 AAR — Accelerated address resolver
30.6 Registers
Table 66: Instances
Base address
Peripheral
Instance
Description
0x4000F000
AAR
AAR
Acelerated Address Resolver
Configuration
Table 67: Register Overview
Register
Offset
Description
TASKS_START
0x000
Start resolving addresses based on IRKs specified in the IRK data structure
TASKS_STOP
0x008
Stop resolving addresses
EVENTS_END
0x100
Address resolution procedure complete
EVENTS_RESOLVED
0x104
Address resolved
EVENTS_NOTRESOLVED 0x108
Address not resolved
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
STATUS
0x400
Resolution status
ENABLE
0x500
Enable AAR
NIRK
0x504
Number of IRKs
IRKPTR
0x508
Pointer to IRK data structure
ADDRPTR
0x510
Pointer to the resolvable address
SCRATCHPTR
0x514
Pointer to data area used for temporary storage
30.6.1 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW END
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for END event
See EVENTS_END
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RESOLVED
Write '1' to Enable interrupt for RESOLVED event
See EVENTS_RESOLVED
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW NOTRESOLVED
Write '1' to Enable interrupt for NOTRESOLVED event
See EVENTS_NOTRESOLVED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
30.6.2 INTENCLR
Address offset: 0x308
Disable interrupt
Page 282
30 AAR — Accelerated address resolver
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW END
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for END event
See EVENTS_END
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RESOLVED
Write '1' to Disable interrupt for RESOLVED event
See EVENTS_RESOLVED
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW NOTRESOLVED
Write '1' to Disable interrupt for NOTRESOLVED event
See EVENTS_NOTRESOLVED
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
30.6.3 STATUS
Address offset: 0x400
Resolution status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
STATUS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..15]
The IRK that was used last time an address was resolved
30.6.4 ENABLE
Address offset: 0x500
Enable AAR
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
3
Enable
Enable or disable AAR
30.6.5 NIRK
Address offset: 0x504
Number of IRKs
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000001
Id
RW Field
A
RW NIRK
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value
Description
[1..16]
Number of Identity root keys available in the IRK data structure
30.6.6 IRKPTR
Address offset: 0x508
Page 283
30 AAR — Accelerated address resolver
Pointer to IRK data structure
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW IRKPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to the IRK data structure
30.6.7 ADDRPTR
Address offset: 0x510
Pointer to the resolvable address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ADDRPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to the resolvable address (6-bytes)
30.6.8 SCRATCHPTR
Address offset: 0x514
Pointer to data area used for temporary storage
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0
Id
RW Field
Value Id
A
RW SCRATCHPTR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Pointer to a scratch data area used for temporary storage
during resolution.A space of minimum 3 bytes must be
reserved.
30.7 Electrical specification
30.7.1 AAR Electrical Specification
Symbol
Description
tAAR,8
Time for address resolution of 8 IRKs
Min.
Typ.
48
Page 284
Max.
Units
µs
31 SPIM — Serial peripheral interface master with
EasyDMA
31 SPIM — Serial peripheral interface master with
EasyDMA
The SPI master can communicate with multiple slaves using individual chip select signals for each of the
slave devices attached to a bus.
Listed here are the main features for the SPIM
STOP
Three SPIM instances
SPI mode 0-3
EasyDMA direct transfer to/from RAM for both SPI Slave and SPI Master
Individual selection of IO pin for each SPI signal
START
•
•
•
•
SPIM
GPIO
RAM
PSEL.MOSI
TXD.PTR
buffer[0]
buffer[1]
MOSI
Pin
SCK
Pin
TXD+1
TXD buffer
EasyDMA
buffer[TXD.MAXCNT-1]
PSEL.SCK
buffer[0]
buffer[1]
MISO
Pin
RXD-1
EasyDMA
PSEL.MISO
RXD.PTR
RXD buffer
ENDRX
ENDTX
STARTED
buffer[RXD.MAXCNT-1]
Figure 71: SPIM — SPI master with EasyDMA
The SPIM does not implement support for chip select directly. Therefore, the CPU must use available GPIOs
to select the correct slave and control this independently of the SPI master. The SPIM supports SPI modes 0
through 3. The CONFIG register allows setting CPOL and CPHA appropriately.
Table 68: SPI modes
Mode
Clock polarity
CPOL
SPI_MODE00 (Active High)
SPI_MODE10 (Active High)
SPI_MODE21 (Active Low)
SPI_MODE31 (Active Low)
Clock phase
CPHA
0 (Leading)
1 (Trailing)
0 (Leading)
1 (Trailing)
31.1 Shared resources
The SPI shares registers and other resources with other peripherals that have the same ID as the SPI.
Therefore, the user must disable all peripherals that have the same ID as the SPI before the SPI can be
configured and used.
Page 285
31 SPIM — Serial peripheral interface master with
EasyDMA
Disabling a peripheral that has the same ID as the SPI will not reset any of the registers that are shared with
the SPI. It is therefore important to configure all relevant SPI registers explicitly to secure that it operates
correctly.
See the Instantiation table in Instantiation on page 25 for details on peripherals and their IDs.
31.2 EasyDMA
The SPI master implements EasyDMA for reading and writing of data packets from and to the DATA RAM
without CPU involvement.
The RXD.PTR and TXD.PTR point to the RXD buffer (receive buffer) and TXD buffer (transmit buffer)
respectively, see Figure 71: SPIM — SPI master with EasyDMA on page 285. RXD.MAXCNT and
TXD.MAXCNT specify the maximum number of bytes allocated to the buffers.
The SPI master will automatically stop transmitting after TXD.MAXCNT bytes have been transmitted and
RXD.MAXCNT bytes have been received. If TXD.MAXCNT is larger than RXD.MAXCNT, the superfluous
received bytes will be ignored. If RXD.MAXCNT is larger than TXD.MAXCNT, the remaining transmitted
bytes will contain the value defined in the ORC register.
If the RXD.PTR and the TXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 24 for more information about the different memory
regions.
The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next
transmission immediately after having received the STARTED event.
The ENDRX/ENDTX event indicate that EasyDMA has finished accessing respectively the RX/TX buffer in
RAM. The END event gets generated when both RX and TX are finished accessing the buffers in RAM.
31.2.1 EasyDMA list
EasyDMA supports one list type.
The supported list type is:
•
Array list
EasyDMA array list
The EasyDMA array list can be represented by the data structure ArrayList_type.
For illustration, see the code example below. This data structure includes only a buffer with size equal
to Channel.MAXCNT. EasyDMA will use the Channel.MAXCNT register to determine when the buffer
is full. Replace 'Channel' by the specific data channel you want to use, for instance 'NRF_SPIM->RXD',
'NRF_SPIM->TXD', 'NRF_TWIM->RXD', etc.
The Channel.MAXCNT register cannot be specified larger than the actual size of the buffer. If
Channel.MAXCNT is specified larger than the size of the buffer, the EasyDMA channel may overflow the
buffer.
This array list does not provide a mechanism to explicitly specify where the next item in the list is located.
Instead, it assumes that the list is organized as a linear array where items are located one after the other in
RAM.
#define BUFFER_SIZE
4
typedef struct ArrayList
{
uint8_t buffer[BUFFER_SIZE];
} ArrayList_type;
ArrayList_type MyArrayList[3];
Page 286
31 SPIM — Serial peripheral interface master with
EasyDMA
//replace 'Channel' below by the specific data channel you want to use,
//
for instance 'NRF_SPIM->RXD', 'NRF_TWIM->RXD', etc.
Channel.MAXCNT = BUFFER_SIZE;
Channel.PTR = &MyArrayList;
Channel.PTR = &MyArrayList
Note: addresses are
assuming that
sizeof(buffer[n]) is one byte
0x20000000 : MyArrayList[0]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000004 : MyArrayList[1]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000008 : MyArrayList[2]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
Figure 72: EasyDMA array list
31.3 SPI master transaction sequence
An SPI master transaction consists of a sequence started by the START task followed by a number of
events, and finally the STOP task.
An SPI master transaction is started by triggering the START task. The ENDTX event will be generated
when the transmitter has transmitted all bytes in the TXD buffer as specified in the TXD.MAXCNT register.
The ENDRX event will be generated when the receiver has filled the RXD buffer, i.e. received the last
possible byte as specified in the RXD.MAXCNT register.
Following a START task, the SPI master will generate an END event when both ENDRX and ENDTX have
been generated.
The SPI master is stopped by triggering the STOP task. A STOPPED event is generated when the SPI
master has stopped.
If the ENDRX event has not already been generated when the SPI master has come to a stop, the SPI
master will generate the ENDRX event explicitly even though the RX buffer is not full.
If the ENDTX event has not already been generated when the SPI master has come to a stop, the SPI
master will generate the ENDTX event explicitly even though all bytes in the TXD buffer, as specified in the
TXD.MAXCNT register, have not been transmitted.
The SPI master is a synchronous interface, and for every byte that is sent, a different byte will be received at
the same time; this is illustrated in Figure 73: SPI master transaction on page 288.
Page 287
31 SPIM — Serial peripheral interface master with
EasyDMA
CSN
SCK
MOSI
0
1
2
n
ORC
ORC
MISO
A
B
C
m-2
m-1
m
ENDRX
ENDTX
CPU
1
2
START
Figure 73: SPI master transaction
31.4 Low power
When putting the system in low power and the peripheral is not needed, lowest possible power consumption
is achieved by stopping, and then disabling the peripheral.
The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent,
software shall wait until the STOPPED event was received as a response before disabling the peripheral
through the ENABLE register.
31.5 Master mode pin configuration
The SCK, MOSI, and MISO signals associated with the SPI master are mapped to physical pins according to
the configuration specified in the PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers respectively.
The PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations are only used as long as
the SPI master is enabled, and retained only as long as the device is in ON mode. PSEL.SCK, PSEL.MOSI
and PSEL.MISO must only be configured when the SPI master is disabled.
To secure correct behavior in the SPI, the pins used by the SPI must be configured in the GPIO peripheral
as described in Table 69: GPIO configuration on page 288 prior to enabling the SPI. This configuration
must be retained in the GPIO for the selected IOs as long as the SPI is enabled.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
Table 69: GPIO configuration
SPI master signal
SCK
MOSI
MISO
SPI master pin
As specified in PSEL.SCK
As specified in PSEL.MOSI
As specified in PSEL.MISO
Direction
Output
Output
Input
Output value
Same as CONFIG.CPOL
0
Not applicable
Page 288
Comments
31 SPIM — Serial peripheral interface master with
EasyDMA
31.6 Registers
Table 70: Instances
Base address
Peripheral
Instance
Description
0x40003000
SPIM
SPIM0
SPI master 0
0x40004000
SPIM
SPIM1
SPI master 1
0x40023000
SPIM
SPIM2
SPI master 2
Configuration
Table 71: Register Overview
Register
Offset
Description
TASKS_START
0x010
Start SPI transaction
TASKS_STOP
0x014
Stop SPI transaction
TASKS_SUSPEND
0x01C
Suspend SPI transaction
TASKS_RESUME
0x020
Resume SPI transaction
EVENTS_STOPPED
0x104
SPI transaction has stopped
EVENTS_ENDRX
0x110
End of RXD buffer reached
EVENTS_END
0x118
End of RXD buffer and TXD buffer reached
EVENTS_ENDTX
0x120
End of TXD buffer reached
EVENTS_STARTED
0x14C
Transaction started
SHORTS
0x200
Shortcut register
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ENABLE
0x500
Enable SPIM
PSEL.SCK
0x508
Pin select for SCK
PSEL.MOSI
0x50C
Pin select for MOSI signal
PSEL.MISO
0x510
Pin select for MISO signal
FREQUENCY
0x524
SPI frequency. Accuracy depends on the HFCLK source selected.
RXD.PTR
0x534
Data pointer
RXD.MAXCNT
0x538
Maximum number of bytes in receive buffer
RXD.AMOUNT
0x53C
Number of bytes transferred in the last transaction
RXD.LIST
0x540
EasyDMA list type
TXD.PTR
0x544
Data pointer
TXD.MAXCNT
0x548
Maximum number of bytes in transmit buffer
TXD.AMOUNT
0x54C
Number of bytes transferred in the last transaction
TXD.LIST
0x550
EasyDMA list type
CONFIG
0x554
Configuration register
ORC
0x5C0
Over-read character. Character clocked out in case and over-read of the TXD buffer.
31.6.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW END_START
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between END event and START task
See EVENTS_END and TASKS_START
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
31.6.2 INTENSET
Address offset: 0x304
Enable interrupt
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31 SPIM — Serial peripheral interface master with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
D
C
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Enable interrupt for ENDRX event
See EVENTS_ENDRX
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Enable interrupt for END event
See EVENTS_END
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDTX
Write '1' to Enable interrupt for ENDTX event
See EVENTS_ENDTX
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STARTED
Write '1' to Enable interrupt for STARTED event
See EVENTS_STARTED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
31.6.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
Value
Description
Write '1' to Disable interrupt for STOPPED event
See EVENTS_STOPPED
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Disable interrupt for ENDRX event
See EVENTS_ENDRX
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Disable interrupt for END event
See EVENTS_END
D
D
C
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDTX
Write '1' to Disable interrupt for ENDTX event
See EVENTS_ENDTX
Page 290
31 SPIM — Serial peripheral interface master with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E
Reset 0x00000000
Id
E
RW Field
0
D
C
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STARTED
Write '1' to Disable interrupt for STARTED event
See EVENTS_STARTED
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
31.6.4 ENABLE
Address offset: 0x500
Enable SPIM
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable SPIM
Enabled
7
Enable SPIM
Enable or disable SPIM
31.6.5 PSEL.SCK
Address offset: 0x508
Pin select for SCK
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
C
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
31.6.6 PSEL.MOSI
Address offset: 0x50C
Pin select for MOSI signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
C
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
31.6.7 PSEL.MISO
Address offset: 0x510
Pin select for MISO signal
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31 SPIM — Serial peripheral interface master with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
C
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
31.6.8 FREQUENCY
Address offset: 0x524
SPI frequency. Accuracy depends on the HFCLK source selected.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x04000000
Id
RW Field
A
RW FREQUENCY
0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
K125
0x02000000
125 kbps
K250
0x04000000
250 kbps
K500
0x08000000
500 kbps
M1
0x10000000
1 Mbps
M2
0x20000000
2 Mbps
M4
0x40000000
4 Mbps
M8
0x80000000
8 Mbps
SPI master data rate
31.6.9 RXD.PTR
Address offset: 0x534
Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
31.6.10 RXD.MAXCNT
Address offset: 0x538
Maximum number of bytes in receive buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in receive buffer
31.6.11 RXD.AMOUNT
Address offset: 0x53C
Number of bytes transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last transaction
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31 SPIM — Serial peripheral interface master with
EasyDMA
31.6.12 RXD.LIST
Address offset: 0x540
EasyDMA list type
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
RW LIST
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable EasyDMA list
ArrayList
1
Use array list
List type
31.6.13 TXD.PTR
Address offset: 0x544
Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
31.6.14 TXD.MAXCNT
Address offset: 0x548
Maximum number of bytes in transmit buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in transmit buffer
31.6.15 TXD.AMOUNT
Address offset: 0x54C
Number of bytes transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last transaction
31.6.16 TXD.LIST
Address offset: 0x550
EasyDMA list type
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
RW LIST
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable EasyDMA list
ArrayList
1
Use array list
List type
Page 293
31 SPIM — Serial peripheral interface master with
EasyDMA
31.6.17 CONFIG
Address offset: 0x554
Configuration register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW ORDER
B
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
MsbFirst
0
Most significant bit shifted out first
LsbFirst
1
Least significant bit shifted out first
Leading
0
Trailing
1
Bit order
RW CPHA
Serial clock (SCK) phase
Sample on leading edge of clock, shift serial data on trailing
edge
Sample on trailing edge of clock, shift serial data on leading
edge
C
RW CPOL
Serial clock (SCK) polarity
ActiveHigh
0
Active high
ActiveLow
1
Active low
31.6.18 ORC
Address offset: 0x5C0
Over-read character. Character clocked out in case and over-read of the TXD buffer.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ORC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Over-read character. Character clocked out in case and overread of the TXD buffer.
31.7 Electrical specification
31.7.1 SPIM master interface electrical specifications
Symbol
Description
fSPIM
Bit rates for SPIM25
Min.
ISPIM,2Mbps
Run current for SPIM, 2 Mbps
50
µA
ISPIM,8Mbps
Run current for SPIM, 8 Mbps
50
µA
ISPIM,IDLE
Idle current for SPIM (STARTed, no CSN activity)
1
tSPIM,START
Time from START task to transmission started
..
Typ.
..
Max.
Units
826
Mbps
µA
..
µs
31.7.2 Serial Peripheral Interface Master (SPIM) timing specifications
Symbol
Description
Min.
Typ.
Max.
Units
tSPIM,CSCK
SCK period
..
..
..
ns
tSPIM,RSCK,LD
SCK rise time, standard drivea
tRF,25pF
tSPIM,RSCK,HD
SCK rise time, high drivea
tHRF,25pF
tSPIM,FSCK,LD
SCK fall time, standard drivea
tRF,25pF
tSPIM,FSCK,HD
SCK fall time, high drivea
tSPIM,WHSCK
SCK high timea
tHRF,25pF
(0.5*tCSCK)
– tRSCK
25
26
a
High bit rates may require GPIOs to be set as High Drive, see GPIO chapter for more details.
The actual maximum data rate depends on the slave's CLK to MISO and MOSI setup and hold timings.
At 25pF load, including GPIO pin capacitance, see GPIO spec.
Page 294
31 SPIM — Serial peripheral interface master with
EasyDMA
Symbol
Description
Min.
tSPIM,WLSCK
SCK low timea
(0.5*tCSCK)
Typ.
tSPIM,SUMI
MISO to CLK edge setup time
19
tSPIM,HMI
CLK edge to MISO hold time
18
tSPIM,VMO
CLK edge to MOSI valid
tSPIM,HMO
MOSI hold time after CLK edge
Max.
Units
– tFSCK
ns
ns
59
20
ns
tCSCK
SCK (out)
CPOL=0
CPHA=0
tWHSCK
tWLSCK
CPOL=1
CPHA=0
tRSCK
tFSCK
CPOL=0
CPHA=1
CPOL=1
CPHA=1
tSUMI
MISO (in)
tHMI
MSb
tVMO
MOSI (out)
MSb
LSb
tHMO
LSb
Figure 74: SPIM timing diagram
Page 295
ns
32 SPIS — Serial peripheral interface slave with
EasyDMA
32 SPIS — Serial peripheral interface slave with
EasyDMA
SPI slave (SPIS) is implemented with EasyDMA support for ultra low power serial communication from an
external SPI master. EasyDMA in conjunction with hardware-based semaphore mechanisms removes all
real-time requirements associated with controlling the SPI slave from a low priority CPU execution context.
PSEL.CSN
PSEL.MISO
PSEL.MOSI
PSEL.SCK
SPIS
CSN
MOSI
MISO
ACQUIRE
SPI slave tranceiver
RELEASE
Semaphore
ACQUIRED
END
DEF
OVERREAD
OVERFLOW
TXD.PTR
EasyDMA
EasyDMA
RXD.PTR
RAM
TXD
RXD
TXD+1
RXD+1
TXD+2
RXD+2
TXD+n
RXD+n
Figure 75: SPI slave
The SPIS supports SPI modes 0 through 3. The CONFIG register allows setting CPOL and CPHA
appropriately.
Table 72: SPI modes
Mode
SPI_MODE0
SPI_MODE1
SPI_MODE2
SPI_MODE3
Clock polarity
CPOL
0 (Leading)
0 (Leading)
1 (Trailing)
1 (Trailing)
Clock phase
CPHA
0 (Active High)
1 (Active Low)
0 (Active High)
1 (Active Low)
32.1 Shared resources
The SPI slave shares registers and other resources with other peripherals that have the same ID as the SPI
slave. Therefore, you must disable all peripherals that have the same ID as the SPI slave before the SPI
slave can be configured and used.
Disabling a peripheral that has the same ID as the SPI slave will not reset any of the registers that are
shared with the SPI slave. It is important to configure all relevant SPI slave registers explicitly to secure that
it operates correctly.
The Instantiation table in Instantiation on page 25 shows which peripherals have the same ID as the SPI
slave.
32.2 EasyDMA
The SPI slave implements EasyDMA for reading and writing to and from the RAM. The END event indicates
that EasyDMA has finished accessing the buffer in RAM.
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32 SPIS — Serial peripheral interface slave with
EasyDMA
If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 24 for more information about the different memory
regions.
32.3 SPI slave operation
SPI slave uses two memory pointers, RXD.PTR and TXD.PTR, that point to the RXD buffer (receive
buffer) and TXD buffer (transmit buffer) respectively. Since these buffers are located in RAM, which can be
accessed by both the SPI slave and the CPU, a hardware based semaphore mechanism is implemented to
enable safe sharing.
See Figure 76: SPI transaction when shortcut between END and ACQUIRE is enabled on page 298.
Before the CPU can safely update the RXD.PTR and TXD.PTR pointers it must first acquire the SPI
semaphore. The CPU can acquire the semaphore by triggering the ACQUIRE task and then receiving
the ACQUIRED event. When the CPU has updated the RXD.PTR and TXD.PTR pointers the CPU must
release the semaphore before the SPI slave will be able to acquire it. The CPU releases the semaphore by
triggering the RELEASE task. This is illustrated in Figure 76: SPI transaction when shortcut between END
and ACQUIRE is enabled on page 298. Triggering the RELEASE task when the semaphore is not granted
to the CPU will have no effect.
The semaphore mechanism does not, at any time, prevent the CPU from performing read or write access
to the RXD.PTR register, the TXD.PTR registers, or the RAM that these pointers are pointing to. The
semaphore is only telling when these can be updated by the CPU so that safe sharing is achieved.
The semaphore is by default assigned to the CPU after the SPI slave is enabled. No ACQUIRED event will
be generated for this initial semaphore handover. An ACQUIRED event will be generated immediately if the
ACQUIRE task is triggered while the semaphore is assigned to the CPU.
The SPI slave will try to acquire the semaphore when CSN goes low. If the SPI slave does not manage to
acquire the semaphore at this point, the transaction will be ignored. This means that all incoming data on
MOSI will be discarded, and the DEF (default) character will be clocked out on the MISO line throughout
the whole transaction. This will also be the case even if the semaphore is released by the CPU during the
transaction. In case of a race condition where the CPU and the SPI slave try to acquire the semaphore at
the same time, as illustrated in lifeline item 2 in Figure 76: SPI transaction when shortcut between END and
ACQUIRE is enabled on page 298, the semaphore will be granted to the CPU.
If the SPI slave acquires the semaphore, the transaction will be granted. The incoming data on MOSI will be
stored in the RXD buffer and the data in the TXD buffer will be clocked out on MISO.
When a granted transaction is completed and CSN goes high, the SPI slave will automatically release the
semaphore and generate the END event.
As long as the semaphore is available the SPI slave can be granted multiple transactions one after the
other. If the CPU is not able to reconfigure the TXD.PTR and RXD.PTR between granted transactions, the
same TX data will be clocked out and the RX buffers will be overwritten. To prevent this from happening,
the END_ACQUIRE shortcut can be used. With this shortcut enabled the semaphore will be handed over to
the CPU automatically after the granted transaction has completed, giving the CPU the ability to update the
TXPTR and RXPTR between every granted transaction.
If the CPU tries to acquire the semaphore while it is assigned to the SPI slave, an immediate handover
will not be granted. However, the semaphore will be handed over to the CPU as soon as the SPI slave
has released the semaphore after the granted transaction is completed. If the END_ACQUIRE shortcut is
enabled and the CPU has triggered the ACQUIRE task during a granted transaction, only one ACQUIRE
request will be served following the END event.
The MAXRX register specifies the maximum number of bytes the SPI slave can receive in one granted
transaction. If the SPI slave receives more than MAXRX number of bytes, an OVERFLOW will be indicated
in the STATUS register and the incoming bytes will be discarded.
The MAXTX parameter specifies the maximum number of bytes the SPI slave can transmit in one granted
transaction. If the SPI slave is forced to transmit more than MAXTX number of bytes, an OVERREAD will be
indicated in the STATUS register and the ORC character will be clocked out.
Page 297
32 SPIS — Serial peripheral interface slave with
EasyDMA
The RXD.AMOUNT and TXD.AMOUNT registers are updated when a granted transaction is completed.
The TXD.AMOUNT register indicates how many bytes were read from the TX buffer in the last transaction,
that is, ORC (over-read) characters are not included in this number. Similarly, the RXD.AMOUNT register
indicates how many bytes were written into the RX buffer in the last transaction.
The ENDRX event is generated when the RX buffer has been filled.
Transaction status
SPI master can use the DEF
character to stop the transaction as
soon as possible if the transaction is
not granted.
Ignored
Granted
MOSI
0
1
2
0
1
2
DEF
DEF
DEF
DEF
A
B
C
Free
SPIS
CPU
CPU
4
3
ACQUIRE
ACQUIRE
2
RELEASE
ACQUIRE
1
RELEASE
Lifeline
CPUPENDING
END
&
ACQUIRED
Free
ACQUIRED
CPU
ACQUIRED
Semaphore assignment
0
MISO
SCK
CSN
Ignored
Figure 76: SPI transaction when shortcut between END and ACQUIRE is enabled
32.4 Pin configuration
The CSN, SCK, MOSI, and MISO signals associated with the SPI slave are mapped to physical pins
according to the configuration specified in the PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO
registers respectively. If the CONNECT field of any of these registers is set to Disconnected, the associated
SPI slave signal will not be connected to any physical pins.
The PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations are only used
as long as the SPI slave is enabled, and retained only as long as the device is in System ON mode, see
POWER — Power supply on page 81 chapter for more information about power modes. When the peripheral
is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field
and PIN_CNF[n] register. PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO must only be configured
when the SPI slave is disabled.
To secure correct behavior in the SPI slave, the pins used by the SPI slave must be configured in the GPIO
peripheral as described in Table 73: GPIO configuration before enabling peripheral on page 299 before
enabling the SPI slave. This is to secure that the pins used by the SPI slave are driven correctly if the SPI
Page 298
32 SPIS — Serial peripheral interface slave with
EasyDMA
slave itself is temporarily disabled, or if the device temporarily enters System OFF. This configuration must
be retained in the GPIO for the selected I/Os as long as the SPI slave is to be recognized by an external SPI
master.
The MISO line is set in high impedance as long as the SPI slave is not selected with CSN.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
Table 73: GPIO configuration before enabling peripheral
SPI signal
CSN
SCK
MOSI
MISO
SPI pin
As specified in PSEL.CSN
As specified in PSEL.SCK
As specified in PSEL.MOSI
As specified in PSEL.MISO
Direction
Input
Input
Input
Input
Output value
Not applicable
Not applicable
Not applicable
Not applicable
Comment
Emulates that the SPI slave is not selected.
32.5 Registers
Table 74: Instances
Base address
Peripheral
Instance
Description
0x40003000
SPIS
SPIS0
SPI slave 0
0x40004000
SPIS
SPIS1
SPI slave 1
0x40023000
SPIS
SPIS2
SPI slave 2
Configuration
Table 75: Register Overview
Register
Offset
Description
TASKS_ACQUIRE
0x024
Acquire SPI semaphore
TASKS_RELEASE
0x028
Release SPI semaphore, enabling the SPI slave to acquire it
EVENTS_END
0x104
Granted transaction completed
EVENTS_ENDRX
0x110
End of RXD buffer reached
EVENTS_ACQUIRED
0x128
Semaphore acquired
SHORTS
0x200
Shortcut register
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
SEMSTAT
0x400
Semaphore status register
STATUS
0x440
Status from last transaction
ENABLE
0x500
Enable SPI slave
PSELSCK
0x508
Pin select for SCK
Deprecated
PSELMISO
0x50C
Pin select for MISO
Deprecated
PSELMOSI
0x510
Pin select for MOSI
Deprecated
PSELCSN
0x514
Pin select for CSN
Deprecated
PSEL.SCK
0x508
Pin select for SCK
PSEL.MISO
0x50C
Pin select for MISO signal
PSEL.MOSI
0x510
Pin select for MOSI signal
PSEL.CSN
0x514
Pin select for CSN signal
RXDPTR
0x534
RXD data pointer
Deprecated
MAXRX
0x538
Maximum number of bytes in receive buffer
Deprecated
AMOUNTRX
0x53C
Number of bytes received in last granted transaction
Deprecated
RXD.PTR
0x534
RXD data pointer
RXD.MAXCNT
0x538
Maximum number of bytes in receive buffer
RXD.AMOUNT
0x53C
Number of bytes received in last granted transaction
TXDPTR
0x544
TXD data pointer
Deprecated
MAXTX
0x548
Maximum number of bytes in transmit buffer
Deprecated
AMOUNTTX
0x54C
Number of bytes transmitted in last granted transaction
Deprecated
TXD.PTR
0x544
TXD data pointer
TXD.MAXCNT
0x548
Maximum number of bytes in transmit buffer
TXD.AMOUNT
0x54C
Number of bytes transmitted in last granted transaction
CONFIG
0x554
Configuration register
Page 299
32 SPIS — Serial peripheral interface slave with
EasyDMA
Register
Offset
Description
DEF
0x55C
Default character. Character clocked out in case of an ignored transaction.
ORC
0x5C0
Over-read character
32.5.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW END_ACQUIRE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between END event and ACQUIRE task
See EVENTS_END and TASKS_ACQUIRE
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
32.5.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
Reset 0x00000000
Id
RW Field
A
RW END
0
Value Id
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for END event
See EVENTS_END
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Enable interrupt for ENDRX event
See EVENTS_ENDRX
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ACQUIRED
Write '1' to Enable interrupt for ACQUIRED event
See EVENTS_ACQUIRED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
32.5.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
Reset 0x00000000
Id
RW Field
A
RW END
0
Value Id
Value
Description
Write '1' to Disable interrupt for END event
See EVENTS_END
B
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Disable interrupt for ENDRX event
Page 300
32 SPIS — Serial peripheral interface slave with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
Reset 0x00000000
Id
RW Field
0
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_ENDRX
C
RW ACQUIRED
Write '1' to Disable interrupt for ACQUIRED event
See EVENTS_ACQUIRED
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
32.5.4 SEMSTAT
Address offset: 0x400
Semaphore status register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000001
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Description
Free
0
Semaphore is free
CPU
1
Semaphore is assigned to CPU
SPIS
2
Semaphore is assigned to SPI slave
CPUPending
3
Semaphore is assigned to SPI but a handover to the CPU is
SEMSTAT
Semaphore status
pending
32.5.5 STATUS
Address offset: 0x440
Status from last transaction
Individual bits are cleared by writing a '1' to the bits that shall be cleared
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
A
RW OVERREAD
B
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NotPresent
0
Read: error not present
Present
1
Read: error present
Clear
1
Write: clear error on writing '1'
NotPresent
0
Read: error not present
Present
1
Read: error present
Clear
1
Write: clear error on writing '1'
TX buffer over-read detected, and prevented
RW OVERFLOW
RX buffer overflow detected, and prevented
32.5.6 ENABLE
Address offset: 0x500
Enable SPI slave
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable SPI slave
Page 301
32 SPIS — Serial peripheral interface slave with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable SPI slave
Enabled
2
Enable SPI slave
32.5.7 PSELSCK ( Deprecated )
Address offset: 0x508
Pin select for SCK
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELSCK
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI SCK signal
0xFFFFFFFF
Disconnect
32.5.8 PSELMISO ( Deprecated )
Address offset: 0x50C
Pin select for MISO
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELMISO
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI MISO signal
0xFFFFFFFF
Disconnect
32.5.9 PSELMOSI ( Deprecated )
Address offset: 0x510
Pin select for MOSI
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELMOSI
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI MOSI signal
0xFFFFFFFF
Disconnect
32.5.10 PSELCSN ( Deprecated )
Address offset: 0x514
Pin select for CSN
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELCSN
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI CSN signal
0xFFFFFFFF
Disconnect
32.5.11 PSEL.SCK
Address offset: 0x508
Pin select for SCK
Page 302
32 SPIS — Serial peripheral interface slave with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
32.5.12 PSEL.MISO
Address offset: 0x50C
Pin select for MISO signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
32.5.13 PSEL.MOSI
Address offset: 0x510
Pin select for MOSI signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
32.5.14 PSEL.CSN
Address offset: 0x514
Pin select for CSN signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
32.5.15 RXDPTR ( Deprecated )
Address offset: 0x534
RXD data pointer
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32 SPIS — Serial peripheral interface slave with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW RXDPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RXD data pointer
32.5.16 MAXRX ( Deprecated )
Address offset: 0x538
Maximum number of bytes in receive buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXRX
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in receive buffer
32.5.17 AMOUNTRX ( Deprecated )
Address offset: 0x53C
Number of bytes received in last granted transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNTRX
Number of bytes received in the last granted transaction
32.5.18 RXD.PTR
Address offset: 0x534
RXD data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RXD data pointer
32.5.19 RXD.MAXCNT
Address offset: 0x538
Maximum number of bytes in receive buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in receive buffer
32.5.20 RXD.AMOUNT
Address offset: 0x53C
Number of bytes received in last granted transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes received in the last granted transaction
Page 304
32 SPIS — Serial peripheral interface slave with
EasyDMA
32.5.21 TXDPTR ( Deprecated )
Address offset: 0x544
TXD data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TXDPTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
TXD data pointer
32.5.22 MAXTX ( Deprecated )
Address offset: 0x548
Maximum number of bytes in transmit buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXTX
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in transmit buffer
32.5.23 AMOUNTTX ( Deprecated )
Address offset: 0x54C
Number of bytes transmitted in last granted transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNTTX
Number of bytes transmitted in last granted transaction
32.5.24 TXD.PTR
Address offset: 0x544
TXD data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
TXD data pointer
32.5.25 TXD.MAXCNT
Address offset: 0x548
Maximum number of bytes in transmit buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in transmit buffer
32.5.26 TXD.AMOUNT
Address offset: 0x54C
Number of bytes transmitted in last granted transaction
Page 305
32 SPIS — Serial peripheral interface slave with
EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transmitted in last granted transaction
32.5.27 CONFIG
Address offset: 0x554
Configuration register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW ORDER
B
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
MsbFirst
0
Most significant bit shifted out first
LsbFirst
1
Least significant bit shifted out first
Leading
0
Trailing
1
Bit order
RW CPHA
Serial clock (SCK) phase
Sample on leading edge of clock, shift serial data on trailing
edge
Sample on trailing edge of clock, shift serial data on leading
edge
C
RW CPOL
Serial clock (SCK) polarity
ActiveHigh
0
Active high
ActiveLow
1
Active low
32.5.28 DEF
Address offset: 0x55C
Default character. Character clocked out in case of an ignored transaction.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW DEF
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Default character. Character clocked out in case of an ignored
transaction.
32.5.29 ORC
Address offset: 0x5C0
Over-read character
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ORC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Over-read character. Character clocked out after an over-read
of the transmit buffer.
Page 306
32 SPIS — Serial peripheral interface slave with
EasyDMA
32.6 Electrical specification
32.6.1 SPIS slave interface electrical specifications
Symbol
Description
fSPIS
Bit rates for SPIS27
Min.
Typ.
Max.
Units
828
ISPIS,2Mbps
Run current for SPIS, 2 Mbps
45
Mbps
µA
ISPIS,8Mbps
Run current for SPIS, 8 Mbps
45
µA
ISPIS,IDLE
Idle current for SPIS (STARTed, no CSN activity)
1
µA
tSPIS,LP,START
Time from RELEASE task to ready to receive/transmit (CSN
tSPIS,CL,START
µs
active), Low power mode
+
tSTART_HFINT
tSPIS,CL,START
Time from RELEASE task to receive/transmit (CSN active),
0.125
µs
Constant latency mode
32.6.2 Serial Peripheral Interface Slave (SPIS) timing specifications
Symbol
Description
tSPIS,CSCKIN,8Mbps
SCK input period at 8Mbps
Min.
Typ.
125
Max.
Units
ns
tSPIS,CSCKIN,4Mbps
SCK input period at 4Mbps
250
ns
tSPIS,CSCKIN,2Mbps
SCK input period at 2Mbps
500
tSPIS,RFSCKIN
SCK input rise/fall time
tSPIS,WHSCKIN
SCK input high time
30
ns
tSPIS,WLSCKIN
SCK input low time
30
ns
tSPIS,SUCSN,LP
CSN to CLK setup time, Low power mode
tSPIS,SUCSN,CL
ns
ns
30
ns
+
tSTART_HFINT
tSPIS,SUCSN,CL
CSN to CLK setup time, Constant latency mode
1000
tSPIS,HCSN
CLK to CSN hold time
2000
ns
tSPIS,ASO
CSN to MISO drivena
1000
ns
tSPIS,DISSO
CSN to MISO disableda
68
ns
tSPIS,CWH
CSN inactive time
tSPIS,VSO
CLK edge to MISO valid
tSPIS,HSO
MISO hold time after CLK edge
2029
ns
tSPIS,SUSI
MOSI to CLK edge setup time
19
ns
tSPIS,HSI
CLK edge to MOSI hold time
18
ns
ns
300
ns
59
ns
CSN (in)
SCK (in)
tSUCSN
CPOL=0
CPHA=0
tCSCKIN
tWHSCKIN
tWLSCKIN
CPOL=1
CPHA=0
tASO
tHSO
tDISSO
MSb
tSUSI
MOSI (in)
tCWH
tRSCKIN
tFSCKIN
tVSO
MISO (out)
tHCSN
LSb
tHSI
MSb
LSb
Figure 77: SPIS timing diagram
27
28
a
29
Higher bit rates may require GPIOs to be set as High Drive, see GPIO chapter for more details.
The actual maximum data rate depends on the master's CLK to MISO and MOSI setup and hold timings.
At 25pF load, including GPIO capacitance, see GPIO spec.
This is to ensure compatibility to SPI masters sampling MISO on the same edge as MOSI is output
Page 307
32 SPIS — Serial peripheral interface slave with
EasyDMA
Master
Slave
CSN (in)
SCK
CPOL=0
CPHA=0
tSUCSN
tCSCK
tWHSCK
tWLSCK
CPOL=1
CPHA=0
tHCSN
tRSCK
tFSCK
CPOL=0
CPHA=1
CPOL=1
CPHA=1
tSUMI
tASO
MISO (in)
MISO (out)
tHMI
tVSO
tDISSO
MSb
LSb
tVMO
tHSI
tSUSI
MOSI (out)
MOSI (in)
tHSO
tHMO
MSb
LSb
Figure 78: Common SPIM and SPIS timing diagram
Page 308
2
33 TWIM — I C compatible two-wire interface
master with EasyDMA
2
33 TWIM — I C compatible two-wire interface master
with EasyDMA
TWI master with EasyDMA (TWIM) is a two-wire half-duplex master which can communicate with multiple
slave devices connected to the same bus
Listed here are the main features for TWIM:
•
•
•
•
2
I C compatible
100 kbps, 250 kbps, or 400 kbps
Support for clock stretching
EasyDMA
The two-wire interface can communicate with a bi-directional wired-AND bus with two lines (SCL, SDA).
The protocol makes it possible to interconnect up to 127 individually addressable devices. TWIM is not
compatible with CBUS.
STOP
RESUME
SUSPEND
STARTTX
STARTRX
The GPIOs used for each two-wire interface line can be chosen from any GPIO on the device and are
independently configurable. This enables great flexibility in device pinout and efficient use of board space
and signal routing.
TWIM
GPIO
RAM
PSEL.SDA
TXD.PTR
buffer[0]
buffer[1]
SDA
Pin
SCL
Pin
TXD+1
EasyDMA
buffer[TXD.MAXCNT-1]
RXD-1
EasyDMA
buffer[0]
TXD buffer
buffer[1]
RXD buffer
PSEL.SCK
RXD.PTR
STOPPED
ERROR
SUSPENDED
LASTTX
LASTRX
TXSTARTED
RXSTARTED
buffer[RXD.MAXCNT-1]
Figure 79: TWI master with EasyDMA
A typical TWI setup consists of one master and one or more slaves. For an example, see Figure 80: A typical
TWI setup comprising one master and three slaves on page 310. This TWIM is only able to operate as a
single master on the TWI bus. Multi-master bus configuration is not supported.
Page 309
2
33 TWIM — I C compatible two-wire interface
master with EasyDMA
VDD
VDD
TWI master
(TWIM)
SDA
SCL
R
R
TWI slave
(EEPROM)
TWI slave
(Sensor)
TWI slave
Address = b1011001
Address = b1011000
Address = b1011011
SCL
SDA
SCL
SDA
SCL
SDA
Figure 80: A typical TWI setup comprising one master and three slaves
This TWI master supports clock stretching performed by the slaves. The TWI master is started by triggering
the STARTTX or STARTRX tasks, and stopped by triggering the STOP task. The TWI master will generate a
STOPPED event when it has stopped following a STOP task.
The TWI master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI
master has been resumed.
After the TWI master is started, the STARTTX task or the STARTRX task should not be triggered again
before the TWI master has stopped, i.e. following a LASTRX, LASTTX or STOPPED event.
If a NACK is clocked in from the slave, the TWI master will generate an ERROR event.
33.1 Shared resources
The TWI master shares registers and other resources with other peripherals that have the same ID as the
TWI master. Therefore, you must disable all peripherals that have the same ID as the TWI master before the
TWI master can be configured and used.
Disabling a peripheral that has the same ID as the TWI master will not reset any of the registers that are
shared with the TWI master. It is therefore important to configure all relevant registers explicitly to secure that
the TWI master operates correctly.
The Instantiation table in Instantiation on page 25 shows which peripherals have the same ID as the TWI.
33.2 EasyDMA
The TWI master implements EasyDMA for reading and writing to and from the RAM.
If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 24 for more information about the different memory
regions.
The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/
TX transmission immediately after having received the RXSTARTED/TXSTARTED event.
The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM.
33.2.1 EasyDMA list
EasyDMA supports one list type.
The supported list type is:
•
Array list
EasyDMA array list
The EasyDMA array list can be represented by the data structure ArrayList_type.
For illustration, see the code example below. This data structure includes only a buffer with size equal
to Channel.MAXCNT. EasyDMA will use the Channel.MAXCNT register to determine when the buffer
is full. Replace 'Channel' by the specific data channel you want to use, for instance 'NRF_SPIM->RXD',
'NRF_SPIM->TXD', 'NRF_TWIM->RXD', etc.
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33 TWIM — I C compatible two-wire interface
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The Channel.MAXCNT register cannot be specified larger than the actual size of the buffer. If
Channel.MAXCNT is specified larger than the size of the buffer, the EasyDMA channel may overflow the
buffer.
This array list does not provide a mechanism to explicitly specify where the next item in the list is located.
Instead, it assumes that the list is organized as a linear array where items are located one after the other in
RAM.
#define BUFFER_SIZE
4
typedef struct ArrayList
{
uint8_t buffer[BUFFER_SIZE];
} ArrayList_type;
ArrayList_type MyArrayList[3];
//replace 'Channel' below by the specific data channel you want to use,
//
for instance 'NRF_SPIM->RXD', 'NRF_TWIM->RXD', etc.
Channel.MAXCNT = BUFFER_SIZE;
Channel.PTR = &MyArrayList;
Channel.PTR = &MyArrayList
Note: addresses are
assuming that
sizeof(buffer[n]) is one byte
0x20000000 : MyArrayList[0]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000004 : MyArrayList[1]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000008 : MyArrayList[2]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
Figure 81: EasyDMA array list
33.3 Master write sequence
A TWI master write sequence is started by triggering the STARTTX task. After the STARTTX task has
been triggered, the TWI master will generate a start condition on the TWI bus, followed by clocking out the
address and the READ/WRITE bit set to 0 (WRITE=0, READ=1).
The address must match the address of the slave device that the master wants to write to. The READ/
WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) generated by the slave.
After receiving the ACK bit, the TWI master will clock out the data bytes found in the transmit buffer located
in RAM at the address specified in the TXD.PTR register. Each byte clocked out from the master will be
followed by an ACK/NACK bit clocked in from the slave.
A typical TWI master write sequence is illustrated in Figure 82: TWI master writing data to a slave on page
312. Occurrence 2 in the figure illustrates clock stretching performed by the TWI master following a
SUSPEND task.
A SUSPENDED event indicates that the SUSPEND task has taken effect; this event can be used to
synchronize the software.
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33 TWIM — I C compatible two-wire interface
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STOPPED
4
STOP
RESUME
3
SUSPEND
STARTTX
TXD.MAXCNT = N+1
LASTTX
SUSPENDED
TWI
CPU Lifeline
2
N
ACK
1
N-1
STOP
2
ACK
Stretch
ACK
1
ACK
0
ACK
ACK
WRITE
START
ADDR
Figure 82: TWI master writing data to a slave
The TWI master will generate a LASTTX event when it starts to transmit the last byte, this is illustrated in
Figure 82: TWI master writing data to a slave on page 312
The TWI master is stopped by triggering the STOP task, this task should be triggered during the
transmission of the last byte to secure that the TWI will stop as fast as possible after sending the last byte. It
is safe to use the shortcut between LASTTX and STOP to accomplish this.
Note that the TWI master does not stop by itself when the whole RAM buffer has been sent, or when an error
occurs. The STOP task must be issued, through the use of a local or PPI shortcut, or in software as part of
the error handler.
The TWI master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI
master has been resumed.
33.4 Master read sequence
A TWI master read sequence is started by triggering the STARTRX task. After the STARTRX task has been
triggered the TWI master will generate a start condition on the TWI bus, followed by clocking out the address
and the READ/WRITE bit set to 1 (WRITE = 0, READ = 1). The address must match the address of the slave
device that the master wants to read from. The READ/WRITE bit is followed by an ACK/NACK bit (ACK=0 or
NACK = 1) generated by the slave.
After having sent the ACK bit the TWI slave will send data to the master using the clock generated by the
master.
Data received will be stored in RAM at the address specified in the RXD.PTR register. The TWI master will
generate an ACK after all but the last byte received from the slave. The TWI master will generate a NACK
after the last byte received to indicate that the read sequence shall stop.
A typical TWI master read sequence is illustrated in Figure 83: The TWI master reading data from a slave on
page 313. Occurrence 2 in the figure illustrates clock stretching performed by the TWI master following a
SUSPEND task.
A SUSPENDED event indicates that the SUSPEND task has taken effect; this event can be used to
synchronize the software.
The TWI master will generate a LASTRX event when it is ready to receive the last byte, this is illustrated
in Figure 83: The TWI master reading data from a slave on page 313. If RXD.MAXCNT > 1 the LASTRX
event is generated after sending the ACK of the previously received byte. If RXD.MAXCNT = 1 the LASTRX
event is generated after receiving the ACK following the address and READ bit.
The TWI master is stopped by triggering the STOP task, this task must be triggered before the NACK bit
is supposed to be transmitted. The STOP task can be triggered at any time during the reception of the last
byte. It is safe to use the shortcut between LASTRX and STOP to accomplish this.
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33 TWIM — I C compatible two-wire interface
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Note that the TWI master does not stop by itself when the RAM buffer is full, or when an error occurs. The
STOP task must be issued, through the use of a local or PPI shortcut, or in software as part of the error
handler.
The TWI master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI
master has been resumed.
LASTRX
3
4
STOP
SUSPEND
RESUME
2
STARTRX
RXD.MAXCNT = M+1
CPU Lifeline
1
M
STOPPED
M-1
SUSPENDED
TWI
2
STOP
NACK
Stretch
ACK
1
ACK
ACK
0
ACK
ACK
READ
START
ADDR
Figure 83: The TWI master reading data from a slave
33.5 Master repeated start sequence
A typical repeated start sequence is one in which the TWI master writes two bytes to the slave followed by
reading four bytes from the slave. This example uses shortcuts to perform the simplest type of repeated start
sequence, i.e. one write followed by one read. The same approach can be used to perform a repeated start
sequence where the sequence is read followed by write.
STOPPED
LASTRX
LASTTX
STOP
STARTRX
2
STARTTX
TXD.MAXCNT = 2
RXD.MAXCNT = 4
CPU Lifeline
STOP
1
3
NACK
2
ACK
1
ACK
0
ACK
ADDR
ACK
READ
1
RESTART
ACK
0
ACK
ADDR
ACK
WRITE
START
CPU Lifeline
The figure Figure 84: A repeated start sequence, where the TWI master writes two bytes followed by reading
4 bytes from the slave on page 313 illustrates this:
Figure 84: A repeated start sequence, where the TWI master writes two bytes followed by reading 4
bytes from the slave
If a more complex repeated start sequence is needed and the TWI firmware drive is serviced in a low priority
interrupt it may be necessary to use the SUSPEND task and SUSPENDED event to guarantee that the
correct tasks are generated at the correct time. This is illustrated in Figure 85: A double repeated start
sequence using the SUSPEND task to secure safe operation in low priority interrupts on page 314.
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33 TWIM — I C compatible two-wire interface
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STOPPED
LASTTX
5
STOP
STARTTX
RESUME
STARTRX
TXD.MAXCNT = 2
SUSPEND
RXD.MAXCNT = 1
STARTTX
TXD.MAXCNT = 1
LASTRX
SUSPENDED
LASTTX
TWI
CPU Lifeline
4
ACK
3
1
STOP
0
ACK
2
ADDR
ACK
WRITE
1
0
NACK
ADDR
RESTART
Stretch
ACK
READ
0
RESTART
ACK
ACK
WRITE
START
ADDR
Figure 85: A double repeated start sequence using the SUSPEND task to secure safe operation in low
priority interrupts
33.6 Low power
When putting the system in low power and the peripheral is not needed, lowest possible power consumption
is achieved by stopping, and then disabling the peripheral.
The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent,
software shall wait until the STOPPED event was received as a response before disabling the peripheral
through the ENABLE register.
33.7 Master mode pin configuration
The SCL and SDA signals associated with the TWI master are mapped to physical pins according to the
configuration specified in the PSEL.SCL and PSEL.SDA registers respectively.
The PSEL.SCL and PSEL.SDA registers and their configurations are only used as long as the TWI master
is enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins
will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n]
register. PSEL.SCL, PSEL.SDA must only be configured when the TWI master is disabled.
To secure correct signal levels on the pins used by the TWI master when the system is in OFF mode, and
when the TWI master is disabled, these pins must be configured in the GPIO peripheral as described in
Table 76: GPIO configuration before enabling peripheral on page 314.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
Table 76: GPIO configuration before enabling peripheral
TWI master signal
SCL
SDA
TWI master pin
As specified in PSEL.SCL
As specified in PSEL.SDA
Direction
Input
Input
Output value
Not applicable
Not applicable
33.8 Registers
Table 77: Instances
Base address
Peripheral
Instance
Description
0x40003000
TWIM
TWIM0
Two-wire interface master 0
0x40004000
TWIM
TWIM1
Two-wire interface master 1
Page 314
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Drive strength
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33 TWIM — I C compatible two-wire interface
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Table 78: Register Overview
Register
Offset
Description
TASKS_STARTRX
0x000
Start TWI receive sequence
TASKS_STARTTX
0x008
Start TWI transmit sequence
TASKS_STOP
0x014
Stop TWI transaction. Must be issued while the TWI master is not suspended.
TASKS_SUSPEND
0x01C
Suspend TWI transaction
TASKS_RESUME
0x020
Resume TWI transaction
EVENTS_STOPPED
0x104
TWI stopped
EVENTS_ERROR
0x124
TWI error
EVENTS_SUSPENDED
0x148
Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
EVENTS_RXSTARTED
0x14C
Receive sequence started
EVENTS_TXSTARTED
0x150
Transmit sequence started
EVENTS_LASTRX
0x15C
Byte boundary, starting to receive the last byte
EVENTS_LASTTX
0x160
Byte boundary, starting to transmit the last byte
SHORTS
0x200
Shortcut register
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ERRORSRC
0x4C4
Error source
ENABLE
0x500
Enable TWIM
PSEL.SCL
0x508
Pin select for SCL signal
PSEL.SDA
0x50C
Pin select for SDA signal
FREQUENCY
0x524
TWI frequency
RXD.PTR
0x534
Data pointer
RXD.MAXCNT
0x538
Maximum number of bytes in receive buffer
RXD.AMOUNT
0x53C
Number of bytes transferred in the last transaction
RXD.LIST
0x540
EasyDMA list type
TXD.PTR
0x544
Data pointer
TXD.MAXCNT
0x548
Maximum number of bytes in transmit buffer
TXD.AMOUNT
0x54C
Number of bytes transferred in the last transaction
TXD.LIST
0x550
EasyDMA list type
ADDRESS
0x588
Address used in the TWI transfer
33.8.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F
Reset 0x00000000
Id
RW Field
A
RW LASTTX_STARTRX
0
Value Id
D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between LASTTX event and STARTRX task
See EVENTS_LASTTX and TASKS_STARTRX
B
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW LASTTX_SUSPEND
Shortcut between LASTTX event and SUSPEND task
See EVENTS_LASTTX and TASKS_SUSPEND
C
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW LASTTX_STOP
Shortcut between LASTTX event and STOP task
See EVENTS_LASTTX and TASKS_STOP
D
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW LASTRX_STARTTX
Shortcut between LASTRX event and STARTTX task
See EVENTS_LASTRX and TASKS_STARTTX
Disabled
0
Disable shortcut
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F
Reset 0x00000000
Id
F
RW Field
0
D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Enable shortcut
RW LASTRX_STOP
Shortcut between LASTRX event and STOP task
See EVENTS_LASTRX and TASKS_STOP
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
33.8.2 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
J
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
I
H G F
D
Value
Description
Enable or disable interrupt for STOPPED event
See EVENTS_STOPPED
D
Disabled
0
Disable
Enabled
1
Enable
RW ERROR
Enable or disable interrupt for ERROR event
See EVENTS_ERROR
F
Disabled
0
Disable
Enabled
1
Enable
RW SUSPENDED
Enable or disable interrupt for SUSPENDED event
See EVENTS_SUSPENDED
G
Disabled
0
Disable
Enabled
1
Enable
RW RXSTARTED
Enable or disable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
H
Disabled
0
Disable
Enabled
1
Enable
RW TXSTARTED
Enable or disable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
I
Disabled
0
Disable
Enabled
1
Enable
RW LASTRX
Enable or disable interrupt for LASTRX event
See EVENTS_LASTRX
J
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Disabled
0
Disable
Enabled
1
Enable
RW LASTTX
Enable or disable interrupt for LASTTX event
See EVENTS_LASTTX
Disabled
0
Disable
Enabled
1
Enable
33.8.3 INTENSET
Address offset: 0x304
Enable interrupt
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
J
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
I
H G F
D
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Enable interrupt for ERROR event
See EVENTS_ERROR
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SUSPENDED
Write '1' to Enable interrupt for SUSPENDED event
See EVENTS_SUSPENDED
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXSTARTED
Write '1' to Enable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTARTED
Write '1' to Enable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW LASTRX
Write '1' to Enable interrupt for LASTRX event
See EVENTS_LASTRX
J
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW LASTTX
Write '1' to Enable interrupt for LASTTX event
See EVENTS_LASTTX
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
33.8.4 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
J
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
I
H G F
Value
Description
Write '1' to Disable interrupt for STOPPED event
See EVENTS_STOPPED
D
D
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Disable interrupt for ERROR event
See EVENTS_ERROR
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33 TWIM — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
J
Reset 0x00000000
Id
F
RW Field
0
I
H G F
D
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SUSPENDED
Write '1' to Disable interrupt for SUSPENDED event
See EVENTS_SUSPENDED
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXSTARTED
Write '1' to Disable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTARTED
Write '1' to Disable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW LASTRX
Write '1' to Disable interrupt for LASTRX event
See EVENTS_LASTRX
J
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW LASTTX
Write '1' to Disable interrupt for LASTTX event
See EVENTS_LASTTX
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
33.8.5 ERRORSRC
Address offset: 0x4C4
Error source
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW OVERRUN
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Overrun error
A new byte was received before previous byte got transferred
into RXD buffer. (Previous data is lost)
B
C
NotReceived
0
Error did not occur
Received
1
Error occurred
NotReceived
0
Error did not occur
Received
1
Error occurred
NotReceived
0
Error did not occur
Received
1
Error occurred
RW ANACK
NACK received after sending the address (write '1' to clear)
RW DNACK
NACK received after sending a data byte (write '1' to clear)
33.8.6 ENABLE
Address offset: 0x500
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33 TWIM — I C compatible two-wire interface
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Enable TWIM
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable TWIM
Enabled
6
Enable TWIM
Enable or disable TWIM
33.8.7 PSEL.SCL
Address offset: 0x508
Pin select for SCL signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
33.8.8 PSEL.SDA
Address offset: 0x50C
Pin select for SDA signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
33.8.9 FREQUENCY
Address offset: 0x524
TWI frequency
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x04000000
Id
RW Field
A
RW FREQUENCY
0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
K100
0x01980000
100 kbps
K250
0x04000000
250 kbps
K400
0x06400000
400 kbps
TWI master clock frequency
33.8.10 RXD.PTR
Address offset: 0x534
Data pointer
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33 TWIM — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
33.8.11 RXD.MAXCNT
Address offset: 0x538
Maximum number of bytes in receive buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[1..255]
Maximum number of bytes in receive buffer
33.8.12 RXD.AMOUNT
Address offset: 0x53C
Number of bytes transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last transaction. In case of
NACK error, includes the NACK'ed byte.
33.8.13 RXD.LIST
Address offset: 0x540
EasyDMA list type
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
RW LIST
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable EasyDMA list
ArrayList
1
Use array list
List type
33.8.14 TXD.PTR
Address offset: 0x544
Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
33.8.15 TXD.MAXCNT
Address offset: 0x548
Maximum number of bytes in transmit buffer
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33 TWIM — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[1..255]
Maximum number of bytes in transmit buffer
33.8.16 TXD.AMOUNT
Address offset: 0x54C
Number of bytes transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last transaction. In case of
NACK error, includes the NACK'ed byte.
33.8.17 TXD.LIST
Address offset: 0x550
EasyDMA list type
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
RW LIST
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable EasyDMA list
ArrayList
1
Use array list
List type
33.8.18 ADDRESS
Address offset: 0x588
Address used in the TWI transfer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ADDRESS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Address used in the TWI transfer
33.9 Electrical specification
33.9.1 TWIM interface electrical specifications
Symbol
Description
Min.
fTWIM
Bit rates for TWIM30
100
Typ.
Max.
Units
400
ITWIM,100kbps
Run current for TWIM, 100 kbps
50
kbps
µA
ITWIM,400kbps
Run current for TWIM, 400 kbps
50
µA
tTWIM,START,LP
Time from STARTRX/STARTTX task to transmission started, Low
tTWIM,START,CL
µs
power mode
+
tSTART_HFINT
tTWIM,START,CL
Time from STARTRX/STARTTX task to transmission started,
1.5
µs
Constant latency mode
30
Higher bit rates or stronger pull-ups may require GPIOs to be set as High Drive, see GPIO chapter for more
details.
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33 TWIM — I C compatible two-wire interface
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33.9.2 Two Wire Interface Master (TWIM) timing specifications
Symbol
Description
fTWIM,SCL,100kbps
SCL clock frequency, 100 kbps
Min.
Typ.
100
Max.
Units
kHz
fTWIM,SCL,250kbps
SCL clock frequency, 250 kbps
250
kHz
fTWIM,SCL,400kbps
SCL clock frequency, 400 kbps
400
kHz
tTWIM,SU_DAT
Data setup time before positive edge on SCL – all modes
300
ns
tTWIM,HD_DAT
Data hold time after negative edge on SCL – all modes
500
ns
tTWIM,HD_STA,100kbps
TWIM master hold time for START and repeated START
10000
ns
4000
ns
2500
ns
5000
ns
2000
ns
1250
ns
5800
ns
2700
ns
2100
ns
condition, 100 kbps
tTWIM,HD_STA,250kbps
TWIM master hold time for START and repeated START
condition, 250kbps
tTWIM,HD_STA,400kbps
TWIM master hold time for START and repeated START
condition, 400 kbps
tTWIM,SU_STO,100kbps
TWIM master setup time from SCL high to STOP condition, 100
kbps
tTWIM,SU_STO,250kbps
TWIM master setup time from SCL high to STOP condition, 250
kbps
tTWIM,SU_STO,400kbps
TWIM master setup time from SCL high to STOP condition, 400
kbps
tTWIM,BUF,100kbps
TWIM master bus free time between STOP and START
conditions, 100 kbps
tTWIM,BUF,250kbps
TWIM master bus free time between STOP and START
conditions, 250 kbps
tTWIM,BUF,400kbps
TWIM master bus free time between STOP and START
conditions, 400 kbps
Figure 86: TWIM timing diagram, 1 byte transaction
R [kΩ]
30
100 kbps
25
400 kbps
20
15
13
10
5
0
0
100
200
300
400
500
cap [pF]
Figure 87: Recommended TWIM pullup value vs. line capacitance
•
•
The I2C specification allows a line capacitance of 400 pF at most.
The nRF52832 internal pullup has a fixed value of typ. 13 kOhm, see RPU in the GPIO chapter.
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34 TWIS — I C compatible two-wire interface
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34 TWIS — I C compatible two-wire interface slave with
EasyDMA
2
TWI slave with EasyDMA (TWIS) is compatible with I C operating at 100 kHz and 400 kHz. The TWI
transmitter and receiver implement EasyDMA.
PSELSDA
PSELSCK
PSELSDA
PREPARETX
PREPARERX
RXD
(signal)
STOPPED
TXD
(signal)
SUSPEND
RESUME
EasyDMA
RXD.PTR
EasyDMA
TXD.PTR
WRITE
READ
RAM
RXD
TXD
RXD+1
TXD+1
RXD+2
TXD+2
RXD+n
TXD+n
Figure 88: TWI slave with EasyDMA
A typical TWI setup consists of one master and one or more slaves. For an example, see Figure 89: A typical
TWI setup comprising one master and three slaves on page 323. TWIS is only able to operate with a single
master on the TWI bus.
VDD
VDD
TWI master
SDA
SCL
R
R
TWI slave
(EEPROM)
TWI slave
(Sensor)
Address = b1011001
Address = b1011000
SCL
SDA
SCL
SDA
TWI slave
(TWIS)
Address = b1011011
SCL
SDA
Figure 89: A typical TWI setup comprising one master and three slaves
The TWI slave state machine is illustrated in Figure 90: TWI slave state machine on page 324 and Table
79: TWI slave state machine symbols on page 324 is explaining the different symbols used in the state
machine.
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34 TWIS — I C compatible two-wire interface
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PREPARETX
PREPARERX
ENABLE
/ STOPPED
Unprepare TX,
Unprepare RX
IDLE
STOP
[ READ && (TX prepared) ]
[ WRITE && (RX prepared) ]
Restart sequence
Stop sequence
TX
RX
entry / Unprepare TX
entry / Unprepare RX
entry / TXSTARTED
entry / RXSTARTED
Figure 90: TWI slave state machine
Table 79: TWI slave state machine symbols
Symbol
ENABLE
PREPARETX
STOP
PREPARERX
STOPPED
RXSTARTED
TXSTARTED
TX prepared
RX prepared
Unprepare TX
Unprepare RX
Stop sequence
Restart sequence
Type
Register
Task
Task
Task
Event
Event
Event
Internal
Internal
Internal
Internal
TWI protocol
TWI protocol
Description
The TWI slave has been enabled via the ENABLE register
The TASKS_PREPARETX task has been triggered
The TASKS_STOP task has been triggered
The TASKS_PREPARERX task has been triggered
The EVENTS_STOPPED event was generated
The EVENTS_RXSTARTED event was generated
The EVENTS_TXSTARTED event was generated
Internal flag indicating that a TASKS_PREPARETX task has been triggered. This flag is not visible to the user.
Internal flag indicating that a TASKS_PREPARERX task has been triggered. This flag is not visible to the user.
Clears the internal 'TX prepared' flag until next TASKS_PREPARETX task.
Clears the internal 'RX prepared' flag until next TASKS_PREPARERX task.
A TWI stop sequence was detected
A TWI restart sequence was detected
The TWI slave supports clock stretching performed by the master.
The TWI slave operates in a low power mode while waiting for a TWI master to initiate a transfer. As long as
the TWI slave is not addressed, it will remain in this low power mode.
To secure correct behaviour of the TWI slave, PSEL.SCL, PSEL.SDA, CONFIG and the ADDRESS[n]
registers, must be configured prior to enabling the TWI slave through the ENABLE register. Similarly,
changing these settings must be performed while the TWI slave is disabled. Failing to do so may result in
unpredictable behaviour.
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34 TWIS — I C compatible two-wire interface
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34.1 Shared resources
The TWI slave shares registers and other resources with other peripherals that have the same ID as the TWI
slave.
Therefore, you must disable all peripherals that have the same ID as the TWI slave before the TWI slave can
be configured and used. Disabling a peripheral that has the same ID as the TWI slave will not reset any of
the registers that are shared with the TWI slave. It is therefore important to configure all relevant registers
explicitly to secure that the TWI slave operates correctly.
The Instantiation table in Instantiation on page 25 shows which peripherals have the same ID as the TWI
slave.
34.2 EasyDMA
The TWI slave implements EasyDMA for reading and writing to and from the RAM.
The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM.
If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 24 for more information about the different memory
regions.
34.3 TWI slave responding to a read command
Before the TWI slave can respond to a read command the TWI slave must be configured correctly and
enabled via the ENABLE register. When enabled the TWI slave will be in its IDLE state where it will consume
IIDLE .
A read command is started when the TWI master generates a start condition on the TWI bus, followed by
clocking out the address and the READ/WRITE bit set to 1 (WRITE=0, READ=1). The READ/WRITE bit is
followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the TWI slave.
The TWI slave is able to listen for up to two addresses at the same time. Which addresses to listen for is
configured in the ADDRESS registers and the CONFIG register.
The TWI slave will only acknowledge (ACK) the read command if the address presented by the master
matches one of the addresses the slave is configured to listen for. The TWI slave will generate a READ
event when it acknowledges the read command.
The TWI slave is only able to detect a read command from the IDLE state.
The TWI slave will set an internal 'TX prepared' flag when the PREPARETX task is triggered.
When the read command is received the TWI slave will enter the TX state if the internal 'TX prepared' flag is
set.
If the internal 'TX prepared' flag is not set when the read command is received, the TWI slave will stretch the
master's clock until the PREPARETX task is triggered and the internal 'TX prepared' flag is set.
The TWI slave will generate the TXSTARTED event and clear the 'TX prepared' flag ('unprepare TX') when
it enters the TX state. In this state the TWI slave will send the data bytes found in the transmit buffer to the
master using the master's clock. The TWI slave will consume ITX in this mode.
The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the TX
state.
The TWI slave is stopped when it receives the stop condition from the TWI master. A STOPPED event will
be generated when the transaction has stopped. The TWI slave will clear the 'TX prepared' flag ('unprepare
TX') and go back to the IDLE state when it has stopped.
The transmit buffer is located in RAM at the address specified in the TXD.PTR register. The TWI slave will
only be able to send TXD.MAXCNT bytes from the transmit buffer for each transaction. If the TWI master
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34 TWIS — I C compatible two-wire interface
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forces the slave to send more than TXD.MAXCNT bytes, the slave will send the byte specified in the ORC
register to the master instead. If this happens, an ERROR event will be generated.
The EasyDMA configuration registers, see TXD.PTR etc., are latched when the TXSTARTED event is
generated.
The TWI slave can be forced to stop by triggering the STOP task. A STOPPED event will be generated when
the TWI slave has stopped. The TWI slave will clear the 'TX prepared' flag and go back to the IDLE state
when it has stopped, see also Terminating an ongoing TWI transaction on page 328.
Each byte sent from the slave will be followed by an ACK/NACK bit sent from the master. The TWI master
will generate a NACK following the last byte that it wants to receive to tell the slave to release the bus so
that the TWI master can generate the stop condition. The TXD.AMOUNT register can be queried after a
transaction to see how many bytes were sent.
A typical TWI slave read command response is illustrated in Figure 91: The TWI slave responding to a read
command on page 326. Occurrence 2 in the figure illustrates clock stretching performed by the TWI slave
following a SUSPEND task.
STOPPED
READ
3
4
SUSPEND
RESUME
2
PREPARETX
TXD.MAXCNT >= N+1
TXD.PTR = 0x20000000
TXSTARTED
TWI
CPU Lifeline
N
STOP
N-1
NACK
2
ACK
Stretch
ACK
1
ACK
1
0
ACK
ACK
READ
START
ADDR
Figure 91: The TWI slave responding to a read command
34.4 TWI slave responding to a write command
Before the TWI slave can respond to a write command the TWI slave must be configured correctly and
enabled via the ENABLE register. When enabled the TWI slave will be in its IDLE state where it will consume
IIDLE.
A write command is started when the TWI master generates a start condition on the TWI bus, followed by
clocking out the address and the READ/WRITE bit set to 0 (WRITE=0, READ=1). The READ/WRITE bit is
followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the slave.
The TWI slave is able to listen for up to two addresses at the same time. Which addresses to listen for is
configured in the ADDRESS registers and the CONFIG register.
The TWI slave will only acknowledge (ACK) the write command if the address presented by the master
matches one of the addresses the slave is configured to listen for. The TWI slave will generate a WRITE
event if it acknowledges the write command.
The TWI slave is only able to detect a write command from the IDLE state.
The TWI slave will set an internal 'RX prepared' flag when the PREPARERX task is triggered.
When the write command is received the TWI slave will enter the RX state if the internal 'RX prepared' flag is
set.
If the internal 'RX prepared' flag is not set when the write command is received, the TWI slave will stretch the
master's clock until the PREPARERX task is triggered and the internal 'RX prepared' flag is set.
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34 TWIS — I C compatible two-wire interface
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The TWI slave will generate the RXSTARTED event and clear the internal 'RX prepared' flag ('unprepare
RX') when it enters the RX state. In this state the TWI slave will be able to receive the bytes sent by the TWI
master. The TWI slave will consume IRX in this mode.
The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the
RX state.
The TWI slave is stopped when it receives the stop condition from the TWI master. A STOPPED event will
be generated when the transaction has stopped. The TWI slave will clear the internal 'RX prepared' flag
('unprepare RX') and go back to the IDLE state when it has stopped.
The receive buffer is located in RAM at the address specified in the TXD.PTR register. The TWI slave will
only be able to receive as many bytes as specified in the RXD.MAXCNT register. If the TWI master tries to
send more bytes to the slave than the slave is able to receive,these bytes will be discarded and the bytes will
be NACKed by the slave. If this happens, an ERROR event will be generated.
The EasyDMA configuration registers, see RXD.PTR etc., are latched when the RXSTARTED event is
generated.
The TWI slave can be forced to stop by triggering the STOP task. A STOPPED event will be generated when
the TWI slave has stopped. The TWI slave will clear the internal 'RX prepared' flag and go back to the IDLE
state when it has stopped, see also Terminating an ongoing TWI transaction on page 328.
The TWI slave will generate an ACK after every byte received from the master. The RXD.AMOUNT register
can be queried after a transaction to see how many bytes were received.
A typical TWI slave write command response is illustrated in Figure 92: The TWI slave responding to a write
command on page 327. Occurrence 2 in the figure illustrates clock stretching performed by the TWI slave
following a SUSPEND task.
M-1
M
STOPPED
2
3
SUSPEND
RESUME
WRITE
PREPARERX
RXD.MAXCNT >= M+1
RXD.PTR = 0x20000000
RXSTARTED
TWI
CPU Lifeline
2
STOP
ACK
Stretch
ACK
1
ACK
ACK
1
0
ACK
ACK
WRITE
START
ADDR
4
Figure 92: The TWI slave responding to a write command
34.5 Master repeated start sequence
An example of a repeated start sequence is one in which the TWI master writes two bytes to the slave
followed by reading four bytes from the slave.
This is illustrated in Figure 93: A repeated start sequence, where the TWI master writes two bytes followed
by reading four bytes from the slave on page 328.
It is here assumed that the receiver does not know in advance what the master wants to read, and that
this information is provided in the first two bytes received in the write part of the repeated start sequence.
To guarantee that the CPU is able to process the received data before the TWI slave starts to reply to the
read command, the SUSPEND task is triggered via a shortcut from the READ event generated when the
read command is received. When the CPU has processed the incoming data and prepared the correct data
response, the CPU will resume the transaction by triggering the RESUME task.
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34 TWIS — I C compatible two-wire interface
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STOPPED
3
RESUME
TXD.MAXCNT = 4
PREPARETX
SUSPEND
TXD.PTR = 0x20000010
PREPARERX
RXD.MAXCNT = 2
RXD.PTR = 0x20000000
TXSTARTED
READ
WRITE
RXSTARTED
TWI
CPU Lifeline
STOP
3
NACK
2
2
ACK
1
1
ACK
0
ACK
ADDR
ACK
READ
1
RESTART
ACK
0
ACK
ACK
WRITE
START
ADDR
Figure 93: A repeated start sequence, where the TWI master writes two bytes followed by reading
four bytes from the slave
34.6 Terminating an ongoing TWI transaction
In some situations, e.g. if the external TWI master is not responding correctly, it may be required to terminate
an ongoing transaction.
This can be achieved by triggering the STOP task. In this situation a STOPPED event will be generated
when the TWI has stopped independent of whether or not a STOP condition has been generated on the TWI
bus. The TWI slave will release the bus when it has stopped and go back to its IDLE state.
34.7 Low power
When putting the system in low power and the peripheral is not needed, lowest possible power consumption
is achieved by stopping, and then disabling the peripheral.
The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent,
software shall wait until the STOPPED event was received as a response before disabling the peripheral
through the ENABLE register.
34.8 Slave mode pin configuration
The SCL and SDA signals associated with the TWI slave are mapped to physical pins according to the
configuration specified in the PSEL.SCL and PSEL.SDA registers respectively.
The PSEL.SCL and PSEL.SDA registers and their configurations are only used as long as the TWI slave is
enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins
will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n]
register. PSEL.SCL and PSEL.SDA must only be configured when the TWI slave is disabled.
To secure correct signal levels on the pins used by the TWI slave when the system is in OFF mode, and
when the TWI slave is disabled, these pins must be configured in the GPIO peripheral as described in Table
80: GPIO configuration before enabling peripheral on page 328.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
Table 80: GPIO configuration before enabling peripheral
TWI slave signal
SCL
SDA
TWI slave pin
As specified in PSEL.SCL
As specified in PSEL.SDA
Direction
Input
Input
Page 328
Output value
Not applicable
Not applicable
Drive strength
S0D1
S0D1
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34 TWIS — I C compatible two-wire interface
slave with EasyDMA
34.9 Registers
Table 81: Instances
Base address
Peripheral
Instance
Description
0x40003000
TWIS
TWIS0
Two-wire interface slave 0
Configuration
0x40004000
TWIS
TWIS1
Two-wire interface slave 1
Table 82: Register Overview
Register
Offset
Description
TASKS_STOP
0x014
Stop TWI transaction
TASKS_SUSPEND
0x01C
Suspend TWI transaction
TASKS_RESUME
0x020
Resume TWI transaction
TASKS_PREPARERX
0x030
Prepare the TWI slave to respond to a write command
TASKS_PREPARETX
0x034
Prepare the TWI slave to respond to a read command
EVENTS_STOPPED
0x104
TWI stopped
EVENTS_ERROR
0x124
TWI error
EVENTS_RXSTARTED
0x14C
Receive sequence started
EVENTS_TXSTARTED
0x150
Transmit sequence started
EVENTS_WRITE
0x164
Write command received
EVENTS_READ
0x168
Read command received
SHORTS
0x200
Shortcut register
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ERRORSRC
0x4D0
Error source
MATCH
0x4D4
Status register indicating which address had a match
ENABLE
0x500
Enable TWIS
PSEL.SCL
0x508
Pin select for SCL signal
PSEL.SDA
0x50C
Pin select for SDA signal
RXD.PTR
0x534
RXD Data pointer
RXD.MAXCNT
0x538
Maximum number of bytes in RXD buffer
RXD.AMOUNT
0x53C
Number of bytes transferred in the last RXD transaction
TXD.PTR
0x544
TXD Data pointer
TXD.MAXCNT
0x548
Maximum number of bytes in TXD buffer
TXD.AMOUNT
0x54C
Number of bytes transferred in the last TXD transaction
ADDRESS[0]
0x588
TWI slave address 0
ADDRESS[1]
0x58C
TWI slave address 1
CONFIG
0x594
Configuration register for the address match mechanism
ORC
0x5C0
Over-read character. Character sent out in case of an over-read of the transmit buffer.
34.9.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
A
RW WRITE_SUSPEND
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between WRITE event and SUSPEND task
See EVENTS_WRITE and TASKS_SUSPEND
B
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW READ_SUSPEND
Shortcut between READ event and SUSPEND task
See EVENTS_READ and TASKS_SUSPEND
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34 TWIS — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
34.9.2 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
F E
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for STOPPED event
See EVENTS_STOPPED
B
Disabled
0
Disable
Enabled
1
Enable
RW ERROR
Enable or disable interrupt for ERROR event
See EVENTS_ERROR
E
Disabled
0
Disable
Enabled
1
Enable
RW RXSTARTED
Enable or disable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
F
Disabled
0
Disable
Enabled
1
Enable
RW TXSTARTED
Enable or disable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
G
Disabled
0
Disable
Enabled
1
Enable
RW WRITE
Enable or disable interrupt for WRITE event
See EVENTS_WRITE
H
Disabled
0
Disable
Enabled
1
Enable
RW READ
Enable or disable interrupt for READ event
See EVENTS_READ
Disabled
0
Disable
Enabled
1
Enable
34.9.3 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
F E
Value
Description
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
B
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Enable interrupt for ERROR event
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34 TWIS — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G
Reset 0x00000000
Id
RW Field
0
F E
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_ERROR
E
RW RXSTARTED
Write '1' to Enable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTARTED
Write '1' to Enable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW WRITE
Write '1' to Enable interrupt for WRITE event
See EVENTS_WRITE
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW READ
Write '1' to Enable interrupt for READ event
See EVENTS_READ
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
34.9.4 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G
Reset 0x00000000
Id
RW Field
A
RW STOPPED
0
Value Id
F E
B
Value
Description
Write '1' to Disable interrupt for STOPPED event
See EVENTS_STOPPED
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Disable interrupt for ERROR event
See EVENTS_ERROR
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXSTARTED
Write '1' to Disable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTARTED
Write '1' to Disable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
Clear
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Disable
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34 TWIS — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G
Reset 0x00000000
Id
G
RW Field
0
F E
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW WRITE
Write '1' to Disable interrupt for WRITE event
See EVENTS_WRITE
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW READ
Write '1' to Disable interrupt for READ event
See EVENTS_READ
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
34.9.5 ERRORSRC
Address offset: 0x4D0
Error source
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B
Reset 0x00000000
Id
RW Field
A
RW OVERFLOW
B
C
0
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NotDetected
0
Error did not occur
Detected
1
Error occurred
NotReceived
0
Error did not occur
Received
1
Error occurred
NotDetected
0
Error did not occur
Detected
1
Error occurred
RX buffer overflow detected, and prevented
RW DNACK
NACK sent after receiving a data byte
RW OVERREAD
TX buffer over-read detected, and prevented
34.9.6 MATCH
Address offset: 0x4D4
Status register indicating which address had a match
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
MATCH
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..1]
Which of the addresses in {ADDRESS} matched the incoming
address
34.9.7 ENABLE
Address offset: 0x500
Enable TWIS
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Disabled
0
Description
Enable or disable TWIS
Disable TWIS
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34 TWIS — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
9
Enable TWIS
34.9.8 PSEL.SCL
Address offset: 0x508
Pin select for SCL signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
34.9.9 PSEL.SDA
Address offset: 0x50C
Pin select for SDA signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
34.9.10 RXD.PTR
Address offset: 0x534
RXD Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RXD Data pointer
34.9.11 RXD.MAXCNT
Address offset: 0x538
Maximum number of bytes in RXD buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in RXD buffer
34.9.12 RXD.AMOUNT
Address offset: 0x53C
Number of bytes transferred in the last RXD transaction
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34 TWIS — I C compatible two-wire interface
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last RXD transaction
34.9.13 TXD.PTR
Address offset: 0x544
TXD Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
TXD Data pointer
34.9.14 TXD.MAXCNT
Address offset: 0x548
Maximum number of bytes in TXD buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in TXD buffer
34.9.15 TXD.AMOUNT
Address offset: 0x54C
Number of bytes transferred in the last TXD transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last TXD transaction
34.9.16 ADDRESS[0]
Address offset: 0x588
TWI slave address 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ADDRESS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
TWI slave address
34.9.17 ADDRESS[1]
Address offset: 0x58C
TWI slave address 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ADDRESS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
TWI slave address
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34 TWIS — I C compatible two-wire interface
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34.9.18 CONFIG
Address offset: 0x594
Configuration register for the address match mechanism
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000001
Id
RW Field
A
RW ADDRESS0
B
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Description
Disabled
0
Disabled
Enabled
1
Enabled
Disabled
0
Disabled
Enabled
1
Enabled
Enable or disable address matching on ADDRESS[0]
RW ADDRESS1
Enable or disable address matching on ADDRESS[1]
34.9.19 ORC
Address offset: 0x5C0
Over-read character. Character sent out in case of an over-read of the transmit buffer.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW ORC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Over-read character. Character sent out in case of an over-read
of the transmit buffer.
34.10 Electrical specification
34.10.1 TWIS slave interface electrical specifications
Symbol
Description
Min.
fTWIS
Bit rates for TWIS31
100
ITWIS,100kbps
Run current for TWIS (Average current to receive and transfer a
Typ.
Max.
Units
400
kbps
45
µA
45
µA
byte to RAM), 100 kbps
ITWIS,400kbps
Run current for TWIS (Average current to receive and transfer a
byte to RAM), 400 kbps
ITWIS,IDLE
Idle current for TWIS
1
µA
tTWIS,START,LP
Time from PREPARERX/PREPARETX task to ready to receive/
tTWIS,START,CL
µs
transmit, Low power mode
+
tSTART_HFINT
tTWIS,START,CL
Time from PREPARERX/PREPARETX task to ready to receive/
1.5
µs
transmit, Constant latency mode
34.10.2 TWIS slave timing specifications
Symbol
Description
fTWIS,SCL,400kbps
SCL clock frequency, 400 kbps
Min.
Typ.
Max.
Units
400
tTWIS,SU_DAT
Data setup time before positive edge on SCL – all modes
300
kHz
ns
tTWIS,HD_DAT
Data hold time after negative edge on SCL – all modes
500
ns
tTWIS,HD_STA,100kbps
TWI slave hold time from for START condition (SDA low to SCL
5200
ns
1300
ns
low), 100 kbps
tTWIS,HD_STA,400kbps
TWI slave hold time from for START condition (SDA low to SCL
low), 400 kbps
31
Higher bit rates or stronger pull-ups may require GPIOs to be set as High Drive, see GPIO chapter for more
details.
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34 TWIS — I C compatible two-wire interface
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Symbol
Description
Min.
tTWIS,SU_STO,100kbps
TWI slave setup time from SCL high to STOP condition, 100 kbps
5200
tTWIS,SU_STO,400kbps
TWI slave setup time from SCL high to STOP condition, 400 kbps
1300
tTWIS,BUF,100kbps
TWI slave bus free time between STOP and START conditions,
Typ.
Max.
Units
ns
ns
4700
ns
1300
ns
100 kbps
tTWIS,BUF,400kbps
TWI slave bus free time between STOP and START conditions,
400 kbps
Figure 94: TWIS timing diagram, 1 byte transaction
Page 336
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
The Universal asynchronous receiver/transmitter with EasyDMA (UARTE) offers fast, full-duplex,
asynchronous serial communication with built-in flow control (CTS, RTS) support in hardware at a rate up to
1 Mbps, and EasyDMA data transfer from/to RAM.
Listed here are the main features for UARTE:
•
•
•
•
•
•
•
•
Full-duplex operation
Automatic hardware flow control
th
Parity checking and generation for the 9 data bit
EasyDMA
Up to 1 Mbps baudrate
Return to IDLE between transactions supported (when using HW flow control)
One stop bit
Least significant bit (LSB) first
PSELRXD
STARTRX
PSELCTS
RXD
(signal)
STOPRX
PSELRTS
RXD.PTR
TXD.PTR
PSELTXD
TXD
(signal)
STARTTX
STOPTX
SUSPEND
RESUME
RX
FIFO
RXTO
ENDTX
EasyDMA
EasyDMA
ENDRX
CTS
NCTS
RAM
RXD
TXD
RXD+1
TXD+1
RXD+2
TXD+2
RXD+n
TXD+n
Figure 95: UARTE configuration
The GPIOs used for each UART interface can be chosen from any GPIO on the device and are
independently configurable. This enables great flexibility in device pinout and efficient use of board space
and signal routing.
35.1 Shared resources
The UARTE shares registers and other resources with other peripherals that have the same ID as the
UARTE.
Therefore, you must disable all peripherals that have the same ID as the UARTE before the UARTE can be
configured and used. Disabling a peripheral that has the same ID as the UARTE will not reset any of the
registers that are shared with the UARTE. It is therefore important to configure all relevant UARTE registers
explicitly to ensure that it operates correctly.
See the Instantiation table in Instantiation on page 25 for details on peripherals and their IDs.
35.2 EasyDMA
The UARTE implements EasyDMA for reading and writing to and from the RAM.
If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 24 for more information about the different memory
regions.
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35 UARTE — Universal asynchronous receiver/
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The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/
TX transmission immediately after having received the RXSTARTED/TXSTARTED event.
The ENDRX/ENDTX event indicates that EasyDMA has finished accessing respectively the RX/TX buffer in
RAM.
35.3 Transmission
The first step of a DMA transmission is storing bytes in the transmit buffer and configuring EasyDMA. This
is achieved by writing the initial address pointer to TXD.PTR, and the number of bytes in the RAM buffer to
TXD.MAXCNT. The UARTE transmission is started by triggering the STARTTX task.
After each byte has been sent over the TXD line, a TXDRDY event will be generated.
When all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have been transmitted, the
UARTE transmission will end automatically and an ENDTX event will be generated.
A UARTE transmission sequence is stopped by triggering the STOPTX task, a TXSTOPPED event will be
generated when the UARTE transmitter has stopped.
If the ENDTX event has not already been generated when the UARTE transmitter has come to a stop, the
UARTE will generate the ENDTX event explicitly even though all bytes in the TXD buffer, as specified in the
TXD.MAXCNT register, have not been transmitted.
N
2
ENDTX
TXDRDY
TXDRDY
N-1
TXDRDY
N-2
2
TXDRDY
TXDRDY
1
STARTTX
TXD.MAXCNT = N+1
1
TXSTARTED
Lifeline
0
TXDRDY
TXD
CTS
If flow control is enabled, a transmission will be automatically suspended when CTS is deactivated and
resumed when CTS is activated again, as illustrated in Figure 96: UARTE transmission on page 338.
A byte that is in transmission when CTS is deactivated will be fully transmitted before the transmission is
suspended.
Figure 96: UARTE transmission
The UARTE transmitter will be in its lowest activity level, and consume the least amount of energy, when
it is stopped, i.e. before it is started via STARTTX or after it has been stopped via STOPTX and the
TXSTOPPED event has been generated. See POWER — Power supply on page 81 for more information
about power modes.
35.4 Reception
The UARTE receiver is started by triggering the STARTRX task. The UARTE receiver is using EasyDMA to
store incoming data in an RX buffer in RAM.
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35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
The RX buffer is located at the address specified in the RXD.PTR register. The RXD.PTR register is doublebuffered and it can be updated and prepared for the next STARTRX task immediately after the RXSTARTED
event is generated. The size of the RX buffer is specified in the RXD.MAXCNT register and the UARTE will
generate an ENDRX event when it has filled up the RX buffer, see Figure 97: UARTE reception on page
339.
For each byte received over the RXD line, an RXDRDY event will be generated. This event is likely to occur
before the corresponding data has been transferred to Data RAM.
The RXD.AMOUNT register can be queried following an ENDRX event to see how many new bytes have
been transferred to the RX buffer in RAM since the previous ENDRX event.
Data RAM
1
2
3
4
5
6
7
8
9
10
11
12
-
10
11
0x20000003
0x20000004
0x20000010
0x20000011
0x20000012
0x20000013
0x20000014
0x20000020
0x20000021
0x20000022
0x20000023
0x20000024
12
12
RXSTARTED
RXDRDY
RXD.PTR = 0x20000020
RXD.PTR = 0x20000030
4
STARTRX
3
0x20000001
0x20000002
RXDRDY
11
10
ENDRX
9
RXDRDY
RXSTARTED
9
RXDRDY
8
8
RXDRDY
7
ENDRX
6
7
RXDRDY
6
RXDRDY
5
RXDRDY
4
5
STARTRX
STARTRX
RXD.MAXCNT = 5
RXD.PTR = 0x20000000
4
2
1
ENDRX_STARTRX = 1
3
RXD.PTR = 0x20000010
Lifeline
3
RXDRDY
2
RXSTARTED
RXDRDY
1
2
RXDRDY
RXD
1
RXDRDY
EasyDMA
-
0x20000000
Figure 97: UARTE reception
The UARTE receiver is stopped by triggering the STOPRX task. An RXTO event is generated when the
UARTE has stopped. The UARTE will make sure that an impending ENDRX event will be generated before
the RXTO event is generated. This means that the UARTE will guarantee that no ENDRX event will be
generated after RXTO, unless the UARTE is restarted or a FLUSHRX command is issued after the RXTO
event is generated.
Important: If the ENDRX event has not already been generated when the UARTE receiver has
come to a stop, which implies that all pending content in the RX FIFO has been moved to the RX
buffer, the UARTE will generate the ENDRX event explicitly even though the RX buffer is not full. In
this scenario the ENDRX event will be generated before the RXTO event is generated.
To be able to know how many bytes have actually been received into the RX buffer, the CPU can read the
RXD.AMOUNT register following the ENDRX event or the RXTO event.
The UARTE is able to receive up to four bytes after the STOPRX task has been triggered as long as these
are sent in succession immediately after the RTS signal is deactivated. This is possible because after the
RTS is deactivated the UARTE is able to receive bytes for an extended period equal to the time it takes to
send 4 bytes on the configured baud rate.
After the RXTO event is generated the internal RX FIFO may still contain data, and to move this data to RAM
the FLUSHRX task must be triggered. To make sure that this data does not overwrite data in the RX buffer,
the RX buffer should be emptied or the RXD.PTR should be updated before the FLUSHRX task is triggered.
Page 339
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
5
6
6
7
Lifeline
2
1
7
8
8
9
9
11, 12, 13, 14
10
10
11
12
13
3
14
ENDRX
4
5
RXTO
3
4
ENDRX
2
3
RXSTARTED
1
2
ENDRX
RXD
1
RXSTARTED
EasyDMA
To make sure that all data in the RX FIFO is moved to the RX buffer, the RXD.MAXCNT register must be set
to RXD.MAXCNT > 4, see Figure 98: UARTE reception with forced stop via STOPRX on page 340. The
UARTE will generate the ENDRX event after completing the FLUSHRX task even if the RX FIFO was empty
or if the RX buffer does not get filled up. To be able to know how many bytes have actually been received
into the RX buffer in this case, the CPU can read the RXD.AMOUNT register following the ENDRX event.
3
4
5
FLUSHRX
STOPRX
ENDRX_STARTRX = 0
STARTRX
RXD.PTR = C
STARTRX
RXD.PTR = B
RXD.PTR = A
RXD.MAXCNT = 5
ENDRX_STARTRX = 1
Timeout
Figure 98: UARTE reception with forced stop via STOPRX
If HW flow control is enabled the RTS signal will be deactivated when the receiver is stopped via the
STOPRX task or when the UARTE is only able to receive four more bytes in its internal RX FIFO.
With flow control disabled, the UARTE will function in the same way as when the flow control is enabled
except that the RTS line will not be used. This means that no signal will be generated when the UARTE has
reached the point where it is only able to receive four more bytes in its internal RX FIFO. Data received when
the internal RX FIFO is filled up, will be lost.
The UARTE receiver will be in its lowest activity level, and consume the least amount of energy, when it is
stopped, i.e. before it is started via STARTRX or after it has been stopped via STOPRX and the RXTO event
has been generated. See POWER — Power supply on page 81 for more information about power modes.
35.5 Error conditions
An ERROR event, in the form of a framing error, will be generated if a valid stop bit is not detected in a
frame. Another ERROR event, in the form of a break condition, will be generated if the RXD line is held
active low for longer than the length of a data frame. Effectively, a framing error is always generated before a
break condition occurs.
An ERROR event will not stop reception. If the error was a parity error, the received byte will still be
transferred into Data RAM, and so will following incoming bytes. If there was a framing error (wrong stop bit),
that specific byte will NOT be stored into Data RAM, but following incoming bytes will.
35.6 Using the UARTE without flow control
If flow control is not enabled, the interface will behave as if the CTS and RTS lines are kept active all the
time.
35.7 Parity configuration
When parity is enabled, the parity will be generated automatically from the even parity of TXD and RXD for
transmission and reception respectively.
35.8 Low power
When putting the system in low power and the peripheral is not needed, lowest possible power consumption
is achieved by stopping, and then disabling the peripheral.
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35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
The STOPTX and STOPRX tasks may not be always needed (the peripheral might already be stopped),
but if STOPTX and/or STOPRX is sent, software shall wait until the TXSTOPPED and/or RXTO event is
received in response, before disabling the peripheral through the ENABLE register.
35.9 Pin configuration
The different signals RXD, CTS (Clear To Send, active low), RTS (Request To Send, active low), and TXD
associated with the UARTE are mapped to physical pins according to the configuration specified in the
PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers respectively.
The PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers and their configurations are only used
as long as the UARTE is enabled, and retained only for the duration the device is in ON mode. PSEL.RXD,
PSEL.RTS, PSEL.RTS and PSEL.TXD must only be configured when the UARTE is disabled.
To secure correct signal levels on the pins by the UARTE when the system is in OFF mode, the pins must be
configured in the GPIO peripheral as described in Table 83: GPIO configuration before enabling peripheral
on page 341.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
Table 83: GPIO configuration before enabling peripheral
UARTE signal
RXD
CTS
RTS
TXD
UARTE pin
As specified in PSEL.RXD
As specified in PSEL.CTS
As specified in PSEL.RTS
As specified in PSEL.TXD
Direction
Input
Input
Output
Output
Output value
Not applicable
Not applicable
1
1
35.10 Registers
Table 84: Instances
Base address
Peripheral
Instance
Description
0x40002000
UARTE
UARTE0
Universal Asynchronous Receiver/
Configuration
Transmitter with EasyDMA
Table 85: Register Overview
Register
Offset
Description
TASKS_STARTRX
0x000
Start UART receiver
TASKS_STOPRX
0x004
Stop UART receiver
TASKS_STARTTX
0x008
Start UART transmitter
TASKS_STOPTX
0x00C
Stop UART transmitter
TASKS_FLUSHRX
0x02C
Flush RX FIFO into RX buffer
EVENTS_CTS
0x100
CTS is activated (set low). Clear To Send.
EVENTS_NCTS
0x104
CTS is deactivated (set high). Not Clear To Send.
EVENTS_RXDRDY
0x108
Data received in RXD (but potentially not yet transferred to Data RAM)
EVENTS_ENDRX
0x110
Receive buffer is filled up
EVENTS_TXDRDY
0x11C
Data sent from TXD
EVENTS_ENDTX
0x120
Last TX byte transmitted
EVENTS_ERROR
0x124
Error detected
EVENTS_RXTO
0x144
Receiver timeout
EVENTS_RXSTARTED
0x14C
UART receiver has started
EVENTS_TXSTARTED
0x150
UART transmitter has started
EVENTS_TXSTOPPED
0x158
Transmitter stopped
SHORTS
0x200
Shortcut register
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
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35 UARTE — Universal asynchronous receiver/
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Register
Offset
Description
ERRORSRC
0x480
Error source
ENABLE
0x500
Enable UART
PSEL.RTS
0x508
Pin select for RTS signal
PSEL.TXD
0x50C
Pin select for TXD signal
PSEL.CTS
0x510
Pin select for CTS signal
PSEL.RXD
0x514
Pin select for RXD signal
BAUDRATE
0x524
Baud rate. Accuracy depends on the HFCLK source selected.
RXD.PTR
0x534
Data pointer
RXD.MAXCNT
0x538
Maximum number of bytes in receive buffer
RXD.AMOUNT
0x53C
Number of bytes transferred in the last transaction
TXD.PTR
0x544
Data pointer
TXD.MAXCNT
0x548
Maximum number of bytes in transmit buffer
TXD.AMOUNT
0x54C
Number of bytes transferred in the last transaction
CONFIG
0x56C
Configuration of parity and hardware flow control
35.10.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x00000000
Id
RW Field
C
RW ENDRX_STARTRX
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between ENDRX event and STARTRX task
See EVENTS_ENDRX and TASKS_STARTRX
D
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW ENDRX_STOPRX
Shortcut between ENDRX event and STOPRX task
See EVENTS_ENDRX and TASKS_STOPRX
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
35.10.2 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L
Reset 0x00000000
Id
RW Field
A
RW CTS
0
Value Id
J
I
H
Value
Description
Enable or disable interrupt for CTS event
See EVENTS_CTS
B
Disabled
0
Disable
Enabled
1
Enable
RW NCTS
Enable or disable interrupt for NCTS event
See EVENTS_NCTS
C
Disabled
0
Disable
Enabled
1
Enable
RW RXDRDY
Enable or disable interrupt for RXDRDY event
See EVENTS_RXDRDY
D
G F E
D
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Disabled
0
Disable
Enabled
1
Enable
RW ENDRX
Enable or disable interrupt for ENDRX event
See EVENTS_ENDRX
Page 342
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L
Reset 0x00000000
Id
E
RW Field
0
J
I
H
G F E
D
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
RW TXDRDY
Enable or disable interrupt for TXDRDY event
See EVENTS_TXDRDY
F
Disabled
0
Disable
Enabled
1
Enable
RW ENDTX
Enable or disable interrupt for ENDTX event
See EVENTS_ENDTX
G
Disabled
0
Disable
Enabled
1
Enable
RW ERROR
Enable or disable interrupt for ERROR event
See EVENTS_ERROR
H
Disabled
0
Disable
Enabled
1
Enable
RW RXTO
Enable or disable interrupt for RXTO event
See EVENTS_RXTO
I
Disabled
0
Disable
Enabled
1
Enable
RW RXSTARTED
Enable or disable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
J
Disabled
0
Disable
Enabled
1
Enable
RW TXSTARTED
Enable or disable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
L
Disabled
0
Disable
Enabled
1
Enable
RW TXSTOPPED
Enable or disable interrupt for TXSTOPPED event
See EVENTS_TXSTOPPED
Disabled
0
Disable
Enabled
1
Enable
35.10.3 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L
Reset 0x00000000
Id
RW Field
A
RW CTS
0
Value Id
J
I
H
G F E
Value
Description
Write '1' to Enable interrupt for CTS event
See EVENTS_CTS
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW NCTS
Write '1' to Enable interrupt for NCTS event
See EVENTS_NCTS
C
D
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXDRDY
Write '1' to Enable interrupt for RXDRDY event
Page 343
35 UARTE — Universal asynchronous receiver/
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L
Reset 0x00000000
Id
RW Field
0
J
I
H
G F E
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_RXDRDY
D
RW ENDRX
Write '1' to Enable interrupt for ENDRX event
See EVENTS_ENDRX
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXDRDY
Write '1' to Enable interrupt for TXDRDY event
See EVENTS_TXDRDY
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDTX
Write '1' to Enable interrupt for ENDTX event
See EVENTS_ENDTX
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Enable interrupt for ERROR event
See EVENTS_ERROR
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXTO
Write '1' to Enable interrupt for RXTO event
See EVENTS_RXTO
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXSTARTED
Write '1' to Enable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
J
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTARTED
Write '1' to Enable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
L
D
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTOPPED
Write '1' to Enable interrupt for TXSTOPPED event
See EVENTS_TXSTOPPED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
35.10.4 INTENCLR
Address offset: 0x308
Disable interrupt
Page 344
35 UARTE — Universal asynchronous receiver/
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L
Reset 0x00000000
Id
RW Field
A
RW CTS
0
Value Id
J
I
H
G F E
Value
Description
Write '1' to Disable interrupt for CTS event
See EVENTS_CTS
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW NCTS
Write '1' to Disable interrupt for NCTS event
See EVENTS_NCTS
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXDRDY
Write '1' to Disable interrupt for RXDRDY event
See EVENTS_RXDRDY
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Disable interrupt for ENDRX event
See EVENTS_ENDRX
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXDRDY
Write '1' to Disable interrupt for TXDRDY event
See EVENTS_TXDRDY
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDTX
Write '1' to Disable interrupt for ENDTX event
See EVENTS_ENDTX
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Disable interrupt for ERROR event
See EVENTS_ERROR
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXTO
Write '1' to Disable interrupt for RXTO event
See EVENTS_RXTO
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXSTARTED
Write '1' to Disable interrupt for RXSTARTED event
See EVENTS_RXSTARTED
J
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTARTED
Write '1' to Disable interrupt for TXSTARTED event
See EVENTS_TXSTARTED
L
D
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXSTOPPED
Write '1' to Disable interrupt for TXSTOPPED event
Page 345
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L
Reset 0x00000000
Id
RW Field
0
J
I
H
G F E
D
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_TXSTOPPED
35.10.5 ERRORSRC
Address offset: 0x480
Error source
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C B A
Reset 0x00000000
Id
RW Field
A
RW OVERRUN
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Overrun error
A start bit is received while the previous data still lies in RXD.
(Previous data is lost.)
B
NotPresent
0
Read: error not present
Present
1
Read: error present
RW PARITY
Parity error
A character with bad parity is received, if HW parity check is
enabled.
C
NotPresent
0
Read: error not present
Present
1
Read: error present
RW FRAMING
Framing error occurred
A valid stop bit is not detected on the serial data input after all
bits in a character have been received.
D
NotPresent
0
Read: error not present
Present
1
Read: error present
RW BREAK
Break condition
The serial data input is '0' for longer than the length of a data
frame. (The data frame length is 10 bits without parity bit, and
11 bits with parity bit.).
NotPresent
0
Read: error not present
Present
1
Read: error present
35.10.6 ENABLE
Address offset: 0x500
Enable UART
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable UARTE
Enabled
8
Enable UARTE
Enable or disable UARTE
35.10.7 PSEL.RTS
Address offset: 0x508
Pin select for RTS signal
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35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
35.10.8 PSEL.TXD
Address offset: 0x50C
Pin select for TXD signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
35.10.9 PSEL.CTS
Address offset: 0x510
Pin select for CTS signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
35.10.10 PSEL.RXD
Address offset: 0x514
Pin select for RXD signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
35.10.11 BAUDRATE
Address offset: 0x524
Baud rate. Accuracy depends on the HFCLK source selected.
Page 347
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x04000000
Id
RW Field
A
RW BAUDRATE
0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Baud1200
0x0004F000
1200 baud (actual rate: 1205)
Baud2400
0x0009D000
2400 baud (actual rate: 2396)
Baud4800
0x0013B000
4800 baud (actual rate: 4808)
Baud9600
0x00275000
9600 baud (actual rate: 9598)
Baud14400
0x003AF000
14400 baud (actual rate: 14401)
Baud19200
0x004EA000
19200 baud (actual rate: 19208)
Baud28800
0x0075C000
28800 baud (actual rate: 28777)
Baud38400
0x009D0000
38400 baud (actual rate: 38369)
Baud57600
0x00EB0000
57600 baud (actual rate: 57554)
Baud76800
0x013A9000
76800 baud (actual rate: 76923)
Baud115200
0x01D60000
115200 baud (actual rate: 115108)
Baud230400
0x03B00000
230400 baud (actual rate: 231884)
Baud250000
0x04000000
250000 baud
Baud460800
0x07400000
460800 baud (actual rate: 457143)
Baud921600
0x0F000000
921600 baud (actual rate: 941176)
Baud1M
0x10000000
1Mega baud
Baud rate
35.10.12 RXD.PTR
Address offset: 0x534
Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
35.10.13 RXD.MAXCNT
Address offset: 0x538
Maximum number of bytes in receive buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in receive buffer
35.10.14 RXD.AMOUNT
Address offset: 0x53C
Number of bytes transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last transaction
35.10.15 TXD.PTR
Address offset: 0x544
Data pointer
Page 348
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
35.10.16 TXD.MAXCNT
Address offset: 0x548
Maximum number of bytes in transmit buffer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of bytes in transmit buffer
35.10.17 TXD.AMOUNT
Address offset: 0x54C
Number of bytes transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of bytes transferred in the last transaction
35.10.18 CONFIG
Address offset: 0x56C
Configuration of parity and hardware flow control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B B B A
Reset 0x00000000
Id
RW Field
A
RW HWFC
B
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disabled
Enabled
1
Enabled
Excluded
0x0
Exclude parity bit
Included
0x7
Include parity bit
Hardware flow control
RW PARITY
Parity
35.11 Electrical specification
35.11.1 UARTE electrical specification
Symbol
Description
fUARTE
Baud rate for UARTE32.
IUARTE1M
Run current at max baud rate.
55
µA
IUARTE115k
Run current at 115200 bps.
55
µA
IUARTE1k2
Run current at 1200 bps.
55
µA
IUARTE,IDLE
Idle current for UARTE (STARTed, no XXX activity)
1
µA
tUARTE,CTSH
CTS high time
32
Min.
Typ.
Max.
Units
1000
kbps
1
Higher baud rates may require GPIOs to be set as High Drive, see GPIO chapter for more details.
Page 349
µs
35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
Symbol
Description
tUARTE,START,LP
Time from STARTRX/STARTTX task to transmission started, low
Min.
Typ.
tUARTE,START,CL
Max.
power mode
+
Units
µs
tSTART_HFINT
tUARTE,START,CL
Time from STARTRX/STARTTX task to transmission started,
constant latency mode
Page 350
1
µs
36 QDEC — Quadrature decoder
36 QDEC — Quadrature decoder
The Quadrature decoder (QDEC) provides buffered decoding of quadrature-encoded sensor signals. It is
suitable for mechanical and optical sensors.
The sample period and accumulation are configurable to match application requirements. The QDEC
provides the following:
•
•
•
•
Decoding of digital waveform from off-chip quadrature encoder.
Sample accumulation eliminating hard real-time requirements to be enforced on application.
Optional input de-bounce filters.
Optional LED output signal for optical encoders.
ACCREAD
ACCDBLREAD
ACC
ACCDBL
+
+
SAMPLE
Quadrature decoder
IO router
On-chip
Off-chip
Phase A
Phase B
LED
Mechanical to electrical
Mechanical
device
Quadrature Encoder
Figure 99: Quadrature decoder configuration
36.1 Sampling and decoding
The QDEC decodes the output from an incremental motion encoder by sampling the QDEC phase input pins
(A and B).
The off-chip quadrature encoder is an incremental motion encoder outputting two waveforms, phase A and
phase B. The two output waveforms are always 90 degrees out of phase, meaning that one always changes
level before the other. The direction of movement is indicated by which of these two waveforms that changes
level first. Invalid transitions may occur, that is when the two waveforms switch simultaneously. This may
occur if the wheel rotates too fast relative to the sample rate set for the decoder.
Page 351
36 QDEC — Quadrature decoder
The QDEC decodes the output from the off-chip encoder by sampling the QDEC phase input pins (A and B)
at a fixed rate as specified in the SAMPLEPER register.
If the SAMPLEPER value needs to be changed, the QDEC shall be stopped using the STOP task.
SAMPLEPER can be then changed upon receiving the STOPPED event, and QDEC can be restarted using
the START task. Failing to do so may result in unpredictable behaviour.
It is good practice to change other registers (LEDPOL, REPORTPER, DBFEN and LEDPRE) only when the
QDEC is stopped.
When started, the decoder continuously samples the two input waveforms and decodes these by comparing
the current sample pair (n) with the previous sample pair (n-1).
The decoding of the sample pairs is described in the table below.
Table 86: Sampled value encoding
Previous
sample pair(n
- 1)
A
B
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
Current
SAMPLE
samples pair(n) register
ACC operation ACCDBL
operation
Description
A
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
No change
Increment
Decrement
No change
Decrement
No change
No change
Increment
Increment
No change
No change
Decrement
No change
Decrement
Increment
No change
No movement
Movement in positive direction
Movement in negative direction
Error: Double transition
Movement in negative direction
No movement
Error: Double transition
Movement in positive direction
Movement in positive direction
Error: Double transition
No movement
Movement in negative direction
Error: Double transition
Movement in negative direction
Movement in positive direction
No movement
B
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-1
2
-1
0
2
1
1
2
0
-1
2
-1
1
0
No change
No change
No change
Increment
No change
No change
Increment
No change
No change
Increment
No change
No change
Increment
No change
No change
No change
36.2 LED output
The LED output follows the sample period, and the LED is switched on a given period before sampling and
switched off immediately after the inputs are sampled. The period the LED is switched on before sampling is
given in the LEDPRE register.
The LED output pin polarity is specified in the LEDPOL register.
For using off-chip mechanical encoders not requiring a LED, the LED output can be disabled by writing
value 'Disconnected' to the CONNECT field of the PSEL.LED register. In this case the QDEC will not acquire
access to a LED output pin and the pin can be used for other purposes by the CPU.
36.3 Debounce filters
Each of the two-phase inputs have digital debounce filters.
When enabled through the DBFEN register, the filter inputs are sampled at a fixed 1 MHz frequency during
the entire sample period (which is specified in the SAMPLEPER register), and the filters require all of the
samples within this sample period to equal before the input signal is accepted and transferred to the output
of the filter.
As a result, only input signal with a steady state longer than twice the period specified in SAMPLEPER are
guaranteed to pass through the filter, and any signal with a steady state shorter than SAMPLEPER will
always be suppressed by the filter. (This is assumed that the frequency during the debounce period never
exceeds 500 kHz (as required by the Nyquist theorem when using a 1 MHz sample frequency).
The LED will always be ON when the debounce filters are enabled, as the inputs in this case will be sampled
continuously.
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36 QDEC — Quadrature decoder
Note that when when the debounce filters are enabled, displacements reported by the QDEC peripheral are
delayed by one SAMPLEPER period.
36.4 Accumulators
The quadrature decoder contains two accumulator registers, ACC and ACCDBL, that accumulate
respectively valid motion sample values and the number of detected invalid samples (double transitions).
The ACC register will accumulate all valid values (1/-1) written to the SAMPLE register. This can be useful
for preventing hard real-time requirements from being enforced on the application. When using the ACC
register the application does not need to read every single sample from the SAMPLE register, but can
instead fetch the ACC register whenever it fits the application. The ACC register will always hold the relative
movement of the external mechanical device since the previous clearing of the ACC register. Sample values
indicating a double transition (2) will not be accumulated in the ACC register.
An ACCOF event will be generated if the ACC receives a SAMPLE value that would cause the register to
overflow or underflow. Any SAMPLE value that would cause an ACC overflow or underflow will be discarded,
but any samples not causing the ACC to overflow or underflow will still be accepted.
The accumulator ACCDBL accumulates the number of detected double transitions since the previous
clearing of the ACCDBL register.
The ACC and ACCDBL registers can be cleared by the READCLRACC and subsequently read using the
ACCREAD and ACCDBLREAD registers.
The ACC register can be separately cleared by the RDCLRACC and subsequently read using the ACCREAD
registers.
The ACCDBL register can be separately cleared by the RDCLRDBL and subsequently read using the
ACCDBLREAD registers.
The REPORTPER register allows automating the capture of several samples before it can send out a
REPORTRDY event in case a non-null displacement has been captured and accumulated, and a DBLRDY
event in case one or more double-displacements have been captured and accumulated. The REPORTPER
field in this register selects after how many samples the accumulators contents are evaluated to send (or not)
REPORTRDY and DBLRDY events.
Using the RDCLRACC task (manually sent upon receiving the event, or using the DBLRDY_RDCLRACC
shortcut), ACCREAD can then be read.
In case at least one double transition has been captured and accumulated, a DBLRDY event is sent. Using
the RDCLRDBL task (manually sent upon receiving the event, or using the DBLRDY_RDCLRDBL shortcut),
ACCDBLREAD can then be read.
36.5 Output/input pins
The QDEC uses a three-pin interface to the off-chip quadrature encoder.
These pins will be acquired when the QDEC is enabled in the ENABLE register. The pins acquired by the
QDEC cannot be written by the CPU, but they can still be read by the CPU.
The pin numbers to be used for the QDEC are selected using the PSEL.n registers.
36.6 Pin configuration
The Phase A, Phase B, and LED signals are mapped to physical pins according to the configuration
specified in the PSEL.A, PSEL.B, and PSEL.LED registers respectively.
If the CONNECT field value 'Disconnected' is specified in any of these registers, the associated signal
will not be connected to any physical pin. The PSEL.A, PSEL.B, and PSEL.LED registers and their
configurations are only used as long as the QDEC is enabled, and retained only as long as the device is in
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36 QDEC — Quadrature decoder
ON mode. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration
in their respective OUT bit field and PIN_CNF[n] register.
To secure correct behavior in the QDEC, the pins used by the QDEC must be configured in the GPIO
peripheral as described in Table 87: GPIO configuration before enabling peripheral on page 354 before
enabling the QDEC. This configuration must be retained in the GPIO for the selected IOs as long as the
QDEC is enabled.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
Table 87: GPIO configuration before enabling peripheral
QDEC signal
Phase A
Phase B
LED
QDEC pin
As specified in PSEL.A
As specified in PSEL.B
As specified in PSEL.LED
Direction
Input
Input
Input
Output value
Not applicable
Not applicable
Not applicable
Comment
36.7 Registers
Table 88: Instances
Base address
Peripheral
Instance
Description
0x40012000
QDEC
QDEC
Quadrature decoder
Configuration
Table 89: Register Overview
Register
Offset
Description
TASKS_START
0x000
Task starting the quadrature decoder
TASKS_STOP
0x004
Task stopping the quadrature decoder
TASKS_READCLRACC
0x008
Read and clear ACC and ACCDBL
TASKS_RDCLRACC
0x00C
Read and clear ACC
TASKS_RDCLRDBL
0x010
Read and clear ACCDBL
EVENTS_SAMPLERDY
0x100
Event being generated for every new sample value written to the SAMPLE register
EVENTS_REPORTRDY
0x104
Non-null report ready
EVENTS_ACCOF
0x108
ACC or ACCDBL register overflow
EVENTS_DBLRDY
0x10C
Double displacement(s) detected
EVENTS_STOPPED
0x110
QDEC has been stopped
SHORTS
0x200
Shortcut register
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ENABLE
0x500
Enable the quadrature decoder
LEDPOL
0x504
LED output pin polarity
SAMPLEPER
0x508
Sample period
SAMPLE
0x50C
Motion sample value
REPORTPER
0x510
Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
ACC
0x514
Register accumulating the valid transitions
ACCREAD
0x518
Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
PSEL.LED
0x51C
Pin select for LED signal
PSEL.A
0x520
Pin select for A signal
PSEL.B
0x524
Pin select for B signal
DBFEN
0x528
Enable input debounce filters
LEDPRE
0x540
Time period the LED is switched ON prior to sampling
ACCDBL
0x544
Register accumulating the number of detected double transitions
ACCDBLREAD
0x548
Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task
36.7.1 SHORTS
Address offset: 0x200
Shortcut register
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36 QDEC — Quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G F E D C B A
Reset 0x00000000
Id
RW Field
A
RW REPORTRDY_READCLRACC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between REPORTRDY event and READCLRACC task
See EVENTS_REPORTRDY and TASKS_READCLRACC
B
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW SAMPLERDY_STOP
Shortcut between SAMPLERDY event and STOP task
See EVENTS_SAMPLERDY and TASKS_STOP
C
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW REPORTRDY_RDCLRACC
Shortcut between REPORTRDY event and RDCLRACC task
See EVENTS_REPORTRDY and TASKS_RDCLRACC
D
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW REPORTRDY_STOP
Shortcut between REPORTRDY event and STOP task
See EVENTS_REPORTRDY and TASKS_STOP
E
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW DBLRDY_RDCLRDBL
Shortcut between DBLRDY event and RDCLRDBL task
See EVENTS_DBLRDY and TASKS_RDCLRDBL
F
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW DBLRDY_STOP
Shortcut between DBLRDY event and STOP task
See EVENTS_DBLRDY and TASKS_STOP
G
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW SAMPLERDY_READCLRACC
Shortcut between SAMPLERDY event and READCLRACC task
See EVENTS_SAMPLERDY and TASKS_READCLRACC
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
36.7.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D C B A
Reset 0x00000000
Id
RW Field
A
RW SAMPLERDY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for SAMPLERDY event
See EVENTS_SAMPLERDY
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REPORTRDY
Write '1' to Enable interrupt for REPORTRDY event
See EVENTS_REPORTRDY
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ACCOF
Write '1' to Enable interrupt for ACCOF event
See EVENTS_ACCOF
Set
1
Enable
Page 355
36 QDEC — Quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D C B A
Reset 0x00000000
Id
D
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DBLRDY
Write '1' to Enable interrupt for DBLRDY event
See EVENTS_DBLRDY
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
36.7.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D C B A
Reset 0x00000000
Id
RW Field
A
RW SAMPLERDY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for SAMPLERDY event
See EVENTS_SAMPLERDY
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REPORTRDY
Write '1' to Disable interrupt for REPORTRDY event
See EVENTS_REPORTRDY
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ACCOF
Write '1' to Disable interrupt for ACCOF event
See EVENTS_ACCOF
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DBLRDY
Write '1' to Disable interrupt for DBLRDY event
See EVENTS_DBLRDY
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Disable interrupt for STOPPED event
See EVENTS_STOPPED
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
36.7.4 ENABLE
Address offset: 0x500
Enable the quadrature decoder
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36 QDEC — Quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable the quadrature decoder
When enabled the decoder pins will be active. When disabled
the quadrature decoder pins are not active and can be used as
GPIO .
Disabled
0
Disable
Enabled
1
Enable
36.7.5 LEDPOL
Address offset: 0x504
LED output pin polarity
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW LEDPOL
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
ActiveLow
0
Led active on output pin low
ActiveHigh
1
Led active on output pin high
LED output pin polarity
36.7.6 SAMPLEPER
Address offset: 0x508
Sample period
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW SAMPLEPER
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Sample period. The SAMPLE register will be updated for every
new sample
128us
0
128 us
256us
1
256 us
512us
2
512 us
1024us
3
1024 us
2048us
4
2048 us
4096us
5
4096 us
8192us
6
8192 us
16384us
7
16384 us
32ms
8
32768 us
65ms
9
65536 us
131ms
10
131072 us
36.7.7 SAMPLE
Address offset: 0x50C
Motion sample value
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
SAMPLE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[-1..2]
Last motion sample
Page 357
36 QDEC — Quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
The value is a 2's complement value, and the sign gives the
direction of the motion. The value '2' indicates a double
transition.
36.7.8 REPORTPER
Address offset: 0x510
Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW REPORTPER
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Specifies the number of samples to be accumulated in the ACC
register before the REPORTRDY and DBLRDY events can be
generated
The report period in [us] is given as: RPUS = SP * RP Where
RPUS is the report period in [us/report], SP is the sample period
in [us/sample] specified in SAMPLEPER, and RP is the report
period in [samples/report] specified in REPORTPER .
10Smpl
0
10 samples / report
40Smpl
1
40 samples / report
80Smpl
2
80 samples / report
120Smpl
3
120 samples / report
160Smpl
4
160 samples / report
200Smpl
5
200 samples / report
240Smpl
6
240 samples / report
280Smpl
7
280 samples / report
1Smpl
8
1 sample / report
36.7.9 ACC
Address offset: 0x514
Register accumulating the valid transitions
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
ACC
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[-1024..1023]
Register accumulating all valid samples (not double transition)
read from the SAMPLE register
Double transitions ( SAMPLE = 2 ) will not be accumulated in
this register. The value is a 32 bit 2's complement value. If a
sample that would cause this register to overflow or underflow
is received, the sample will be ignored and an overflow event
( ACCOF ) will be generated. The ACC register is cleared by
triggering the READCLRACC or the RDCLRACC task.
36.7.10 ACCREAD
Address offset: 0x518
Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
Page 358
36 QDEC — Quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
ACCREAD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[-1024..1023]
Snapshot of the ACC register.
The ACCREAD register is updated when the READCLRACC or
RDCLRACC task is triggered
36.7.11 PSEL.LED
Address offset: 0x51C
Pin select for LED signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
36.7.12 PSEL.A
Address offset: 0x520
Pin select for A signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
36.7.13 PSEL.B
Address offset: 0x524
Pin select for B signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
36.7.14 DBFEN
Address offset: 0x528
Enable input debounce filters
Page 359
36 QDEC — Quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW DBFEN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Debounce input filters disabled
Enabled
1
Debounce input filters enabled
Enable input debounce filters
36.7.15 LEDPRE
Address offset: 0x540
Time period the LED is switched ON prior to sampling
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A
Reset 0x00000010
Id
RW Field
A
RW LEDPRE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Value
Description
[1..511]
Period in us the LED is switched on prior to sampling
36.7.16 ACCDBL
Address offset: 0x544
Register accumulating the number of detected double transitions
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
ACCDBL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..15]
Register accumulating the number of detected double or illegal
transitions. ( SAMPLE = 2 ).
When this register has reached its maximum value the
accumulation of double / illegal transitions will stop. An
overflow event ( ACCOF ) will be generated if any double or
illegal transitions are detected after the maximum value was
reached. This field is cleared by triggering the READCLRACC or
RDCLRDBL task.
36.7.17 ACCDBLREAD
Address offset: 0x548
Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
ACCDBLREAD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..15]
Snapshot of the ACCDBL register. This field is updated when the
READCLRACC or RDCLRDBL task is triggered.
36.8 Electrical specification
36.8.1 QDEC Electrical Specification
Symbol
Description
IQDEC
Run current
Min.
Typ.
Max.
tSAMPLE
Time between sampling signals from quadrature decoder
128
131072
µs
tLED
Time from LED is turned on to signals are sampled
0
511
µs
5
Page 360
Units
µA
37 SAADC — Successive approximation analogto-digital converter
37 SAADC — Successive approximation analog-todigital converter
The ADC is a differential successive approximation register (SAR) analog-to-digital converter.
Listed here are the main features of SAADC:
•
•
•
•
•
•
•
•
•
•
•
•
8/10/12-bit resolution, 14-bit resolution with oversampling
Up to eight input channels
• One channel per single-ended input and two channels per differential input
• Scan mode can be configured with both single-ended channels and differential channels.
Full scale input range (0 to VDD)
Sampling triggered via a task from software or a PPI channel for full flexibility on sample frequency
source from low power 32.768kHz RTC or more accurate 1/16MHz Timers
One-shot conversion mode to sample a single channel
Scan mode to sample a series of channels in sequence. Sample delay between channels is tack + tconv
which may vary between channels according to user configuration of tack.
Support for direct sample transfer to RAM using EasyDMA
Interrupts on single sample and full buffer events
Samples stored as 16-bit 2’s complement values for differential and single-ended sampling
Continuous sampling without the need of an external timer
Internal resistor string
Limit checking on the fly
37.1 Shared resources
The ADC can coexist with COMP and other peripherals using one of AIN0-AIN7, provided these are
assigned to different pins.
It is not recommended to select the same analog input pin for both modules.
37.2 Overview
The ADC supports up to eight external analog input channels, depending on package variant. It can be
operated in a one-shot mode with sampling under software control, or a continuous conversion mode with a
programmable sampling rate.
The analog inputs can be configured as eight single-ended inputs, four differential inputs or a combination
of these. Each channel can be configured to select AIN0 to AIN7 pins, or the VDD pin. Channels can be
sampled individually in one-shot or continuous sampling modes, or, using scan mode, multiple channels can
be sampled in sequence. Channels can also be oversampled to improve noise performance.
Page 361
37 SAADC — Successive approximation analogto-digital converter
PSEL_A
PSEL_A
PSEL_A
PSEL_A
PSEL_A
PSEL_A
CH[X].CONFIG
PSEL_A
PSEL_A
PSEL_A
PSEL_A
PSEL_A
PSEL_A
CH[X].PSELP
NC
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
VDD
NC
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
VDD
ADC
RAM
MUX
RESULT
P
RESP
RESULT
SAR
core
GAIN
RESULT
EasyDMA
RESULT
RESULT
RESULT
N
RESN
RESULT
RESULT
MUX
RESULT.PTR
START
SAMPLE
VDD
Internal reference
REFSEL
STARTED
END
STOPPED
STOP
CH[X].PSELN
PSEL_A
PSEL_A
PSEL_A
PSEL_A
PSEL_A
PSEL_A
Figure 100: Simplified ADC block diagram
Internally, the ADC is always a differential analog-to-digital converter, but by default it is configured with
single-ended input in the MODE field of the CH[n].CONFIG register. In single-ended mode, the negative
input will be shorted to ground internally.
The assumption in single-ended mode is that the internal ground of the ADC is the same as the external
ground that the measured voltage is referred to. The ADC is thus sensitive to ground bounce on the PCB in
single-ended mode. If this is a concern we recommend using differential measurement.
37.3 Digital output
The output result of the ADC depends on the settings in the CH[n].CONFIG and RESOLUTION registers as
follows:
RESULT = [V(P) – V(N) ] * GAIN/REFERENCE * 2(RESOLUTION
- m)
where
V(P)
is the voltage at input P
V(N)
is the voltage at input N
GAIN
is the selected gain setting
REFERENCE
is the selected reference voltage
and m=0 if CONFIG.MODE=SE, or m=1 if CONFIG.MODE=Diff.
The result generated by the ADC will deviate from the expected due DC errors like offset, gain, differential
non-linearity (DNL), and integral non-linearity (INL). See Electrical specification for details on these
parameters. The result can also vary due to AC errors like non-linearities in the GAIN block, settling errors
due to high source impedance and sampling jitter. For battery measurement the DC errors are most
noticeable.
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37 SAADC — Successive approximation analogto-digital converter
The ADC has a wide selection of gains controlled in the GAIN field of the CH[n].CONFIG register. If
CH[n].CONFIG.REFSEL=0, the input range of the ADC core is nominally ±0.6 V differential and the input
must be scaled accordingly.
The ADC has a temperature dependent offset. If the ADC is to operate over a large temperature range, we
recommend running CALIBRATEOFFSET at regular intervals, a CALIBRATEDONE event will be fired when
the calibration is complete
37.4 Analog inputs and channels
Up to eight analog input channels, CH[n](n=0..7), can be configured.
See Shared resources on page 361 for shared input with comparators.
Any one of the available channels can be enabled for the ADC to operate in one-shot mode. If more than
one CH[n] is configured, the ADC enters scan mode.
An analog input is selected as a positive converter input if CH[n].PSELP is set, setting CH[n].PSELP also
enables the particular channel.
An analog input is selected as a negative converter input if CH[n].PSELN is set. The CH[n].PSELN register
will have no effect unless differential mode is enabled, see MODE field in CH[n].CONFIG register.
If more than one of the CH[n].PSELP registers is set, the device enters scan mode. Input selections in scan
mode are controlled by the CH[n].PSELP and CH[n].PSELN registers, where CH[n].PSELN is only used if
the particular scan channel is specified as differential, see MODE field in CH[n].CONFIG register.
Important: Channels selected for COMP cannot be used at the same time for ADC sampling, though
channels not selected for use by these blocks can be used by the ADC.
Table 90: Legal connectivity CH[n] vs. analog input
Channel input
CH[n].PSELP
CH[n].PSELP
CH[n].PSELN
CH[n].PSELN
Source
AIN0…AIN7
VDD
AIN0…AIN7
VDD
Connectivity
Yes(any)
Yes
Yes(any)
Yes
37.5 Operation modes
The ADC input configuration supports one-shot mode, continuous mode and scan mode.
Scan mode and oversampling cannot be combined.
37.5.1 One-shot mode
One-shot operation is configured by enabling only one of the available channels defined by CH[n].PSELP,
CH[n].PSELN, and CH[n].CONFIG registers.
Upon a SAMPLE task, the ADC starts to sample the input voltage. The CH[n].CONFIG.TACQ controls the
acquisition time.
A DONE event signals that one sample has been taken.
In this mode, the RESULTDONE event has the same meaning as DONE when no oversampling takes place.
Note that both events may occur before the actual value has been transferred into RAM by EasyDMA. For
more information, see EasyDMA on page 365.
37.5.2 Continuous mode
Continuous sampling can be achieved by using the internal timer in the ADC, or triggering the SAMPLE task
from one of the general purpose timers through the PPI.
Care shall be taken to ensure that the sample rate fulfils the following criteria, depending on how many
channels are active:
fSAMPLE < 1/[tACQ + tconv]
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37 SAADC — Successive approximation analogto-digital converter
The SAMPLERATE register can be used as a local timer instead of triggering individual SAMPLE tasks.
When SAMPLERATE.MODE is set to Timers, it is sufficient to trigger SAMPLE task only once in order to
start the SAADC and triggering the STOP task will stop sampling. The SAMPLERATE.CC field controls the
sample rate.
The SAMPLERATE timer mode cannot be combined with SCAN mode, and only one channel can be
enabled in this mode.
A DONE event signals that one sample has been taken.
In this mode, the RESULTDONE event has the same meaning as DONE when no oversampling takes place.
Note that both events may occur before the actual value has been transferred into RAM by EasyDMA.
37.5.3 Oversampling
An accumulator in the ADC can be used to average noise on the analog input. In general, oversampling
improves the signal-to-noise ratio (SNR). Oversampling, however, does not improve the integral non-linearity
(INL), or differential non-linearity (DNL).
Oversampling and scan should not be combined, since oversampling and scan will average over input
channels.
The accumulator is controlled in the OVERSAMPLE register. The SAMPLE task must be set 2
number of times before the result is written to RAM. This can be achieved by:
•
•
•
OVERSAMPLE
Configuring a fixed sampling rate using the local timer or a general purpose timer and PPI to trigger a
SAMPLE task
OVERSAMPLE
Triggering SAMPLE 2
times from software
Enabling BURST mode
OVERSAMPLE
CH[n].CONFIG.BURST can be enabled to avoid setting SAMPLE task 2
times. With
OVERSAMPLE
BURST = 1 the ADC will sample the input 2
times as fast as it can (actual timing:
OVERSAMPLE
= "number of channels enabled". See Scan mode on page 364 for more information
about Scan mode.
37.7 Resistor ladder
The ADC has an internal resistor string for positive and negative input.
See Figure 104: Resistor ladder for positive input (negative input is equivalent, using RESN instead of
RESP) on page 367. The resistors are controlled in the CH[n].CONFIG.RESP and CH[n].CONFIG.RESN
registers.
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37 SAADC — Successive approximation analogto-digital converter
RESP = Pullup
R
Output
Input
R
RESP = Pulldown
Figure 104: Resistor ladder for positive input (negative input is equivalent, using RESN instead of
RESP)
37.8 Reference
The ADC can use two different references, controlled in the REFSEL field of the CH[n].CONFIG register.
These are:
•
•
Internal reference
VDD as reference
The internal reference results in an input range of ±0.6 V on the ADC core. VDD as reference results in an
input range of ±VDD/4 on the ADC core. The gain block can be used to change the effective input range of
the ADC.
Input range = (+- 0.6 V or +-VDD/4)/Gain
For example, choosing VDD as reference, single ended input (grounded negative input), and a gain of 1/4
the input range will be:
Input range = (VDD/4)/(1/4) = VDD
With internal reference, single ended input (grounded negative input), and a gain of 1/6 the input range will
be:
Input range = (0.6 V)/(1/6) = 3.6 V
The AIN0-AIN7 inputs cannot exceed VDD, or be lower than VSS.
37.9 Acquisition time
To sample the input voltage, the ADC connects a capacitor to the input.
For illustration, see Figure 105: Simplified ADC sample network on page 368. The acquisition time
indicates how long the capacitor is connected, see TACQ field in CH[n].CONFIG register. The required
acquisition time depends on the source (Rsource) resistance. For high source resistance the acquisition time
should be increased, see Table 91: Acquisition time on page 368.
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37 SAADC — Successive approximation analogto-digital converter
ADC
Rsource
TACQ
Figure 105: Simplified ADC sample network
Table 91: Acquisition time
TACQ [µs]
3
5
10
15
20
40
Maximum source resistance [kOhm]
10
40
100
200
400
800
37.10 Limits event monitoring
A channel can be event monitored by configuring limit register CH[n].LIMIT.
If the conversion result is higher than the defined high limit, or lower than the defined low limit, the
appropriate event will get fired.
VIN
CH[n].LIMIT.HIGH
CH[n].LIMIT.LOW
t
EVENTS_CH[n].LIMITL
EVENTS_CH[n].LIMITH
EVENTS_CH[n].LIMITH
EVENTS_CH[n].LIMITH
events
Figure 106: Example of limits monitoring on channel 'n'
Note that when setting the limits, CH[n].LIMIT.HIGH shall always be higher than or equal to
CH[n].LIMIT.LOW . In other words, an event can be fired only when the input signal has been sampled
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37 SAADC — Successive approximation analogto-digital converter
outside of the defined limits. It is not possible to fire an event when the input signal is inside a defined range
by swapping high and low limits.
The comparison to limits always takes place, there is no need to enable it. If comparison is not required on a
channel, the software shall simply ignore the related events. In that situation, the value of the limits registers
is irrelevant, so it does not matter if CH[n].LIMIT.LOW is lower than CH[n].LIMIT.HIGH or not.
37.11 Registers
Table 92: Instances
Base address
Peripheral
Instance
Description
0x40007000
SAADC
SAADC
Analog to digital converter
Configuration
Table 93: Register Overview
Register
Offset
Description
TASKS_START
0x000
Start the ADC and prepare the result buffer in RAM
TASKS_SAMPLE
0x004
Take one ADC sample, if scan is enabled all channels are sampled
TASKS_STOP
0x008
Stop the ADC and terminate any on-going conversion
TASKS_CALIBRATEOFFSET0x00C
Starts offset auto-calibration
EVENTS_STARTED
0x100
The ADC has started
EVENTS_END
0x104
The ADC has filled up the Result buffer
EVENTS_DONE
0x108
A conversion task has been completed. Depending on the mode, multiple conversions might be
EVENTS_RESULTDONE
0x10C
needed for a result to be transferred to RAM.
A result is ready to get transferred to RAM.
EVENTS_CALIBRATEDONE0x110
Calibration is complete
EVENTS_STOPPED
0x114
The ADC has stopped
EVENTS_CH[0].LIMITH
0x118
Last results is equal or above CH[0].LIMIT.HIGH
EVENTS_CH[0].LIMITL
0x11C
Last results is equal or below CH[0].LIMIT.LOW
EVENTS_CH[1].LIMITH
0x120
Last results is equal or above CH[1].LIMIT.HIGH
EVENTS_CH[1].LIMITL
0x124
Last results is equal or below CH[1].LIMIT.LOW
EVENTS_CH[2].LIMITH
0x128
Last results is equal or above CH[2].LIMIT.HIGH
EVENTS_CH[2].LIMITL
0x12C
Last results is equal or below CH[2].LIMIT.LOW
EVENTS_CH[3].LIMITH
0x130
Last results is equal or above CH[3].LIMIT.HIGH
EVENTS_CH[3].LIMITL
0x134
Last results is equal or below CH[3].LIMIT.LOW
EVENTS_CH[4].LIMITH
0x138
Last results is equal or above CH[4].LIMIT.HIGH
EVENTS_CH[4].LIMITL
0x13C
Last results is equal or below CH[4].LIMIT.LOW
EVENTS_CH[5].LIMITH
0x140
Last results is equal or above CH[5].LIMIT.HIGH
EVENTS_CH[5].LIMITL
0x144
Last results is equal or below CH[5].LIMIT.LOW
EVENTS_CH[6].LIMITH
0x148
Last results is equal or above CH[6].LIMIT.HIGH
EVENTS_CH[6].LIMITL
0x14C
Last results is equal or below CH[6].LIMIT.LOW
EVENTS_CH[7].LIMITH
0x150
Last results is equal or above CH[7].LIMIT.HIGH
EVENTS_CH[7].LIMITL
0x154
Last results is equal or below CH[7].LIMIT.LOW
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
STATUS
0x400
Status
ENABLE
0x500
Enable or disable ADC
CH[0].PSELP
0x510
Input positive pin selection for CH[0]
CH[0].PSELN
0x514
Input negative pin selection for CH[0]
CH[0].CONFIG
0x518
Input configuration for CH[0]
CH[0].LIMIT
0x51C
High/low limits for event monitoring a channel
CH[1].PSELP
0x520
Input positive pin selection for CH[1]
CH[1].PSELN
0x524
Input negative pin selection for CH[1]
CH[1].CONFIG
0x528
Input configuration for CH[1]
CH[1].LIMIT
0x52C
High/low limits for event monitoring a channel
CH[2].PSELP
0x530
Input positive pin selection for CH[2]
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37 SAADC — Successive approximation analogto-digital converter
Register
Offset
Description
CH[2].PSELN
0x534
Input negative pin selection for CH[2]
CH[2].CONFIG
0x538
Input configuration for CH[2]
CH[2].LIMIT
0x53C
High/low limits for event monitoring a channel
CH[3].PSELP
0x540
Input positive pin selection for CH[3]
CH[3].PSELN
0x544
Input negative pin selection for CH[3]
CH[3].CONFIG
0x548
Input configuration for CH[3]
CH[3].LIMIT
0x54C
High/low limits for event monitoring a channel
CH[4].PSELP
0x550
Input positive pin selection for CH[4]
CH[4].PSELN
0x554
Input negative pin selection for CH[4]
CH[4].CONFIG
0x558
Input configuration for CH[4]
CH[4].LIMIT
0x55C
High/low limits for event monitoring a channel
CH[5].PSELP
0x560
Input positive pin selection for CH[5]
CH[5].PSELN
0x564
Input negative pin selection for CH[5]
CH[5].CONFIG
0x568
Input configuration for CH[5]
CH[5].LIMIT
0x56C
High/low limits for event monitoring a channel
CH[6].PSELP
0x570
Input positive pin selection for CH[6]
CH[6].PSELN
0x574
Input negative pin selection for CH[6]
CH[6].CONFIG
0x578
Input configuration for CH[6]
CH[6].LIMIT
0x57C
High/low limits for event monitoring a channel
CH[7].PSELP
0x580
Input positive pin selection for CH[7]
CH[7].PSELN
0x584
Input negative pin selection for CH[7]
CH[7].CONFIG
0x588
Input configuration for CH[7]
CH[7].LIMIT
0x58C
High/low limits for event monitoring a channel
RESOLUTION
0x5F0
Resolution configuration
OVERSAMPLE
0x5F4
Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is
SAMPLERATE
0x5F8
Controls normal or continuous sample rate
RESULT.PTR
0x62C
Data pointer
RESULT.MAXCNT
0x630
Maximum number of buffer words to transfer
RESULT.AMOUNT
0x634
Number of buffer words transferred since last START
applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.
37.11.1 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
A
RW STARTED
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for STARTED event
See EVENTS_STARTED
B
Disabled
0
Disable
Enabled
1
Enable
RW END
Enable or disable interrupt for END event
See EVENTS_END
C
Disabled
0
Disable
Enabled
1
Enable
RW DONE
Enable or disable interrupt for DONE event
See EVENTS_DONE
D
Disabled
0
Disable
Enabled
1
Enable
RW RESULTDONE
Enable or disable interrupt for RESULTDONE event
See EVENTS_RESULTDONE
Disabled
0
Disable
Enabled
1
Enable
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37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
E
RW CALIBRATEDONE
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for CALIBRATEDONE event
See EVENTS_CALIBRATEDONE
F
Disabled
0
Disable
Enabled
1
Enable
RW STOPPED
Enable or disable interrupt for STOPPED event
See EVENTS_STOPPED
G
Disabled
0
Disable
Enabled
1
Enable
RW CH0LIMITH
Enable or disable interrupt for CH[0].LIMITH event
See EVENTS_CH[0].LIMITH
H
Disabled
0
Disable
Enabled
1
Enable
RW CH0LIMITL
Enable or disable interrupt for CH[0].LIMITL event
See EVENTS_CH[0].LIMITL
I
Disabled
0
Disable
Enabled
1
Enable
RW CH1LIMITH
Enable or disable interrupt for CH[1].LIMITH event
See EVENTS_CH[1].LIMITH
J
Disabled
0
Disable
Enabled
1
Enable
RW CH1LIMITL
Enable or disable interrupt for CH[1].LIMITL event
See EVENTS_CH[1].LIMITL
K
Disabled
0
Disable
Enabled
1
Enable
RW CH2LIMITH
Enable or disable interrupt for CH[2].LIMITH event
See EVENTS_CH[2].LIMITH
L
Disabled
0
Disable
Enabled
1
Enable
RW CH2LIMITL
Enable or disable interrupt for CH[2].LIMITL event
See EVENTS_CH[2].LIMITL
M
Disabled
0
Disable
Enabled
1
Enable
RW CH3LIMITH
Enable or disable interrupt for CH[3].LIMITH event
See EVENTS_CH[3].LIMITH
N
Disabled
0
Disable
Enabled
1
Enable
RW CH3LIMITL
Enable or disable interrupt for CH[3].LIMITL event
See EVENTS_CH[3].LIMITL
O
Disabled
0
Disable
Enabled
1
Enable
RW CH4LIMITH
Enable or disable interrupt for CH[4].LIMITH event
See EVENTS_CH[4].LIMITH
P
Disabled
0
Disable
Enabled
1
Enable
RW CH4LIMITL
Enable or disable interrupt for CH[4].LIMITL event
See EVENTS_CH[4].LIMITL
Q
Disabled
0
Disable
Enabled
1
Enable
RW CH5LIMITH
Enable or disable interrupt for CH[5].LIMITH event
See EVENTS_CH[5].LIMITH
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37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
R
RW Field
0
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
RW CH5LIMITL
Enable or disable interrupt for CH[5].LIMITL event
See EVENTS_CH[5].LIMITL
S
Disabled
0
Disable
Enabled
1
Enable
RW CH6LIMITH
Enable or disable interrupt for CH[6].LIMITH event
See EVENTS_CH[6].LIMITH
T
Disabled
0
Disable
Enabled
1
Enable
RW CH6LIMITL
Enable or disable interrupt for CH[6].LIMITL event
See EVENTS_CH[6].LIMITL
U
Disabled
0
Disable
Enabled
1
Enable
RW CH7LIMITH
Enable or disable interrupt for CH[7].LIMITH event
See EVENTS_CH[7].LIMITH
V
Disabled
0
Disable
Enabled
1
Enable
RW CH7LIMITL
Enable or disable interrupt for CH[7].LIMITL event
See EVENTS_CH[7].LIMITL
Disabled
0
Disable
Enabled
1
Enable
37.11.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
A
RW STARTED
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for STARTED event
See EVENTS_STARTED
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Enable interrupt for END event
See EVENTS_END
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DONE
Write '1' to Enable interrupt for DONE event
See EVENTS_DONE
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RESULTDONE
Write '1' to Enable interrupt for RESULTDONE event
See EVENTS_RESULTDONE
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
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37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
E
RW CALIBRATEDONE
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for CALIBRATEDONE event
See EVENTS_CALIBRATEDONE
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH0LIMITH
Write '1' to Enable interrupt for CH[0].LIMITH event
See EVENTS_CH[0].LIMITH
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH0LIMITL
Write '1' to Enable interrupt for CH[0].LIMITL event
See EVENTS_CH[0].LIMITL
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH1LIMITH
Write '1' to Enable interrupt for CH[1].LIMITH event
See EVENTS_CH[1].LIMITH
J
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH1LIMITL
Write '1' to Enable interrupt for CH[1].LIMITL event
See EVENTS_CH[1].LIMITL
K
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH2LIMITH
Write '1' to Enable interrupt for CH[2].LIMITH event
See EVENTS_CH[2].LIMITH
L
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH2LIMITL
Write '1' to Enable interrupt for CH[2].LIMITL event
See EVENTS_CH[2].LIMITL
M
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH3LIMITH
Write '1' to Enable interrupt for CH[3].LIMITH event
See EVENTS_CH[3].LIMITH
N
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH3LIMITL
Write '1' to Enable interrupt for CH[3].LIMITL event
See EVENTS_CH[3].LIMITL
O
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH4LIMITH
Write '1' to Enable interrupt for CH[4].LIMITH event
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37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
0
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_CH[4].LIMITH
P
RW CH4LIMITL
Write '1' to Enable interrupt for CH[4].LIMITL event
See EVENTS_CH[4].LIMITL
Q
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH5LIMITH
Write '1' to Enable interrupt for CH[5].LIMITH event
See EVENTS_CH[5].LIMITH
R
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH5LIMITL
Write '1' to Enable interrupt for CH[5].LIMITL event
See EVENTS_CH[5].LIMITL
S
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH6LIMITH
Write '1' to Enable interrupt for CH[6].LIMITH event
See EVENTS_CH[6].LIMITH
T
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH6LIMITL
Write '1' to Enable interrupt for CH[6].LIMITL event
See EVENTS_CH[6].LIMITL
U
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH7LIMITH
Write '1' to Enable interrupt for CH[7].LIMITH event
See EVENTS_CH[7].LIMITH
V
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH7LIMITL
Write '1' to Enable interrupt for CH[7].LIMITL event
See EVENTS_CH[7].LIMITL
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
37.11.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
A
RW STARTED
0
Value Id
Value
Description
Write '1' to Disable interrupt for STARTED event
See EVENTS_STARTED
Clear
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Disable
Page 374
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
B
RW Field
0
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Disable interrupt for END event
See EVENTS_END
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DONE
Write '1' to Disable interrupt for DONE event
See EVENTS_DONE
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RESULTDONE
Write '1' to Disable interrupt for RESULTDONE event
See EVENTS_RESULTDONE
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CALIBRATEDONE
Write '1' to Disable interrupt for CALIBRATEDONE event
See EVENTS_CALIBRATEDONE
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Disable interrupt for STOPPED event
See EVENTS_STOPPED
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH0LIMITH
Write '1' to Disable interrupt for CH[0].LIMITH event
See EVENTS_CH[0].LIMITH
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH0LIMITL
Write '1' to Disable interrupt for CH[0].LIMITL event
See EVENTS_CH[0].LIMITL
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH1LIMITH
Write '1' to Disable interrupt for CH[1].LIMITH event
See EVENTS_CH[1].LIMITH
J
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH1LIMITL
Write '1' to Disable interrupt for CH[1].LIMITL event
See EVENTS_CH[1].LIMITL
K
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH2LIMITH
Write '1' to Disable interrupt for CH[2].LIMITH event
See EVENTS_CH[2].LIMITH
Clear
1
Disable
Disabled
0
Read: Disabled
Page 375
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
L
RW Field
0
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Read: Enabled
RW CH2LIMITL
Write '1' to Disable interrupt for CH[2].LIMITL event
See EVENTS_CH[2].LIMITL
M
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH3LIMITH
Write '1' to Disable interrupt for CH[3].LIMITH event
See EVENTS_CH[3].LIMITH
N
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH3LIMITL
Write '1' to Disable interrupt for CH[3].LIMITL event
See EVENTS_CH[3].LIMITL
O
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH4LIMITH
Write '1' to Disable interrupt for CH[4].LIMITH event
See EVENTS_CH[4].LIMITH
P
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH4LIMITL
Write '1' to Disable interrupt for CH[4].LIMITL event
See EVENTS_CH[4].LIMITL
Q
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH5LIMITH
Write '1' to Disable interrupt for CH[5].LIMITH event
See EVENTS_CH[5].LIMITH
R
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH5LIMITL
Write '1' to Disable interrupt for CH[5].LIMITL event
See EVENTS_CH[5].LIMITL
S
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH6LIMITH
Write '1' to Disable interrupt for CH[6].LIMITH event
See EVENTS_CH[6].LIMITH
T
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH6LIMITL
Write '1' to Disable interrupt for CH[6].LIMITL event
See EVENTS_CH[6].LIMITL
U
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW CH7LIMITH
Write '1' to Disable interrupt for CH[7].LIMITH event
See EVENTS_CH[7].LIMITH
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Page 376
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
V U T S R Q P O N M L K J
Reset 0x00000000
Id
RW Field
V
RW CH7LIMITL
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for CH[7].LIMITL event
See EVENTS_CH[7].LIMITL
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
37.11.4 STATUS
Address offset: 0x400
Status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
R
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Ready
0
ADC is ready. No on-going conversion.
Busy
1
ADC is busy. Conversion in progress.
STATUS
Status
37.11.5 ENABLE
Address offset: 0x500
Enable or disable ADC
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable ADC
Enabled
1
Enable ADC
Enable or disable ADC
When enabled, the ADC will acquire access to the analog input
pins specified in the CH[n].PSELP and CH[n].PSELN registers.
37.11.6 CH[0].PSELP
Address offset: 0x510
Input positive pin selection for CH[0]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
Page 377
37 SAADC — Successive approximation analogto-digital converter
37.11.7 CH[0].PSELN
Address offset: 0x514
Input negative pin selection for CH[0]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog negative input, enables differential channel
37.11.8 CH[0].CONFIG
Address offset: 0x518
Input configuration for CH[0]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
D
E
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
Page 378
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
F
RW Field
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
40us
5
40 us
SE
0
Diff
1
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
Differential
RW BURST
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.9 CH[0].LIMIT
Address offset: 0x51C
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.10 CH[1].PSELP
Address offset: 0x520
Input positive pin selection for CH[1]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
37.11.11 CH[1].PSELN
Address offset: 0x524
Input negative pin selection for CH[1]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
Analog negative input, enables differential channel
Page 379
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
37.11.12 CH[1].CONFIG
Address offset: 0x528
Input configuration for CH[1]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
D
E
0
F
E E E
D
C C C
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
Disabled
0
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Differential
RW BURST
Enable burst mode
Burst mode is disabled (normal operation)
Page 380
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
samples as fast as it can, and sends the average to Data RAM.
37.11.13 CH[1].LIMIT
Address offset: 0x52C
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.14 CH[2].PSELP
Address offset: 0x530
Input positive pin selection for CH[2]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
37.11.15 CH[2].PSELN
Address offset: 0x534
Input negative pin selection for CH[2]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
Analog negative input, enables differential channel
Page 381
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
VDD
9
VDD
37.11.16 CH[2].CONFIG
Address offset: 0x538
Input configuration for CH[2]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
D
E
0
F
E E E
D
C C C
B B
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Differential
RW BURST
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.17 CH[2].LIMIT
Address offset: 0x53C
High/low limits for event monitoring a channel
Page 382
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.18 CH[3].PSELP
Address offset: 0x540
Input positive pin selection for CH[3]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
37.11.19 CH[3].PSELN
Address offset: 0x544
Input negative pin selection for CH[3]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog negative input, enables differential channel
37.11.20 CH[3].CONFIG
Address offset: 0x548
Input configuration for CH[3]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
0
Value Id
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Positive channel resistor control
Page 383
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
B
C
D
E
RW Field
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
Differential
RW BURST
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.21 CH[3].LIMIT
Address offset: 0x54C
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.22 CH[4].PSELP
Address offset: 0x550
Input positive pin selection for CH[4]
Page 384
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
37.11.23 CH[4].PSELN
Address offset: 0x554
Input negative pin selection for CH[4]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog negative input, enables differential channel
37.11.24 CH[4].CONFIG
Address offset: 0x558
Input configuration for CH[4]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
Page 385
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
D
E
RW Field
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
Differential
RW BURST
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.25 CH[4].LIMIT
Address offset: 0x55C
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.26 CH[5].PSELP
Address offset: 0x560
Input positive pin selection for CH[5]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
Analog positive input channel
Page 386
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
37.11.27 CH[5].PSELN
Address offset: 0x564
Input negative pin selection for CH[5]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog negative input, enables differential channel
37.11.28 CH[5].CONFIG
Address offset: 0x568
Input configuration for CH[5]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
D
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
Internal reference (0.6 V)
Page 387
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
E
RW Field
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
VDD1_4
1
VDD/4 as reference
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
Differential
RW BURST
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.29 CH[5].LIMIT
Address offset: 0x56C
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.30 CH[6].PSELP
Address offset: 0x570
Input positive pin selection for CH[6]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
37.11.31 CH[6].PSELN
Address offset: 0x574
Input negative pin selection for CH[6]
Page 388
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog negative input, enables differential channel
37.11.32 CH[6].CONFIG
Address offset: 0x578
Input configuration for CH[6]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
D
E
0
F
E E E
D
C C C
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
Differential
Page 389
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
G
RW BURST
0
F
E E E
D
C C C
B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.33 CH[6].LIMIT
Address offset: 0x57C
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.34 CH[7].PSELP
Address offset: 0x580
Input positive pin selection for CH[7]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
Analog positive input channel
37.11.35 CH[7].PSELN
Address offset: 0x584
Input negative pin selection for CH[7]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
A
RW PSELN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
Analog negative input, enables differential channel
Page 390
37 SAADC — Successive approximation analogto-digital converter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
37.11.36 CH[7].CONFIG
Address offset: 0x588
Input configuration for CH[7]
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
G
Reset 0x00020000
Id
RW Field
A
RW RESP
B
C
D
E
0
F
E E E
D
C C C
B B
Value Id
Value
Description
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
Positive channel resistor control
RW RESN
Negative channel resistor control
RW GAIN
Gain control
RW REFSEL
Reference control
RW TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
F
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
SE
0
Diff
1
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
RW MODE
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
G
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Differential
RW BURST
Enable burst mode
samples as fast as it can, and sends the average to Data RAM.
37.11.37 CH[7].LIMIT
Address offset: 0x58C
Page 391
37 SAADC — Successive approximation analogto-digital converter
High/low limits for event monitoring a channel
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0x7FFF8000
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
B
Value Id
Value
Description
RW LOW
[-32768 to +32767]
Low level limit
RW HIGH
[-32768 to +32767]
High level limit
37.11.38 RESOLUTION
Address offset: 0x5F0
Resolution configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000001
Id
RW Field
A
RW VAL
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value
Description
Set the resolution
8bit
0
8 bit
10bit
1
10 bit
12bit
2
12 bit
14bit
3
14 bit
37.11.39 OVERSAMPLE
Address offset: 0x5F4
Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is
applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW OVERSAMPLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Bypass
0
Bypass oversampling
Over2x
1
Oversample 2x
Over4x
2
Oversample 4x
Over8x
3
Oversample 8x
Over16x
4
Oversample 16x
Over32x
5
Oversample 32x
Over64x
6
Oversample 64x
Over128x
7
Oversample 128x
Over256x
8
Oversample 256x
Oversample control
37.11.40 SAMPLERATE
Address offset: 0x5F8
Controls normal or continuous sample rate
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
Reset 0x00000000
Id
RW Field
A
RW CC
B
RW MODE
0
Value Id
A A A A A A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[80..2047]
Capture and compare value. Sample rate is 16 MHz/CC
Select mode for sample rate control
Task
0
Rate is controlled from SAMPLE task
Timers
1
Rate is controlled from local timer (use CC to control the rate)
Page 392
37 SAADC — Successive approximation analogto-digital converter
37.11.41 RESULT.PTR
Address offset: 0x62C
Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Data pointer
37.11.42 RESULT.MAXCNT
Address offset: 0x630
Maximum number of buffer words to transfer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum number of buffer words to transfer
37.11.43 RESULT.AMOUNT
Address offset: 0x634
Number of buffer words transferred since last START
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
AMOUNT
Number of buffer words transferred since last START. This
register can be read after an END or STOPPED event.
37.12 Electrical specification
37.12.1 SAADC Electrical Specification
Symbol
Description
Min.
Typ.
DNL
Differential non-linearity, 10-bit resolution
-0.95
0)
Figure 123: Frame disassemble illustration
Page 426
b5
b6
b7
P
CRC 2 (8 bit)
P
EoF
42 NFCT — Near field communication tag
42.8 Antenna interface
In ACTIVATED state, an amplitude regulator will adjust the voltage swing on the antenna pins to a value that
is within the Vswing limit.
Refer to NFCT Electrical Specification on page 439.
42.9 NFCT antenna recommendations
The NFCT antenna coil must be connected differential between NFC1 and NFC2 pins of the device.
Two external capacitors should be used to tune the resonance of the antenna circuit to 13.56 MHz.
Cp1
Ctune1
Cint1
NFC1
ANTENNA
Lant
Rin
NFC2
Cp2
Ctune2
Cint2
Figure 124: NFCT antenna recommendations
The required tuning capacitor value is given by the below equations:
An antenna inductance of Lant = 2 µH will give tuning capacitors in the range of 130 pF on each pin. For good
performance, match the total capacitance on NFC1 and NFC2.
42.10 Battery protection
If the antenna is exposed to a strong NFC field, current may flow in the opposite direction on the supply due
to parasitic diodes and ESD structures.
If the battery used does not tolerate return current, a series diode must be placed between the battery and
the device in order to protect the battery.
Page 427
42 NFCT — Near field communication tag
42.11 References
NFC Forum, NFC Analog Specification version 1.0, www.nfc-forum.org
NFC Forum, NFC Digital Protocol Technical Specification version 1.1, www.nfc-forum.org
NFC Forum, NFC Activity Technical Specification version 1.1, www.nfc-forum.org
42.12 Registers
Table 102: Instances
Base address
Peripheral
Instance
Description
0x40005000
NFCT
NFCT
Near Field Communication Tag
Configuration
Table 103: Register Overview
Register
Offset
Description
TASKS_ACTIVATE
0x000
Activate NFC peripheral for incoming and outgoing frames, change state to activated
TASKS_DISABLE
0x004
Disable NFC peripheral
TASKS_SENSE
0x008
Enable NFC sense field mode, change state to sense mode
TASKS_STARTTX
0x00C
Start transmission of a outgoing frame, change state to transmit
TASKS_ENABLERXDATA 0x01C
Initializes the EasyDMA for receive.
TASKS_GOIDLE
0x024
Force state machine to IDLE state
TASKS_GOSLEEP
0x028
Force state machine to SLEEP_A state
EVENTS_READY
0x100
The NFC peripheral is ready to receive and send frames
EVENTS_FIELDDETECTED 0x104
Remote NFC field detected
EVENTS_FIELDLOST
Remote NFC field lost
0x108
EVENTS_TXFRAMESTART 0x10C
Marks the start of the first symbol of a transmitted frame
EVENTS_TXFRAMEEND
Marks the end of the last transmitted on-air symbol of a frame
0x110
EVENTS_RXFRAMESTART 0x114
Marks the end of the first symbol of a received frame
EVENTS_RXFRAMEEND 0x118
Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended
accessing the RX buffer
EVENTS_ERROR
0x11C
NFC error reported. The ERRORSTATUS register contains details on the source of the error.
EVENTS_RXERROR
0x128
NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the
EVENTS_ENDRX
0x12C
RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.
EVENTS_ENDTX
0x130
Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer
error.
EVENTS_AUTOCOLRESSTARTED
0x138
Auto collision resolution process has started
EVENTS_COLLISION
0x148
NFC Auto collision resolution error reported.
EVENTS_SELECTED
0x14C
NFC Auto collision resolution successfully completed
EVENTS_STARTED
0x150
EasyDMA is ready to receive or send frames.
SHORTS
0x200
Shortcut register
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ERRORSTATUS
0x404
NFC Error Status register
FRAMESTATUS.RX
0x40C
Result of last incoming frames
CURRENTLOADCTRL
0x430
Current value driven to the NFC Load Control
FIELDPRESENT
0x43C
Indicates the presence or not of a valid field
FRAMEDELAYMIN
0x504
Minimum frame delay
FRAMEDELAYMAX
0x508
Maximum frame delay
FRAMEDELAYMODE
0x50C
Configuration register for the Frame Delay Timer
PACKETPTR
0x510
Packet pointer for TXD and RXD data storage in Data RAM
MAXLEN
0x514
Size of allocated for TXD and RXD data storage buffer in Data RAM
TXD.FRAMECONFIG
0x518
Configuration of outgoing frames
TXD.AMOUNT
0x51C
Size of outgoing frame
RXD.FRAMECONFIG
0x520
Configuration of incoming frames
Page 428
42 NFCT — Near field communication tag
Register
Offset
Description
RXD.AMOUNT
0x524
Size of last incoming frame
NFCID1_LAST
0x590
Last NFCID1 part (4, 7 or 10 bytes ID)
NFCID1_2ND_LAST
0x594
Second last NFCID1 part (7 or 10 bytes ID)
NFCID1_3RD_LAST
0x598
Third last NFCID1 part (10 bytes ID)
SENSRES
0x5A0
NFC-A SENS_RES auto-response settings
SELRES
0x5A4
NFC-A SEL_RES auto-response settings
42.12.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
A
RW FIELDDETECTED_ACTIVATE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between FIELDDETECTED event and ACTIVATE task
See EVENTS_FIELDDETECTED and TASKS_ACTIVATE
B
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW FIELDLOST_SENSE
Shortcut between FIELDLOST event and SENSE task
See EVENTS_FIELDLOST and TASKS_SENSE
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
42.12.2 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for READY event
See EVENTS_READY
B
Disabled
0
Disable
Enabled
1
Enable
RW FIELDDETECTED
Enable or disable interrupt for FIELDDETECTED event
See EVENTS_FIELDDETECTED
C
Disabled
0
Disable
Enabled
1
Enable
RW FIELDLOST
Enable or disable interrupt for FIELDLOST event
See EVENTS_FIELDLOST
D
Disabled
0
Disable
Enabled
1
Enable
RW TXFRAMESTART
Enable or disable interrupt for TXFRAMESTART event
See EVENTS_TXFRAMESTART
E
Disabled
0
Disable
Enabled
1
Enable
RW TXFRAMEEND
Enable or disable interrupt for TXFRAMEEND event
See EVENTS_TXFRAMEEND
F
Disabled
0
Disable
Enabled
1
Enable
RW RXFRAMESTART
Enable or disable interrupt for RXFRAMESTART event
Page 429
42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
RW Field
0
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
See EVENTS_RXFRAMESTART
G
RW RXFRAMEEND
Enable or disable interrupt for RXFRAMEEND event
See EVENTS_RXFRAMEEND
H
Disabled
0
Disable
Enabled
1
Enable
RW ERROR
Enable or disable interrupt for ERROR event
See EVENTS_ERROR
K
Disabled
0
Disable
Enabled
1
Enable
RW RXERROR
Enable or disable interrupt for RXERROR event
See EVENTS_RXERROR
L
Disabled
0
Disable
Enabled
1
Enable
RW ENDRX
Enable or disable interrupt for ENDRX event
See EVENTS_ENDRX
M
Disabled
0
Disable
Enabled
1
Enable
RW ENDTX
Enable or disable interrupt for ENDTX event
See EVENTS_ENDTX
N
Disabled
0
Disable
Enabled
1
Enable
RW AUTOCOLRESSTARTED
Enable or disable interrupt for AUTOCOLRESSTARTED event
See EVENTS_AUTOCOLRESSTARTED
R
Disabled
0
Disable
Enabled
1
Enable
RW COLLISION
Enable or disable interrupt for COLLISION event
See EVENTS_COLLISION
S
Disabled
0
Disable
Enabled
1
Enable
RW SELECTED
Enable or disable interrupt for SELECTED event
See EVENTS_SELECTED
T
Disabled
0
Disable
Enabled
1
Enable
RW STARTED
Enable or disable interrupt for STARTED event
See EVENTS_STARTED
Disabled
0
Disable
Enabled
1
Enable
42.12.3 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for READY event
See EVENTS_READY
Page 430
42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
B
RW Field
0
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW FIELDDETECTED
Write '1' to Enable interrupt for FIELDDETECTED event
See EVENTS_FIELDDETECTED
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW FIELDLOST
Write '1' to Enable interrupt for FIELDLOST event
See EVENTS_FIELDLOST
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXFRAMESTART
Write '1' to Enable interrupt for TXFRAMESTART event
See EVENTS_TXFRAMESTART
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXFRAMEEND
Write '1' to Enable interrupt for TXFRAMEEND event
See EVENTS_TXFRAMEEND
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXFRAMESTART
Write '1' to Enable interrupt for RXFRAMESTART event
See EVENTS_RXFRAMESTART
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXFRAMEEND
Write '1' to Enable interrupt for RXFRAMEEND event
See EVENTS_RXFRAMEEND
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Enable interrupt for ERROR event
See EVENTS_ERROR
K
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXERROR
Write '1' to Enable interrupt for RXERROR event
See EVENTS_RXERROR
L
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Enable interrupt for ENDRX event
See EVENTS_ENDRX
M
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDTX
Write '1' to Enable interrupt for ENDTX event
See EVENTS_ENDTX
Set
1
Enable
Page 431
42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
N
RW Field
0
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW AUTOCOLRESSTARTED
Write '1' to Enable interrupt for AUTOCOLRESSTARTED event
See EVENTS_AUTOCOLRESSTARTED
R
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COLLISION
Write '1' to Enable interrupt for COLLISION event
See EVENTS_COLLISION
S
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SELECTED
Write '1' to Enable interrupt for SELECTED event
See EVENTS_SELECTED
T
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STARTED
Write '1' to Enable interrupt for STARTED event
See EVENTS_STARTED
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
42.12.4 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for READY event
See EVENTS_READY
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW FIELDDETECTED
Write '1' to Disable interrupt for FIELDDETECTED event
See EVENTS_FIELDDETECTED
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW FIELDLOST
Write '1' to Disable interrupt for FIELDLOST event
See EVENTS_FIELDLOST
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXFRAMESTART
Write '1' to Disable interrupt for TXFRAMESTART event
See EVENTS_TXFRAMESTART
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Page 432
42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
RW Field
E
RW TXFRAMEEND
0
Value Id
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for TXFRAMEEND event
See EVENTS_TXFRAMEEND
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXFRAMESTART
Write '1' to Disable interrupt for RXFRAMESTART event
See EVENTS_RXFRAMESTART
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXFRAMEEND
Write '1' to Disable interrupt for RXFRAMEEND event
See EVENTS_RXFRAMEEND
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ERROR
Write '1' to Disable interrupt for ERROR event
See EVENTS_ERROR
K
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW RXERROR
Write '1' to Disable interrupt for RXERROR event
See EVENTS_RXERROR
L
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDRX
Write '1' to Disable interrupt for ENDRX event
See EVENTS_ENDRX
M
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ENDTX
Write '1' to Disable interrupt for ENDTX event
See EVENTS_ENDTX
N
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW AUTOCOLRESSTARTED
Write '1' to Disable interrupt for AUTOCOLRESSTARTED event
See EVENTS_AUTOCOLRESSTARTED
R
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW COLLISION
Write '1' to Disable interrupt for COLLISION event
See EVENTS_COLLISION
S
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SELECTED
Write '1' to Disable interrupt for SELECTED event
See EVENTS_SELECTED
T
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STARTED
Write '1' to Disable interrupt for STARTED event
Page 433
42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
T S R
Reset 0x00000000
Id
RW Field
0
N
M L K
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_STARTED
42.12.5 ERRORSTATUS
Address offset: 0x404
NFC Error Status register
Write a bit to '1' to clear it. Writing '0' has no effect.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D C
Reset 0x00000000
0
Value Id
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW FRAMEDELAYTIMEOUT
Value
Description
C
RW NFCFIELDTOOSTRONG
Field level is too high at max load resistance
D
RW NFCFIELDTOOWEAK
Field level is too low at min load resistance
No STARTTX task triggered before expiration of the time set in
FRAMEDELAYMAX
42.12.6 FRAMESTATUS.RX
Address offset: 0x40C
Result of last incoming frames
Write a bit to '1' to clear it. Writing '0' has no effect.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B
Reset 0x00000000
Id
RW Field
A
RW CRCERROR
B
C
0
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
CRCCorrect
0
Valid CRC detected
CRCError
1
CRC received does not match local check
ParityOK
0
Frame received with parity OK
ParityError
1
Frame received with parity error
NoOverrun
0
No overrun detected
Overrun
1
Overrun error
No valid End of Frame detected
RW PARITYSTATUS
Parity status of received frame
RW OVERRUN
Overrun detected
42.12.7 CURRENTLOADCTRL
Address offset: 0x430
Current value driven to the NFC Load Control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
CURRENTLOADCTRL
Current value driven to the NFC Load Control
42.12.8 FIELDPRESENT
Address offset: 0x43C
Page 434
42 NFCT — Near field communication tag
Indicates the presence or not of a valid field
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
FIELDPRESENT
Indicates the presence or not of a valid field. Available only in
the activated state.
B
R
NoField
0
No valid field detected
FieldPresent
1
Valid field detected
NotLocked
0
Not locked to field
Locked
1
Locked to field
LOCKDETECT
Indicates if the low level has locked to the field
42.12.9 FRAMEDELAYMIN
Address offset: 0x504
Minimum frame delay
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000480
Id
RW Field
A
RW FRAMEDELAYMIN
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0
Value
Description
Minimum frame delay in number of 13.56 MHz clocks
42.12.10 FRAMEDELAYMAX
Address offset: 0x508
Maximum frame delay
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00001000
Id
RW Field
A
RW FRAMEDELAYMAX
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Maximum frame delay in number of 13.56 MHz clocks
42.12.11 FRAMEDELAYMODE
Address offset: 0x50C
Configuration register for the Frame Delay Timer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000001
Id
RW Field
A
RW FRAMEDELAYMODE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Description
FreeRun
0
Window
1
ExactVal
2
Frame is transmitted exactly at FRAMEDELAYMAX
WindowGrid
3
Frame is transmitted on a bit grid between FRAMEDELAYMIN
Configuration register for the Frame Delay Timer
Transmission is independent of frame timer and will start when
the STARTTX task is triggered. No timeout.
Frame is transmitted between FRAMEDELAYMIN and
FRAMEDELAYMAX
and FRAMEDELAYMAX
42.12.12 PACKETPTR
Address offset: 0x510
Packet pointer for TXD and RXD data storage in Data RAM
Page 435
42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Packet pointer for TXD and RXD data storage in Data RAM. This
address is a byte aligned RAM address.
42.12.13 MAXLEN
Address offset: 0x514
Size of allocated for TXD and RXD data storage buffer in Data RAM
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXLEN
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..257]
Size of allocated for TXD and RXD data storage buffer in Data
RAM
42.12.14 TXD.FRAMECONFIG
Address offset: 0x518
Configuration of outgoing frames
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D
Reset 0x00000017
Id
RW Field
A
RW PARITY
B
C
D
0
C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1
Value Id
Value
Description
NoParity
0
Parity is not added in TX frames
Parity
1
Parity is added TX frames
DiscardEnd
0
Unused bits is discarded at end of frame
DiscardStart
1
Unused bits is discarded at start of frame
NoSoF
0
Start of Frame symbol not added
SoF
1
Start of Frame symbol added
NoCRCTX
0
CRC is not added to the frame
CRC16TX
1
16 bit CRC added to the frame based on all the data read from
Adding parity or not in the frame
RW DISCARDMODE
Discarding unused bits in start or at end of a Frame
RW SOF
Adding SoF or not in TX frames
RW CRCMODETX
CRC mode for outgoing frames
RAM that is used in the frame
42.12.15 TXD.AMOUNT
Address offset: 0x51C
Size of outgoing frame
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B B B B B B B B B A A A
Reset 0x00000000
Id
RW Field
A
RW TXDATABITS
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..7]
Number of bits in the last or first byte read from RAM that shall
be included in the frame (excluding parity bit).
The DISCARDMODE field in FRAMECONFIG.TX selects if unused
bits is discarded at the start or at the end of a frame. A value of
0 data bytes and 0 data bits is invalid.
B
RW TXDATABYTES
[0..257]
Number of complete bytes that shall be included in the frame,
excluding CRC, parity and framing
Page 436
42 NFCT — Near field communication tag
42.12.16 RXD.FRAMECONFIG
Address offset: 0x520
Configuration of incoming frames
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
Reset 0x00000015
Id
RW Field
A
RW PARITY
B
C
0
B
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1
Value Id
Value
Description
NoParity
0
Parity is not expected in RX frames
Parity
1
Parity is expected in RX frames
NoSoF
0
Start of Frame symbol is not expected in RX frames
SoF
1
Start of Frame symbol is expected in RX frames
NoCRCRX
0
CRC is not expected in RX frames
CRC16RX
1
Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS
Parity expected or not in RX frame
RW SOF
SoF expected or not in RX frames
RW CRCMODERX
CRC mode for incoming frames
updated
42.12.17 RXD.AMOUNT
Address offset: 0x524
Size of last incoming frame
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B B B B B B B B B A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RXDATABITS
Number of bits in the last byte in the frame, if less than 8
(including CRC, but excluding parity and SoF/EoF framing).
Frames with 0 data bytes and less than 7 data bits are invalid
and are not received properly.
B
R
RXDATABYTES
Number of complete bytes received in the frame (including CRC,
but excluding parity and SoF/EoF framing)
42.12.18 NFCID1_LAST
Address offset: 0x590
Last NFCID1 part (4, 7 or 10 bytes ID)
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00006363
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1
Id
RW Field
Value
A
RW NFCID1_Z
Description
NFCID1 byte Z (very last byte sent)
B
RW NFCID1_Y
NFCID1 byte Y
C
RW NFCID1_X
NFCID1 byte X
D
RW NFCID1_W
NFCID1 byte W
42.12.19 NFCID1_2ND_LAST
Address offset: 0x594
Second last NFCID1 part (7 or 10 bytes ID)
Page 437
42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00000000
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW NFCID1_V
Value
Description
NFCID1 byte V
B
RW NFCID1_U
NFCID1 byte U
C
RW NFCID1_T
NFCID1 byte T
42.12.20 NFCID1_3RD_LAST
Address offset: 0x598
Third last NFCID1 part (10 bytes ID)
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00000000
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW NFCID1_S
Value
Description
NFCID1 byte S
B
RW NFCID1_R
NFCID1 byte R
C
RW NFCID1_Q
NFCID1 byte Q
42.12.21 SENSRES
Address offset: 0x5A0
NFC-A SENS_RES auto-response settings
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E E E E D D D D C C B A A A A A
Reset 0x00000001
Id
RW Field
A
RW BITFRAMESDD
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value
Description
Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES
response in the NFC Forum, NFC Digital Protocol Technical
Specification
SDD00000
0
SDD pattern 00000
SDD00001
1
SDD pattern 00001
SDD00010
2
SDD pattern 00010
SDD00100
4
SDD pattern 00100
SDD01000
8
SDD pattern 01000
SDD10000
16
SDD pattern 10000
B
RW RFU5
Reserved for future use. Shall be 0.
C
RW NFCIDSIZE
NFCID1 size. This value is used by the Auto collision resolution
engine.
D
NFCID1Single
0
NFCID1 size: single (4 bytes)
NFCID1Double
1
NFCID1 size: double (7 bytes)
NFCID1Triple
2
NFCID1 size: triple (10 bytes)
RW PLATFCONFIG
Tag platform configuration as defined by the b4:b1 of byte 2
in SENS_RES response in the NFC Forum, NFC Digital Protocol
Technical Specification
E
RW RFU74
Reserved for future use. Shall be 0.
42.12.22 SELRES
Address offset: 0x5A4
NFC-A SEL_RES auto-response settings
Page 438
42 NFCT — Near field communication tag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D D C C B A A
Reset 0x00000000
Id
RW Field
A
RW RFU10
B
RW CASCADE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Reserved for future use. Shall be 0.
Cascade bit (controlled by hardware, write has no effect)
Complete
0
NFCID1 complete
NotComplete
1
NFCID1 not complete
C
RW RFU43
Reserved for future use. Shall be 0.
D
RW PROTOCOL
Protocol as defined by the b7:b6 of SEL_RES response in the
E
RW RFU7
NFC Forum, NFC Digital Protocol Technical Specification
Reserved for future use. Shall be 0.
42.13 Electrical specification
42.13.1 NFCT Electrical Specification
Symbol
Description
fc
Frequency of operation
Min.
Typ.
Max.
CMI
Carrier modulation index
DR
Data Rate
106
fs
Modulation sub-carrier frequency
fc/16
Vswing
Peak differential Input voltage swing on NFC1 and NFC2
Vsense
Peak differential Field detect threshold level on NFC1-NFC235
1.0
Vp
Isense
Current in SENSE STATE
100
nA
Iactivated
Current in ACTIVATED STATE
480
Rin_min
Minimum input resistance when regulating voltage swing
Rin_max
Maximum input resistance when regulating voltage swing
1.0
Rin_loadmod
Input resistance when load modulating
8
Imax
Maximum input current on NFC pins
13.56
Units
MHz
95
%
kbps
MHz
VDD
Vp
µA
40
Ω
kΩ
22
Ω
80
mA
Max.
Units
500
us
20
us
42.13.2 NFCT Timing Parameters
Symbol
Description
tactivate
Time from task_ACTIVATE in SENSE or DISABLE state to
Min.
Typ.
ACTIVATE_A or IDLE state36
tsense
Time from remote field is present in SENSE mode to
FIELDDETECTED event is asserted
DISABLE
ACTIVATE
SENSE
TASKS
tactivate
tsense
tsense
RF-Carrier
MODES
DISABLE
SENSE_FIELD
IDLERU
Activated
DISABLE
FIELDDETECTED
FIELDLOST
READY
FIELDDETECTED
EVENTS
Figure 125: NFCT timing parameters (Shortcuts for FIELDDETECTED and FIELDLOST are disabled)
35
36
Input is high impedance in sense mode
Does not account for voltage supply and oscillator startup times
Page 439
43 PDM — Pulse density modulation interface
43 PDM — Pulse density modulation interface
The pulse density modulation (PDM) module enables input of pulse density modulated signals from external
audio frontends, for example, digital microphones. The PDM module generates the PDM clock and supports
single-channel or dual-channel (Left and Right) data input. Data is transferred directly to RAM buffers using
EasyDMA.
Listed here are the main features for PDM:
•
•
•
•
Up to two PDM microphones configured as a Left/Right pair using the same data input
16 kHz output sample rate, 16-bit samples
EasyDMA support for sample buffering
HW decimation filters
The PDM module illustrated in Figure 126: PDM module on page 440 is interfacing up to two digital
microphones with the PDM interface. It implements EasyDMA, which relieves real-time requirements
associated with controlling the PDM slave from a low priority CPU execution context. It also includes all
the necessary digital filter elements to produce PCM samples. The PDM module allows continuous audio
streaming.
CLK
Band-pass and
Decimation (left)
PDM to PCM
Band-pass and
Decimation (right)
RAM
PDM to PCM
EasyDMA
Sampling
DIN
Master clock
generator
Figure 126: PDM module
43.1 Master clock generator
The FREQ field in the master clock's PDMCLKCTRL register allows adjusting the PDM clock's frequency.
The master clock generator does not add any jitter to the HFCLK source chosen. It is recommended (but not
mandatory) to use the Xtal as HFCLK source.
43.2 Module operation
By default, bits from the left PDM microphone are sampled on PDM_CLK falling edge, bits for the right are
sampled on the rising edge of PDM_CLK, resulting in two bitstreams. Each bitstream is fed into a digital filter
which converts the PDM stream into 16-bit PCM samples, and filters and down-samples them to reach the
appropriate sample rate.
The EDGE field in the MODE register allows swapping Left and Right, so that Left will be sampled on rising
edge, and Right on falling.
The PDM module uses EasyDMA to store the samples coming out from the filters into one buffer in RAM.
Depending on the mode chosen in the OPERATION field in the MODE register, memory either contains
alternating left and right 16-bit samples (Stereo), or only left 16-bit samples (Mono).
To ensure continuous PDM sampling, it is up to the application to update the EasyDMA destination address
pointer as the previous buffer is filled.
Page 440
43 PDM — Pulse density modulation interface
The continuous transfer can be started or stopped by sending the START and STOP tasks. STOP becomes
effective after the current frame has finished transferring, which will generate the STOPPED event. The
STOPPED event indicates that all activity in the module are finished, and that the data is available in RAM
(EasyDMA has finished transferring as well). Attempting to restart before receiving the STOPPED event may
result in unpredictable behaviour.
43.3 Decimation filter
In order to convert the incoming data stream into PCM audio samples, a decimation filter is included in the
PDM interface module.
The input of the filter is the two-channel PDM serial stream (with left channel on clock high, right channel on
clock low), its output is 2 × 16-bit PCM samples at a sample rate 64 times lower than the PDM clock rate.
The filter stage of each channel is followed by a digital volume control, to attenuate or amplify the output
samples in a range of -20 dB to +20 dB around the default (reset) setting, defined by GPDM,default. The gain is
controlled by the GAINL and GAINR registers.
As an example, if the goal is to achieve 2500 RMS output samples (16 bit) with a 1 kHz 90 dBA signal into a
-26 dBFS sensitivity PDM microphone, the user will have to sum the PDM module's default gain ( GPDM,default
) and the gain introduced by the microphone and acoustic path of his implementation (an attenuation would
translate into a negative gain), and adjust GAINL and GAINR by this amount. Assuming that only the PDM
module influences the gain, GAINL and GAINR must be set to -GPDM,default dB to achieve the requirement.
With GPDM,default=3.2 dB, and as GAINL and GAINR are expressed in 0.5 dB steps, the closest value to
program would be 3.0 dB, which can be calculated as:
GAINL = GAINR = (DefaultGain - (2 * 3))
Remember to check that the resulting values programmed into GAINL and GAINR fall within MinGain and
MaxGain.
43.4 EasyDMA
Samples will be written directly to RAM, and EasyDMA must be configured accordingly.
The address pointer for the EasyDMA channel is set in SAMPLE.PTR register. If the destination address set
in SAMPLE.PTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or
RAM corruption. See Memory on page 24 for more information about the different memory regions.
DMA supports Stereo (Left+Right 16-bit samples) and Mono (Left only) data transfer, depending on setting in
the OPERATION field in the MODE register. The samples are stored little endian.
Table 104: DMA sample storage
MODE.OPERATION
Bits per sample
Stereo
Mono
32 (2x16)
16
Result stored per RAM
word
L+R
2xL
Physical RAM allocated
(32 bit words)
ceil(SAMPLE.MAXCNT/2)
ceil(SAMPLE.MAXCNT/2)
Result boundary indexes
in RAM
R0=[31:16]; L0=[15:0]
L1=[31:16]; L0=[15:0]
Note
Default
The destination buffer in RAM consists of one block, the size of which is set in SAMPLE.MAXCNT register.
Format is number of 16-bit samples. The physical RAM allocated is always:
(RAM allocation, in bytes) = SAMPLE.MAXCNT * 2;
(but the mapping of the samples depends on MODE.OPERATION.
If OPERATION=Stereo, RAM will contain a succession of Left and Right samples.
If OPERATION=Mono, RAM will contain a succession of mono samples.
Page 441
43 PDM — Pulse density modulation interface
For a given value of SAMPLE.MAXCNT, the buffer in RAM can contain half the stereo sampling time as
compared to the mono sampling time.
The PDM acquisition can be started by the START task, after the SAMPLE.PTR and SAMPLE.MAXCNT
registers have been written. When starting the module, it will take some time for the filters to start outputting
valid data. Transients from the PDM microphone itself may also occur. The first few samples (typically
around 50) might hence contain invalid values or transients. It is therefore advised to discard the first few
samples after a PDM start.
As soon as the STARTED event is received, the firmware can write the next SAMPLE.PTR value (this
register is double-buffered), to ensure continuous operation.
When the buffer in RAM is filled with samples, an END event is triggered. The firmware can start processing
the data in the buffer. Meanwhile, the PDM module starts acquiring data into the new buffer pointed to by
SAMPLE.PTR, and sends a new STARTED event, so that the firmware can update SAMPLE.PTR to the
next buffer address.
43.5 Hardware example
Connect the microphone clock to CLK, and data to DIN.
Vdd
L/R
nRFxxxxx
CLK
CLK
DATA
DIN
CLK
DIN
Figure 127: Example of a single PDM microphone, wired as left
Vdd
L/R
nRFxxxxx
CLK
CLK
DATA
DIN
CLK
DIN
Figure 128: Example of a single PDM microphone, wired as right
Note that in a single-microphone (mono) configuration, depending on the microphone’s implementation,
either the left or the right channel (sampled at falling or rising CLK edge respectively) will contain reliable
data. If two microphones are used, one of them has to be set as left, the other as right (L/R pin tied high or
to GND on the respective microphone). It is strongly recommended to use two microphones of exactly the
same brand and type so that their timings in left and right operation match.
Vdd
L/R
nRFxxxxx
CLK
CLK
DATA
DIN
Vdd
CLK
L/R
DATA
CLK
DIN
Figure 129: Example of two PDM microphones
43.6 Pin configuration
The CLK and DIN signals associated to the PDM module are mapped to physical pins according to the
configuration specified in the PSEL.CLK and PSEL.DIN registers respectively. If the CONNECT field in
any PSEL register is set to Disconnected, the associated PDM module signal will not be connected to the
required physical pins, and will not operate properly.
Page 442
43 PDM — Pulse density modulation interface
The PSEL.CLK and PSEL.DIN registers and their configurations are only used as long as the PDM module
is enabled, and retained only as long as the device is in System ON mode. See POWER — Power supply on
page 81 for more information about power modes. When the peripheral is disabled, the pins will behave as
regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register.
To ensure correct behaviour in the PDM module, the pins used by the PDM module must be configured in
the GPIO peripheral as described in Table 105: GPIO configuration before enabling peripheral on page
443 before enabling the PDM module. This is to ensure that the pins used by the PDM module are driven
correctly if the PDM module itself is temporarily disabled or the device temporarily enters System OFF. This
configuration must be retained in the GPIO for the selected I/Os as long as the PDM module is supposed to
be connected to an external PDM circuit.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behaviour.
Table 105: GPIO configuration before enabling peripheral
PDM signal
CLK
DIN
PDM pin
As specified in PSEL.CLK
As specified in PSEL.DIN
Direction
Output
Input
Output value
0
Not applicable
Comment
43.7 Registers
Table 106: Instances
Base address
Peripheral
Instance
Description
0x4001D000
PDM
PDM
Pulse Density Modulation (Digital
Configuration
Microphone Interface)
Table 107: Register Overview
Register
Offset
Description
TASKS_START
0x000
Starts continuous PDM transfer
TASKS_STOP
0x004
Stops PDM transfer
EVENTS_STARTED
0x100
PDM transfer has started
EVENTS_STOPPED
0x104
PDM transfer has finished
EVENTS_END
0x108
The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ENABLE
0x500
PDM module enable register
PDMCLKCTRL
0x504
PDM clock generator control
MODE
0x508
Defines the routing of the connected PDM microphones' signals
GAINL
0x518
Left output gain adjustment
GAINR
0x51C
Right output gain adjustment
PSEL.CLK
0x540
Pin number configuration for PDM CLK signal
PSEL.DIN
0x544
Pin number configuration for PDM DIN signal
SAMPLE.PTR
0x560
RAM address pointer to write samples to with EasyDMA
SAMPLE.MAXCNT
0x564
Number of samples to allocate memory for in EasyDMA mode
task has been received) to Data RAM
43.7.1 INTEN
Address offset: 0x300
Enable or disable interrupt
Page 443
43 PDM — Pulse density modulation interface
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW STARTED
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for STARTED event
See EVENTS_STARTED
B
Disabled
0
Disable
Enabled
1
Enable
RW STOPPED
Enable or disable interrupt for STOPPED event
See EVENTS_STOPPED
C
Disabled
0
Disable
Enabled
1
Enable
RW END
Enable or disable interrupt for END event
See EVENTS_END
Disabled
0
Disable
Enabled
1
Enable
43.7.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW STARTED
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for STARTED event
See EVENTS_STARTED
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW END
Write '1' to Enable interrupt for END event
See EVENTS_END
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
43.7.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW STARTED
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for STARTED event
See EVENTS_STARTED
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Disable interrupt for STOPPED event
Page 444
43 PDM — Pulse density modulation interface
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_STOPPED
C
RW END
Write '1' to Disable interrupt for END event
See EVENTS_END
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
43.7.4 ENABLE
Address offset: 0x500
PDM module enable register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Enable or disable PDM module
43.7.5 PDMCLKCTRL
Address offset: 0x504
PDM clock generator control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x08400000
Id
RW Field
A
RW FREQ
0
0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
1000K
0x08000000
PDM_CLK = 32 MHz / 32 = 1.000 MHz
Default
0x08400000
PDM_CLK = 32 MHz / 31 = 1.032 MHz
1067K
0x08800000
PDM_CLK = 32 MHz / 30 = 1.067 MHz
PDM_CLK frequency
43.7.6 MODE
Address offset: 0x508
Defines the routing of the connected PDM microphones' signals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B A
Reset 0x00000000
Id
RW Field
A
RW OPERATION
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Stereo
0
Mono
1
Description
Mono or stereo operation
Sample and store one pair (Left + Right) of 16bit samples per
RAM word R=[31:16]; L=[15:0]
Sample and store two successive Left samples (16 bit each) per
RAM word L1=[31:16]; L0=[15:0]
B
RW EDGE
Defines on which PDM_CLK edge Left (or mono) is sampled
LeftFalling
0
Left (or mono) is sampled on falling edge of PDM_CLK
LeftRising
1
Left (or mono) is sampled on rising edge of PDM_CLK
Page 445
43 PDM — Pulse density modulation interface
43.7.7 GAINL
Address offset: 0x518
Left output gain adjustment
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A
Reset 0x00000028
Id
RW Field
A
RW GAINL
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
Value
Description
Left output gain adjustment, in 0.5 dB steps, around the default
module gain (see electrical parameters)
0x00 -20 dB gain adjust
0x01 -19.5 dB gain adjust
(...)
0x27 -0.5 dB gain adjust
0x28 0 dB gain adjust
0x29 +0.5 dB gain adjust
(...)
0x4F +19.5 dB gain adjust
0x50 +20 dB gain adjust
MinGain
0x00
-20dB gain adjustment (minimum)
DefaultGain
0x28
0dB gain adjustment ('2500 RMS' requirement)
MaxGain
0x50
+20dB gain adjustment (maximum)
43.7.8 GAINR
Address offset: 0x51C
Right output gain adjustment
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000028
Id
RW Field
A
RW GAINR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
Value
Description
Right output gain adjustment, in 0.5 dB steps, around the
default module gain (see electrical parameters)
MinGain
0x00
-20dB gain adjustment (minimum)
DefaultGain
0x28
0dB gain adjustment ('2500 RMS' requirement)
MaxGain
0x50
+20dB gain adjustment (maximum)
43.7.9 PSEL.CLK
Address offset: 0x540
Pin number configuration for PDM CLK signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
43.7.10 PSEL.DIN
Address offset: 0x544
Page 446
43 PDM — Pulse density modulation interface
Pin number configuration for PDM DIN signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
B
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
43.7.11 SAMPLE.PTR
Address offset: 0x560
RAM address pointer to write samples to with EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0
Id
RW Field
Value Id
A
RW SAMPLEPTR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Address to write PDM samples to over DMA
43.7.12 SAMPLE.MAXCNT
Address offset: 0x564
Number of samples to allocate memory for in EasyDMA mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW BUFFSIZE
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
[0..32767]
Length of DMA RAM allocation in number of samples
43.8 Electrical specification
43.8.1 PDM Electrical Specification
Symbol
Description
IPDM,stereo
PDM module active current, stereo operation37
Min.
Typ.
1.4
fPDM,CLK
PDM clock speed
1.032
tPDM,JITTER
Jitter in PDM clock output
TdPDM,CLK
PDM clock duty cycle
tPDM,DATA
Max.
Units
mA
MHz
20
ns
60
%
Decimation filter delay
5
ms
tPDM,cv
Allowed clock edge to data valid
125
ns
tPDM,ci
Allowed (other) clock edge to data invalid
0
ns
tPDM,s
Data setup time at fPDM,CLK=1.024 MHz
65
ns
tPDM,h
Data hold time at fPDM,CLK=1.024 MHz
0
GPDM,default
Default (reset) absolute gain of the PDM module
37
40
50
ns
3.2
Average current including PDM and DMA transfers, excluding clock and power supply base currents
Page 447
dB
43 PDM — Pulse density modulation interface
tPDM,CLK
CLK
tPDM,cv
tPDM,s
DIN (L)
tPDM,cv
tPDM,s tPDM,h=tPDM,ci
DIN(R)
Figure 130: PDM timing diagram
Page 448
tPDM,h=tPDM,ci
2
44 I S — Inter-IC sound interface
2
44 I S — Inter-IC sound interface
2
2
The I S (Inter-IC Sound) module, supports the original two-channel I S format, and left or right-aligned
formats. It implements EasyDMA for sample transfer directly to and from RAM without CPU intervention.
2
The I S peripheral has the following main features:
•
•
•
•
•
•
Master and Slave mode
Simultaneous bi-directional (TX and RX) audio streaming
2
Original I S and left- or right-aligned format
8, 16 and 24-bit sample width
Low-jitter Master Clock generator
Various sample rates
PSEL.MCK
PSEL.LRCK
PSEL.SCK
PSEL.SDIN PSEL.SDOUT
I2S
CONFIG.MCKEN
Master clock
generator
MCK
CONFIG.MCKFREQ
CONFIG.RATIO
Div
CONFIG.FORMAT
Div
CONFIG.MODE
Serial tranceiever
TXD.PTR
RXD.PTR
RXTXD.MAXCNT
EasyDMA
SDOUT
SDIN
SCK
LRCK
CONFIG.ALIGN
RAM
2
Figure 131: I S master
44.1 Mode
2
The I S protocol specification defines two modes of operation, Master and Slave.
2
The I S mode decides which of the two sides (Master or Slave) shall provide the clock signals LRCK and
SCK, and these signals are always supplied by the Master to the Slave.
44.2 Transmitting and receiving
2
The I S module supports both transmission (TX) and reception (RX) of serial data. In both cases the serial
data is shifted synchronously to the clock signals SCK and LRCK.
Page 449
2
44 I S — Inter-IC sound interface
TX data is written to the SDOUT pin on the falling edge of SCK, and RX data is read from the SDIN pin on
the rising edge of SCK. The most significant bit (MSB) is always transmitted first.
TX and RX are available in both Master and Slave modes and can be enabled/disabled independently in the
CONFIG.TXEN on page 459 and CONFIG.RXEN on page 459.
Transmission and/or reception is started by triggering the START task. When started and transmission
is enabled (in CONFIG.TXEN on page 459), the TXPTRUPD event will be generated for every
RXTXD.MAXCNT on page 462 number of transmitted data words (containing one or more samples).
Similarly, when started and reception is enabled (in CONFIG.RXEN on page 459), the RXPTRUPD event
will be generated for every RXTXD.MAXCNT on page 462 received data words.
RXTXD.MAXCNT
Left 0
Right 0
Left 1
RIght 1
Left 2
Right 2
Left 3
A
A
A
A
C
C
C
Right 3
C
Left 4
E
B
B
B
B
D
D
D
D
F
RXPTRUPD
TXPTRUPD
RXPTRUPD
RXPTRUPD
TXPTRUPD
RXD.PTR = H
TXD.PTR = G
RXD.PTR = F
TXD.PTR = E
TXD.PTR = C
RXD.PTR = D
START
TXD.PTR = A
RXD.PTR = B
CPU
TXPTRUPD
LRCK
SCK
SDIN
SDOUT
RXTXD.MAXCNT
Figure 132: Transmitting and receiving. CONFIG.FORMAT = Aligned, CONFIG.SWIDTH = 8Bit,
CONFIG.CHANNELS = Stereo, RXTXD.MAXCNT = 1.
44.3 Left right clock (LRCK)
2
The Left Right Clock (LRCK), often referred to as "word clock", "sample clock" or "word select" in I S
context, is the clock defining the frames in the serial bit streams sent and received on SDOUT and SDIN,
respectively.
In I2S mode, each frame contains one left and right sample pair, with the left sample being transferred during
the low half period of LRCK followed by the right sample being transferred during the high period of LRCK.
In Aligned mode, each frame contains one left and right sample pair, with the left sample being transferred
during the high half period of LRCK followed by the right sample being transferred during the low period of
LRCK.
Consequently, the LRCK frequency is equivalent to the audio sample rate.
When operating in Master mode, the LRCK is generated from the MCK, and the frequency of LRCK is then
given as:
LRCK = MCK / CONFIG.RATIO
LRCK always toggles around the falling edge of the serial clock SCK.
44.4 Serial clock (SCK)
The serial clock (SCK), often referred to as the serial bit clock, pulses once for each data bit being
transferred on the serial data lines SDIN and SDOUT.
Page 450
2
44 I S — Inter-IC sound interface
When operating in Master mode the SCK is generated from the MCK, and the frequency of SCK is then
given as:
SCK = 2 * LRCK * CONFIG.SWIDTH
The falling edge of the SCK falls on the toggling edge of LRCK.
2
When operating in Slave mode SCK is provided by the external I S master.
44.5 Master clock (MCK)
The master clock (MCK) is the clock from which LRCK and SCK are derived when operating in Master mode.
The MCK is generated by an internal MCK generator. This generator always needs to be enabled when in
Master mode, but the generator can also be enabled when in Slave mode. Enabling the generator when in
slave mode can be useful in the case where the external Master is not able to generate its own master clock.
The MCK generator is enabled/disabled in the register CONFIG.MCKEN on page 460, and the generator
is started or stopped by the START or STOP tasks.
In Master mode the LRCK and the SCK frequencies are closely related, as both are derived from MCK and
set indirectly through CONFIG.RATIO on page 460 and CONFIG.SWIDTH on page 461.
When configuring these registers, the user is responsible for fulfilling the following requirements:
1. SCK frequency can never exceed the MCK frequency, which can be formulated as:
CONFIG.RATIO >= 2 * CONFIG.SWIDTH
2. The MCK/LRCK ratio shall be a multiple of 2 * CONFIG.SWIDTH, which can be formulated as:
Integer = (CONFIG.RATIO / (2 * CONFIG.SWIDTH))
2
The MCK signal can be routed to an output pin (specified in PSEL.MCK) to supply external I S devices that
require the MCK to be supplied from the outside.
2
When operating in Slave mode, the I S module does not use the MCK and the MCK generator does not
need to be enabled.
RATIO =
MCK
LRCK
MCK
LRCK
SWIDTH
SCK
Figure 133: Relation between RATIO, MCK and LRCK.
Table 108: Configuration examples
Desired LRCK [Hz]
16000
16000
16000
32000
32000
32000
44100
44100
44100
CONFIG.SWIDTH
16Bit
16Bit
16Bit
16Bit
16Bit
16Bit
16Bit
16Bit
16Bit
CONFIG.RATIO
32X
64X
256X
32X
64X
256X
32X
64X
256X
CONFIG.MCKFREQ
32MDIV63
32MDIV31
32MDIV8
32MDIV31
32MDIV16
32MDIV4
32MDIV23
32MDIV11
32MDIV3
MCK [Hz]
507936.5
1032258.1
4000000.0
1032258.1
2000000.0
8000000.0
1391304.3
2909090.9
10666666.7
LRCK [Hz]
15873.0
16129.0
15625.0
32258.1
31250.0
31250.0
43478.3
45454.5
41666.7
LRCK error [%]
-0.8
0.8
-2.3
0.8
-2.3
-2.3
-1.4
3.1
-5.5
44.6 Width, alignment and format
The CONFIG.SWIDTH register primarily defines the sample width of the data written to memory. In master
mode, it then also sets the amount of bits per frame. In Slave mode it controls padding/trimming if required.
Left, right, transmitted, and received samples always have the same width. The CONFIG.FORMAT register
specifies the position of the data frames with respect to the LRCK edges in both Master and Slave modes.
Page 451
2
44 I S — Inter-IC sound interface
2
When using I S format, the first bit in a half-frame (containing one left or right sample) gets sampled on the
second rising edge of the SCK after a LRCK edge. When using Aligned mode, the first bit in a half-frame
gets sampled on the first rising edge of SCK following a LRCK edge.
For data being received on SDIN the sample value can be either right or left-aligned inside a half-frame, as
specified in CONFIG.ALIGN on page 461. CONFIG.ALIGN on page 461 affects only the decoding of
the incoming samples (SDIN), while the outgoing samples (SDOUT) are always left-aligned (or justified).
When using left-alignment, each half-frame starts with the MSB of the sample value (both for data being sent
on SDOUT and received on SDIN).
When using right-alignment, each half-frame of data being received on SDIN ends with the LSB of the
sample value, while each half-frame of data being sent on SDOUT starts with the MSB of the sample value
(same as for left-alignment).
In Master mode, the size of a half-frame (in number of SCK periods) equals the sample width (in number of
bits), and in this case the alignment setting does not care as each half-frame in any case will start with the
MSB and end with the LSB of the sample value.
In slave mode, however, the sample width does not need to equal the frame size. This means you might
have extra or fewer SCK pulses per half-frame than what the sample width specified in CONFIG.SWIDTH
requires.
In the case where we use left-alignment and the number of SCK pulses per half-frame is higher than the
sample width, the following will apply:
•
•
For data received on SDIN, all bits after the LSB of the sample value will be discarded.
For data sent on SDOUT, all bits after the LSB of the sample value will be 0.
In the case where we use left-alignment and the number of SCK pulses per frame is lower than the sample
width, the following will apply:
•
Data sent and received on SDOUT and SDIN will be truncated with the LSBs being removed first.
In the case where we use right-alignment and the number of SCK pulses per frame is higher than the
sample width, the following will apply:
•
•
For data received on SDIN, all bits before the MSB of the sample value will be discarded.
For data sent on SDOUT, all bits after the LSB of the sample value will be 0 (same behavior as for leftalignment).
In the case where we use right-alignment and the number of SCK pulses per frame is lower than the
sample width, the following will apply:
•
•
Data received on SDIN will be sign-extended to "sample width" number of bits before being written to
memory.
Data sent on SDOUT will be truncated with the LSBs being removed first (same behavior as for leftalignment).
frame
left
LRCK
right
left
SCK
SDIN or SDOUT
2
Figure 134: I S format. CONFIG.SWIDTH equalling half-frame size.
frame
LRCK
left
right
SCK
SDATA
Figure 135: Aligned format. CONFIG.SWIDTH equalling half-frame size.
Page 452
left
2
44 I S — Inter-IC sound interface
44.7 EasyDMA
2
The I S module implements EasyDMA for accessing internal Data RAM without CPU intervention.
The source and destination pointers for the TX and RX data are configured in TXD.PTR on page 462 and
RXD.PTR on page 462. The memory pointed to by these pointers will only be read or written when TX or
RX are enabled in CONFIG.TXEN on page 459 and CONFIG.RXEN on page 459.
The addresses written to the pointer registers TXD.PTR on page 462 and RXD.PTR on page 462 are
double-buffered in hardware, and these double buffers are updated for every RXTXD.MAXCNT on page
462 words (containing one or more samples) read/written from/to memory. The events TXPTRUPD and
RXPTRUPD are generated whenever the TXD.PTR and RXD.PTR are transferred to these double buffers.
If TXD.PTR on page 462 is not pointing to the Data RAM region when transmission is enabled, or
RXD.PTR on page 462 is not pointing to the Data RAM region when reception is enabled, an EasyDMA
transfer may result in a HardFault and/or memory corruption. See Memory on page 24 for more information
about the different memory regions.
2
Due to the nature of I S, where the number of transmitted samples always equals the number of received
samples (at least when both TX and RX are enabled), one common register RXTXD.MAXCNT on page
462 is used for specifying the sizes of these two memory buffers. The size of the buffers is specified in
a number of 32-bit words. Such a 32-bit memory word can either contain four 8-bit samples, two 16-bit
samples or one right-aligned 24-bit sample sign extended to 32 bit.
In stereo mode (CONFIG.CHANNELS=Stereo), the samples are stored as "left and right sample
pairs" in memory. Figure Figure 136: Memory mapping for 8 bit stereo. CONFIG.SWIDTH = 8Bit,
CONFIG.CHANNELS = Stereo. on page 453, Figure 138: Memory mapping for 16 bit stereo.
CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Stereo. on page 454 and Figure 140: Memory
mapping for 24 bit stereo. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Stereo. on page 454 show
how the samples are mapped to memory in this mode. The mapping is valid for both RX and TX.
In mono mode (CONFIG.CHANNELS=Left or Right), RX sample from only one channel in the frame is
stored in memory, the other channel sample is ignored. Illustrations Figure 137: Memory mapping for 8
bit mono. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Left. on page 454, Figure 139: Memory
mapping for 16 bit mono, left channel only. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Left. on
page 454 and Figure 141: Memory mapping for 24 bit mono, left channel only. CONFIG.SWIDTH = 24Bit,
CONFIG.CHANNELS = Left. on page 455 show how RX samples are mapped to memory in this mode.
For TX, the same outgoing sample read from memory is transmitted on both left and right in a frame,
resulting in a mono output stream.
31
24 23
16 15
8 7
0
x.PTR
Right sample 1
Left sample 1
Right sample 0
Left sample 0
x.PTR + 4
Right sample 3
Left sample 3
Right sample 2
Left sample 2
Left sample
n-1
Right sample
n-1
Right sample
n-2
Left sample
n-2
x.PTR + (n*2) - 4
Figure 136: Memory mapping for 8 bit stereo. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo.
Page 453
2
44 I S — Inter-IC sound interface
31
24 23
16 15
8 7
0
x.PTR
Left sample 3
Left sample 2
Left sample 1
Left sample 0
x.PTR + 4
Left sample 7
Left sample 6
Left sample 5
Left sample 4
Left sample
n-1
Left sample
n-2
Left sample
n-3
Left sample
n-4
x.PTR + n - 4
Figure 137: Memory mapping for 8 bit mono. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Left.
31
16 15
0
x.PTR
Right sample 0
Left sample 0
x.PTR + 4
Right sample 1
Left sample 1
Right sample n - 1
Left sample n - 1
x.PTR + (n*4) - 4
Figure 138: Memory mapping for 16 bit stereo. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS =
Stereo.
31
16 15
0
x.PTR
Left sample 1
Left sample 0
x.PTR + 4
Left sample 3
Left sample 2
Left sample n - 1
Left sample n - 2
x.PTR + (n*2) - 4
Figure 139: Memory mapping for 16 bit mono, left channel only. CONFIG.SWIDTH = 16Bit,
CONFIG.CHANNELS = Left.
31
23
0
x.PTR
Sign ext.
Left sample 0
x.PTR + 4
Sign ext.
Right sample 0
x.PTR + (n*8) - 8
Sign ext.
Left sample n - 1
x.PTR + (n*8) - 4
Sign ext.
Right sample n - 1
Figure 140: Memory mapping for 24 bit stereo. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS =
Stereo.
Page 454
2
44 I S — Inter-IC sound interface
31
23
0
x.PTR
Sign ext.
Left sample 0
x.PTR + 4
Sign ext.
Left sample 1
x.PTR + (n*4) - 4
Sign ext.
Left sample n - 1
Figure 141: Memory mapping for 24 bit mono, left channel only. CONFIG.SWIDTH = 24Bit,
CONFIG.CHANNELS = Left.
44.8 Module operation
2
Described here is a typical operating procedure for the I S module.
2
1. Configure the I S module using the CONFIG registers
// Enable reception
NRF_I2S->CONFIG.RXEN = (I2S_CONFIG_RXEN_RXEN_Enabled CONFIG.TXEN = (I2S_CONFIG_TXEN_TXEN_Enabled CONFIG.MCKEN = (I2S_CONFIG_MCKEN_MCKEN_Enabled CONFIG.MCKFREQ = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 CONFIG.RATIO = I2S_CONFIG_RATIO_RATIO_256X CONFIG.SWIDTH = I2S_CONFIG_SWIDTH_SWIDTH_16Bit CONFIG.ALIGN = I2S_CONFIG_ALIGN_ALIGN_Left CONFIG.FORMAT = I2S_CONFIG_FORMAT_FORMAT_I2S CONFIG.CHANNELS = I2S_CONFIG_CHANNELS_CHANNELS_Stereo PSEL.MCK = (0 EVENTS_TXPTRUPD != 0)
{
NRF_I2S->TXD.PTR = my_next_tx_buf;
NRF_I2S->EVENTS_TXPTRUPD = 0;
}
if(NRF_I2S->EVENTS_RXPTRUPD != 0)
{
NRF_I2S->RXD.PTR = my_next_rx_buf;
NRF_I2S->EVENTS_RXPTRUPD = 0;
}
44.9 Pin configuration
2
The MCK, SCK, LRCK, SDIN and SDOUT signals associated with the I S module are mapped to physical
pins according to the pin numbers specified in the PSEL.x registers.
2
These pins are acquired whenever the I S module is enabled through the register ENABLE on page 459.
2
When a pin is acquired by the I S module, the direction of the pin (input or output) will be configured
automatically, and any pin direction setting done in the GPIO module will be overridden. The directions for
2
the various I S pins are shown below in Table 109: GPIO configuration before enabling peripheral (master
mode) on page 456 and Table 110: GPIO configuration before enabling peripheral (slave mode) on page
457.
2
To secure correct signal levels on the pins when the system is in OFF mode, and when the I S module is
disabled, these pins must be configured in the GPIO peripheral directly.
Table 109: GPIO configuration before enabling peripheral (master mode)
I2S signal
MCK
LRCK
I2S pin
As specified in PSEL.MCK
As specified in PSEL.LRCK
Direction
Output
Output
Page 456
Output value
0
0
Comment
2
44 I S — Inter-IC sound interface
I2S signal
SCK
SDIN
SDOUT
I2S pin
As specified in PSEL.SCK
As specified in PSEL.SDIN
As specified in PSEL.SDOUT
Direction
Output
Input
Output
Output value
0
Not applicable
0
Comment
Table 110: GPIO configuration before enabling peripheral (slave mode)
I2S signal
MCK
LRCK
SCK
SDIN
SDOUT
I2S pin
As specified in PSEL.MCK
As specified in PSEL.LRCK
As specified in PSEL.SCK
As specified in PSEL.SDIN
As specified in PSEL.SDOUT
Direction
Output
Input
Input
Input
Output
Output value
0
Not applicable
Not applicable
Not applicable
0
Comment
44.10 Registers
Table 111: Instances
Base address
Peripheral
Instance
Description
0x40025000
I2S
I2S
Inter-IC Sound Interface
Configuration
Table 112: Register Overview
Register
Offset
Description
TASKS_START
0x000
Starts continuous I2S transfer. Also starts MCK generator when this is enabled.
TASKS_STOP
0x004
Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED}
EVENTS_RXPTRUPD
0x104
event to be generated.
The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started
and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on
the SDIN pin.
EVENTS_STOPPED
0x108
I2S transfer stopped.
EVENTS_TXPTRUPD
0x114
The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started
and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the
SDOUT pin.
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ENABLE
0x500
Enable I2S module.
CONFIG.MODE
0x504
I2S mode.
CONFIG.RXEN
0x508
Reception (RX) enable.
CONFIG.TXEN
0x50C
Transmission (TX) enable.
CONFIG.MCKEN
0x510
Master clock generator enable.
CONFIG.MCKFREQ
0x514
Master clock generator frequency.
CONFIG.RATIO
0x518
MCK / LRCK ratio.
CONFIG.SWIDTH
0x51C
Sample width.
CONFIG.ALIGN
0x520
Alignment of sample within a frame.
CONFIG.FORMAT
0x524
Frame format.
CONFIG.CHANNELS
0x528
Enable channels.
RXD.PTR
0x538
Receive buffer RAM start address.
TXD.PTR
0x540
Transmit buffer RAM start address.
RXTXD.MAXCNT
0x550
Size of RXD and TXD buffers.
PSEL.MCK
0x560
Pin select for MCK signal.
PSEL.SCK
0x564
Pin select for SCK signal.
PSEL.LRCK
0x568
Pin select for LRCK signal.
PSEL.SDIN
0x56C
Pin select for SDIN signal.
PSEL.SDOUT
0x570
Pin select for SDOUT signal.
44.10.1 INTEN
Address offset: 0x300
Enable or disable interrupt
Page 457
2
44 I S — Inter-IC sound interface
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F
Reset 0x00000000
Id
RW Field
B
RW RXPTRUPD
0
Value Id
C B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for RXPTRUPD event
See EVENTS_RXPTRUPD
C
Disabled
0
Disable
Enabled
1
Enable
RW STOPPED
Enable or disable interrupt for STOPPED event
See EVENTS_STOPPED
F
Disabled
0
Disable
Enabled
1
Enable
RW TXPTRUPD
Enable or disable interrupt for TXPTRUPD event
See EVENTS_TXPTRUPD
Disabled
0
Disable
Enabled
1
Enable
44.10.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F
Reset 0x00000000
Id
RW Field
B
RW RXPTRUPD
0
Value Id
C B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for RXPTRUPD event
See EVENTS_RXPTRUPD
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TXPTRUPD
Write '1' to Enable interrupt for TXPTRUPD event
See EVENTS_TXPTRUPD
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
44.10.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F
Reset 0x00000000
Id
RW Field
B
RW RXPTRUPD
0
Value Id
Value
Description
Write '1' to Disable interrupt for RXPTRUPD event
See EVENTS_RXPTRUPD
C
C B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to Disable interrupt for STOPPED event
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44 I S — Inter-IC sound interface
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
F
Reset 0x00000000
Id
RW Field
0
C B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_STOPPED
F
RW TXPTRUPD
Write '1' to Disable interrupt for TXPTRUPD event
See EVENTS_TXPTRUPD
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
44.10.4 ENABLE
Address offset: 0x500
Enable I2S module.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Enable I2S module.
44.10.5 CONFIG.MODE
Address offset: 0x504
I2S mode.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW MODE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Master
0
Slave
1
Description
I2S mode.
Master mode. SCK and LRCK generated from internal master
clcok (MCK) and output on pins defined by PSEL.xxx.
Slave mode. SCK and LRCK generated by external master and
received on pins defined by PSEL.xxx
44.10.6 CONFIG.RXEN
Address offset: 0x508
Reception (RX) enable.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW RXEN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Disabled
0
Enabled
1
Description
Reception (RX) enable.
Reception disabled and now data will be written to the RXD.PTR
address.
Reception enabled.
44.10.7 CONFIG.TXEN
Address offset: 0x50C
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44 I S — Inter-IC sound interface
Transmission (TX) enable.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000001
Id
RW Field
A
RW TXEN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Disabled
0
Enabled
1
Description
Transmission (TX) enable.
Transmission disabled and now data will be read from the
RXD.TXD address.
Transmission enabled.
44.10.8 CONFIG.MCKEN
Address offset: 0x510
Master clock generator enable.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000001
Id
RW Field
A
RW MCKEN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Disabled
0
Enabled
1
Description
Master clock generator enable.
Master clock generator disabled and PSEL.MCK not
connected(available as GPIO).
Master clock generator running and MCK output on PSEL.MCK.
44.10.9 CONFIG.MCKFREQ
Address offset: 0x514
Master clock generator frequency.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x20000000
Id
RW Field
A
RW MCKFREQ
0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
32MDIV2
0x80000000
32 MHz / 2 = 16.0 MHz
32MDIV3
0x50000000
32 MHz / 3 = 10.6666667 MHz
32MDIV4
0x40000000
32 MHz / 4 = 8.0 MHz
32MDIV5
0x30000000
32 MHz / 5 = 6.4 MHz
32MDIV6
0x28000000
32 MHz / 6 = 5.3333333 MHz
32MDIV8
0x20000000
32 MHz / 8 = 4.0 MHz
32MDIV10
0x18000000
32 MHz / 10 = 3.2 MHz
32MDIV11
0x16000000
32 MHz / 11 = 2.9090909 MHz
32MDIV15
0x11000000
32 MHz / 15 = 2.1333333 MHz
32MDIV16
0x10000000
32 MHz / 16 = 2.0 MHz
32MDIV21
0x0C000000
32 MHz / 21 = 1.5238095
32MDIV23
0x0B000000
32 MHz / 23 = 1.3913043 MHz
32MDIV30
0x08800000
32 MHz / 30 = 1.0666667 MHz
32MDIV31
0x08400000
32 MHz / 31 = 1.0322581 MHz
32MDIV32
0x08000000
32 MHz / 32 = 1.0 MHz
32MDIV42
0x06000000
32 MHz / 42 = 0.7619048 MHz
32MDIV63
0x04100000
32 MHz / 63 = 0.5079365 MHz
32MDIV125
0x020C0000
32 MHz / 125 = 0.256 MHz
Master clock generator frequency.
44.10.10 CONFIG.RATIO
Address offset: 0x518
MCK / LRCK ratio.
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44 I S — Inter-IC sound interface
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000006
Id
RW Field
A
RW RATIO
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
Value Id
Value
Description
32X
0
LRCK = MCK / 32
48X
1
LRCK = MCK / 48
64X
2
LRCK = MCK / 64
96X
3
LRCK = MCK / 96
128X
4
LRCK = MCK / 128
192X
5
LRCK = MCK / 192
256X
6
LRCK = MCK / 256
384X
7
LRCK = MCK / 384
512X
8
LRCK = MCK / 512
MCK / LRCK ratio.
44.10.11 CONFIG.SWIDTH
Address offset: 0x51C
Sample width.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000001
Id
RW Field
A
RW SWIDTH
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value Id
Value
Description
8Bit
0
8 bit.
16Bit
1
16 bit.
24Bit
2
24 bit.
Sample width.
44.10.12 CONFIG.ALIGN
Address offset: 0x520
Alignment of sample within a frame.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ALIGN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Left
0
Left-aligned.
Right
1
Right-aligned.
Alignment of sample within a frame.
44.10.13 CONFIG.FORMAT
Address offset: 0x524
Frame format.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW FORMAT
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
I2S
0
Original I2S format.
Aligned
1
Alternate (left- or right-aligned) format.
Frame format.
44.10.14 CONFIG.CHANNELS
Address offset: 0x528
Enable channels.
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44 I S — Inter-IC sound interface
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A
Reset 0x00000000
Id
RW Field
A
RW CHANNELS
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Stereo
0
Stereo.
Left
1
Left only.
Right
2
Right only.
Enable channels.
44.10.15 RXD.PTR
Address offset: 0x538
Receive buffer RAM start address.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Receive buffer Data RAM start address. When receiving, words
containing samples will be written to this address. This address
is a word aligned Data RAM address.
44.10.16 TXD.PTR
Address offset: 0x540
Transmit buffer RAM start address.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Transmit buffer Data RAM start address. When transmitting,
words containing samples will be fetched from this address. This
address is a word aligned Data RAM address.
44.10.17 RXTXD.MAXCNT
Address offset: 0x550
Size of RXD and TXD buffers.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW MAXCNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Size of RXD and TXD buffers in number of 32 bit words.
44.10.18 PSEL.MCK
Address offset: 0x560
Pin select for MCK signal.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
C
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
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44 I S — Inter-IC sound interface
44.10.19 PSEL.SCK
Address offset: 0x564
Pin select for SCK signal.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
C
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
44.10.20 PSEL.LRCK
Address offset: 0x568
Pin select for LRCK signal.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
C
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
44.10.21 PSEL.SDIN
Address offset: 0x56C
Pin select for SDIN signal.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
C
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
44.10.22 PSEL.SDOUT
Address offset: 0x570
Pin select for SDOUT signal.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
C
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
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44 I S — Inter-IC sound interface
44.11 Electrical specification
44.11.1 I2S timing specification
Symbol
Description
Min.
tS_SDIN
SDIN setup time before SCK rising
20
Typ.
Max.
Units
ns
tH_SDIN
SDIN hold time after SCK rising
15
ns
tS_SDOUT
SDOUT setup time after SCK falling
40
ns
tH_SDOUT
SDOUT hold time before SCK falling
6
tSCK_LRCK
SCLK falling to LRCK edge
-5
fMCK
ns
0
5
ns
MCK frequency
4000
kHz
fLRCK
LRCK frequency
48
kHz
fSCK
SCK frequency
2000
kHz
DCCK
Clock duty cycle (MCK, LRCK, SCK)
55
%
45
tSCK_LRCK
LRCK
SCK
tS_SDIN
tH_SDIN
SDIN
tH_SDOUT
SDOUT
Figure 142: I2S timing diagram
Page 464
tS_SDOUT
45 MWU — Memory watch unit
45 MWU — Memory watch unit
The Memory watch unit (MWU) can be used to generate events when a memory region is accessed
by the CPU. The MWU can be configured to trigger events for access to Data RAM and Peripheral
memory segments. The MWU allows an application developer to generate memory access events during
development for debugging or during production execution for failure detection and recovery.
Listed here are the main features for MWU:
•
•
•
•
•
Six memory regions, four user-configurable and two fixed regions in peripheral address space
Flexible configuration of regions with START and END addresses
Generate events on CPU read and/or write to a defined region of Data RAM or peripheral memory
address space
Programmable maskable or non-maskable (NMI) interrupt on events
Peripheral interfaces can be watched for read and write access using subregions of the two fixed memory
regions
Table 113: Memory regions
Memory region
REGION[0..3]
PREGION[0]
PREGION[1]
START address
Configurable
0x40000000
0x40020000
END address
Configurable
0x4001FFFF
0x4003FFFF
Each MWU region is defined by a start address and an end address, configured by the START and END
registers respectively. These addresses are byte aligned and inclusive. The END register value has to be
greater or equal to the START register value. Each region is associated with a pair of events that indicate
that either a write access or a read access from the CPU has been detected inside the region.
For regions containing subregions (see below), a set of status registers PERREGION[0..1].SUBSTATWA
and PERREGION[0..1].SUBSTATRA indicate which subregion(s) caused the EVENT_PREGION[0..1].WA
and EVENT_PREGION[0..1].RA respectively.
The MWU is only able to detect memory accesses in the Data RAM and Peripheral memory segments from
the CPU, see Memory on page 24 for more information about the different memory segments. EasyDMA
accesses are not monitored by the MWU. The MWU requires two HCLK cycles to detect and generate the
event.
The peripheral regions, PREGION[0...1], are divided into 32 equally sized subregions, SR[0...31]. All
subregions are excluded in the main region by default, and any can be included by specifying them in the
SUBS register. When a subregion is excluded from the main region, the memory watch mechanism will not
trigger any events when that subregion is accessed.
Subregions in PREGION[0..1] cannot be individually configured for read or write access watch. Watch
configuration is only possible for a region as a whole. The PRGNiRA and PRGNiWA (i=0..1) fields in the
REGIONEN register control watching read and write access.
REGION[0..3] can be individually enabled for read and/or write access watching through their respective
RGNiRA and RGNiWA (i=0..3) fields in the REGIONEN register.
REGIONENSET and REGIONENCLR allow respectively enabling and disabling one or multiple REGIONs or
PREGIONs watching in a single write access.
45.1 Registers
Table 114: Instances
Base address
Peripheral
Instance
Description
0x40020000
MWU
MWU
Memory Watch Unit
Page 465
Configuration
45 MWU — Memory watch unit
Table 115: Register Overview
Register
Offset
Description
EVENTS_REGION[0].WA 0x100
Write access to region 0 detected
EVENTS_REGION[0].RA 0x104
Read access to region 0 detected
EVENTS_REGION[1].WA 0x108
Write access to region 1 detected
EVENTS_REGION[1].RA 0x10C
Read access to region 1 detected
EVENTS_REGION[2].WA 0x110
Write access to region 2 detected
EVENTS_REGION[2].RA 0x114
Read access to region 2 detected
EVENTS_REGION[3].WA 0x118
Write access to region 3 detected
EVENTS_REGION[3].RA 0x11C
Read access to region 3 detected
EVENTS_PREGION[0].WA 0x160
Write access to peripheral region 0 detected
EVENTS_PREGION[0].RA 0x164
Read access to peripheral region 0 detected
EVENTS_PREGION[1].WA 0x168
Write access to peripheral region 1 detected
EVENTS_PREGION[1].RA 0x16C
Read access to peripheral region 1 detected
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
NMIEN
0x320
Enable or disable non-maskable interrupt
NMIENSET
0x324
Enable non-maskable interrupt
NMIENCLR
0x328
Disable non-maskable interrupt
PERREGION[0].SUBSTATWA
0x400
Source of event/interrupt in region 0, write access detected while corresponding subregion was
enabled for watching
PERREGION[0].SUBSTATRA
0x404
Source of event/interrupt in region 0, read access detected while corresponding subregion was
enabled for watching
PERREGION[1].SUBSTATWA
0x408
Source of event/interrupt in region 1, write access detected while corresponding subregion was
enabled for watching
PERREGION[1].SUBSTATRA
0x40C
Source of event/interrupt in region 1, read access detected while corresponding subregion was
enabled for watching
REGIONEN
0x510
Enable/disable regions watch
REGIONENSET
0x514
Enable regions watch
REGIONENCLR
0x518
Disable regions watch
REGION[0].START
0x600
Start address for region 0
REGION[0].END
0x604
End address of region 0
REGION[1].START
0x610
Start address for region 1
REGION[1].END
0x614
End address of region 1
REGION[2].START
0x620
Start address for region 2
REGION[2].END
0x624
End address of region 2
REGION[3].START
0x630
Start address for region 3
REGION[3].END
0x634
End address of region 3
PREGION[0].START
0x6C0
Reserved for future use
PREGION[0].END
0x6C4
Reserved for future use
PREGION[0].SUBS
0x6C8
Subregions of region 0
PREGION[1].START
0x6D0
Reserved for future use
PREGION[1].END
0x6D4
Reserved for future use
PREGION[1].SUBS
0x6D8
Subregions of region 1
45.1.1 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW REGION0WA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for REGION[0].WA event
See EVENTS_REGION[0].WA
Disabled
0
Disable
Page 466
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
B
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Enable
RW REGION0RA
Enable or disable interrupt for REGION[0].RA event
See EVENTS_REGION[0].RA
C
Disabled
0
Disable
Enabled
1
Enable
RW REGION1WA
Enable or disable interrupt for REGION[1].WA event
See EVENTS_REGION[1].WA
D
Disabled
0
Disable
Enabled
1
Enable
RW REGION1RA
Enable or disable interrupt for REGION[1].RA event
See EVENTS_REGION[1].RA
E
Disabled
0
Disable
Enabled
1
Enable
RW REGION2WA
Enable or disable interrupt for REGION[2].WA event
See EVENTS_REGION[2].WA
F
Disabled
0
Disable
Enabled
1
Enable
RW REGION2RA
Enable or disable interrupt for REGION[2].RA event
See EVENTS_REGION[2].RA
G
Disabled
0
Disable
Enabled
1
Enable
RW REGION3WA
Enable or disable interrupt for REGION[3].WA event
See EVENTS_REGION[3].WA
H
Disabled
0
Disable
Enabled
1
Enable
RW REGION3RA
Enable or disable interrupt for REGION[3].RA event
See EVENTS_REGION[3].RA
I
Disabled
0
Disable
Enabled
1
Enable
RW PREGION0WA
Enable or disable interrupt for PREGION[0].WA event
See EVENTS_PREGION[0].WA
J
Disabled
0
Disable
Enabled
1
Enable
RW PREGION0RA
Enable or disable interrupt for PREGION[0].RA event
See EVENTS_PREGION[0].RA
K
Disabled
0
Disable
Enabled
1
Enable
RW PREGION1WA
Enable or disable interrupt for PREGION[1].WA event
See EVENTS_PREGION[1].WA
L
Disabled
0
Disable
Enabled
1
Enable
RW PREGION1RA
Enable or disable interrupt for PREGION[1].RA event
See EVENTS_PREGION[1].RA
Disabled
0
Disable
Enabled
1
Enable
45.1.2 INTENSET
Address offset: 0x304
Enable interrupt
Page 467
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW REGION0WA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for REGION[0].WA event
See EVENTS_REGION[0].WA
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION0RA
Write '1' to Enable interrupt for REGION[0].RA event
See EVENTS_REGION[0].RA
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1WA
Write '1' to Enable interrupt for REGION[1].WA event
See EVENTS_REGION[1].WA
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1RA
Write '1' to Enable interrupt for REGION[1].RA event
See EVENTS_REGION[1].RA
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2WA
Write '1' to Enable interrupt for REGION[2].WA event
See EVENTS_REGION[2].WA
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2RA
Write '1' to Enable interrupt for REGION[2].RA event
See EVENTS_REGION[2].RA
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3WA
Write '1' to Enable interrupt for REGION[3].WA event
See EVENTS_REGION[3].WA
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3RA
Write '1' to Enable interrupt for REGION[3].RA event
See EVENTS_REGION[3].RA
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0WA
Write '1' to Enable interrupt for PREGION[0].WA event
See EVENTS_PREGION[0].WA
J
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0RA
Write '1' to Enable interrupt for PREGION[0].RA event
See EVENTS_PREGION[0].RA
K
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION1WA
Write '1' to Enable interrupt for PREGION[1].WA event
Page 468
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_PREGION[1].WA
L
RW PREGION1RA
Write '1' to Enable interrupt for PREGION[1].RA event
See EVENTS_PREGION[1].RA
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
45.1.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW REGION0WA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for REGION[0].WA event
See EVENTS_REGION[0].WA
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION0RA
Write '1' to Disable interrupt for REGION[0].RA event
See EVENTS_REGION[0].RA
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1WA
Write '1' to Disable interrupt for REGION[1].WA event
See EVENTS_REGION[1].WA
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1RA
Write '1' to Disable interrupt for REGION[1].RA event
See EVENTS_REGION[1].RA
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2WA
Write '1' to Disable interrupt for REGION[2].WA event
See EVENTS_REGION[2].WA
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2RA
Write '1' to Disable interrupt for REGION[2].RA event
See EVENTS_REGION[2].RA
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3WA
Write '1' to Disable interrupt for REGION[3].WA event
See EVENTS_REGION[3].WA
Clear
1
Disable
Page 469
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
H
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3RA
Write '1' to Disable interrupt for REGION[3].RA event
See EVENTS_REGION[3].RA
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0WA
Write '1' to Disable interrupt for PREGION[0].WA event
See EVENTS_PREGION[0].WA
J
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0RA
Write '1' to Disable interrupt for PREGION[0].RA event
See EVENTS_PREGION[0].RA
K
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION1WA
Write '1' to Disable interrupt for PREGION[1].WA event
See EVENTS_PREGION[1].WA
L
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION1RA
Write '1' to Disable interrupt for PREGION[1].RA event
See EVENTS_PREGION[1].RA
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
45.1.4 NMIEN
Address offset: 0x320
Enable or disable non-maskable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW REGION0WA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable non-maskable interrupt for REGION[0].WA
event
See EVENTS_REGION[0].WA
B
Disabled
0
Disable
Enabled
1
Enable
RW REGION0RA
Enable or disable non-maskable interrupt for REGION[0].RA
event
See EVENTS_REGION[0].RA
C
Disabled
0
Disable
Enabled
1
Enable
RW REGION1WA
Enable or disable non-maskable interrupt for REGION[1].WA
event
See EVENTS_REGION[1].WA
Disabled
0
Disable
Enabled
1
Enable
Page 470
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
D
RW REGION1RA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable non-maskable interrupt for REGION[1].RA
event
See EVENTS_REGION[1].RA
E
Disabled
0
Disable
Enabled
1
Enable
RW REGION2WA
Enable or disable non-maskable interrupt for REGION[2].WA
event
See EVENTS_REGION[2].WA
F
Disabled
0
Disable
Enabled
1
Enable
RW REGION2RA
Enable or disable non-maskable interrupt for REGION[2].RA
event
See EVENTS_REGION[2].RA
G
Disabled
0
Disable
Enabled
1
Enable
RW REGION3WA
Enable or disable non-maskable interrupt for REGION[3].WA
event
See EVENTS_REGION[3].WA
H
Disabled
0
Disable
Enabled
1
Enable
RW REGION3RA
Enable or disable non-maskable interrupt for REGION[3].RA
event
See EVENTS_REGION[3].RA
I
Disabled
0
Disable
Enabled
1
Enable
RW PREGION0WA
Enable or disable non-maskable interrupt for PREGION[0].WA
event
See EVENTS_PREGION[0].WA
J
Disabled
0
Disable
Enabled
1
Enable
RW PREGION0RA
Enable or disable non-maskable interrupt for PREGION[0].RA
event
See EVENTS_PREGION[0].RA
K
Disabled
0
Disable
Enabled
1
Enable
RW PREGION1WA
Enable or disable non-maskable interrupt for PREGION[1].WA
event
See EVENTS_PREGION[1].WA
L
Disabled
0
Disable
Enabled
1
Enable
RW PREGION1RA
Enable or disable non-maskable interrupt for PREGION[1].RA
event
See EVENTS_PREGION[1].RA
Disabled
0
Disable
Enabled
1
Enable
45.1.5 NMIENSET
Address offset: 0x324
Enable non-maskable interrupt
Page 471
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW REGION0WA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable non-maskable interrupt for REGION[0].WA
event
See EVENTS_REGION[0].WA
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION0RA
Write '1' to Enable non-maskable interrupt for REGION[0].RA
event
See EVENTS_REGION[0].RA
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1WA
Write '1' to Enable non-maskable interrupt for REGION[1].WA
event
See EVENTS_REGION[1].WA
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1RA
Write '1' to Enable non-maskable interrupt for REGION[1].RA
event
See EVENTS_REGION[1].RA
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2WA
Write '1' to Enable non-maskable interrupt for REGION[2].WA
event
See EVENTS_REGION[2].WA
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2RA
Write '1' to Enable non-maskable interrupt for REGION[2].RA
event
See EVENTS_REGION[2].RA
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3WA
Write '1' to Enable non-maskable interrupt for REGION[3].WA
event
See EVENTS_REGION[3].WA
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3RA
Write '1' to Enable non-maskable interrupt for REGION[3].RA
event
See EVENTS_REGION[3].RA
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0WA
Write '1' to Enable non-maskable interrupt for PREGION[0].WA
event
See EVENTS_PREGION[0].WA
Page 472
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
J
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0RA
Write '1' to Enable non-maskable interrupt for PREGION[0].RA
event
See EVENTS_PREGION[0].RA
K
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION1WA
Write '1' to Enable non-maskable interrupt for PREGION[1].WA
event
See EVENTS_PREGION[1].WA
L
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION1RA
Write '1' to Enable non-maskable interrupt for PREGION[1].RA
event
See EVENTS_PREGION[1].RA
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
45.1.6 NMIENCLR
Address offset: 0x328
Disable non-maskable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW REGION0WA
0
Value Id
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable non-maskable interrupt for REGION[0].WA
event
See EVENTS_REGION[0].WA
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION0RA
Write '1' to Disable non-maskable interrupt for REGION[0].RA
event
See EVENTS_REGION[0].RA
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1WA
Write '1' to Disable non-maskable interrupt for REGION[1].WA
event
See EVENTS_REGION[1].WA
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION1RA
Write '1' to Disable non-maskable interrupt for REGION[1].RA
event
See EVENTS_REGION[1].RA
Page 473
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
E
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2WA
Write '1' to Disable non-maskable interrupt for REGION[2].WA
event
See EVENTS_REGION[2].WA
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION2RA
Write '1' to Disable non-maskable interrupt for REGION[2].RA
event
See EVENTS_REGION[2].RA
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3WA
Write '1' to Disable non-maskable interrupt for REGION[3].WA
event
See EVENTS_REGION[3].WA
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REGION3RA
Write '1' to Disable non-maskable interrupt for REGION[3].RA
event
See EVENTS_REGION[3].RA
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0WA
Write '1' to Disable non-maskable interrupt for PREGION[0].WA
event
See EVENTS_PREGION[0].WA
J
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION0RA
Write '1' to Disable non-maskable interrupt for PREGION[0].RA
event
See EVENTS_PREGION[0].RA
K
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION1WA
Write '1' to Disable non-maskable interrupt for PREGION[1].WA
event
See EVENTS_PREGION[1].WA
L
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PREGION1RA
Write '1' to Disable non-maskable interrupt for PREGION[1].RA
event
See EVENTS_PREGION[1].RA
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Page 474
45 MWU — Memory watch unit
45.1.7 PERREGION[0].SUBSTATWA
Address offset: 0x400
Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for
watching
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW SR0
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
Value Id
Value
Description
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
Subregion 0 in region 0 (write '1' to clear)
RW SR1
Subregion 1 in region 0 (write '1' to clear)
RW SR2
Subregion 2 in region 0 (write '1' to clear)
RW SR3
Subregion 3 in region 0 (write '1' to clear)
RW SR4
Subregion 4 in region 0 (write '1' to clear)
RW SR5
Subregion 5 in region 0 (write '1' to clear)
RW SR6
Subregion 6 in region 0 (write '1' to clear)
RW SR7
Subregion 7 in region 0 (write '1' to clear)
RW SR8
Subregion 8 in region 0 (write '1' to clear)
RW SR9
Subregion 9 in region 0 (write '1' to clear)
RW SR10
Subregion 10 in region 0 (write '1' to clear)
RW SR11
Subregion 11 in region 0 (write '1' to clear)
RW SR12
Subregion 12 in region 0 (write '1' to clear)
RW SR13
Subregion 13 in region 0 (write '1' to clear)
RW SR14
Subregion 14 in region 0 (write '1' to clear)
RW SR15
Subregion 15 in region 0 (write '1' to clear)
RW SR16
Subregion 16 in region 0 (write '1' to clear)
Page 475
I H G F E D C B A
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
R
S
T
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
RW SR17
I H G F E D C B A
Subregion 17 in region 0 (write '1' to clear)
RW SR18
Subregion 18 in region 0 (write '1' to clear)
RW SR19
Subregion 19 in region 0 (write '1' to clear)
RW SR20
Subregion 20 in region 0 (write '1' to clear)
RW SR21
Subregion 21 in region 0 (write '1' to clear)
RW SR22
Subregion 22 in region 0 (write '1' to clear)
RW SR23
Subregion 23 in region 0 (write '1' to clear)
RW SR24
Subregion 24 in region 0 (write '1' to clear)
RW SR25
Subregion 25 in region 0 (write '1' to clear)
RW SR26
Subregion 26 in region 0 (write '1' to clear)
RW SR27
Subregion 27 in region 0 (write '1' to clear)
RW SR28
Subregion 28 in region 0 (write '1' to clear)
RW SR29
Subregion 29 in region 0 (write '1' to clear)
RW SR30
Subregion 30 in region 0 (write '1' to clear)
RW SR31
Subregion 31 in region 0 (write '1' to clear)
45.1.8 PERREGION[0].SUBSTATRA
Address offset: 0x404
Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for
watching
Page 476
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW SR0
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
Value Id
Value
Description
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
Subregion 0 in region 0 (write '1' to clear)
RW SR1
Subregion 1 in region 0 (write '1' to clear)
RW SR2
Subregion 2 in region 0 (write '1' to clear)
RW SR3
Subregion 3 in region 0 (write '1' to clear)
RW SR4
Subregion 4 in region 0 (write '1' to clear)
RW SR5
Subregion 5 in region 0 (write '1' to clear)
RW SR6
Subregion 6 in region 0 (write '1' to clear)
RW SR7
Subregion 7 in region 0 (write '1' to clear)
RW SR8
Subregion 8 in region 0 (write '1' to clear)
RW SR9
Subregion 9 in region 0 (write '1' to clear)
RW SR10
Subregion 10 in region 0 (write '1' to clear)
RW SR11
Subregion 11 in region 0 (write '1' to clear)
RW SR12
Subregion 12 in region 0 (write '1' to clear)
RW SR13
Subregion 13 in region 0 (write '1' to clear)
RW SR14
Subregion 14 in region 0 (write '1' to clear)
RW SR15
Subregion 15 in region 0 (write '1' to clear)
RW SR16
Subregion 16 in region 0 (write '1' to clear)
RW SR17
Subregion 17 in region 0 (write '1' to clear)
RW SR18
Subregion 18 in region 0 (write '1' to clear)
Page 477
I H G F E D C B A
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
T
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
RW SR19
I H G F E D C B A
Subregion 19 in region 0 (write '1' to clear)
RW SR20
Subregion 20 in region 0 (write '1' to clear)
RW SR21
Subregion 21 in region 0 (write '1' to clear)
RW SR22
Subregion 22 in region 0 (write '1' to clear)
RW SR23
Subregion 23 in region 0 (write '1' to clear)
RW SR24
Subregion 24 in region 0 (write '1' to clear)
RW SR25
Subregion 25 in region 0 (write '1' to clear)
RW SR26
Subregion 26 in region 0 (write '1' to clear)
RW SR27
Subregion 27 in region 0 (write '1' to clear)
RW SR28
Subregion 28 in region 0 (write '1' to clear)
RW SR29
Subregion 29 in region 0 (write '1' to clear)
RW SR30
Subregion 30 in region 0 (write '1' to clear)
RW SR31
Subregion 31 in region 0 (write '1' to clear)
45.1.9 PERREGION[1].SUBSTATWA
Address offset: 0x408
Source of event/interrupt in region 1, write access detected while corresponding subregion was enabled for
watching
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW SR0
Value Id
Value
Description
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
Subregion 0 in region 1 (write '1' to clear)
Page 478
I H G F E D C B A
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
B
RW SR1
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
Value Id
Value
Description
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
Subregion 1 in region 1 (write '1' to clear)
RW SR2
Subregion 2 in region 1 (write '1' to clear)
RW SR3
Subregion 3 in region 1 (write '1' to clear)
RW SR4
Subregion 4 in region 1 (write '1' to clear)
RW SR5
Subregion 5 in region 1 (write '1' to clear)
RW SR6
Subregion 6 in region 1 (write '1' to clear)
RW SR7
Subregion 7 in region 1 (write '1' to clear)
RW SR8
Subregion 8 in region 1 (write '1' to clear)
RW SR9
Subregion 9 in region 1 (write '1' to clear)
RW SR10
Subregion 10 in region 1 (write '1' to clear)
RW SR11
Subregion 11 in region 1 (write '1' to clear)
RW SR12
Subregion 12 in region 1 (write '1' to clear)
RW SR13
Subregion 13 in region 1 (write '1' to clear)
RW SR14
Subregion 14 in region 1 (write '1' to clear)
RW SR15
Subregion 15 in region 1 (write '1' to clear)
RW SR16
Subregion 16 in region 1 (write '1' to clear)
RW SR17
Subregion 17 in region 1 (write '1' to clear)
RW SR18
Subregion 18 in region 1 (write '1' to clear)
RW SR19
Subregion 19 in region 1 (write '1' to clear)
Page 479
I H G F E D C B A
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
U
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
NoAccess
0
No write access occurred in this subregion
Access
1
Write access(es) occurred in this subregion
RW SR20
I H G F E D C B A
Subregion 20 in region 1 (write '1' to clear)
RW SR21
Subregion 21 in region 1 (write '1' to clear)
RW SR22
Subregion 22 in region 1 (write '1' to clear)
RW SR23
Subregion 23 in region 1 (write '1' to clear)
RW SR24
Subregion 24 in region 1 (write '1' to clear)
RW SR25
Subregion 25 in region 1 (write '1' to clear)
RW SR26
Subregion 26 in region 1 (write '1' to clear)
RW SR27
Subregion 27 in region 1 (write '1' to clear)
RW SR28
Subregion 28 in region 1 (write '1' to clear)
RW SR29
Subregion 29 in region 1 (write '1' to clear)
RW SR30
Subregion 30 in region 1 (write '1' to clear)
RW SR31
Subregion 31 in region 1 (write '1' to clear)
45.1.10 PERREGION[1].SUBSTATRA
Address offset: 0x40C
Source of event/interrupt in region 1, read access detected while corresponding subregion was enabled for
watching
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW SR0
B
Value Id
Value
Description
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
Subregion 0 in region 1 (write '1' to clear)
RW SR1
Subregion 1 in region 1 (write '1' to clear)
Page 480
I H G F E D C B A
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
C
RW SR2
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
Value Id
Value
Description
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
Subregion 2 in region 1 (write '1' to clear)
RW SR3
Subregion 3 in region 1 (write '1' to clear)
RW SR4
Subregion 4 in region 1 (write '1' to clear)
RW SR5
Subregion 5 in region 1 (write '1' to clear)
RW SR6
Subregion 6 in region 1 (write '1' to clear)
RW SR7
Subregion 7 in region 1 (write '1' to clear)
RW SR8
Subregion 8 in region 1 (write '1' to clear)
RW SR9
Subregion 9 in region 1 (write '1' to clear)
RW SR10
Subregion 10 in region 1 (write '1' to clear)
RW SR11
Subregion 11 in region 1 (write '1' to clear)
RW SR12
Subregion 12 in region 1 (write '1' to clear)
RW SR13
Subregion 13 in region 1 (write '1' to clear)
RW SR14
Subregion 14 in region 1 (write '1' to clear)
RW SR15
Subregion 15 in region 1 (write '1' to clear)
RW SR16
Subregion 16 in region 1 (write '1' to clear)
RW SR17
Subregion 17 in region 1 (write '1' to clear)
RW SR18
Subregion 18 in region 1 (write '1' to clear)
RW SR19
Subregion 19 in region 1 (write '1' to clear)
RW SR20
Subregion 20 in region 1 (write '1' to clear)
Page 481
I H G F E D C B A
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
V
W
X
Y
Z
a
b
c
d
e
f
RW Field
Value Id
Value
Description
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
NoAccess
0
No read access occurred in this subregion
Access
1
Read access(es) occurred in this subregion
RW SR21
I H G F E D C B A
Subregion 21 in region 1 (write '1' to clear)
RW SR22
Subregion 22 in region 1 (write '1' to clear)
RW SR23
Subregion 23 in region 1 (write '1' to clear)
RW SR24
Subregion 24 in region 1 (write '1' to clear)
RW SR25
Subregion 25 in region 1 (write '1' to clear)
RW SR26
Subregion 26 in region 1 (write '1' to clear)
RW SR27
Subregion 27 in region 1 (write '1' to clear)
RW SR28
Subregion 28 in region 1 (write '1' to clear)
RW SR29
Subregion 29 in region 1 (write '1' to clear)
RW SR30
Subregion 30 in region 1 (write '1' to clear)
RW SR31
Subregion 31 in region 1 (write '1' to clear)
45.1.11 REGIONEN
Address offset: 0x510
Enable/disable regions watch
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW RGN0WA
B
C
D
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disable
0
Disable write access watch in this region
Enable
1
Enable write access watch in this region
Disable
0
Disable read access watch in this region
Enable
1
Enable read access watch in this region
Disable
0
Disable write access watch in this region
Enable
1
Enable write access watch in this region
Enable/disable write access watch in region[0]
RW RGN0RA
Enable/disable read access watch in region[0]
RW RGN1WA
Enable/disable write access watch in region[1]
RW RGN1RA
Enable/disable read access watch in region[1]
Page 482
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
E
F
G
H
I
J
K
L
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disable
0
Disable read access watch in this region
Enable
1
Enable read access watch in this region
Disable
0
Disable write access watch in this region
Enable
1
Enable write access watch in this region
Disable
0
Disable read access watch in this region
Enable
1
Enable read access watch in this region
Disable
0
Disable write access watch in this region
Enable
1
Enable write access watch in this region
Disable
0
Disable read access watch in this region
Enable
1
Enable read access watch in this region
Disable
0
Disable write access watch in this PREGION
Enable
1
Enable write access watch in this PREGION
Disable
0
Disable read access watch in this PREGION
Enable
1
Enable read access watch in this PREGION
Disable
0
Disable write access watch in this PREGION
Enable
1
Enable write access watch in this PREGION
Disable
0
Disable read access watch in this PREGION
Enable
1
Enable read access watch in this PREGION
RW RGN2WA
Enable/disable write access watch in region[2]
RW RGN2RA
Enable/disable read access watch in region[2]
RW RGN3WA
Enable/disable write access watch in region[3]
RW RGN3RA
Enable/disable read access watch in region[3]
RW PRGN0WA
Enable/disable write access watch in PREGION[0]
RW PRGN0RA
Enable/disable read access watch in PREGION[0]
RW PRGN1WA
Enable/disable write access watch in PREGION[1]
RW PRGN1RA
Enable/disable read access watch in PREGION[1]
45.1.12 REGIONENSET
Address offset: 0x514
Enable regions watch
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW RGN0WA
B
C
D
E
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable write access watch in this region
Disabled
0
Write access watch in this region is disabled
Enabled
1
Write access watch in this region is enabled
Set
1
Enable read access watch in this region
Disabled
0
Read access watch in this region is disabled
Enabled
1
Read access watch in this region is enabled
Set
1
Enable write access watch in this region
Disabled
0
Write access watch in this region is disabled
Enabled
1
Write access watch in this region is enabled
Set
1
Enable read access watch in this region
Disabled
0
Read access watch in this region is disabled
Enabled
1
Read access watch in this region is enabled
Set
1
Enable write access watch in this region
Disabled
0
Write access watch in this region is disabled
Enable write access watch in region[0]
RW RGN0RA
Enable read access watch in region[0]
RW RGN1WA
Enable write access watch in region[1]
RW RGN1RA
Enable read access watch in region[1]
RW RGN2WA
Enable write access watch in region[2]
Page 483
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
F
G
H
I
J
K
L
RW Field
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Write access watch in this region is enabled
Set
1
Enable read access watch in this region
Disabled
0
Read access watch in this region is disabled
Enabled
1
Read access watch in this region is enabled
Set
1
Enable write access watch in this region
Disabled
0
Write access watch in this region is disabled
Enabled
1
Write access watch in this region is enabled
Set
1
Enable read access watch in this region
Disabled
0
Read access watch in this region is disabled
Enabled
1
Read access watch in this region is enabled
Set
1
Enable write access watch in this PREGION
Disabled
0
Write access watch in this PREGION is disabled
Enabled
1
Write access watch in this PREGION is enabled
Set
1
Enable read access watch in this PREGION
Disabled
0
Read access watch in this PREGION is disabled
Enabled
1
Read access watch in this PREGION is enabled
Set
1
Enable write access watch in this PREGION
Disabled
0
Write access watch in this PREGION is disabled
Enabled
1
Write access watch in this PREGION is enabled
Set
1
Enable read access watch in this PREGION
Disabled
0
Read access watch in this PREGION is disabled
Enabled
1
Read access watch in this PREGION is enabled
RW RGN2RA
Enable read access watch in region[2]
RW RGN3WA
Enable write access watch in region[3]
RW RGN3RA
Enable read access watch in region[3]
RW PRGN0WA
Enable write access watch in PREGION[0]
RW PRGN0RA
Enable read access watch in PREGION[0]
RW PRGN1WA
Enable write access watch in PREGION[1]
RW PRGN1RA
Enable read access watch in PREGION[1]
45.1.13 REGIONENCLR
Address offset: 0x518
Disable regions watch
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
A
RW RGN0WA
B
C
D
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable write access watch in this region
Disabled
0
Write access watch in this region is disabled
Enabled
1
Write access watch in this region is enabled
Clear
1
Disable read access watch in this region
Disabled
0
Read access watch in this region is disabled
Enabled
1
Read access watch in this region is enabled
Clear
1
Disable write access watch in this region
Disabled
0
Write access watch in this region is disabled
Enabled
1
Write access watch in this region is enabled
Clear
1
Disable read access watch in this region
Disabled
0
Read access watch in this region is disabled
Enabled
1
Read access watch in this region is enabled
Disable write access watch in region[0]
RW RGN0RA
Disable read access watch in region[0]
RW RGN1WA
Disable write access watch in region[1]
RW RGN1RA
Disable read access watch in region[1]
Page 484
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
L K J
Reset 0x00000000
Id
RW Field
E
RW RGN2WA
F
G
H
I
J
K
L
0
I
H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable write access watch in this region
Disabled
0
Write access watch in this region is disabled
Enabled
1
Write access watch in this region is enabled
Clear
1
Disable read access watch in this region
Disabled
0
Read access watch in this region is disabled
Enabled
1
Read access watch in this region is enabled
Clear
1
Disable write access watch in this region
Disabled
0
Write access watch in this region is disabled
Enabled
1
Write access watch in this region is enabled
Clear
1
Disable read access watch in this region
Disabled
0
Read access watch in this region is disabled
Enabled
1
Read access watch in this region is enabled
Clear
1
Disable write access watch in this PREGION
Disabled
0
Write access watch in this PREGION is disabled
Enabled
1
Write access watch in this PREGION is enabled
Clear
1
Disable read access watch in this PREGION
Disabled
0
Read access watch in this PREGION is disabled
Enabled
1
Read access watch in this PREGION is enabled
Clear
1
Disable write access watch in this PREGION
Disabled
0
Write access watch in this PREGION is disabled
Enabled
1
Write access watch in this PREGION is enabled
Clear
1
Disable read access watch in this PREGION
Disabled
0
Read access watch in this PREGION is disabled
Enabled
1
Read access watch in this PREGION is enabled
Disable write access watch in region[2]
RW RGN2RA
Disable read access watch in region[2]
RW RGN3WA
Disable write access watch in region[3]
RW RGN3RA
Disable read access watch in region[3]
RW PRGN0WA
Disable write access watch in PREGION[0]
RW PRGN0RA
Disable read access watch in PREGION[0]
RW PRGN1WA
Disable write access watch in PREGION[1]
RW PRGN1RA
Disable read access watch in PREGION[1]
45.1.14 REGION[0].START
Address offset: 0x600
Start address for region 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW START
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Start address for region
45.1.15 REGION[0].END
Address offset: 0x604
End address of region 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW END
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
End address of region.
Page 485
45 MWU — Memory watch unit
45.1.16 REGION[1].START
Address offset: 0x610
Start address for region 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW START
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Start address for region
45.1.17 REGION[1].END
Address offset: 0x614
End address of region 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW END
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
End address of region.
45.1.18 REGION[2].START
Address offset: 0x620
Start address for region 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW START
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Start address for region
45.1.19 REGION[2].END
Address offset: 0x624
End address of region 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW END
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
End address of region.
45.1.20 REGION[3].START
Address offset: 0x630
Start address for region 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW START
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Start address for region
45.1.21 REGION[3].END
Address offset: 0x634
End address of region 3
Page 486
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW END
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
End address of region.
45.1.22 PREGION[0].START
Address offset: 0x6C0
Reserved for future use
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
START
Reserved for future use
45.1.23 PREGION[0].END
Address offset: 0x6C4
Reserved for future use
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
END
Reserved for future use
45.1.24 PREGION[0].SUBS
Address offset: 0x6C8
Subregions of region 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW SR0
B
C
D
E
F
G
Value Id
Value
Description
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Include or exclude subregion 0 in region
RW SR1
Include or exclude subregion 1 in region
RW SR2
Include or exclude subregion 2 in region
RW SR3
Include or exclude subregion 3 in region
RW SR4
Include or exclude subregion 4 in region
RW SR5
Include or exclude subregion 5 in region
RW SR6
Include or exclude subregion 6 in region
Page 487
I H G F E D C B A
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
H
RW SR7
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
Value Id
Value
Description
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Include or exclude subregion 7 in region
RW SR8
Include or exclude subregion 8 in region
RW SR9
Include or exclude subregion 9 in region
RW SR10
Include or exclude subregion 10 in region
RW SR11
Include or exclude subregion 11 in region
RW SR12
Include or exclude subregion 12 in region
RW SR13
Include or exclude subregion 13 in region
RW SR14
Include or exclude subregion 14 in region
RW SR15
Include or exclude subregion 15 in region
RW SR16
Include or exclude subregion 16 in region
RW SR17
Include or exclude subregion 17 in region
RW SR18
Include or exclude subregion 18 in region
RW SR19
Include or exclude subregion 19 in region
RW SR20
Include or exclude subregion 20 in region
RW SR21
Include or exclude subregion 21 in region
RW SR22
Include or exclude subregion 22 in region
RW SR23
Include or exclude subregion 23 in region
RW SR24
Include or exclude subregion 24 in region
RW SR25
Include or exclude subregion 25 in region
Page 488
I H G F E D C B A
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
a
b
c
d
e
f
RW Field
Value Id
Value
Description
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
RW SR26
I H G F E D C B A
Include or exclude subregion 26 in region
RW SR27
Include or exclude subregion 27 in region
RW SR28
Include or exclude subregion 28 in region
RW SR29
Include or exclude subregion 29 in region
RW SR30
Include or exclude subregion 30 in region
RW SR31
Include or exclude subregion 31 in region
45.1.25 PREGION[1].START
Address offset: 0x6D0
Reserved for future use
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
START
Reserved for future use
45.1.26 PREGION[1].END
Address offset: 0x6D4
Reserved for future use
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
END
Reserved for future use
45.1.27 PREGION[1].SUBS
Address offset: 0x6D8
Subregions of region 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
A
RW SR0
Value Id
Value
Exclude
0
Description
Include or exclude subregion 0 in region
Exclude
Page 489
I H G F E D C B A
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
RW Field
Value Id
Value
Description
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
RW SR1
Include or exclude subregion 1 in region
RW SR2
Include or exclude subregion 2 in region
RW SR3
Include or exclude subregion 3 in region
RW SR4
Include or exclude subregion 4 in region
RW SR5
Include or exclude subregion 5 in region
RW SR6
Include or exclude subregion 6 in region
RW SR7
Include or exclude subregion 7 in region
RW SR8
Include or exclude subregion 8 in region
RW SR9
Include or exclude subregion 9 in region
RW SR10
Include or exclude subregion 10 in region
RW SR11
Include or exclude subregion 11 in region
RW SR12
Include or exclude subregion 12 in region
RW SR13
Include or exclude subregion 13 in region
RW SR14
Include or exclude subregion 14 in region
RW SR15
Include or exclude subregion 15 in region
RW SR16
Include or exclude subregion 16 in region
RW SR17
Include or exclude subregion 17 in region
RW SR18
Include or exclude subregion 18 in region
Page 490
I H G F E D C B A
45 MWU — Memory watch unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
f
e d c b a Z Y X W V U T S R Q P O N M L K J
Reset 0x00000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id
RW Field
T
RW SR19
U
V
W
X
Y
Z
a
b
c
d
e
f
Value Id
Value
Description
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Exclude
0
Exclude
Include
1
Include
Include or exclude subregion 19 in region
RW SR20
Include or exclude subregion 20 in region
RW SR21
Include or exclude subregion 21 in region
RW SR22
Include or exclude subregion 22 in region
RW SR23
Include or exclude subregion 23 in region
RW SR24
Include or exclude subregion 24 in region
RW SR25
Include or exclude subregion 25 in region
RW SR26
Include or exclude subregion 26 in region
RW SR27
Include or exclude subregion 27 in region
RW SR28
Include or exclude subregion 28 in region
RW SR29
Include or exclude subregion 29 in region
RW SR30
Include or exclude subregion 30 in region
RW SR31
Include or exclude subregion 31 in region
Page 491
I H G F E D C B A
46 EGU — Event generator unit
46 EGU — Event generator unit
The Event generator unit (EGU) provides support for inter-layer signaling. This means support for atomic
triggering of both CPU execution and hardware tasks from both firmware (by CPU) and hardware (by PPI).
This feature can, for instance, be used for triggering CPU execution at a lower priority execution from a
higher priority execution, or to handle a peripheral's ISR execution at a lower priority for some of its events.
However, triggering any priority from any priority is possible.
Listed here are the main EGU features:
•
•
•
Enables SW triggering of interrupts
6 EGU instances – separate interrupt vectors
Up to 16 separate event flags per interrupt for multiplexing
The EGU implements a set of tasks which can individually be triggered to generate the corresponding event,
i.e., the corresponding event for TASKS_TRIGGER[n] is EVENTS_TRIGGERED[n].
Table 116: EGU configuration
EGU instance
0-5
Number of event flags
16
46.1 Registers
Table 117: Instances
Base address
Peripheral
Instance
Description
0x40014000
EGU
EGU0
Event Generator Unit 0
0x40015000
EGU
EGU1
Event Generator Unit 1
0x40016000
EGU
EGU2
Event Generator Unit 2
0x40017000
EGU
EGU3
Event Generator Unit 3
0x40018000
EGU
EGU4
Event Generator Unit 4
0x40019000
EGU
EGU5
Event Generator Unit 5
Configuration
Table 118: Register Overview
Register
Offset
Description
TASKS_TRIGGER[0]
0x000
Trigger 0 for triggering the corresponding TRIGGERED[0] event
TASKS_TRIGGER[1]
0x004
Trigger 1 for triggering the corresponding TRIGGERED[1] event
TASKS_TRIGGER[2]
0x008
Trigger 2 for triggering the corresponding TRIGGERED[2] event
TASKS_TRIGGER[3]
0x00C
Trigger 3 for triggering the corresponding TRIGGERED[3] event
TASKS_TRIGGER[4]
0x010
Trigger 4 for triggering the corresponding TRIGGERED[4] event
TASKS_TRIGGER[5]
0x014
Trigger 5 for triggering the corresponding TRIGGERED[5] event
TASKS_TRIGGER[6]
0x018
Trigger 6 for triggering the corresponding TRIGGERED[6] event
TASKS_TRIGGER[7]
0x01C
Trigger 7 for triggering the corresponding TRIGGERED[7] event
TASKS_TRIGGER[8]
0x020
Trigger 8 for triggering the corresponding TRIGGERED[8] event
TASKS_TRIGGER[9]
0x024
Trigger 9 for triggering the corresponding TRIGGERED[9] event
TASKS_TRIGGER[10]
0x028
Trigger 10 for triggering the corresponding TRIGGERED[10] event
TASKS_TRIGGER[11]
0x02C
Trigger 11 for triggering the corresponding TRIGGERED[11] event
TASKS_TRIGGER[12]
0x030
Trigger 12 for triggering the corresponding TRIGGERED[12] event
TASKS_TRIGGER[13]
0x034
Trigger 13 for triggering the corresponding TRIGGERED[13] event
TASKS_TRIGGER[14]
0x038
Trigger 14 for triggering the corresponding TRIGGERED[14] event
TASKS_TRIGGER[15]
0x03C
Trigger 15 for triggering the corresponding TRIGGERED[15] event
EVENTS_TRIGGERED[0] 0x100
Event number 0 generated by triggering the corresponding TRIGGER[0] task
EVENTS_TRIGGERED[1] 0x104
Event number 1 generated by triggering the corresponding TRIGGER[1] task
EVENTS_TRIGGERED[2] 0x108
Event number 2 generated by triggering the corresponding TRIGGER[2] task
EVENTS_TRIGGERED[3] 0x10C
Event number 3 generated by triggering the corresponding TRIGGER[3] task
EVENTS_TRIGGERED[4] 0x110
Event number 4 generated by triggering the corresponding TRIGGER[4] task
Page 492
46 EGU — Event generator unit
Register
Offset
Description
EVENTS_TRIGGERED[5] 0x114
Event number 5 generated by triggering the corresponding TRIGGER[5] task
EVENTS_TRIGGERED[6] 0x118
Event number 6 generated by triggering the corresponding TRIGGER[6] task
EVENTS_TRIGGERED[7] 0x11C
Event number 7 generated by triggering the corresponding TRIGGER[7] task
EVENTS_TRIGGERED[8] 0x120
Event number 8 generated by triggering the corresponding TRIGGER[8] task
EVENTS_TRIGGERED[9] 0x124
Event number 9 generated by triggering the corresponding TRIGGER[9] task
EVENTS_TRIGGERED[10] 0x128
Event number 10 generated by triggering the corresponding TRIGGER[10] task
EVENTS_TRIGGERED[11] 0x12C
Event number 11 generated by triggering the corresponding TRIGGER[11] task
EVENTS_TRIGGERED[12] 0x130
Event number 12 generated by triggering the corresponding TRIGGER[12] task
EVENTS_TRIGGERED[13] 0x134
Event number 13 generated by triggering the corresponding TRIGGER[13] task
EVENTS_TRIGGERED[14] 0x138
Event number 14 generated by triggering the corresponding TRIGGER[14] task
EVENTS_TRIGGERED[15] 0x13C
Event number 15 generated by triggering the corresponding TRIGGER[15] task
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
46.1.1 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
P O N M L K J
Reset 0x00000000
Id
RW Field
A
RW TRIGGERED0
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for TRIGGERED[0] event
See EVENTS_TRIGGERED[0]
B
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED1
Enable or disable interrupt for TRIGGERED[1] event
See EVENTS_TRIGGERED[1]
C
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED2
Enable or disable interrupt for TRIGGERED[2] event
See EVENTS_TRIGGERED[2]
D
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED3
Enable or disable interrupt for TRIGGERED[3] event
See EVENTS_TRIGGERED[3]
E
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED4
Enable or disable interrupt for TRIGGERED[4] event
See EVENTS_TRIGGERED[4]
F
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED5
Enable or disable interrupt for TRIGGERED[5] event
See EVENTS_TRIGGERED[5]
G
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED6
Enable or disable interrupt for TRIGGERED[6] event
See EVENTS_TRIGGERED[6]
H
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED7
Enable or disable interrupt for TRIGGERED[7] event
See EVENTS_TRIGGERED[7]
Disabled
0
Disable
Page 493
46 EGU — Event generator unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
P O N M L K J
Reset 0x00000000
Id
I
RW Field
0
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Enable
RW TRIGGERED8
Enable or disable interrupt for TRIGGERED[8] event
See EVENTS_TRIGGERED[8]
J
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED9
Enable or disable interrupt for TRIGGERED[9] event
See EVENTS_TRIGGERED[9]
K
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED10
Enable or disable interrupt for TRIGGERED[10] event
See EVENTS_TRIGGERED[10]
L
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED11
Enable or disable interrupt for TRIGGERED[11] event
See EVENTS_TRIGGERED[11]
M
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED12
Enable or disable interrupt for TRIGGERED[12] event
See EVENTS_TRIGGERED[12]
N
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED13
Enable or disable interrupt for TRIGGERED[13] event
See EVENTS_TRIGGERED[13]
O
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED14
Enable or disable interrupt for TRIGGERED[14] event
See EVENTS_TRIGGERED[14]
P
Disabled
0
Disable
Enabled
1
Enable
RW TRIGGERED15
Enable or disable interrupt for TRIGGERED[15] event
See EVENTS_TRIGGERED[15]
Disabled
0
Disable
Enabled
1
Enable
46.1.2 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
P O N M L K J
Reset 0x00000000
Id
RW Field
A
RW TRIGGERED0
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for TRIGGERED[0] event
See EVENTS_TRIGGERED[0]
B
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED1
Write '1' to Enable interrupt for TRIGGERED[1] event
See EVENTS_TRIGGERED[1]
Set
1
Enable
Page 494
46 EGU — Event generator unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
P O N M L K J
Reset 0x00000000
Id
C
RW Field
0
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED2
Write '1' to Enable interrupt for TRIGGERED[2] event
See EVENTS_TRIGGERED[2]
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED3
Write '1' to Enable interrupt for TRIGGERED[3] event
See EVENTS_TRIGGERED[3]
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED4
Write '1' to Enable interrupt for TRIGGERED[4] event
See EVENTS_TRIGGERED[4]
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED5
Write '1' to Enable interrupt for TRIGGERED[5] event
See EVENTS_TRIGGERED[5]
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED6
Write '1' to Enable interrupt for TRIGGERED[6] event
See EVENTS_TRIGGERED[6]
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED7
Write '1' to Enable interrupt for TRIGGERED[7] event
See EVENTS_TRIGGERED[7]
I
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED8
Write '1' to Enable interrupt for TRIGGERED[8] event
See EVENTS_TRIGGERED[8]
J
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED9
Write '1' to Enable interrupt for TRIGGERED[9] event
See EVENTS_TRIGGERED[9]
K
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED10
Write '1' to Enable interrupt for TRIGGERED[10] event
See EVENTS_TRIGGERED[10]
L
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED11
Write '1' to Enable interrupt for TRIGGERED[11] event
See EVENTS_TRIGGERED[11]
Set
1
Enable
Disabled
0
Read: Disabled
Page 495
46 EGU — Event generator unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
P O N M L K J
Reset 0x00000000
Id
M
RW Field
0
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Enabled
1
Read: Enabled
RW TRIGGERED12
Write '1' to Enable interrupt for TRIGGERED[12] event
See EVENTS_TRIGGERED[12]
N
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED13
Write '1' to Enable interrupt for TRIGGERED[13] event
See EVENTS_TRIGGERED[13]
O
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED14
Write '1' to Enable interrupt for TRIGGERED[14] event
See EVENTS_TRIGGERED[14]
P
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED15
Write '1' to Enable interrupt for TRIGGERED[15] event
See EVENTS_TRIGGERED[15]
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
46.1.3 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
P O N M L K J
Reset 0x00000000
Id
RW Field
A
RW TRIGGERED0
0
Value Id
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for TRIGGERED[0] event
See EVENTS_TRIGGERED[0]
B
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED1
Write '1' to Disable interrupt for TRIGGERED[1] event
See EVENTS_TRIGGERED[1]
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED2
Write '1' to Disable interrupt for TRIGGERED[2] event
See EVENTS_TRIGGERED[2]
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED3
Write '1' to Disable interrupt for TRIGGERED[3] event
See EVENTS_TRIGGERED[3]
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED4
Write '1' to Disable interrupt for TRIGGERED[4] event
Page 496
46 EGU — Event generator unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
P O N M L K J
Reset 0x00000000
Id
RW Field
0
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_TRIGGERED[4]
F
RW TRIGGERED5
Write '1' to Disable interrupt for TRIGGERED[5] event
See EVENTS_TRIGGERED[5]
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED6
Write '1' to Disable interrupt for TRIGGERED[6] event
See EVENTS_TRIGGERED[6]
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED7
Write '1' to Disable interrupt for TRIGGERED[7] event
See EVENTS_TRIGGERED[7]
I
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED8
Write '1' to Disable interrupt for TRIGGERED[8] event
See EVENTS_TRIGGERED[8]
J
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED9
Write '1' to Disable interrupt for TRIGGERED[9] event
See EVENTS_TRIGGERED[9]
K
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED10
Write '1' to Disable interrupt for TRIGGERED[10] event
See EVENTS_TRIGGERED[10]
L
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED11
Write '1' to Disable interrupt for TRIGGERED[11] event
See EVENTS_TRIGGERED[11]
M
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED12
Write '1' to Disable interrupt for TRIGGERED[12] event
See EVENTS_TRIGGERED[12]
N
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED13
Write '1' to Disable interrupt for TRIGGERED[13] event
See EVENTS_TRIGGERED[13]
O
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED14
Write '1' to Disable interrupt for TRIGGERED[14] event
See EVENTS_TRIGGERED[14]
Page 497
46 EGU — Event generator unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
P O N M L K J
Reset 0x00000000
Id
P
0
RW Field
I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW TRIGGERED15
Write '1' to Disable interrupt for TRIGGERED[15] event
See EVENTS_TRIGGERED[15]
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
46.2 Electrical specification
46.2.1 EGU Electrical Specification
Symbol
Description
tEGU,EVT
Latency between setting an EGU event flag and the system
Min.
setting an interrupt
Page 498
Typ.
1
Max.
Units
cycles
47 PWM — Pulse width modulation
47 PWM — Pulse width modulation
The PWM module enables the generation of pulse width modulated signals on GPIO. The module
implements an up or up-and-down counter with four PWM channels that drive assigned GPIOs.
Three PWM modules can provide up to 12 PWM channels with individual frequency control in groups of up to
four channels. Furthermore, a built-in decoder and EasyDMA capabilities make it possible to manipulate the
PWM duty cycles without CPU intervention. Arbitrary duty-cycle sequences are read from Data RAM and can
be chained to implement ping-pong buffering or repeated into complex loops.
Listed here are the main features of one PWM module:
•
•
•
•
•
•
•
Fixed PWM base frequency with programmable clock divider
Up to four PWM channels with individual polarity and duty-cycle values
Edge or center-aligned pulses across PWM channels
Multiple duty-cycle arrays (sequences) defined in Data RAM
Autonomous and glitch-free update of duty cycle values directly from memory through EasyDMA
Change of polarity, duty-cycle, and base frequency possibly on every PWM period
Data RAM sequences can be repeated or connected into loops
Sequence 0
DATA RAM
STARTED
STOPPED
EasyDMA
START
Sequence 1
PWM
STOP
SEQSTART[0]
SEQSTART[1]
SEQ[n].REFRESH
SEQSTARTED[0]
SEQSTARTED[1]
SEQEND[0]
SEQEND[1]
Decoder
NEXTSTEP
Carry/Reload
COMP0
PSEL.OUT[0]
COMP1
PSEL.OUT[1]
COMP2
PSEL.OUT[2]
COMP3
PSEL.OUT[3]
Wave Counter
PWM_CLK
COUNTERTOP
PRESCALER
Figure 143: PWM Module
47.1 Wave counter
The wave counter is responsible for generating the pulses at a duty-cycle that depends on the compare
values, and at a frequency that depends on COUNTERTOP.
There is one common 15-bit counter with four compare channels. Thus, all four channels will share the same
period (PWM frequency), but can have individual duty-cycle and polarity. The polarity is set by the value
read from RAM (see Figure 146: Decoder memory access modes on page 502), while the MODE register
controls if the counter counts up, or up and down. The timer top value is controlled by the COUNTERTOP
register. This register value in conjunction with the selected PRESCALER of the PWM_CLK will result in a
given PWM period. A COUNTERTOP value smaller than the compare setting will result in a state where no
PWM edges are generated. Respectively, OUT[n] is held high, given that the polarity is set to FallingEdge.
All the compare registers are internal and can only be configured through the decoder presented later.
COUNTERTOP can be safely written at any time. It will get sampled following a START task. If
DECODER.LOAD is anything else than WaveForm, it will also get sampled following a STARTSEQ[n] task,
Page 499
47 PWM — Pulse width modulation
and when loading a new value from RAM during a sequence playback. If DECODER.LOAD=WaveForm, the
register value is ignored, and taken from RAM instead (see Decoder with EasyDMA on page 502 below).
Figure 144: PWM up counter example - FallingEdge polarity on page 500 shows the counter operating in
up (MODE=PWM_MODE_Up) mode with three PWM channels with the same frequency but different duty
cycle. The counter is automatically reset to zero when COUNTERTOP is reached and OUT[n] will invert.
OUT[n] is held low if the compare value is 0 and held high respectively if set to COUNTERTOP given that the
polarity is set to FallingEdge. Running in up counter mode will result in pulse widths that are edge-aligned.
See the code example below:
uint16_t pwm_seq[4] = {PWM_CH0_DUTY, PWM_CH1_DUTY, PWM_CH2_DUTY,
PWM_CH3_DUTY};
NRF_PWM0->PSEL.OUT[0] = (first_pin PSEL.OUT[0] = (first_pin OUT. PWM
generation can then only be restarted through a SEQSTART[n] task. SEQSTART[n] will resume PWM
generation after having loaded the first value from the RAM buffer defined in the SEQ[n].PTR register.
The table below provides indication of when specific registers get sampled by the hardware. Care should be
taken when updating these registers to avoid values to be applied earlier than expected.
Table 119: When to safely update PWM registers
Register
SEQ[n].PTR
SEQ[n].CNT
SEQ[0].ENDDELAY
SEQ[1].ENDDELAY
Taken into account by hardware
When sending the SEQSTART[n] task
When sending the SEQSTART[n] task
When sending the SEQSTART[0] task
Recommended (safe) update
After having received the SEQSTARTED[n] event
After having received the SEQSTARTED[n] event
Before starting sequence [0] through a SEQSTART[0] task
Every time a new value from sequence [0] has been loaded from
RAM and gets applied to the Wave Counter (indicated by the
PWMPERIODEND event)
When no more value from sequence [0] gets loaded from RAM
(indicated by the SEQEND[0] event)
When sending the SEQSTART[1] task
Every time a new value from sequence [1] has been loaded from
RAM and gets applied to the Wave Counter (indicated by the
PWMPERIODEND event)
At any time during sequence [1] (which starts when the SEQSTARTED[1]
event is fired)
Before starting sequence [1] through a SEQSTART[1] task
When no more value from sequence [1] gets loaded from RAM
(indicated by the SEQEND[1] event)
At any time during sequence [0] (which starts when the SEQSTARTED[0]
event is fired)
Before starting sequence [0] through a SEQSTART[0] task
SEQ[0].REFRESH
When sending the SEQSTART[0] task
At any time during sequence [1] (which starts when the SEQSTARTED[1]
event is fired)
SEQ[1].REFRESH
Every time a new value from sequence [0] has been loaded from
RAM and gets applied to the Wave Counter (indicated by the
PWMPERIODEND event)
When sending the SEQSTART[1] task
At any time during sequence [0] (which starts when the SEQSTARTED[0]
event is fired)
COUNTERTOP
Every time a new value from sequence [1] has been loaded from
RAM and gets applied to the Wave Counter (indicated by the
PWMPERIODEND event)
In DECODER.LOAD=WaveForm: this register is ignored.
MODE
In all other LOAD modes: at the end of current PWM period (indicated
by the PWMPERIODEND event)
Immediately
After a STOP task has been issued, and the STOPPED event has been
received.
Before starting PWM generation through a SEQSTART[n] task
Immediately
After a STOP task has been issued, and the STOPPED event has been
received.
Before starting PWM generation through a SEQSTART[n] task
Immediately
After a STOP task has been issued, and the STOPPED event has been
received.
Before starting PWM generation through a SEQSTART[n] task
Immediately
After a STOP task has been issued, and the STOPPED event has been
received.
Before starting PWM generation through a SEQSTART[n] task
Immediately
After a STOP task has been issued, and the STOPPED event has been
received.
Before enabling the PWM instance through the ENABLE register
DECODER
PRESCALER
LOOP
PSEL.OUT[n]
Before starting sequence [1] through a SEQSTART[1] task
Before starting PWM generation through a SEQSTART[n] task
Important: SEQ[n].REFRESH and SEQ[n].ENDDELAY are ignored at the end of a complex
sequence, indicated by a LOOPSDONE event. The reason for this is that the last value loaded from
RAM is maintained until further action from software (restarting a new sequence, or stopping PWM
generation).
Page 503
47 PWM — Pulse width modulation
Figure 147: Simple sequence example on page 504 depicts the source code used for configuration and
timing details in a sequence where only sequence 0 is used and only run once with a new PWM duty cycle
for each period.
NRF_PWM0->PSEL.OUT[0] = (first_pin TASKS_SEQSTART[0] = 1;
SEQ[0].CNT=4, SEQ[0].REFRESH=0, SEQ[0].ENDDELAY=0, LOOP.CNT=0
SEQ[0].PTR
Event/Tasks
SEQSTART[0]
P
COMPARE
O
0
L
P
COMPARE
O
1
L
P
COMPARE
O
2
L
Continues With Last Setting
P
COMPARE
O
3
L
PWM Pulse Period
SEQSTARTED[0]
SEQEND[0]
Figure 147: Simple sequence example
A more complex example is shown in Figure 148: Example using two sequences on page 505, where
LOOP.CNT>0 . In this case, an automated playback takes place, consisting of SEQ[0], delay 0, SEQ[1],
delay 1, then again SEQ[0], etc. The user can choose to start a complex playback with SEQ[0] or SEQ[1]
through sending the SEQSTART[0] or SEQSTART[1] task.
The complex playback always ends with delay 1.
The two sequences 0 and 1 are defined with address of values tables in Data RAM (pointed by SEQ[n].PTR)
and respective buffer size (SEQ[n].CNT). The rate at which a new value is loaded is defined individually
for each sequence by SEQ[n].REFRESH . The chaining of sequence 1 following sequence 0 is implicit, the
LOOP.CNT register allows the chaining of sequence 1 to sequence 0 for a determined number of times. In
other words, it allows to repeat a complex sequence a number of times in a fully automated way.
In the example below, sequence 0 is defined with SEQ[0].REFRESH set to one - that means that a
new PWM duty cycle is pushed every second PWM period. This complex sequence is started with the
SEQSTART[0] task, so SEQ[0] is played first. Since SEQ[0].ENDDELAY=1 there will be one PWM period
delay between last period on sequence 0 and the first period on sequence 1. Since SEQ[1].ENDDELAY=0
there is no delay 1, so SEQ[0] would be started immediately after the end of SEQ[1]. However, as
LOOP.CNT is one, the playback stops after having played only once SEQ[1], and both SEQEND[1] and
LOOPSDONE are generated (their order is not guaranteed in this case).
Page 504
47 PWM — Pulse width modulation
NRF_PWM0->PSEL.OUT[0] = (first_pin SEQ[1].PTR = ((uint32_t)(seq1_ram) SEQ[1].CNT = ((sizeof(seq1_ram) / sizeof(uint16_t)) SEQ[1].REFRESH = 0;
NRF_PWM0->SEQ[1].ENDDELAY = 0;
NRF_PWM0->TASKS_SEQSTART[0] = 1;
SEQ[0].CNT=2, SEQ[1].CNT=3, SEQ[0].REFRESH=1, SEQ[1].REFRESH=0, SEQ[0].ENDDELAY=1, SEQ[1].ENDDELAY=0, LOOP.CNT=1
SEQ[0].PTR
Event/Tasks
SEQSTART[0]
P
O COMPARE
L
P
O COMPARE
L
PWM Clock Period
(continued below)
SEQSTARTED[0]
SEQEND[0]
SEQ[1].PTR
1 PWM period
SEQ[0].ENDDELAY=1
(continuation)
P
O COMPARE
L
P
O COMPARE
L
PWM Generation maintains
last played value
Event/Tasks
SEQSTARTED[1]
SEQEND[1]
LOOPSDONE
Figure 148: Example using two sequences
The decoder can also be configured to asynchronously load a new PWM duty cycle. If the DECODER.MODE
register is set to NextStep - then the NEXTSTEP task will cause an update of the internal compare registers
on the next PWM period.
The figures below provide an overview of each part of an arbitrary sequence, in various modes
(LOOP.CNT=0 and LOOP.CNT>0). In particular are represented:
•
•
•
•
•
Initial and final duty cycle on the PWM output(s)
Chaining of SEQ[0] and SEQ[1] if LOOP.CNT>0
Influence of registers on the sequence
Events fired during a sequence
DMA activity (loading of next value and applying it to the output(s))
Note that the single-shot example applies also to SEQ[1], only SEQ[0] is represented for simplicity.
Page 505
Page 506
Figure 150: Complex sequence (LOOP.CNT>0) starting with SEQ[0]
SEQ[1].ENDDELA
Y
SEQ[1].CNT
SEQ[0].ENDDELA
Y
SEQ[0].CNT
SEQ[1].CNT
(LOOP.CNT - 1) ...
EVENTS_SEQSTARTED[1]
EVENTS_SEQEND[1]
EVENTS_LOOPSDONE
EVENTS_SEQEND[0]
EVENTS_SEQSTARTED[0]
EVENTS_SEQSTARTED[1]
EVENTS_SEQEND[1]
SEQ[0].ENDDELA
Y
SEQ[0].CNT
SEQ[1].ENDDELA
Y
SEQ[1].CNT
LOOP.CNT
EVENTS_SEQEND[0]
EVENTS_SEQSTARTED[0]
EVENTS_SEQSTARTED[1]
EVENTS_SEQEND[1]
SEQ[0].ENDDELA
Y
SEQ[0].CNT
Loop counter
EVENTS_SEQEND[0]
TASKS_SEQSTART[0]
EVENTS_SEQSTARTED[0]
EVENTS_SEQEND[0]
TASKS_SEQSTART[0]
EVENTS_SEQSTARTED[0]
SEQ[0].ENDDELA
Y
SEQ[0].CNT
47 PWM — Pulse width modulation
100% duty cycle
last loaded
duty cycle
maintained
Previously
loaded duty
cycle
New value load
0% duty cycle
Figure 149: Single shot (LOOP.CNT=0)
1
100% duty cycle
Previously
loaded duty
cycle
last loaded
duty cycle
maintained
New value load
0% duty cycle
47 PWM — Pulse width modulation
SEQ[1].ENDDELA
Y
SEQ[1].CNT
SEQ[0].ENDDELA
Y
SEQ[0].CNT
1
SEQ[1].CNT
SEQ[0].ENDDELA
Y
(LOOP.CNT - 1) ...
SEQ[0].CNT
SEQ[1].CNT
SEQ[1].ENDDELA
Y
LOOP.CNT
Loop counter
100% duty cycle
Previously
loaded
duty cycle
last loaded
duty cycle
maintained
0% duty cycle
EVENTS_SEQSTARTED[1]
EVENTS_SEQEND[1]
EVENTS_LOOPSDONE
EVENTS_SEQEND[0]
EVENTS_SEQSTARTED[0]
EVENTS_SEQSTARTED[1]
EVENTS_SEQEND[1]
EVENTS_SEQEND[0]
EVENTS_SEQSTARTED[0]
TASKS_SEQSTART[1]
EVENTS_SEQSTARTED[1]
EVENTS_SEQEND[1]
New value load
Figure 151: Complex sequence (LOOP.CNT>0) starting with SEQ[1]
Note that if a sequence is in use in a simple or complex sequence, it must have a length of SEQ[n].CNT > 0 .
47.3 Limitations
The previous compare value will be repeated if the PWM period is selected to be shorter than the time it
takes for the EasyDMA to fetch from RAM and update the internal compare registers.
This is to ensure a glitch-free operation even if very short PWM periods are chosen.
47.4 Pin configuration
The OUT[n] (n=0..3) signals associated to each channel of the PWM module are mapped to
physical pins according to the configuration specified in the respective PSEL.OUT[n] registers. If a
PSEL.OUT[n].CONNECT is set to Disconnected, the associated PWM module signal will not be connected
to any physical pins.
The PSEL.OUT[n] registers and their configurations are only used as long as the PWM module is enabled
and PWM generation is active (wave counter started), and retained only as long as the device is in System
ON mode, see POWER chapter for more information about power modes.
To ensure correct behaviour in the PWM module, the pins used by the PWM module must be configured in
the GPIO peripheral as described in Table 120: Recommended GPIO configuration before starting PWM
generation on page 508 before enabling the PWM module. The pins' idle state is defined by the OUT
registers in the GPIO module. This is to ensure that the pins used by the PWM module are driven correctly,
if PWM generation is stopped through a STOP task, the PWM module itself is temporarily disabled, or the
device temporarily enters System OFF. This configuration must be retained in the GPIO for the selected IOs
as long as the PWM module is supposed to be connected to an external PWM circuit.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behaviour.
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47 PWM — Pulse width modulation
Table 120: Recommended GPIO configuration before starting PWM generation
PWM signal
OUT[n]
PWM pin
As specified in PSEL.OUT[n]
(n=0..3)
Direction
Output
Output value
0
Comment
Idle state defined in GPIO->OUT
47.5 Registers
Table 121: Instances
Base address
Peripheral
Instance
Description
0x4001C000
PWM
PWM0
Pulse Width Modulation Unit 0
0x40021000
PWM
PWM1
Pulse Width Modulation Unit 1
0x40022000
PWM
PWM2
Pulse Width Modulation Unit 2
Configuration
Table 122: Register Overview
Register
Offset
Description
TASKS_STOP
0x004
Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence
TASKS_SEQSTART[0]
0x008
playback
Loads the first PWM value on all enabled channels from sequence 0, and starts playing that
sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to
start it was not running.
TASKS_SEQSTART[1]
0x00C
Loads the first PWM value on all enabled channels from sequence 1, and starts playing that
sequence at the rate defined in SEQ[1]REFRESH and/or DECODER.MODE. Causes PWM generation to
start it was not running.
TASKS_NEXTSTEP
0x010
EVENTS_STOPPED
0x104
Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep.
Does not cause PWM generation to start it was not running.
Response to STOP task, emitted when PWM pulses are no longer generated
EVENTS_SEQSTARTED[0] 0x108
First PWM period started on sequence 0
EVENTS_SEQSTARTED[1] 0x10C
First PWM period started on sequence 1
EVENTS_SEQEND[0]
0x110
Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter
EVENTS_SEQEND[1]
0x114
Emitted at end of every sequence 1, when last value from RAM has been applied to wave counter
EVENTS_PWMPERIODEND0x118
Emitted at the end of each PWM period
EVENTS_LOOPSDONE
0x11C
Concatenated sequences have been played the amount of times defined in LOOP.CNT
SHORTS
0x200
Shortcut register
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ENABLE
0x500
PWM module enable register
MODE
0x504
Selects operating mode of the wave counter
COUNTERTOP
0x508
Value up to which the pulse generator counter counts
PRESCALER
0x50C
Configuration for PWM_CLK
DECODER
0x510
Configuration of the decoder
LOOP
0x514
Amount of playback of a loop
SEQ[0].PTR
0x520
Beginning address in Data RAM of this sequence
SEQ[0].CNT
0x524
Amount of values (duty cycles) in this sequence
SEQ[0].REFRESH
0x528
Amount of additional PWM periods between samples loaded into compare register
SEQ[0].ENDDELAY
0x52C
Time added after the sequence
SEQ[1].PTR
0x540
Beginning address in Data RAM of this sequence
SEQ[1].CNT
0x544
Amount of values (duty cycles) in this sequence
SEQ[1].REFRESH
0x548
Amount of additional PWM periods between samples loaded into compare register
SEQ[1].ENDDELAY
0x54C
Time added after the sequence
PSEL.OUT[0]
0x560
Output pin select for PWM channel 0
PSEL.OUT[1]
0x564
Output pin select for PWM channel 1
PSEL.OUT[2]
0x568
Output pin select for PWM channel 2
PSEL.OUT[3]
0x56C
Output pin select for PWM channel 3
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47 PWM — Pulse width modulation
47.5.1 SHORTS
Address offset: 0x200
Shortcut register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
E D C B A
Reset 0x00000000
Id
RW Field
A
RW SEQEND0_STOP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Shortcut between SEQEND[0] event and STOP task
See EVENTS_SEQEND[0] and TASKS_STOP
B
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW SEQEND1_STOP
Shortcut between SEQEND[1] event and STOP task
See EVENTS_SEQEND[1] and TASKS_STOP
C
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW LOOPSDONE_SEQSTART0
Shortcut between LOOPSDONE event and SEQSTART[0] task
See EVENTS_LOOPSDONE and TASKS_SEQSTART[0]
D
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW LOOPSDONE_SEQSTART1
Shortcut between LOOPSDONE event and SEQSTART[1] task
See EVENTS_LOOPSDONE and TASKS_SEQSTART[1]
E
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW LOOPSDONE_STOP
Shortcut between LOOPSDONE event and STOP task
See EVENTS_LOOPSDONE and TASKS_STOP
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
47.5.2 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G F E D C B
Reset 0x00000000
Id
RW Field
B
RW STOPPED
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Enable or disable interrupt for STOPPED event
See EVENTS_STOPPED
C
Disabled
0
Disable
Enabled
1
Enable
RW SEQSTARTED0
Enable or disable interrupt for SEQSTARTED[0] event
See EVENTS_SEQSTARTED[0]
D
Disabled
0
Disable
Enabled
1
Enable
RW SEQSTARTED1
Enable or disable interrupt for SEQSTARTED[1] event
See EVENTS_SEQSTARTED[1]
E
Disabled
0
Disable
Enabled
1
Enable
RW SEQEND0
Enable or disable interrupt for SEQEND[0] event
See EVENTS_SEQEND[0]
F
Disabled
0
Disable
Enabled
1
Enable
RW SEQEND1
Enable or disable interrupt for SEQEND[1] event
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47 PWM — Pulse width modulation
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G F E D C B
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable
Enabled
1
Enable
See EVENTS_SEQEND[1]
G
RW PWMPERIODEND
Enable or disable interrupt for PWMPERIODEND event
See EVENTS_PWMPERIODEND
H
Disabled
0
Disable
Enabled
1
Enable
RW LOOPSDONE
Enable or disable interrupt for LOOPSDONE event
See EVENTS_LOOPSDONE
Disabled
0
Disable
Enabled
1
Enable
47.5.3 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G F E D C B
Reset 0x00000000
Id
RW Field
B
RW STOPPED
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for STOPPED event
See EVENTS_STOPPED
C
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SEQSTARTED0
Write '1' to Enable interrupt for SEQSTARTED[0] event
See EVENTS_SEQSTARTED[0]
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SEQSTARTED1
Write '1' to Enable interrupt for SEQSTARTED[1] event
See EVENTS_SEQSTARTED[1]
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SEQEND0
Write '1' to Enable interrupt for SEQEND[0] event
See EVENTS_SEQEND[0]
F
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SEQEND1
Write '1' to Enable interrupt for SEQEND[1] event
See EVENTS_SEQEND[1]
G
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PWMPERIODEND
Write '1' to Enable interrupt for PWMPERIODEND event
See EVENTS_PWMPERIODEND
H
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW LOOPSDONE
Write '1' to Enable interrupt for LOOPSDONE event
Page 510
47 PWM — Pulse width modulation
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G F E D C B
Reset 0x00000000
Id
RW Field
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
See EVENTS_LOOPSDONE
47.5.4 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
H G F E D C B
Reset 0x00000000
Id
RW Field
B
RW STOPPED
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for STOPPED event
See EVENTS_STOPPED
C
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SEQSTARTED0
Write '1' to Disable interrupt for SEQSTARTED[0] event
See EVENTS_SEQSTARTED[0]
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SEQSTARTED1
Write '1' to Disable interrupt for SEQSTARTED[1] event
See EVENTS_SEQSTARTED[1]
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SEQEND0
Write '1' to Disable interrupt for SEQEND[0] event
See EVENTS_SEQEND[0]
F
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW SEQEND1
Write '1' to Disable interrupt for SEQEND[1] event
See EVENTS_SEQEND[1]
G
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW PWMPERIODEND
Write '1' to Disable interrupt for PWMPERIODEND event
See EVENTS_PWMPERIODEND
H
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW LOOPSDONE
Write '1' to Disable interrupt for LOOPSDONE event
See EVENTS_LOOPSDONE
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
47.5.5 ENABLE
Address offset: 0x500
Page 511
47 PWM — Pulse width modulation
PWM module enable register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disabled
Enabled
1
Enable
Enable or disable PWM module
47.5.6 MODE
Address offset: 0x504
Selects operating mode of the wave counter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW UPDOWN
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Up
0
Up counter - edge aligned PWM duty-cycle
UpAndDown
1
Up and down counter - center aligned PWM duty cycle
Selects up or up and down as wave counter mode
47.5.7 COUNTERTOP
Address offset: 0x508
Value up to which the pulse generator counter counts
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A
Reset 0x000003FF
Id
RW Field
A
RW COUNTERTOP
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Value
Description
[3..32767]
Value up to which the pulse generator counter counts. This
register is ignored when DECODER.MODE=WaveForm and only
values from RAM will be used.
47.5.8 PRESCALER
Address offset: 0x50C
Configuration for PWM_CLK
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A
Reset 0x00000000
Id
RW Field
A
RW PRESCALER
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
DIV_1
0
Divide by 1 (16MHz)
DIV_2
1
Divide by 2 ( 8MHz)
DIV_4
2
Divide by 4 ( 4MHz)
DIV_8
3
Divide by 8 ( 2MHz)
DIV_16
4
Divide by 16 ( 1MHz)
DIV_32
5
Divide by 32 ( 500kHz)
DIV_64
6
Divide by 64 ( 250kHz)
DIV_128
7
Divide by 128 ( 125kHz)
Pre-scaler of PWM_CLK
47.5.9 DECODER
Address offset: 0x510
Configuration of the decoder
Page 512
47 PWM — Pulse width modulation
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
B
Reset 0x00000000
Id
RW Field
A
RW LOAD
0
Value Id
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
How a sequence is read from RAM and spread to the compare
register
Common
0
1st half word (16-bit) used in all PWM channels 0..3
Grouped
1
1st half word (16-bit) used in channel 0..1; 2nd word in channel
Individual
2
1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3
WaveForm
3
1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in
2..3
COUNTERTOP
B
RW MODE
Selects source for advancing the active sequence
RefreshCount
0
NextStep
1
SEQ[n].REFRESH is used to determine loading internal compare
registers
NEXTSTEP task causes a new value to be loaded to internal
compare registers
47.5.10 LOOP
Address offset: 0x514
Amount of playback of a loop
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CNT
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Disabled
0
Description
Amount of playback of pattern cycles
Looping disabled (stop at the end of the sequence)
47.5.11 SEQ[0].PTR
Address offset: 0x520
Beginning address in Data RAM of this sequence
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Beginning address in Data RAM of this sequence
47.5.12 SEQ[0].CNT
Address offset: 0x524
Amount of values (duty cycles) in this sequence
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CNT
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Disabled
0
Description
Amount of values (duty cycles) in this sequence
Sequence is disabled, and shall not be started as it is empty
47.5.13 SEQ[0].REFRESH
Address offset: 0x528
Amount of additional PWM periods between samples loaded into compare register
Page 513
47 PWM — Pulse width modulation
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000001
Id
RW Field
A
RW CNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value
Description
Amount of additional PWM periods between samples loaded
into compare register (load every REFRESH.CNT+1 PWM
periods)
Continuous
0
Update every PWM period
47.5.14 SEQ[0].ENDDELAY
Address offset: 0x52C
Time added after the sequence
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Time added after the sequence in PWM periods
47.5.15 SEQ[1].PTR
Address offset: 0x540
Beginning address in Data RAM of this sequence
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW PTR
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Beginning address in Data RAM of this sequence
47.5.16 SEQ[1].CNT
Address offset: 0x544
Amount of values (duty cycles) in this sequence
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CNT
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Disabled
0
Description
Amount of values (duty cycles) in this sequence
Sequence is disabled, and shall not be started as it is empty
47.5.17 SEQ[1].REFRESH
Address offset: 0x548
Amount of additional PWM periods between samples loaded into compare register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000001
Id
RW Field
A
RW CNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value
Description
Amount of additional PWM periods between samples loaded
into compare register (load every REFRESH.CNT+1 PWM
periods)
Continuous
0
Update every PWM period
47.5.18 SEQ[1].ENDDELAY
Address offset: 0x54C
Page 514
47 PWM — Pulse width modulation
Time added after the sequence
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW CNT
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Time added after the sequence in PWM periods
47.5.19 PSEL.OUT[0]
Address offset: 0x560
Output pin select for PWM channel 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
C
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
47.5.20 PSEL.OUT[1]
Address offset: 0x564
Output pin select for PWM channel 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
C
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
47.5.21 PSEL.OUT[2]
Address offset: 0x568
Output pin select for PWM channel 2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
C
RW CONNECT
Value Id
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
47.5.22 PSEL.OUT[3]
Address offset: 0x56C
Output pin select for PWM channel 3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
A
RW PIN
Value Id
Value
Description
[0..31]
Pin number
Page 515
47 PWM — Pulse width modulation
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C
A A A A A
Reset 0xFFFFFFFF
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id
RW Field
C
RW CONNECT
Value Id
Value
Description
Disconnected
1
Disconnect
Connected
0
Connect
Connection
47.6 Electrical specification
47.6.1 PWM Electrical Specification
Symbol
Description
IPWM,16MHz
PWM run current, Prescaler set to DIV_1 (16 MHz), excluding
Min.
Typ.
Max.
Units
200
µA
150
µA
150
µA
DMA and GPIO
IPWM,8MHz
PWM run current, Prescaler set to DIV_2 (8 MHz), excluding
DMA and GPIO
IPWM,125kHz
PWM run current, Prescaler set to DIV_128 (125 kHz), excluding
DMA and GPIO
Page 516
48 SPI — Serial peripheral interface master
48 SPI — Serial peripheral interface master
The SPI master provides a simple CPU interface which includes a TXD register for sending data and an RXD
register for receiving data. This section is added for legacy support for now.
PSEL.MISO
MISO
PSEL.SCK
PSEL.MOSI
RXD-1
TXD+1
RXD
TXD
MOSI
READY
Figure 152: SPI master
RXD-1 and TXD+1 illustrate the double buffered version of RXD and TXD respectively.
48.1 Functional description
The TXD and RXD registers are double-buffered to enable some degree of uninterrupted data flow in and
out of the SPI master.
The SPI master does not implement support for chip select directly. Therefore, the CPU must use available
GPIOs to select the correct slave and control this independently of the SPI master. The SPI master supports
SPI modes 0 through 3.
Table 123: SPI modes
Mode
Clock polarity
CPOL
SPI_MODE00 (Leading)
SPI_MODE10 (Leading)
SPI_MODE21 (Trailing)
SPI_MODE31 (Trailing)
Clock phase
CPHA
0 (Active High)
1 (Active Low)
0 (Active High)
1 (Active Low)
48.1.1 SPI master mode pin configuration
The different signals SCK, MOSI, and MISO associated with the SPI master are mapped to physical pins.
This mapping is according to the configuration specified in the PSELSCK, PSELMOSI, and PSELMISO
registers respectively. If a value of 0xFFFFFFFF is specified in any of these registers, the associated SPI
master signal is not connected to any physical pin. The PSELSCK, PSELMOSI, and PSELMISO registers
and their configurations are only used as long as the SPI master is enabled, and retained only as long as
the device is in ON mode. PSELSCK, PSELMOSI, and PSELMISO must only be configured when the SPI
master is disabled.
To secure correct behavior in the SPI, the pins used by the SPI must be configured in the GPIO peripheral
as described in Table 124: GPIO configuration on page 518 prior to enabling the SPI. The SCK must
Page 517
48 SPI — Serial peripheral interface master
always be connected to a pin, and that pin's input buffer must always be connected for the SPI to work. This
configuration must be retained in the GPIO for the selected IOs as long as the SPI is enabled.
Only one peripheral can be assigned to drive a particular GPIO pin at a time, failing to do so may result in
unpredictable behavior.
Table 124: GPIO configuration
SPI master signal
SCK
MOSI
MISO
SPI master pin
As specified in PSELSCK
As specified in PSELMOSI
As specified in PSELMISO
Direction
Output
Output
Input
Output value
Same as CONFIG.CPOL
0
Not applicable
48.1.2 Shared resources
The SPI shares registers and other resources with other peripherals that have the same ID as the SPI.
Therefore, the user must disable all peripherals that have the same ID as the SPI before the SPI can be
configured and used.
Disabling a peripheral that has the same ID as the SPI will not reset any of the registers that are shared with
the SPI. It is therefore important to configure all relevant SPI registers explicitly to secure that it operates
correctly.
See the Instantiation table in Instantiation on page 25 for details on peripherals and their IDs.
48.1.3 SPI master transaction sequence
An SPI master transaction is started by writing the first byte, which is to be transmitted by the SPI master, to
the TXD register.
Since the transmitter is double buffered, the second byte can be written to the TXD register immediately after
the first one. The SPI master will then send these bytes in the order they are written to the TXD register.
The SPI master is a synchronous interface, and for every byte that is sent, a different byte will be received at
the same time; this is illustrated in Figure 153: SPI master transaction on page 519. Bytes that are received
will be moved to the RXD register where the CPU can extract them by reading the register. The RXD register
is double buffered in the same way as the TXD register, and a second byte can therefore be received at the
same time as the first byte is being extracted from RXD by the CPU. The SPI master will generate a READY
event every time a new byte is moved to the RXD register. The double buffered byte will be moved from
RXD-1 to RXD as soon as the first byte is extracted from RXD. The SPI master will stop when there are no
more bytes to send in TXD and TXD+1.
Page 518
48 SPI — Serial peripheral interface master
CSN
n-1
n
MISO
A
B
C
m-2
m-1
m
6
7
m-1 = RXD
m = RXD
TXD = n
5
m-2 = RXD
C = RXD
4
TXD = n-1
B = RXD
TXD = 2
TXD = 1
3
TXD = n-2
2
A = RXD
1
TXD = 0
CPU
READY
n-2
READY
2
READY
1
READY
0
READY
MOSI
READY
SCK
Figure 153: SPI master transaction
The READY event of the third byte transaction is delayed until B is extracted from RXD in occurrence
number 3 on the horizontal lifeline. The reason for this is that the third event is generated first when C is
moved from RXD-1 to RXD after B is read.
CSN
SCK
MOSI (CPHA=1)
1
Figure 154: SPI master transaction
Page 519
READY
MISO
Lifeline
READY
Lifeline
MISO
MOSI
SCK
(CPHA=0)
CSN
The SPI master will move the incoming byte to the RXD register after a short delay following the SCK clock
period of the last bit in the byte. This also means that the READY event will be delayed accordingly, see
Figure 154: SPI master transaction on page 519. Therefore, it is important that you always clear the
READY event, even if the RXD register and the data that is being received is not used.
1
48 SPI — Serial peripheral interface master
48.2 Registers
Table 125: Instances
Base address
Peripheral
Instance
Description
0x40003000
SPI
SPI0
SPI master 0
Configuration
Deprecated
0x40004000
SPI
SPI1
SPI master 1
Deprecated
0x40023000
SPI
SPI2
SPI master 2
Deprecated
Table 126: Register Overview
Register
Offset
Description
EVENTS_READY
0x108
TXD byte sent and RXD byte received
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ENABLE
0x500
Enable SPI
PSELSCK
0x508
Pin select for SCK
Deprecated
PSELMOSI
0x50C
Pin select for MOSI
Deprecated
PSELMISO
0x510
Pin select for MISO
Deprecated
PSEL.SCK
0x508
Pin select for SCK
PSEL.MOSI
0x50C
Pin select for MOSI
PSEL.MISO
0x510
Pin select for MISO
RXD
0x518
RXD register
TXD
0x51C
TXD register
FREQUENCY
0x524
SPI frequency
CONFIG
0x554
Configuration register
48.2.1 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Enable interrupt for READY event
See EVENTS_READY
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
48.2.2 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A
Reset 0x00000000
Id
RW Field
A
RW READY
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
Write '1' to Disable interrupt for READY event
See EVENTS_READY
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
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48 SPI — Serial peripheral interface master
48.2.3 ENABLE
Address offset: 0x500
Enable SPI
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A
Reset 0x00000000
Id
RW Field
A
RW ENABLE
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
Disabled
0
Disable SPI
Enabled
1
Enable SPI
Enable or disable SPI
48.2.4 PSELSCK ( Deprecated )
Address offset: 0x508
Pin select for SCK
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELSCK
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI SCK signal
0xFFFFFFFF
Disconnect
48.2.5 PSELMOSI ( Deprecated )
Address offset: 0x50C
Pin select for MOSI
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELMOSI
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI MOSI signal
0xFFFFFFFF
Disconnect
48.2.6 PSELMISO ( Deprecated )
Address offset: 0x510
Pin select for MISO
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELMISO
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI MISO signal
0xFFFFFFFF
Disconnect
48.2.7 PSEL.SCK
Address offset: 0x508
Pin select for SCK
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELSCK
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI SCK signal
0xFFFFFFFF
Disconnect
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48 SPI — Serial peripheral interface master
48.2.8 PSEL.MOSI
Address offset: 0x50C
Pin select for MOSI
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELMOSI
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI MOSI signal
0xFFFFFFFF
Disconnect
48.2.9 PSEL.MISO
Address offset: 0x510
Pin select for MISO
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
Id
RW Field
A
RW PSELMISO
1
Value Id
Disconnected
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value
Description
[0..31]
Pin number configuration for SPI MISO signal
0xFFFFFFFF
Disconnect
48.2.10 RXD
Address offset: 0x518
RXD register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
R
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
RXD
RX data received. Double buffered
48.2.11 TXD
Address offset: 0x51C
TXD register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A
Reset 0x00000000
Id
RW Field
A
RW TXD
0
Value Id
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value
Description
TX data to send. Double buffered
48.2.12 FREQUENCY
Address offset: 0x524
SPI frequency
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x04000000
Id
RW Field
A
RW FREQUENCY
0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
K125
0x02000000
125 kbps
K250
0x04000000
250 kbps
K500
0x08000000
500 kbps
M1
0x10000000
1 Mbps
SPI master data rate
Page 522
48 SPI — Serial peripheral interface master
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x04000000
Id
0
RW Field
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
M2
0x20000000
2 Mbps
M4
0x40000000
4 Mbps
M8
0x80000000
8 Mbps
48.2.13 CONFIG
Address offset: 0x554
Configuration register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id
C B A
Reset 0x00000000
Id
RW Field
A
RW ORDER
B
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value Id
Value
Description
MsbFirst
0
Most significant bit shifted out first
LsbFirst
1
Least significant bit shifted out first
Leading
0
Trailing
1
Bit order
RW CPHA
Serial clock (SCK) phase
Sample on leading edge of clock, shift serial data on trailing
edge
Sample on trailing edge of clock, shift serial data on leading
edge
C
RW CPOL
Serial clock (SCK) polarity
ActiveHigh
0
Active high
ActiveLow
1
Active low
48.3 Electrical specification
48.3.1 SPI master interface
Symbol
Description
Max.
Units
fSPI
Bit rates for SPI38
Min.
Typ.
839
Mbps
ISPI,2Mbps
Run current for SPI, 2 Mbps
50
µA
ISPI,8Mbps
Run current for SPI, 8 Mbps
50
µA
ISPI,IDLE
Idle current for SPI (STARTed, no CSN activity)
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