Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
DATASHEET
1
GD25Q128E
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
Contents
1
FEATURES .........................................................................................................................................................4
2
GENERAL DESCRIPTIONS..............................................................................................................................5
3
MEMORY ORGANIZATION ...............................................................................................................................9
4
DEVICE OPERATIONS.................................................................................................................................... 10
4.1
SPI MODE ............................................................................................................................................................ 10
4.2
HOLD FUNCTION ................................................................................................................................................... 10
4.3
RESET FUNCTION .................................................................................................................................................. 11
5
DATA PROTECTION ........................................................................................................................................ 12
6
STATUS REGISTER ........................................................................................................................................ 14
7
COMMAND DESCRIPTIONS .......................................................................................................................... 18
7.1
WRITE ENABLE (WREN) (06H) ................................................................................................................................ 21
7.2
WRITE DISABLE (WRDI) (04H) ................................................................................................................................ 21
7.3
READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H) .............................................................................................. 21
7.4
WRITE STATUS REGISTER (WRSR) (01H OR 31H OR 11H) ........................................................................................... 22
7.5
WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ................................................................................................. 22
7.6
READ DATA BYTES (READ) (03H)............................................................................................................................. 23
7.7
READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH) .............................................................................................. 23
7.8
DUAL OUTPUT FAST READ (3BH) .............................................................................................................................. 24
7.9
QUAD OUTPUT FAST READ (6BH) ............................................................................................................................. 25
7.10
DUAL I/O FAST READ (BBH) .................................................................................................................................... 25
7.11
QUAD I/O FAST READ (EBH) ................................................................................................................................... 26
7.12
SET BURST WITH WRAP (77H) ................................................................................................................................. 28
7.13
PAGE PROGRAM (PP) (02H) .................................................................................................................................... 28
7.14
QUAD PAGE PROGRAM (32H) .................................................................................................................................. 29
7.15
SECTOR ERASE (SE) (20H) ....................................................................................................................................... 30
7.16
32KB BLOCK ERASE (BE) (52H) ............................................................................................................................... 30
7.17
64KB BLOCK ERASE (BE) (D8H)............................................................................................................................... 31
7.18
CHIP ERASE (CE) (60/C7H) ..................................................................................................................................... 31
7.19
READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ................................................................................................... 32
7.20
READ IDENTIFICATION (RDID) (9FH) ......................................................................................................................... 32
7.21
READ UNIQUE ID (4BH) .......................................................................................................................................... 33
7.22
ERASE SECURITY REGISTERS (44H) ............................................................................................................................ 34
7.23
PROGRAM SECURITY REGISTERS (42H) ....................................................................................................................... 34
7.24
READ SECURITY REGISTERS (48H) ............................................................................................................................. 35
7.25
ENABLE RESET (66H) AND RESET (99H) ..................................................................................................................... 36
7.26
PROGRAM/ERASE SUSPEND (PES) (75H) ................................................................................................................... 36
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Uniform Sector
Dual and Quad Serial Flash
7.27
PROGRAM/ERASE RESUME (PER) (7AH) ................................................................................................................... 37
7.28
DEEP POWER-DOWN (DP) (B9H) ............................................................................................................................. 37
7.29
RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) ......................................................................... 38
7.30
READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH)................................................................................................. 38
ELECTRICAL CHARACTERISTICS .............................................................................................................. 40
8
8.1
POWER-ON TIMING ................................................................................................................................................ 40
8.2
INITIAL DELIVERY STATE ........................................................................................................................................... 40
8.3
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 40
8.4
CAPACITANCE MEASUREMENT CONDITIONS................................................................................................................. 41
8.5
DC CHARACTERISTICS .............................................................................................................................................. 42
8.6
AC CHARACTERISTICS .............................................................................................................................................. 45
ORDERING INFORMATION............................................................................................................................ 52
9
9.1
10
11
GD25Q128E
VALID PART NUMBERS ............................................................................................................................................ 53
PACKAGE INFORMATION ......................................................................................................................... 55
10.1
PACKAGE SOP8 208MIL ........................................................................................................................................ 55
10.2
PACKAGE SOP16 300MIL ...................................................................................................................................... 56
10.3
PACKAGE USON8 (4X4MM, 0.45MM THICKNESS) ....................................................................................................... 57
10.4
PACKAGE WSON8 (6X5MM) ................................................................................................................................... 58
10.5
PACKAGE WSON8 (8X6MM) ................................................................................................................................... 59
10.6
PACKAGE TFBGA-24BALL (4X6 BALL ARRAY) ............................................................................................................. 60
10.7
PACKAGE TFBGA-24BALL (5X5 BALL ARRAY) ............................................................................................................. 61
REVISION HISTORY .................................................................................................................................... 62
3
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
1 FEATURES
◆ 128M-bit Serial Flash
◆ Fast Program/Erase Speed
- 16M-Byte
- Page Program time: 0.5ms typical
- 256 Bytes per programmable page
- Sector Erase time: 45ms typical
- Block Erase time: 0.15s/0.25s typical
◆ Standard, Dual, Quad SPI
- Chip Erase time: 50s typical
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#, RESET#
- Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#, RESET#
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3, RESET#
◆ Flexible Architecture
- Uniform Sector of 4K-Byte
- Uniform Block of 32/64K-Byte
◆ High Speed Clock Frequency
◆ Low Power Consumption
- 133MHz for fast read with 30PF load
- Dual I/O Data transfer up to 266Mbits/s
- 14μA typical standby current
- Quad I/O Data transfer up to 532Mbits/s
- 1μA typical deep power down current
◆ Software/Hardware Write Protection
◆ Advanced Security Features
- Write protect all/portion of memory via software
- 128-bit Unique ID for each device
- Enable/Disable protection with WP# Pin
- Serial Flash Discoverable parameters (SFDP) register
- Top/Bottom Block protection
- 3x1024-Byte Security Registers With OTP Locks
◆ Endurance and Data Retention
◆ Single Power Supply Voltage
- Minimum 100,000 Program/Erase Cycles
- Full voltage range: 2.7-3.6V
- 20-year data retention typical
◆ Package Information
◆ Allows XiP (eXecute in Place) Operation
- SOP8 208mil
- High speed Read reduce overall XiP instruction fetch time
- SOP16 300mil
- Continuous Read with Wrap further reduce data latency to
- USON8 (4x4mm, 0.45mm thickness)
fill up SoC cache
- WSON8 (6x5mm)
- WSON8 (8x6mm)
- TFBGA-24ball (6x4 Ball Array)
- TFBGA-24ball (5x5 Ball Array)
4
Uniform Sector
Dual and Quad Serial Flash
2
GD25Q128E
GENERAL DESCRIPTIONS
The GD25Q128E (128M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and the Dual/Quad SPI:
Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), I/O3 (HOLD#/RESET#). The Dual I/O data is
transferred with speed of 266Mbit/s, and the Quad I/O data is transferred with speed of 532Mbit/s.
CONNECTION DIAGRAM
CS#
1
8
VCC
CS#
1
8
SO
(IO1)
2
7
HOLD#/
RESET#
(IO3)
SO
(IO1)
2
HOLD#/
7 RESET#
(IO3)
3
6
SCLK
4
5
SI
(IO0)
Top View
WP#
(IO2)
3
6
SCLK
WP#
(IO2)
VSS
4
5
SI
(IO0)
VSS
Top View
VCC
8 - LEAD USON/WSON
8 - LEAD SOP
Table 1. Pin Description for SOP8/DIP8/USON8/WSON8 Package
Pin No.
Pin Name
I/O
Description
1
CS#
I
2
SO (IO1)
I/O
Data Output (Data Input Output 1)
3
WP# (IO2)
I/O
Write Protect Input (Data Input Output 2)
4
VSS
5
SI (IO0)
I/O
6
SCLK
I
7
HOLD#/RESET# (IO3)
I/O
8
VCC
Chip Select Input
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold or Reset Input (Data Input Output 3)
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
HOLD#/
RESET#
(IO3)
1
16
SCLK
VCC
2
15
SI
(IO0)
DNU or
RESET#(1)
3
14
NC
13
NC
NC
4
Top View
NC
5
12
NC
NC
6
11
NC
CS#
7
10
VSS
SO
(IO1)
8
9
WP#
(IO2)
16-LEAD SOP
5
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
Table 2. Pin Description for SOP16 Package
Pin No.
Pin Name
I/O
Description
1
HOLD#/RESET# (IO3)
I/O
2
VCC
Power Supply
3
DNU
Do Not Use (It may connect to internal signal inside)
3(1)
RESET#
I
Reset Input
7
CS#
I
Chip Select Input
8
SO (IO1)
I/O
Data Output (Data Input Output 1)
9
WP# (IO2)
I/O
Write Protect Input (Data Input Output 2)
10
VSS
15
SI (IO0)
I/O
16
SCLK
I
Hold or Reset Input (Data Input Output 3)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Note:
1. Only for special order, Pin 3 of 16-LEAD SOP package is RESET# pin. Please contact GigaDevice for detail.
2. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
3. The DNU pin must be floating. It may connect to internal signal inside.
Top View
Top View
A2
A3
A4
NC
NC
DNU or
RESET#(1)
A2
A3
A4
A5
NC
NC
DNU or
RESET#(1)
NC
B1
B2
B3
B4
NC
SCLK
VSS
VCC
B1
B2
B3
B4
B5
NC
SCLK
VSS
VCC
NC
C1
C2
C3
C4
NC
CS#
NC
WP#
(IO2)
C1
C2
C3
C4
C5
D1
D2
D3
D4
NC
CS#
NC
WP#
(IO2)
NC
NC
SO
(IO1)
D3
D4
HOLD#/
SI(IO0) RESET#
(IO3)
D1
D2
NC
SO
(IO1)
HOLD#/
SI(IO0) RESET#
(IO3)
D5
NC
E1
E2
E3
E4
NC
NC
NC
NC
E1
E2
E3
E4
E5
NC
NC
NC
NC
NC
F1
F2
F3
F4
NC
NC
NC
NC
24-BALL TFBGA (5x5 ball array)
24-BALL TFBGA (6x4 ball array)
6
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
Table 3. Pin Description for TFBGA24 Package
Pin No.
Pin Name
I/O
Description
A4
DNU
A4(1)
RESET#
I
Reset Input
B2
SCLK
I
Serial Clock Input
B3
VSS
Ground
B4
VCC
Power Supply
C2
CS#
I
C4
WP# (IO2)
I/O
Write Protect Input (Data Input Output 2)
D2
SO (IO1)
I/O
Data Output (Data Input Output 1)
D3
SI (IO0)
I/O
Data Input (Data Input Output 0)
D4
HOLD#/RESET# (IO3)
I/O
Hold or Reset Input (Data Input Output 3)
Do Not Use (It may connect to internal signal inside)
Chip Select Input
Note:
1. Only for special order, Ball A4 of TFBGA-24 package is RESET# pin. Please contact GigaDevice for detail.
2. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
3. The DNU ball must be floating. It may connect to internal signal inside.
7
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
BLOCK DIAGRAM
Write Control
Logic
Status
Register
HOLD#/
RESET#
(IO3)
SCLK
SPI
Command &
Control Logic
High Voltage
Generators
Page Address
Latch/Counter
Write Protect Logic
and Row Decode
WP#(IO2)
Flash
Memory
CS#
Column Decode And
256-Byte Page Buffer
SI(IO0)
SO(IO1)
Byte Address
Latch/Counter
8
Uniform Sector
Dual and Quad Serial Flash
3
GD25Q128E
MEMORY ORGANIZATION
GD25Q128E
Each device has
Each block has
Each sector has
Each page has
16M
64/32K
4K
256
Bytes
64K
256/128
16
-
pages
4K
16/8
-
-
sectors
256/512
-
-
-
blocks
UNIFORM BLOCK SECTOR ARCHITECTURE
GD25Q128E 64K Bytes Block Sector Architecture
Block
255
254
……
……
2
1
0
Sector
Address range
4095
FFF000H
FFFFFFH
……
……
……
4080
FF0000H
FF0FFFH
4079
FEF000H
FEFFFFH
……
……
……
4064
FE0000H
FE0FFFH
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
47
02F000H
02FFFFH
……
……
……
32
020000H
020FFFH
31
01F000H
01FFFFH
……
……
……
16
010000H
010FFFH
15
00F000H
00FFFFH
……
……
……
0
000000H
000FFFH
9
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
4 DEVICE OPERATIONS
4.1
SPI Mode
Standard SPI
The GD25Q128E features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial
Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising
edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25Q128E supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH and
BBH) commands. These commands allow data to be transferred to or from the device at twice the rate of the standard SPI.
When using the Dual SPI commands, the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25Q128E supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O Fast Read” (6BH,
EBH) commands. These commands allow data to be transferred to or from the device at four times the rate of the standard
SPI. When using the Quad SPI commands, the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and the WP#
and HOLD#/RESET# pins become bidirectional I/O pins: IO2 and IO3. The Quad SPI commands require the non-volatile
Quad Enable bit (QE) in Status Register set to 1.
4.2
HOLD Function
The HOLD/RST bit is used to determine whether HOLD or RESET function should be implemented on the hardware pin for
8-pin packages. When HOLD/RST=0, the HOLD#/RESET# pin acts as HOLD# pin. The HOLD function is available when
QE=0. If QE=1, The HOLD function is disabled, and the HOLD#/RESET# pin acts as dedicated data I/O pin.
The HOLD# signal goes low to stop any serial communications with the device, except the operation of write status register,
programming, or erasing in progress.
The operation of HOLD needs CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low.
If SCLK is not low, HOLD operation will not start until SCLK is low. The HOLD condition ends on rising edge of HOLD#
signal with SCLK being low. If SCLK is not low, HOLD operation will not end until SCLK is low.
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation. If CS# is driven high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with the chip, the HOLD# must be at high
and then CS# must be at low.
Figure 1 HOLD Condition
CS#
SCLK
HOLD#
HOLD
HOLD
10
Uniform Sector
Dual and Quad Serial Flash
4.3
GD25Q128E
RESET Function
The HOLD/RST bit is used to determine whether HOLD or RESET function should be implemented on the hardware pin for
8-pin packages. When HOLD/RST=1, the HOLD#/RESET# pin acts as RESET# pin. The hardware RESET function is
available when QE=0. If QE=1, The RESET function is disabled, and the HOLD#/RESET# pin acts as dedicated data I/O
pin. For 16-pin and 24-ball packages, a dedicated RESET# is used to do the hardware RESET and it is independent of QE
bit setting. The RESET# pin goes low for a minimum period of tRLRH (1μs) will reset the flash. After reset cycle, the flash
is at the following states:
-Standby mode
-All the volatile bits will return to the default status as power on.
Figure 2 RESET Condition
CS#
RESET#
RESET
11
Uniform Sector
Dual and Quad Serial Flash
5
GD25Q128E
DATA PROTECTION
The GD25Q128E provide the following data protection methods:
◆
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up / Software Reset (66H+99H)
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
◆
Software Protection Mode: The Block Protect bits (BP4-BP0) define the section of the memory array that can be
read but not changed.
◆
Hardware Protection Mode: WP# goes low to protect the Block Protect bits (BP4-BP0) and the SRP bits (SRP1 and
SRP0).
◆
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command and Software Reset (66H+99H).
◆
Write Inhibit Voltage (VWI): Device would reset automatically when VCC is below a certain threshold VWI.
Table 4. GD25Q128E Protected area size (CMP=0)
Status Register Content
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
X
X
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
252 to 255
FC0000H-FFFFFFH
256KB
Upper 1/64
0
0
0
1
0
248 to 255
F80000H-FFFFFFH
512KB
Upper 1/32
0
0
0
1
1
240 to 255
F00000H-FFFFFFH
1MB
Upper 1/16
0
0
1
0
0
224 to 255
E00000H-FFFFFFH
2MB
Upper 1/8
0
0
1
0
1
192 to 255
C00000H-FFFFFFH
4MB
Upper 1/4
0
0
1
1
0
128 to 255
800000H-FFFFFFH
8MB
Upper 1/2
0
1
0
0
1
0 to 3
000000H-03FFFFH
256KB
Lower 1/64
0
1
0
1
0
0 to 7
000000H-07FFFFH
512KB
Lower 1/32
0
1
0
1
1
0 to 15
000000H-0FFFFFH
1MB
Lower 1/16
0
1
1
0
0
0 to 31
000000H-1FFFFFH
2MB
Lower 1/8
0
1
1
0
1
0 to 63
000000H-3FFFFFH
4MB
Lower 1/4
0
1
1
1
0
0 to 127
000000H-7FFFFFH
8MB
Lower 1/2
X
X
1
1
1
0 to 255
000000H-FFFFFFH
16MB
ALL
1
0
0
0
1
255
FFF000H-FFFFFFH
4KB
Top Block
1
0
0
1
0
255
FFE000H-FFFFFFH
8KB
Top Block
1
0
0
1
1
255
FFC000H-FFFFFFH
16KB
Top Block
1
0
1
0
X
255
FF8000H-FFFFFFH
32KB
Top Block
1
0
1
1
0
255
FF8000H-FFFFFFH
32KB
Top Block
1
1
0
0
1
0
000000H-000FFFH
4KB
Bottom Block
1
1
0
1
0
0
000000H-001FFFH
8KB
Bottom Block
12
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
1
1
0
1
1
0
000000H-003FFFH
16KB
Bottom Block
1
1
1
0
X
0
000000H-007FFFH
32KB
Bottom Block
1
1
1
1
0
0
000000H-007FFFH
32KB
Bottom Block
Table 5. GD25Q128E Protected area size (CMP=1)
Status Register Content
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
X
X
0
0
0
0 to 255
000000H-FFFFFFH
ALL
ALL
0
0
0
0
1
0 to 251
000000H-FBFFFFH
16128KB
Lower 63/64
0
0
0
1
0
0 to 247
000000H-F7FFFFH
15872KB
Lower 31/32
0
0
0
1
1
0 to 239
000000H-EFFFFFH
15MB
Lower 15/16
0
0
1
0
0
0 to 223
000000H-DFFFFFH
14MB
Lower 7/8
0
0
1
0
1
0 to 191
000000H-BFFFFFH
12MB
Lower 3/4
0
0
1
1
0
0 to 127
000000H-7FFFFFH
8MB
Lower 1/2
0
1
0
0
1
4 to 255
040000H-FFFFFFH
16128KB
Upper 63/64
0
1
0
1
0
8 to 255
080000H-FFFFFFH
15872KB
Upper 31/32
0
1
0
1
1
16 to 255
100000H-FFFFFFH
15MB
Upper 15/16
0
1
1
0
0
32 to 255
200000H-FFFFFFH
14MB
Upper 7/8
0
1
1
0
1
64 to 255
400000H-FFFFFFH
12MB
Upper 3/4
0
1
1
1
0
128 to 255
800000H-FFFFFFH
8MB
Upper 1/2
X
X
1
1
1
NONE
NONE
NONE
NONE
1
0
0
0
1
0 to 255
000000H-FFEFFFH
16380KB
L-4095/4096
1
0
0
1
0
0 to 255
000000H-FFDFFFH
16376KB
L-2047/2048
1
0
0
1
1
0 to 255
000000H-FFBFFFH
16368KB
L-1023/1024
1
0
1
0
X
0 to 255
000000H-FF7FFFH
16352KB
L-511/512
1
0
1
1
0
0 to 255
000000H-FF7FFFH
16352KB
L-511/512
1
1
0
0
1
0 to 255
001000H-FFFFFFH
16380KB
U-4095/4096
1
1
0
1
0
0 to 255
002000H-FFFFFFH
16376KB
U-2047/2048
1
1
0
1
1
0 to 255
004000H-FFFFFFH
16368KB
U-1023/1024
1
1
1
0
X
0 to 255
008000H-FFFFFFH
16352KB
U-511/512
1
1
1
1
0
0 to 255
008000H-FFFFFFH
16352KB
U-511/512
13
Uniform Sector
Dual and Quad Serial Flash
6
GD25Q128E
STATUS REGISTER
Table 6. Status Register-SR No.1
No.
Name
Description
Note
S7
SRP0
Status Register Protection Bit
Non-volatile writable
S6
BP4
Block Protect Bit
Non-volatile writable
S5
BP3
Block Protect Bit
Non-volatile writable
S4
BP2
Block Protect Bit
Non-volatile writable
S3
BP1
Block Protect Bit
Non-volatile writable
S2
BP0
Block Protect Bit
Non-volatile writable
S1
WEL
Write Enable Latch
Volatile, read only
S0
WIP
Erase/Write In Progress
Volatile, read only
Table 7. Status Register-SR No.2
No.
Name
Description
Note
S15
SUS1
Erase Suspend Bit
Volatile, read only
S14
CMP
Complement Protect Bit
Non-volatile writable
S13
LB3
Security Register Lock Bit
Non-volatile writable (OTP)
S12
LB2
Security Register Lock Bit
Non-volatile writable (OTP)
S11
LB1
Security Register Lock Bit
Non-volatile writable (OTP)
S10
SUS2
Program Suspend Bit
Volatile, read only
S9
QE
Quad Enable Bit
Non-volatile writable
S8
SRP1
Status Register Protection Bit
Non-volatile writable
Table 8. Status Register-SR No.3
No.
Name
Description
Note
S23
HOLD/RST
HOLD# or RESET# Function
Non-volatile writable
S22
DRV1
Output Driver Strength Bit
Non-volatile writable
S21
DRV0
Output Driver Strength Bit
Non-volatile writable
S20
Reserved
Reserved
Reserved
S19
Reserved
Reserved
Reserved
S18
Reserved
Reserved
Reserved
S17
Reserved
Reserved
Reserved
S16
DC
Dummy Configuration Bit
Non-volatile writable
The status and control bits of the Status Register are as follows:
WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When
WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means
the device is not in program/erase/write status register progress.
14
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write
Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase
command is accepted.
BP4, BP3, BP2, BP1, BP0 bits
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table 4&5)
becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect
(BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip
Erase (CE) command is executed, if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block Protect
(BP2, BP1, and BP0) bits are 1 and CMP=1.
SRP1, SRP0 bits
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits
control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1
SRP0
#WP
Status Register
0
0
X
Software Protected
0
1
0
Hardware Protected
0
1
1
Hardware Unprotected
1
0
X
1
1
X
Power Supply LockDown(1)(2)
One Time Program(2)
Description
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
WP#=0, the Status Register locked and cannot be written to.
WP#=1, the Status Register is unlocked and can be written to
after a Write Enable command, WEL=1.
Status Register is protected and cannot be written to again until
the next Power-Down, Power-Up cycle.
Status Register is permanently protected and cannot be written
to.
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact GigaDevice for details.
QE bit
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE
bit is set to 0 (Default) the WP# pin and HOLD#/RESET# pin are enable. When the QE pin is set to 1, the Quad IO2 and
IO3 pins are enabled. (It is best to set the QE bit to 0 to avoid short issues if the WP# or HOLD#/RESET# pin is tied directly
to the power supply or ground.)
LB3, LB2, LB1 bits
The LB3, LB2 and LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13, S12 and S11) that
provide the write protect control and status to the Security Registers. The default state of LB3, LB2 and LB1 bits are 0, the
security registers are unlocked. The LB3, LB2 and LB1 bits can be set to 1 individually using the Write Register instruction.
15
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
The LB3, LB2 and LB1 bits are One Time Programmable, once they are set to 1, the Security Registers will become readonly permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the BP4-BP0 bits to
provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The
default setting is CMP=0.
SUS1, SUS2 bits
The SUS1 and SUS2 bits are read only bits in the status register (S15 and S10) that are set to 1 after executing an
Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 bit to 1, and the Program Suspend will set
the SUS2 bit to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command, software reset
(66H+99H) command, as well as a power-down, power-up cycle.
DC bit
The Dummy Configuration (DC) bit is non-volatile, which selects the number of dummy cycles between the end of address
and the start of read data output. Dummy cycles provide additional latency that is needed to complete the initial read access
of the flash array before data can be returned to the host system. Some read commands require additional dummy cycles
as the SCLK frequency increases.
The following dummy cycle tables provide different dummy cycle settings that are configured.
Command
BBH
EBH
DC bit
Numbers of Dummy Cycles
Freq.(MHz)
0 (default)
4
104
1
8
133R
0 (default)
6
104
1
10
133R
Note:
1. “R” means VCC range=3.0V~3.6V.
Reserved bit
It is recommended to set the value of the reserved bit as “0”.
DRV1, DRV0 bits
The DRV1 and DRV0 bits are used to determine the output driver strength for the Read operations.
Table 9. Driver Strength for Read Operations
DRV1, DRV0
Driver Strength
00
100%
01
75% (default)
10
50%
11
25%
HOLD/RST bit
The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware pin
for 8-pin packages. When HOLD/RST=0, the pin acts as HOLD#, When the HOLD/RST=1, the pin acts as RESET#.
16
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
However, the HOLD# or RESET# function are only available when QE=0, If QE=1, The HOLD# and RESET# functions are
disabled, the pin acts as dedicated data I/O pin.
17
Uniform Sector
Dual and Quad Serial Flash
7
GD25Q128E
COMMAND DESCRIPTIONS
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first
rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, with most
significant bit first on SI, and each bit is latched on the rising edges of SCLK.
Every command sequence starts with a one-byte command code. Depending on the command, this might be followed by
address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command sequence
has been completed. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down,
and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can be
completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return to
deselected status.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write
Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command is
rejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS# being driven low
is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL
will not be reset.
Table 10. Commands
Command Name
Byte 1
Byte 2
Byte 3
Write Enable
06H
Write Disable
04H
Read Status Register-1
05H
(S7-S0)
(cont.)
Read Status Register-2
35H
(S15-S8)
(cont.)
Read Status Register-3
15H
(S23-S16)
(cont.)
Write Status Register-1
01H
S7-S0
Write Status Register-2
31H
S15-S8
Write Status Register-3
11H
S23-S16
Volatile SR write
Enable
Byte 4
Byte 5
Byte 6
Byte 7
03H
A23-A16
A15-A8
A7-A0
(D7-D0)
(cont.)
Fast Read
0BH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
(cont.)
Dual Output Fast Read
3BH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)(1)
(cont.)
6BH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)(2)
(cont.)
Read
Byte 9
50H
Read Data
Quad Output Fast
Byte 8
Dual I/O Fast Read
BBH
A23-A16(3) A15-A8(3)
A7-A0(3)
M7-M0(4) (D7-D0)(1)
(cont.)
Quad I/O Fast Read
EBH
A23-A16(5) A15-A8(5)
A7-A0(5)
M7-M0(6)
dummy (D7-D0)(2) (cont.)
Set Burst with Wrap
77H
dummy(7)
dummy(7)
Page Program
02H
A23-A16
A15-A8
dummy
dummy(7) W7-W0(7)
A7-A0
18
D7-D0
Next Byte
Uniform Sector
Dual and Quad Serial Flash
Quad Page Program
32H
A23-A16
A15-A8
A7-A0
Sector Erase
20H
A23-A16
A15-A8
A7-A0
Block Erase (32K)
52H
A23-A16
A15-A8
A7-A0
Block Erase (64K)
D8H
A23-A16
A15-A8
A7-A0
00H
00H
00H
Chip Erase
Read Manufacturer/
Device ID
GD25Q128E
D7-D0(8)
Next Byte
C7/60H
90H
(MID7-
MID0)
(ID7-ID0)
Read Identification
9FH
Read Unique ID
4BH
00H
00H
00H
44H
A23-A16
A15-A8
A7-A0
42H
A23-A16
A15-A8
A7-A0
D7-D0
Next Byte
48H
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
ABH
dummy
dummy
dummy
(ID7-ID0)
(cont.)
5AH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
Erase Security
Registers(9)
Program Security
Registers(9)
Read Security
Registers(9)
Enable Reset
66H
Reset
99H
Program/Erase
Suspend
Program/Erase
Resume
Deep Power-Down
Release From Deep
Power-Down
MID0)
(ID15-ID8) (ID7-ID0)
(MID7-
(cont.)
(cont.)
dummy
(UID7UID0)
(cont.)
(cont.)
75H
7AH
B9H
ABH
Release From Deep
Power-Down and Read
Device ID
Read Serial Flash
Discoverable
Parameter
Note:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Quad Output Data
IO0 = (D4, D0, …)
IO1 = (D5, D1, …)
IO2 = (D6, D2, …)
IO3 = (D7, D3, …)
3. Dual Input Address
19
(cont.)
Uniform Sector
Dual and Quad Serial Flash
IO0 = A22, A20, A18, A16, A14, A12, A10, A8
A6, A4, A2, A0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9
A7, A5, A3, A1
GD25Q128E
4. Dual Input Mode bit
IO0 = M6, M4, M2, M0
IO1 = M7, M5, M3, M1
5. Quad Input Address
IO0 = A20, A16, A12, A8,
A4, A0
IO1 = A21, A17, A13, A9,
A5, A1
IO2 = A22, A18, A14, A10, A6, A2
IO3 = A23, A19, A15, A11, A7, A3
6. Quad Input Mode bit
IO0 = M4, M0
IO1 = M5, M1
IO2 = M6, M2
IO3 = M7, M3
7. Dummy bits and Wrap Bits
IO0 = (x, x, x, x, x, x, W4, x)
IO1 = (x, x, x, x, x, x, W5, x)
IO2 = (x, x, x, x, x, x, W6, x)
IO3 = (x, x, x, x, x, x, x, x)
8. Quad Output Data
IO0 = D4, D0, …
IO1 = D5, D1, …
IO2 = D6, D2, …
IO3 = D7, D3, …
9. Security Registers Address
Security Register1: A23-A16=00H, A15-A12=1H, A11-A10 = 00b, A9-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A12=2H, A11-A10 = 00b, A9-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A12=3H, A11-A10 = 00b, A9-A0= Byte Address;
TABLE OF ID DEFINITIONS
GD25Q128E
Operation Code
MID7-MID0
ID15-ID8
ID7-ID0
9FH
C8
40
18
90H
C8
17
ABH
17
20
Uniform Sector
Dual and Quad Serial Flash
7.1
GD25Q128E
Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must
be set prior to every Page Program (PP), Quad Page Program (QPP), Sector Erase (SE), Block Erase (BE), Chip Erase
(CE), Write Status Register (WRSR) and Erase/Program Security Registers command.
The Write Enable (WREN) command sequence: CS# goes low sending the Write Enable command CS# goes high.
Figure 3. Write Enable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
06H
High-Z
SO
7.2 Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit may be
set to 0 by issuing the Write Disable (WRDI) command to disable Page Program (PP), Quad Page Program (QPP), Sector
Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR), that require WEL be set to 1 for execution.
The WRDI command can be used by the user to protect memory areas against inadvertent writes that can possibly corrupt
the contents of the memory. The WRDI command is ignored during an embedded operation while WIP bit =1.
The WEL bit is reset by following condition: Write Disable command (WRDI), Power-up, and upon completion of the Write
Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands.
The Write Disable command sequence: CS# goes low Sending the Write Disable command CS# goes high.
Figure 4. Write Disable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
SO
04H
High-Z
7.3 Read Status Register (RDSR) (05H or 35H or 15H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any
time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it
is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible
to read the Status Register continuously. For command code of “05H” / “35H” / “15H”, the SO will output Status Register
bits S7~S0 / S15~S8 / S23~S16.
21
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
Figure 5. Read Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
05H or 35H or 15H
SI
High-Z
SO
7
Status Register 1/2/3
6 5 4 3 2 1 0
MSB
7
Status Register 1/2/3
6 5 4 3 2 1 0
7
MSB
7.4 Write Status Register (WRSR) (01H or 31H or 11H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register. For command
code of “01H” / “31H” / “11H”, the Status Register bits S7~S0 / S15~S8 / S23~S16 would be written. CS# must be driven
high after the eighth bit of the data byte has been latched in. Otherwise, the Write Status Register (WRSR) command is not
executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While
the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it
is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2,
BP1, and BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register (WRSR)
command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the
Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the
device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the
Hardware Protected Mode is entered.
Figure 6. Write Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
01H/31H/11H
7
6
High-Z
MSB
SCLK
Command
SI
SO
7.5
Status Register in
5
4
3
2
1
0
Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system
configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting
the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be
issued prior to a Write Status Register command and any other commands can’t be inserted between them. Otherwise,
Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command will not set
22
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit
values.
Figure 7. Write Enable for Volatile Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
50H
High-Z
SO
7.6
Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit is latched-in on the rising
edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit is shifted out, at a Max
frequency fR, on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 8. Read Data Bytes Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
SO
03H
High-Z
24-bit address
23 22 21
3
2
1
0
MSB
MSB
7
6
5
Data Out1
4 3 2 1
Data Out2
0
7.7 Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at
that address, is shifted out on SO, and each bit is shifted out, at a Max frequency f C, on the falling edge of SCLK. The first
byte address can be at any location. The address is automatically incremented to the next higher address after each byte
of data is shifted out.
23
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
Figure 9. Read Data Bytes at Higher Speed Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
0BH
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
7
6
5
4
3
2
1
0
7.8
Data Out1
5 4 3 2
7 6
MSB
SO
1
0
Data Out2
7 6 5
MSB
Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is latched
in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The first byte addressed can be at any location. The address is automatically incremented to the next higher address after
each byte of data is shifted out.
Figure 10. Dual Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24-bit address
3BH
23 22 21
3
2
1
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI
SO
6
0
6
Data Out1
Data Out2
7 5 3 1 7 5 3 1
MSB
MSB
7
24
4
2
0
6
4
2
0
Uniform Sector
Dual and Quad Serial Flash
7.9
GD25Q128E
Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is latched
in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0.
The first byte addressed can be at any location. The address is automatically incremented to the next higher address after
each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad Output
Fast Read command.
Figure 11. Quad Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
IO0
24-bit address
6BH
23 22 21
IO1
High-Z
IO2
High-Z
IO3
High-Z
CS#
3
2
1
0
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
IO0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
IO3
7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4
7.10 Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, and each bit is latched in on the
rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed
can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted
out.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits
(M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Dual I/O
Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. If the “Continuous
Read Mode” bits (M5-4) ≠ (1, 0), the next command requires the command code, thus returning to normal operation. A
“Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command.
25
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
Figure 12. Dual I/O Fast Read Sequence Diagram ((M5-4) ≠ (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
SCLK
Command
IO0
BBH
IO1
A23-16
CS#
A15-8
A7-0
M7-0
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
IO0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
IO1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte1
Byte2
Byte3
Byte4
Figure 13. Dual I/O Fast Read Sequence Diagram ((M5-4) = (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
IO0
6
4
2
0
6
4
2
0
6
4
2
0
6
IO1
7
5
3
1
7
5
3
1
7
5
3
1
7
SCLK
A23-16
CS#
A15-8
A7-0
4
2
0
5
3
1
M7-0
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
IO0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
IO1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte1
Byte2
Byte3
Byte4
7.11 Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-byte
address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, and each
bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1,
IO2, IO3. The first byte addressed can be at any location. The address is automatically incremented to the next higher
address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for
the Quad I/O Fast read command.
26
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad
I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. If the “Continuous
Read Mode” bits (M5-4) ≠ (1, 0), the next command requires the command code, thus returning to normal operation. A
“Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command.
Figure 14. Quad I/O Fast Read Sequence Diagram ((M5-4) ≠ (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
4
0
4
0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
2
6
IO3
7
3
7
3
7
3
7
3
7
3
7
3
7
SCLK
Command
IO0
EBH
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Figure 15. Quad I/O Fast Read Sequence Diagram ((M5-4) = (1, 0))
CS#
0
1
2
3
4
5
6
7
IO0
4
0
4
0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
2
6
2
6
IO3
7
3
7
3
7
3
7
3
7
3
7
3
7
8
9 10 11 12 13 14 15
SCLK
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap”
(77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around”
feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited to either
an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once
it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary
automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache
afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap”
27
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation
while W6-W5 is used to specify the length of the wrap around section within a page.
7.12 Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” command to access a fixed length of
8/16/32/64-byte section within a 256-byte page, in standard SPI mode.
The Set Burst with Wrap command sequence: CS# goes low Send Set Burst with Wrap command Send 24 dummy
bits Send 8 bits “Wrap bits” CS# goes high.
W6,W5
W4=0
W4=1 (default)
Wrap Around
Wrap Length
Wrap Around
Wrap Length
0, 0
Yes
8-byte
No
N/A
0, 1
Yes
16-byte
No
N/A
1, 0
Yes
32-byte
No
N/A
1, 1
Yes
64-byte
No
N/A
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” command will use
the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to
normal read operation, another Set Burst with Wrap command should be issued to set W4=1.
Figure 16. Set Burst with Wrap Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
x
x
x
x
x
x
4
x
IO1
x
x
x
x
x
x
5
x
IO2
x
x
x
x
x
x
6
x
IO3
x
x
x
x
x
x
x
x
SCLK
Command
IO0
77H
W6-W4
7.13 Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and
at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same page (from the address whose 8
least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program
command sequence: CS# goes low sending Page Program command 3-byte address on SI at least 1 byte data on
SI CS# goes high. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256
data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device,
they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page.
28
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP)
command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is t PP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
is not executed.
Figure 17. Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
23 22 21
3
2
1
0 7
MSB
5
4
3
2
1
2078
2079
2077
2076
2075
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
6
0
MSB
2074
02H
Data Byte 1
2073
SI
24-bit address
1
0
SCLK
Data Byte 2
SI
7
6
5
4
3
2
MSB
Data Byte 3
1
0 7
6
5
4
3
MSB
2
Data Byte 256
1
0
7
6
5
4
3
2
MSB
7.14 Quad Page Program (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use Quad
Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The
quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address bytes
and at least one data byte on IO pins.
If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are
guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are
correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS#
must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page Program (PP)
command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad
Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit.
The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
is not executed.
29
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
Figure 18. Quad Page Program Sequence Diagram
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35
543
0
542
CS#
SCLK
0 4
0
4
0
Byte
256
4 0
IO1
5
1
5
1
5 1
IO2
6
2
6
2
6 2
IO3
7
3
7
3
7 3
Command
IO0
24-bit address
32H
23 22 21
3
2
Byte1 Byte2
1
MSB
7.15 Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by
driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address
for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low sending Sector Erase command 3-byte address on SI CS#
goes high.. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector
Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is
tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write
in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector
Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit is not
executed.
Figure 19. Sector Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
20H
24 Bits Address
23 22
MSB
2
1
0
7.16 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is
entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block
is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low sending 32KB Block Erase command 3-byte address on
SI CS# goes high. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise
30
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle
(whose duration is tBE1) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check
the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle,
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) bits is not executed.
Figure 20. 32KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bits Address
52H
23 22
MSB
2
1
0
7.17 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is
entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block
is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low sending 64KB Block Erase command 3-byte address on
SI CS# goes high. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise
the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle
(whose duration is tBE2) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check
the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle,
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) bits is not executed.
Figure 21. 64KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
D8H
24 Bits Address
23 22
MSB
2
1
0
7.18 Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS#
Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the
sequence.
The Chip Erase command sequence: CS# goes low sending Chip Erase command CS# goes high. CS# must be
driven high after the eighth bit of the command code has been latched in; otherwise the Chip Erase command is not executed.
31
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is t CE) is initiated. While the Chip Erase
cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in
Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed, if the
Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block Protect (BP2, BP1, and BP0) bits are 1 and CMP=1.
Figure 22. Chip Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
60H or C7H
7.19 Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command that
provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first.
Figure 23. Read Manufacture ID/ Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
90H
23 22 21
3
2
1
0
High-Z
SO
CS#
24-bit address
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
SO
7
Manufacturer ID
6 5 4 3 2 1
MSB
Device ID
0
7
6
5
4
3
2
1
0
MSB
7.20 Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of
device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the
device in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is followed
32
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
by the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock. The Read
Identification (RDID) command is terminated by driving CS# high at any time during data output. When CS# is driven high,
the device is in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode
and execute commands.
Figure 24. Read Identification ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
7
6
SCLK
SI
9FH
SO
Manufacturer ID
5 4 3 2 1
0
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
Memory Type ID15-ID8
7 6 5 4 3 2 1 0
SO
MSB
Capacity ID7-ID0
6 5 4 3 2 1
7
0
MSB
7.21 Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The Unique
ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low sending Read Unique ID command 3-Byte Address
(000000H) Dummy Byte128bit Unique ID Out CS# goes high.
Figure 25. Read Unique ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
24-bit address
(000000H)
23 22 21
3 2
Command
SI
4BH
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
SO
7
6
5
4
3
2
1
0
7 6
MSB
33
Data Out1
5 4 3 2
1
0
Data Out2
7 6 5
MSB
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
7.22 Erase Security Registers (44H)
The GD25Q128E provides 3x1024-Byte Security Registers which can be erased and programmed individually. These
registers may be used by the system manufacturers to store security and other important information separately from the
main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low sending Erase Security Registers command 3-byte
address on SI CS# goes high. The command sequence is shown below. CS# must be driven high after the eighth bit of
the last address byte has been latched in; otherwise the Erase Security Registers command is not executed. As soon as
CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security
Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit
(LB1, LB2, LB3) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the
Security Registers will be permanently locked; the Erase Security Registers command will be ignored.
Address
A23-16
A15-12
A11-10
A9-0
Security Register #1
00H
0001b
00b
Don't care
Security Register #2
00H
0010b
00b
Don't care
Security Register #3
00H
0011b
00b
Don't care
Figure 26. Erase Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
44H
24 Bits Address
23 22
MSB
2
1
0
7.23 Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. Each security register contains four
pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL)
bit before sending the Program Security Registers command. The Program Security Registers command is entered by
driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon as
CS# is driven high, the self-timed Program Security Registers cycle (whose duration is t PP) is initiated. While the Program
Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB1, LB2, LB3) is set to 1, the Security Registers will be permanently locked. Program
Security Registers command will be ignored.
Address
A23-16
A15-12
A11-10
A9-0
Security Register #1
00H
0001b
00b
Byte Address
Security Register #2
00H
0010b
00b
Byte Address
Security Register #3
00H
0011b
00b
Byte Address
34
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
Figure 27. Program Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
23 22 21
3
2
Data Byte 1
1
0 7
5
4
3
2
1
0
2078
2079
6
2077
7
2076
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2073
MSB
2072
MSB
CS#
6
2075
42H
2074
SI
24-bit address
1
0
SCLK
Data Byte 2
SI
7
6
5
4
3
Data Byte 3
2
1
0 7
MSB
6
5
4
3
Data Byte 256
2
1
0
MSB
5
4
3
2
MSB
7.24 Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte address
(A23-A0) and a dummy byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at that
address, is shifted out on SO, and each bit is shifted out, at a Max frequency f C, on the falling edge of SCLK. The first byte
addressed can be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out. Once the A9-0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the
command is completed by driving CS# high.
Address
A23-16
A15-12
A11-10
A9-0
Security Register #1
00H
0001b
00b
Byte Address
Security Register #2
00H
0010b
00b
Byte Address
Security Register #3
00H
0011b
00b
Byte Address
Figure 28. Read Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
48H
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
SO
7
6
5
4
3
2
1
0
7
MSB
35
Data Out1
6 5 4 3 2
1
Data Out2
0 7 6 5
MSB
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
7.25 Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default
power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status
(WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Deep Power Down Mode, Continuous Read Mode
bit setting (M7-M0) and Wrap Bit Setting (W6-W4).
The “Enable Reset (66H)” and “Reset (99H)” command sequence as follow: CS# goes low Sending Enable Reset
command CS# goes high CS# goes low Sending Reset command CS# goes high. Once the Reset command is
accepted by the device, the device will take approximately t RST / tRST_E to reset. During this period, no command will be
accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when
Reset command sequence is accepted by the device. It is recommended to check the WIP bit and the SUS1/SUS2 bit in
Status Register before issuing the Reset command sequence.
Figure 29. Enable Reset and Reset command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCLK
SI
Command
Command
66H
99H
High-Z
SO
7.26 Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase
operation and then read data from any other sector or block. The Write Status Register command (01H, 31H, 11H) and
Erase/Program Security Registers command (44H, 42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page
Program command (02H, 32H) are not allowed during Program suspend. The Write Status Register command (01H, 31H,
11H) and Erase Security Registers command (44H) and Erase commands (20H, 52H, D8H, C7H, 60H) are not allowed
during Erase suspend. Program/Erase Suspend is valid only during the page program or sector/block erase operation. A
maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS1/SUS2 bit in the Status Register
equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS1/SUS2
bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared from 1
to 0 within “tsus” and the SUS1/SUS2 bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off
during the suspend period will reset the device and release the suspend state.
Figure 30. Program/Erase Suspend Sequence Diagram
CS#
0
1
2
3
4
5
6
7
tSUS
SCLK
Command
SI
SO
75H
High-Z
Accept read command
36
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
7.27 Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a
Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the
SUS1/SUS2 bit equal to 1 and the WIP bit equal to 0. After issued the SUS1/SUS2 bit in the status register will be cleared
from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase
operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a
Program/Erase Suspend is active.
Figure 31. Program/Erase Resume Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
7AH
Resume Erase/Program
7.28 Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the
Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active
use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device,
and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep
Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command.
Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down and Read Device ID (RDI) command or software reset command. The Release from Deep Power-Down and
Read Device ID (RDI) command releases the device from Deep Power-Down mode, also allows the Device ID of the device
to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always in the Standby Mode after PowerUp.
The Deep Power-Down command sequence: CS# goes low sending Deep Power-Down command CS# goes high.
CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down
(DP) command is not executed. As soon as CS# is driven high, it requires a delay of t DP before the supply current is reduced
to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 32. Deep Power-Down Sequence Diagram
CS#
0
1
2
3
4
5
6
7
tDP
SCLK
Command
SI
Deep Power-down mode
B9H
37
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
7.29 Release from Deep Power-Down and Read Device ID (RDI) (ABH)
The Release from Power-Down and Read Device ID command is a multi-purpose command. It can be used to release the
device from the Power-Down state or obtain the devices electronic identification (ID) number.
To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the
instruction code “ABH” and driving CS# high. Release from Power-Down will take the time duration of tRES1 (See AC
Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin must
remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS#
pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the
falling edge of SCLK with most significant bit (MSB) first. The Device ID value is listed in Manufacturer and Device
Identification table. The Device ID can be read continuously. The command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as
previously described, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC
Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If
the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (when
WIP equals 1) the command is ignored and will not have any effects on the current cycle.
Figure 33. Release Power-Down Sequence Diagram
CS#
0
1
2
3
4
5
6
t RES1
7
SCLK
Command
SI
ABH
Deep Power-down mode
Stand-by mode
Figure 34. Release Power-Down/Read Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
SO
ABH
High-Z
t RES2
3 Dummy Bytes
23 22
2
1
0
MSB
7
6
Device ID
5 4 3 2
MSB
1
0
Deep Power-down Mode Stand-by
Mode
7.30 Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and
feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be
interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple
vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard
of JEDEC Standard No.216B.
38
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
Figure 35. Read Serial Flash Discoverable Parameter command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
5AH
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
SO
7
6
5
4
3
2
1
0
7 6
MSB
Data Out1
5 4 3 2
1
0
Data Out2
7 6 5
MSB
Table 11. Signature and Parameter Identification Data Values (Please contact GigaDevice for Details)
39
Uniform Sector
Dual and Quad Serial Flash
8
GD25Q128E
ELECTRICAL CHARACTERISTICS
8.1 Power-On Timing
Figure 36. Power-On Timing Sequence Diagram
Vcc(max)
Chip Selection is not allowed
Vcc(min)
tVSL
Device is fully
accessible
VWI
Time
Table 12. Power-Up Timing and Write Inhibit Threshold
Symbol
Parameter
Min.
tVSL
VCC (min.) to device operation
1.8
VWI
Write Inhibit Voltage
1.5
Max.
Unit
ms
2.5
V
8.2 Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each Byte contains FFH). The Status Register
contains 00H, except that DRV0 bit (S21) is set to 1.
8.3
Absolute Maximum Ratings
Parameter
Value
Ambient Operating Temperature
-40 to 85
Unit
℃
-40 to 105
-40 to 125
℃
Storage Temperature
-65 to 150
Transient Input/Output Voltage (note: overshoot)
-2.0 to VCC+2.0
V
Applied Input/Output Voltage
-0.6 to VCC+0.4
V
-0.6 to 4.2
V
VCC
40
Uniform Sector
Dual and Quad Serial Flash
GD25Q128E
Figure 37. Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
8.4 Capacitance Measurement Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
CIN
Input Capacitance
6
pF
VIN=0V
COUT
Output Capacitance
8
pF
VOUT=0V
CL
Load Capacitance
30
pF
Input Rise And Fall time
5
ns
Input Pulse Voltage
0.1VCC to 0.8VCC
V
Input Timing Reference Voltage
0.2VCC to 0.7VCC
V
0.5VCC
V
Output Timing Reference Voltage
Figure 38. Absolute Maximum Ratings Diagram
Input timing reference level
0.8VCC
0.7VCC
0.1VCC
0.2VCC
Output timing reference level
AC Measurement Level
Note: Input pulse rise and fall time are
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