GT24C16A
Advanced
GT24C16A
2-WIRE
16K Bits
Serial EEPROM
Copyright © 2014 Giantec Semiconductor Inc. (Giantec). All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time without
notice. Giantec products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment,
aerospace or military, or other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance
and optimization on the functionality and etc. Giantec assumes no liability arising out of the application or use of any information, products or services described herein. Customers
are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products.
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GT24C16A
Table of Contents
1.
2.
3.
4.
Features ..................................................................................................................................................................... 3
General Description ............................................................................................................................................. 3
Functional Block Diagram ................................................................................................................................ 4
Pin Configuration................................................................................................................................................... 5
4.1 8-Pin SOIC, TSSOP, PDIP and MSOP ................................................................................................... 5
4.2 8-Lead UDFN and XDFN ........................................................................................................................ 5
4.3 5-Pin SOT23 ........................................................................................................................................... 5
4.4 Pin Definition ........................................................................................................................................... 5
4.5 Pin Descriptions ...................................................................................................................................... 6
5. Device Operation................................................................................................................................................... 7
5.1 2-WIRE Bus ............................................................................................................................................ 7
5.2 The Bus Protocol .................................................................................................................................... 7
5.3 Start Condition ........................................................................................................................................ 7
5.4 Stop Condition......................................................................................................................................... 7
5.5 Acknowledge ........................................................................................................................................... 7
5.6 Reset ....................................................................................................................................................... 7
5.7 Standby Mode ......................................................................................................................................... 7
5.8 Device Addressing .................................................................................................................................. 7
5.9 Write Operation ....................................................................................................................................... 8
5.10 Read Operation..................................................................................................................................... 8
5.11 Diagrams ............................................................................................................................................... 9
5.12 Timing Diagrams ................................................................................................................................. 12
6. Electrical Characteristics .............................................................................................................................. 13
6.1 Absolute Maximum Ratings .................................................................................................................. 13
6.2 Operating Range................................................................................................................................... 13
6.3 Capacitance .......................................................................................................................................... 13
6.4 DC Electrical Characteristic .................................................................................................................. 14
6.5 AC Electrical Characteristic .................................................................................................................. 15
7. Ordering Information......................................................................................................................................... 16
8. Top Markings ......................................................................................................................................................... 17
8.1 SOIC Package ...................................................................................................................................... 17
8.2 TSSOP Package ................................................................................................................................... 17
8.3 PDIP Package ....................................................................................................................................... 17
8.4 MSOP Package .................................................................................................................................... 17
8.5 UDFN Package ..................................................................................................................................... 18
8.6 XDFN Package ..................................................................................................................................... 18
8.7 SOT23 Package.................................................................................................................................... 18
9. Package Information ......................................................................................................................................... 19
9.1 SOIC ..................................................................................................................................................... 19
9.2 TSSOP .................................................................................................................................................. 20
9.3 PDIP ...................................................................................................................................................... 21
9.4 MSOP.................................................................................................................................................... 22
9.5 UDFN .................................................................................................................................................... 23
9.6 XDFN .................................................................................................................................................... 24
9.7 SOT23 .....................................................................................................Error! Bookmark not defined.
10. Revision History ................................................................................................................................................ 26
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GT24C16A
1. Features
2
–
TM
Two-Wire Serial Interface, I C
Compatible
Page write mode
–
Bi-directional data transfer protocol
Partial page writes allowed
Wide-voltage Operation
Self timed write cycle: 5 ms (max.)
–
Noise immunity on inputs, besides Schmitt trigger
High-reliability
VCC = 1.7V to 5.5V
Speed: 400 KHz (1.7V) and 1 MHz (2.5V~5.5V)
Standby current (max.): 1 A, 1.7V
Read current (max.): 0.5 mA, 5.5V
Write current (max.): 0.5 mA, 5.5V
Industrial grade
Hardware Data Protection
Packages: SOIC, TSSOP, PDIP, MSOP, UDFN,
–
–
–
Sequential & Random Read Features
Memory organization: 16Kb (2,048 x 8)
Page Size: 16 bytes
Data retention: 100 years
XDFN and SOT23
Write Protect Pin
Endurance: 1 million cycles
Lead-free, RoHS, Halogen free, Green
2. General Description
The GT24C16A is an industrial standard electrically
function via WP pin to cease from overwriting the data
erasable programmable read only memory (EEPROM)
stored inside the memory array.
device that utilizes the industrial standard 2-wire interface
In order to refrain the state machine entering into a wrong
for communications. The GT24C16A contains a memory
state during power-up sequence or a power toggle off-on
array of 16K bits (2,048x8), which is organized in 16-byte
condition, a power on reset circuit is embedded. During
per page.
power-up, the device does not respond to any instructions
The EEPROM operates in a wide voltage range from 1.7V
until the supply voltage (VCC) has reached an acceptable
to 5.5V, which fits most application. The product provides
stable level above the reset threshold voltage. Once VCC
low-power operations and low standby current. The device
passes the power on reset threshold, the device is reset
is offered in Lead-free, RoHS, halogen free or Green
and enters into the Standby mode. This would also avoid
package. The available package types are 8-pin SOIC,
any inadvertent Write operations during power-up stage.
TSSOP, PDIP, MSOP, UDFN, XDFN and SOT23.
During power-down process, the device will enter into
The GT24C16A is compatible to the standard 2-wire bus
standby mode, once VCC drops below the power on reset
protocol. The simple bus consists of Serial Clock (SCL) and
threshold voltage. In addition, the device will be in standby
Serial Data (SDA) signals. Utilizing such bus protocol, a
mode after receiving the Stop command, provided that no
Master device, such as a microcontroller, can usually
internal write operation is in progress. Nevertheless, it is not
control one or more Slave devices, alike this GT24C16A.
recommended to send an command until the VCC reaches
The bit stream over the SDA line includes a series of bytes,
its operating level.
which identifies a particular Slave device, an instruction, an
address within that Slave device, and a series of data, if
appropriate. The GT24C16A also has a Write Protect
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GT24C16A
3. Functional Block Diagram
8
SDA
5
SCL
6
WP
7
X DECODER
VCC
HIGH VOLTAGE
GENERATOR
TIMING &
CONTROL
CONTROL LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
1
A1
2
A2
3
WORD ADDRESS
COUNTER
ACK
Y DECODER
CLOCK
DI/O
GND 4
DATA REGISTER
nMOS
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EEPROM ARRAY
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GT24C16A
4. Pin Configuration
4.1 8-Pin SOIC, TSSOP, PDIP and MSOP
4.2 8-Lead UDFN and XDFN
Top View
Top View
A0
1
8
VCC
A0
1
8
VCC
A1
2
7
WP
A1
2
7
WP
A2
3
6
SCL
A2
3
6
SCL
GND
4
5
SDA
GND
4
5
SDA
4.3 5-Pin SOT23
Top View
SCL
1
GND
2
SDA
3
5
WP
4
VCC
4.4 Pin Definition
Pin No.
Pin Name
I/O
1
A0
I
Device Address Input
2
A1
I
Device Address Input
3
A2
I
Device Address Input
4
GND
-
Ground
5
SDA
I/O
6
SCL
I
Serial Clock Input
7
WP
I
Write Protect Input
8
VCC
-
Power Supply
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Definition
Serial Address and Data input and Data out put
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GT24C16A
4.5 Pin Descriptions
SCL
default to 'zero'. Thus, only one device can be connected on
This input clock pin is used to synchronize the data transfer
a single bus system.
to and from the device.
WP
SDA
WP is the Write Protect pin. While the WP pin is connected
The SDA is a bi-directional pin used to transfer addresses
to the power supply of GT24C16A, the entire array
and data into and out of the device. The SDA pin is an open
becomes Write Protected (i.e. the device becomes Read
drain output and can be wired with other open drain or open
only). When WP is tied to Ground or left floating, the normal
collector outputs. However, the SDA pin requires a pull-up
write operations are allowed.
resistor connected to the power supply.
VCC
A0, A1, A2
Supply voltage
The A0, A1 and A2 are the device address inputs.
For
GT24C16A, the A0, A1, and A2 pins are not connected and
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GND
Ground of supply voltage
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GT24C16A
5. Device Operation
The GT24C16A serial interface supports communications
2
loss), or needs to be terminated mid-stream. The reset is
using industrial standard 2-wire bus protocol, such as I C.
initiated when the Master device creates a Start condition.
5.1 2-WIRE Bus
To do this, it may be necessary for the Master device to
The two-wire bus is defined as Serial Data (SDA), and
monitor the SDA line while cycling the SCL up to nine times.
Serial Clock (SCL). The protocol defines any device that
(For each clock signal transition to High, the Master checks
sends data onto the SDA bus as a transmitter, and the
for a High level on SDA.)
receiving devices as receivers. The bus is controlled by
5.7 Standby Mode
Master device that generates the SCL, controls the bus
While in standby mode, the power consumption is minimal.
access, and generates the Start and Stop conditions. The
The GT24C16A enters into standby mode during one of the
GT24C16A is the Slave device.
following conditions: a) After Power-up, while no Op-code is
5.2 The Bus Protocol
sent; b) After the completion of an operation and followed
Data transfer may be initiated only when the bus is not busy.
by the Stop signal, provided that the previous operation is
During a data transfer, the SDA line must remain stable
not Write related; or c) After the completion of any internal
whenever the SCL line is high. Any changes in the SDA line
write operations.
while the SCL line is high will be interpreted as a Start or
5.8 Device Addressing
Stop condition.
The Master begins a transmission on by sending a Start
The state of the SDA line represents valid data after a Start
condition, then sends the address of the particular Slave
condition. The SDA line must be stable for the duration of
devices to be communicated. The Slave device address is 8
the High period of the clock signal. The data on the SDA line
bits format as shown in Figure. 5-5.
may be changed during the Low period of the clock signal.
The four most significant bits of the Slave address are fixed
There is one clock pulse per bit of data. Each data transfer
(1010) for GT24C16A.
is initiated with a Start condition and terminated by a Stop
The GT24C16A utilizes bits B0, B1 and B2 to address one
condition.
of the eight 256-byte blocks in the device. Only one
5.3 Start Condition
GT24C16A unit can be connected onto the same 2-wire
The Start condition precedes all commands to the device
bus.
and is defined as a High to Low transition of SDA when SCL
The last bit of the Slave address specifies whether a Read
is High. The EEPROM monitors the SDA and SCL lines and
or Write operation is to be performed. When this bit is set to
will not respond until the Start condition is met.
1, Read operation is selected. While it is set to 0, Write
5.4 Stop Condition
operation is selected.
The Stop condition is defined as a Low to High transition of
After the Master transmits the Start condition and Slave
SDA when SCL is High. All operations must end with a Stop
address byte appropriately, the associated 2-wire Slave
condition.
device, GT24C16A, will respond with ACK on the SDA line.
5.5 Acknowledge
Then GT24C16A will pull down the SDA on the ninth clock
After a successful data transfer, each receiving device is
cycle, signaling that it received the eight bits of data.
required to generate an ACK. The Acknowledging device
The GT24C16A then prepares for a Read or Write operation
pulls down the SDA line.
by monitoring the bus.
5.6 Reset
The GT24C16A contains a reset function in case the 2-wire
bus transmission on is accidentally interrupted (e.g. a power
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GT24C16A
5.9 Write Operation
condition followed by the Slave address for a Write
5.9.1 Byte Write
operation. If the EEPROM is still busy with the Write
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the byte address that is to be
written into the address pointer of the GT24C16A. After
receiving another ACK from the Slave, the Master device
transmits the data byte to be written into the address
memory location. The GT24C16A acknowledges once more
and the Master generates the Stop condition, at which time
operation, no ACK will be returned. If the GT24C16A has
completed the Write operation, an ACK will be returned and
the host can then proceed with the next Read or Write
operation.
5.10 Read Operation
Read operations are initiated in the same manner as Write
operations, except that the (R/W) bit of the Slave address is
set to ―1‖. There are three Read operation options: current
address read, random address read and sequential read.
the device begins its internal programming cycle. While this
5.10.1 Current Address Read
internal cycle is in progress, the device will not respond to
The GT24C16A contains an internal address counter which
any request from the Master device.
maintains the address of the last byte
5.9.2 Page Write
incremented by one. For example, if the previous operation
The GT24C16A is capable of 16-byte Page-Write operation.
A Page-Write is initiated in the same manner as a Byte
Write, but instead of terminating the internal Write cycle
after the first data word is transferred, the Master device
can transmit up to 15 more bytes. After the receipt of each
data word, the EEPROM responds immediately with an
ACK on SDA line, and the four lower order data word
address bits are internally incremented by one, while the
higher order bits of the data word address remain constant.
If a byte address is incremented from the last byte of a page,
it returns to the first byte of that page. If the Master device
accessed,
is either a Read or Write operation addressed to the
address location n, the internal address counter would
increment to address location n+1. When the EEPROM
receives the Slave Addressing Byte with a Read operation
(R/W bit set to ―1‖), it will respond an ACK and transmit the
8-bit data byte stored at address location n+1. The Master
should not acknowledge the transfer but should generate a
Stop condition so the GT24C16A discontinues transmission.
If 'n' is the last byte of the memory, the data from location '0'
will be transmitted. (Refer to Figure 5-8. Current Address
Read Diagram.)
should transmit more than 16 bytes prior to issuing the Stop
5.10.2 Random Address Read
condition, the address counter will ―roll over,‖ and the
Selective Read operations allow the Master device to select
previously written data will be overwritten. Once all 16 bytes
at random any memory location for a Read operation. The
are received and the Stop condition has been sent by the
Master device first performs a 'dummy' Write operation by
Master, the internal programming cycle begins. At this point,
sending the Start condition, Slave address and byte
all received data is written to the GT24C16A in a single
address of the location it wishes to read. After the
Write cycle. All inputs are disabled until completion of the
GT24C16A acknowledges the byte address, the Master
internal Write cycle.
device resends the Start condition and the Slave address,
5.9.3 Acknowledge (ACK) Polling
this time with the R/W bit set to one. The EEPROM then
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
GT24C16A initiates the internal Write cycle. ACK polling
responds with its ACK and sends the data requested. The
Master device does not send an ACK but will generate a
Stop condition. (Refer to Figure 5-9. Random Address Read
Diagram.)
can be initiated immediately. This involves issuing the Start
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GT24C16A
5.10.3 Sequential Read
followed by a Stop condition. The data output is sequential,
Sequential Reads can be initiated as either a Current
with the data from address n followed by the data from
Address Read or Random Address Read. After the
address n+1,n+2 ... etc.. The address counter increments
GT24C16A sends the initial byte sequence, the Master
by one automatically, allowing the entire memory contents
device now responds with an ACK indicating it requires
to be serially read during sequential Read operation. When
additional data from the GT24C16A. The EEPROM
the memory address boundary of the array is reached, the
continues to output data for each ACK received. The Master
address counter ―rolls over‖ to address 0, and the device
device terminates the sequential Read operation by pulling
continues to output data. (Refer to Figure 5-10. Sequential
SDA High (no ACK) indicating the last data word to be read,
Read Diagram).
5.11 Diagrams
Figure 5-1. Typical System Bus Configuration
VCC
SDA
SCL
Master
Transmitter/Receiver
GT24CXX
Figure 5-2. Output Acknowledge
SCL from Master
1
8
9
Data Output from
Transmitter
TAA
Data Output from
Receiver
TAA
ACK
SDA
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STOP
CONDITION
SCL
START
CONDITION
Figure 5-3. Start and Stop Conditions
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GT24C16A
Figure 5-4. Data Validity Protocol
Data Change
SCL
Data Stable
Data Stable
SDA
Figure 5-5. Slave Address
Bit
7
6
5
4
3
2
1
0
1
0
1
0
B2
B1
B0
R/W
Figure 5-6. Byte Write
S
T
A
R
T
Device
Address
SDA
Bus
Activity
W
R
I
T
E
Byte Address
A
C
K
M
S
B
S
T
O
P
Data
A
C
K
A
C
K
L
S
B
R/W
Figure 5-7. Page Write
S
T
A
R
T
W
R
I
T
E Byte Address(n)
A
A
C
C
K
K
Device
Address
SDA
Bus
Activity
M
S
B
Data(n+1)
A
C
K
Data(n+15)
A
C
K
A
C
K
L
S
B
R/W
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Data(n)
S
T
O
P
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GT24C16A
Figure 5-8. Current Address Read
S
T
A
R
T
R
E
A
D
Device
Address
S
T
O
P
Data
A
C
K
SDA
Bus
Activity
M
S
B
L
S
B
N
O
A
C
K
R/W
Figure 5-9. Random Address Read
S
T
A
R
T
Device
Address
SDA
Bus
Activity
W
R
I
T
E
Byte
Address(n)
A
C
K
M
S
B
S
T
A
R
T
Device
Address
A
C
K
R
E
A
D
S
T
O
P
Data n
A
C
K
N
O
L
S
B
R/W
A
C
K
DUMMY WRITE
Figure 5-10. Sequential Read
Device
Address
SDA
Bus
Activity
R
E
A
D
Data Byte n
A
C
K
Data Byte n+1
A
C
K
S
T
O
Data Byte n+x P
Data Byte n+2
A
C
K
A
C
K
N
O
R/W
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C
K
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GT24C16A
5.12 Timing Diagrams
Figure 5-11. Bus Timing
TR
TF
THIGH
TLOW
TSU:STO
SCL
TSU:STA
THD:STA
TSU:DAT
THD:DAT
TBUF
SDAIN
TAA
TDH
SDAOUT
TSU:WP THD:WP
WP
Figure 5-12. Write Cycle Timing
SCL
SDA
ACK
Word n
TWR
STOP
Condition
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START
Condition
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GT24C16A
6. Electrical Characteristics
6.1 Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
VS
Supply Voltage
-0.5 to + 6.5
V
VP
Voltage on Any Pin
-0.5 to + 6.5
V
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
IOUT
Output Current
5
mA
Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
6.2 Operating Range
Range
Ambient Temperature (TA)
VCC
Industrial
–40°C to +85°C
1.7V to 5.5V
Note: Giantec offers Industrial grade for Commercial applications (0C to +70C).
6.3 Capacitance
Symbol
Parameter[1, 2]
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
pF
CI/O
Input / Output Capacitance
VI/O = 0V
8
pF
Notes:
[1]
Tested initially and after any design or process changes that may affect these parameters and not 100% tested.
Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V
[2]
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GT24C16A
6.4 DC Electrical Characteristic
Industrial: TA = –40°C to +85°C, VCC = 1.7V ~ 5.5V
Symbol
Parameter
[1]
VCC
Test Conditions
Min.
Max.
Unit
1.7
5.5
V
VCC
Supply Voltage
VIH
Input High Voltage
0.7*VCC
VCC+1
V
VIL
Input Low Voltage
-1
0.3* VCC
V
ILI
Input Leakage Current
5V
—
2
μA
ILO
Output Leakage Current
5V
—
2
μA
VIN = VCC max
VOL1
Output Low Voltage
1.7V
IOL = 0.15 mA
—
0.2
V
VOL2
Output Low Voltage
2.5V
IOL = 2.1 mA
—
0.4
V
ISB1
Standby Current
1.7V
VIN = VCC or GND
0.2
1
μA
ISB2
Standby Current
2.5V
VIN = VCC or GND
0.3
1
μA
ISB3
Standby Current
5.5V
VIN = VCC or GND
0.5
1
μA
1.7V
Read at 400 KHz
—
0.15
mA
2.5V
Read at 1 MHz
—
0.2
mA
5.5V
Read at 1 MHz
—
0.5
mA
1.7V
Write at 400 KHz
—
0.3
mA
2.5V
Write at 1 MHz
—
0.4
mA
5.5V
Write at 1 MHz
—
0.5
mA
ICC1
ICC2
Read Current
Write Current
Note: The parameters are characterized but not 100% tested.
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GT24C16A
6.5 AC Electrical Characteristic
Industrial: TA = –40°C to +85°C, Supply voltage = 1.7V to 5.5V
Symbol
Parameter
[1] [2]
1.7VVCC5.5V
Min.
Max.
FSCL
SCK Clock Frequency
TLOW
Clock Low Period
1200
—
THIGH
Clock High Period
600
2.5VVCC5.5V
Min.
400
Max.
Unit
1000
KHz
600
—
ns
—
400
—
ns
TR
Rise Time (SCL and SDA)
—
300
—
300
ns
TF
Fall Time (SCL and SDA)
—
300
—
100
ns
TSU:STA
Start Condition Setup Time
600
—
250
—
ns
TSU:STO
Stop Condition Setup Time
600
—
250
—
ns
THD:STA
Start Condition Hold Time
600
—
250
—
ns
TSU:DAT
Data In Setup Time
100
—
100
—
ns
THD:DAT
Data In Hold Time
0
—
0
—
ns
100
900
50
400
ns
100
—
50
—
ns
—
5
—
5
ms
1000
—
400
—
ns
TAA
Clock to Output Access time (SCL
Low to SDA Data Out Valid)
TDH
Data Out Hold Time (SCL Low to
SDA Data Out Change)
TWR
Write Cycle Time
TBUF
Bus Free Time Before New
Transmission
TSU:WP
WP pin Setup Time
600
—
600
THD:WP
WP pin Hold Time
1200
—
1200
—
ns
—
100
—
50
ns
T
Notes:
Noise Suppression Time
[1]
[2]
The parameters are characterized but not 100% tested.
AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5.0V), 10 kΩ (1.7V)
CL = 100 pF
Input pulse voltages: 0.3*VCC to 0.7*VCC
Input rise and fall times: ≤ 50 ns
Timing reference voltages: half VCC level
Giantec Semiconductor, Inc.
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GT24C16A
7. Ordering Information
Industrial Grade: -40°C to +85°C, Lead-free
Voltage Range
1.7V~5.5V
Part Number*
Package
GT24C16A-2GLI-TR
150-mil SOIC
GT24C16A-2ZLI-TR
3 x 4.4 mm TSSOP
GT24C16A-2PLI
300-mil PDIP
GT24C16A-2SLI-TR
3 x 3 mm MSOP
GT24C16A-2UDLI-TR
2 x 3 x 0.55 mm UDFN
GT24C16A-2XDLI-TR
1.8 x 2.2 x 0.4 mm XDFN
GT24C16A-2TFLI-TR
2.9 x 1.6 mm SOT23
*
1. Contact Giantec Sales Representatives for availability and other package information.
2. The product is packed in tape and reel ―-TR‖ (4K per reel), except UDFN is 5K per reel, SOT23 is 3K per reel.
3. Refer to Giantec website for related declaration document on lead free, RoHS, halogen free or Green, whichever is applicable.
4. Giantec offers Industrial grade for Commercial applications (0C to +70C).
Giantec Semiconductor, Inc.
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GT24C16A
8. Top Markings
8.1 SOIC Package
G: Giantec Logo
416A-2GLI: GT24C16A-2GLI-TR
YWW: Date Code, Y=year, WW=week
8.2 TSSOP Package
GT: Giantec Logo
416A-2ZLI: GT24C16A-2ZLI-TR
YWW: Date Code, Y=year, WW=week
8.3 PDIP Package
YWW
2416A-2PLI
GT: Giantec Logo
2416A-2PLI: GT24C16A-2PLI
YWW: Date Code, Y=year, WW=week
8.4 MSOP Package
GT: Giantec Logo
416A2SU: GT24C16A-2SLI-TR
YWW: Date Code, Y=year, WW=week
Giantec Semiconductor, Inc.
C2
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GT24C16A
8.5 UDFN Package
GT: Giantec Logo
44A: GT24C16A-2UDLI-TR
YWW: Date Code, Y=year, WW=week
8.6 XDFN Package
GT: Giantec Logo
44A: GT24C16A-2XDLI-TR
YWW: Date Code, Y=year, WW=week
8.7 SOT23 Package
416A: GT24C16A-2TFLI-TR
YW: Date Code, Y=year, W=week
Giantec Semiconductor, Inc.
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GT24C16A
9. Package Information
9.1 SOIC
8L 150mil SOIC Package Outline
Detail A
D
E
E1
b
ZD
Detail A
GAUGE
PLANE
A
SEATING
PLANE
e
SYMBOLS
A1
DIMENSIONS IN MILLIMETERS
Θ
DIMENSIONS IN INCHES
MIN
NOM
MAX
MIN
NOM
MAX
A
1.35
--
1.75
0.053
--
0.069
A1
0.10
--
0.25
0.004
--
0.010
b
0.33
--
0.51
0.013
--
0.020
D
4.80
--
5.00
0.189
--
0.197
Note:
E
5.80
--
6.20
0.228
--
0.244
1. Controlling Dimension:MM
E1
3.80
--
4.00
0.150
--
0.157
2. Dimension D and E1 do not include
Mold protrusion
3. Dimension b does not include
dambar protrusion/intrusion.
4. Refer to Jedec standard MS-012
5. Drawing is not to scale
e
L
1.27 BSC.
0.38
L1
Θ
--
0.050 BSC.
1.27
0.015
0.25 BSC.
ZD
--
0.050
0.010 BSC.
0.545 REF.
0
Giantec Semiconductor, Inc.
C2
L
L1
0.021 REF.
8°
0
--
8°
www.giantec-semi.com
19/26
GT24C16A
9.2 TSSOP
8L 3x4.4mm TSSOP Package Outline
D
C
e
8
L
E
E1
1
Θ
12°(4X)
A2
0.10mm
b
A1
A
SYMBOLS
A
A1
A2
b
c
D
E
E1
e
L
Θ
DIMENSIONS IN MILLIMETERS
MIN
-0.05
0.80
0.19
0.09
2.90
4.30
0.45
0
Giantec Semiconductor, Inc.
C2
Note:
1. Controlling Dimension:MM
2. Dimension D and E do not include Mold protrusion
3. Dimension b does not include dambar protrusion/intrusion.
4. Refer to Jedec standard MO-153 AA
5. Drawing is not to scale
6. Package may have exposed tie bar.
NOM
--1.00
--3.00
4.40
6.4 BSC
0.65 BSC
0.60
--
DIMENSIONS IN INCHES
MAX
1.20
0.15
1.05
0.30
0.20
3.10
4.50
MIN
-0.002
0.031
0.007
0.004
0.114
0.169
0.75
8°
0.018
0
NOM
--0.039
--0.118
0.173
0.252 BSC
0.026 BSC
0.024
--
MAX
0.047
0.006
0.041
0.012
0.008
0.122
0.177
0.030
8°
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GT24C16A
9.3 PDIP
8L 300mil PDIP Package Outline
D
E
E1
eB
ZD
A2
A1
A
L
Note:
1. Controlling Dimension:MM
2. Dimension D and E1 do not include Mold protrusion
3. Dimension b2 and b3 do not include dambar protrusion/instrusion
4. Drawing is not to scale
b3
e
SYMBOLS
b
DIMENSIONS IN MILLIMETERS
A
A1
A2
b
b2
b3
D
E
E1
e
eB
L
ZD
Giantec Semiconductor, Inc.
C2
MIN
3.60
0.38
3.25
0.36
1.40
0.81
9.01
7.49
6.20
8.12
3.18
NOM
---------2.54 BSC.
--0.825 REF.
DIMENSIONS IN INCHES
MAX
4.20
0.75
3.45
0.56
1.65
1.17
9.53
8.26
6.60
MIN
0.142
0.015
0.128
0.014
0.055
0.032
0.355
0.295
0.244
9.65
3.80
0.320
0.125
NOM
---------0.100 BSC.
--0.032 REF.
MAX
0.165
0.030
0.136
0.022
0.065
0.046
0.375
0.325
0.260
0.380
0.150
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GT24C16A
9.4 MSOP
8L 120mil MSOP package Outline
D
C
e
L
E
12°(4X)
E1
A2
θ
A
A1
b
SYMBOLS
DIMENSIONS IN MILLIMETERS
A
A1
A2
b
C
D
E
E1
e
L
Θ
MIN
-0.05
0.75
0.25
0.13
2.90
2.90
-0
NOM
--0.85
--3.00
3.00
4.90 BSC
0.65 BSC
---
DIMENSIONS IN INCHES
MAX
1.10
0.15
0.95
0.40
0.23
3.10
3.10
MIN
-0.002
0.030
0.010
0.005
0.114
0.114
0.55
7°
-0
NOM
--0.033
--0.118
0.118
0.193 BSC
0.026 BSC
---
MAX
0.043
0.006
0.037
0.016
0.009
0.122
0.122
0.022
7°
Note:
1. Controlling Dimension:MM
2. Dimension D and E1 do not include Mold protrusion
3. Refer to Jedec standard MO187
4. Drawing is not to scale
Giantec Semiconductor, Inc.
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GT24C16A
9.5 UDFN
8L 2x3mm UDFN Package Outline
D2
D
e
K
E2
E
PIN#1
IDENTIFICATION
CHAMFER
L
b
PIN#1 DOT
BY MARKING
BOTTOM VIEW
TOP VIEW
A
A1
A2
SIDE VIEW
SYMBOLS
DIMENSIONS IN MILLIMETERS
A
A1
b
A2
D
D2
E
E2
e
K
L
MIN
0.50
0.00
0.18
1.25
1.15
0.40
0.20
NOM
0.55
-0.25
0.152 REF
2.00 BSC
1.40
3.00 BSC
1.30
0.50 BSC.
-0.30
DIMENSIONS IN INCHES
MAX
0.60
0.05
0.30
MIN
0.020
0.000
0.007
1.50
0.049
1.40
0.045
-0.40
0.016
0.008
NOM
0.022
-0.010
0.006 REF
0.079 BSC
0.055
0.118 BSC
0.051
0.020 BSC.
-0.012
MAX
0.024
0.002
0.012
0.059
0.055
-0.016
Note:
1. Controlling Dimension:MM
2. Drawing is not to scale
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GT24C16A
9.6 XDFN
8L 1.8x2.2mm XDFN Package Outline
e1
e
D
L
E1
E
0.10
PIN#1 ID
0.10
0.15
b
D1
PIN#1 DOT BY
MARKING
TOP VIEW
SYMBOLS
A1
SIDE VIEW
MIN
NOM
MAX
DIMENSIONS IN INCHES
MIN
NOM
MAX
A
--
--
0.40
--
--
0.016
0.00
--
0.05
0.000
--
0.002
b
0.15
0.20
0.25
0.006
0.008
0.010
D
1.70
1.80
1.90
0.067
0.071
0.075
E
2.10
2.20
2.30
0.083
0.087
0.091
D1
1.30BSC
0.05BSC
E1
1.00BSC
0.04BSC
e1
1.20REF
0.047REF
e
0.40TYP
0.26
0.30
0.02TYP
0.35
0.010
0.012
0.014
Note:
1. Controlling Dimension:MM
2. Drawing is not to scale
Giantec Semiconductor, Inc.
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DIMENSIONS IN MILLIMETERS
A1
L
A
BOTTOM VIEW
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GT24C16A
9.7 SOT23
5L 2.9x1.6mm SOT23
D
0.25
b
L
E1
E
Θ
c
e
e1
Note:
1. Dimension D and E1 do not include Mold protrusion
2. Dimension b does not include dambar protrusion/intrusion.
A2
A
3. Refer to Jedec standard MO-193 AB
4. Drawing is not to scale
A1
SYMBOLS
DIMENSIONS IN MILLIMETERS
MIN
NOM
MAX
NOM
MAX
A
--
--
1.250
--
--
0.049
A1
0.000
--
0.150
0.000
--
0.006
A2
1.000
1.100
1.200
0.039
0.043
0.047
b
0.360
--
0.500
0.014
--
0.020
c
0.140
--
0.200
0.006
--
0.008
D
2.826
2.926
3.026
0.111
0.115
0.119
E
2.600
2.800
3.000
0.102
0.110
0.118
E1
1.526
1.626
1.726
0.060
0.064
0.068
e
0.95(BSC)
e1
0.037(BSC)
1.90(BSC)
0.075(BSC)
L
0.350
0.450
0.600
0.014
0.018
0.024
Θ
0°
--
8°
0°
--
8°
Giantec Semiconductor, Inc.
C2
DIMENSIONS IN INCHES
MIN
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GT24C16A
10. Revision History
Revision
Date
Descriptions
C0
Feb. 2014
Initial version
C1
Jun. 2016
Update table6.1 and table6.4
C2
May.2017
Change SOT23-5 package thickness from 0.9mm to 1.25mm
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C2
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