NRF21540-QDAA-R7

nRF21540 Product Specification v1.0 4446_194 v1.0 / 2020-08-20 Key features Key features: Applications: • Front-end module with RF PA and LNA • Smart Home applications • Supports Bluetooth Low Energy, IEEE 802.15.4, and proprietary applications • Industrial and factory automation • Max output power 22 dBm • Asset tracking • Adjustable output power to ±1 dB from 5 to 21 dBm • Advanced CE remote controls • User programmable modes for TX gain • Sports and fitness • Non-volatile memory storage for gain settings • Toys • Dual antenna port with antenna diversity support • Medical • Receive gain +13 dB • Beacons • Single-ended 50 Ω matched input and output • 110 mA @ +20 dBm output power • 38 mA @ +10 dBm output power • Control interface via I/O, SPI, or a combination of both • Supply voltage 1.7 to 3.6 V, suitable for 1.8 V ±5% systems • Operating temperature -40°C to 105°C • Package variant QFN16 4 x 4 mm ® 4446_194 v1.0 ii Contents Key features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii 1 Revision history. 5 2 About this document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Document status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Register tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Fields and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 DUMMY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6 7 7 7 3 Product overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Device control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 5.2 5.3 5.4 5.5 Operational states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Antenna control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State transition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UICR programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SPI interface. 7 Electrical specification. 8 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 11 13 13 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3 TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.4 SPI timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 17 17 18 18 Register interface. 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 CONFREG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2 CONFREG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.3 CONFREG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.4 CONFREG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.5 PARTNUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.6 HW_REVISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.7 HW_ID0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.8 HW_ID1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 21 21 21 22 22 22 Hardware and layout. 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2 Mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.1 QFN 4 x 4 mm package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4446_194 v1.0 iii 9.3 Reference circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Recommended operating conditions. 11 Absolute maximum ratings. 12 Ordering information. 12.1 12.2 12.3 12.4 12.5 . . . . . . . . . . . . . . . . . . . . 4446_194 v1.0 27 . . . . . . . . . . . . . . . . . . . . . . . . . 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Box labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code ranges and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal notices. 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv 29 29 30 31 32 34 1 Revision history Date Version Description August 2020 1.0 First release 4446_194 v1.0 5 2 About this document This document is organized into chapters that are based on the modules and peripherals available in the IC. 2.1 Document status The document status reflects the level of maturity of the document. Document name Description Objective Product Specification (OPS) Applies to document versions up to 1.0. This document contains target specifications for product development. Product Specification (PS) Applies to document versions 1.0 and higher. This document contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Table 1: Defined document names 2.2 Register tables Individual registers are described using register tables. These tables are built up of two sections. The first three colored rows describe the position and size of the different fields in the register. The following rows describe the fields in more detail. 2.2.1 Fields and values The Id (Field Id) row specifies the bits that belong to the different fields in the register. If a field has enumerated values, then every value will be identified with a unique value id in the Value Id column. A blank space means that the field is reserved and read as undefined, and it also must be written as 0 to secure forward compatibility. If a register is divided into more than one field, a unique field name is specified for each field in the Field column. The Value Id may be omitted in the single-bit bit fields when values can be substituted with a Boolean type enumerator range, e.g. true/false, disable(d)/enable(d), on/ off, and so on. Values are usually provided as decimal or hexadecimal. Hexadecimal values have a 0x prefix, decimal values have no prefix. The Value column can be populated in the following ways: • Individual enumerated values, for example 1, 3, 9. • Range of values, e.g. [0..4], indicating all values from and including 0 and 4. • Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or alternatively the field's translation and limitations are described in the text instead. 4446_194 v1.0 6 About this document If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all but the first field. Subsequent fields will indicate inheritance with '..'. A feature marked Deprecated should not be used for new designs. 2.2.2 Permissions Different fields in a register might have different access permissions enforced by hardware. The access permission for each register field is documented in the Access column in the following ways: Access Description Hardware behavior RO Read-only Field can only be read. A write will be ignored. WO Write-only Field can only be written. A read will return an undefined value. RW Read-write Field can be read and written multiple times. W1 Write-once Field can only be written once per reset. Any subsequent write will be ignored. A read will return an undefined value. RW1 Read-write-once Field can be read multiple times, but only written once per reset. Any subsequent write will be ignored. Table 2: Register field permission schemes 2.3 Registers Register Offset Description DUMMY 0x514 Example of a register controlling a dummy feature Table 3: Register overview 2.3.1 DUMMY Address offset: 0x514 Example of a register controlling a dummy feature Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D D D D Reset 0x00050002 ID Access Field A RW FIELD_A C C C B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value ID Value Description Example of a read-write field with several enumerated values Disabled 0 The example feature is disabled NormalMode 1 The example feature is enabled in normal mode ExtendedMode 2 The example feature is enabled along with extra functionality B RW FIELD_B C RW FIELD_C D RW FIELD_D Example of a deprecated read-write field Disabled 0 The override feature is disabled Enabled 1 The override feature is enabled Example of a read-write field with a valid range of values ValidRange [2..7] Example of allowed values for this field Example of a read-write field with no restriction on the values 4446_194 v1.0 7 Deprecated 3 Product overview nRF21540 is an RF front-end module suitable for Bluetooth Low Energy and IEEE 802.15.4 range extension. Device features include a configurable gain Power amplifier (PA) in the transmit path (TX) and a Low noise amplifier (LNA) in the receive path (RX). Single-ended operation on both TRX and ANT1/2 ports is supported and requires only three external components (for single antenna operation) for the RF path. The device is controlled through a set of input pins. Alternatively, the device can be controlled by writing to internal control registers through the SPI interface. The two antenna ports enable applications using antenna diversity and can be selected using pin ANT_SEL. Highly configurable gain in Transmit state enables the application to implement adaptive gain control algorithms. Gain settings can be stored for factory device calibration to user configurable output power through onboard non-volatile memory. 4446_194 v1.0 8 4 Block diagram The block diagram illustrates the overall system. MODE RX_EN ANT_SEL TX_EN PDN SCK MOSI MISO CSN Control ANT1 RF switch RX RF switch ANT2 TX RF switch Figure 1: nRF21540 Block diagram 4446_194 v1.0 9 TRX 5 Device control nRF21540 uses an internal state machine to control the operation of the device. The state machine can be controlled through direct pin control or through the built in SPI slave interface. 5.1 Operational states This section describes how nRF21540 can be set to different operational states. When PDN is set to 0, the device is in Power-down state. When PDN is set to 1, the device is activated and enters Program state. All registers will contain reset values when the device enters Program state. It can be set to any other state (Receive, Transmit, and UICR Program) using pin control or the SPI interface. State transitions are controlled by pins PDN, RX_EN, and TX_EN or bit fields in SPI registers CONFREG0 and CONFREG1. State transitions are shown in the following figure. For timings required when switching between operating states, see State transition timing on page 11. When the device is in Receive state, the receive path is active and the transmit path is disabled. In the Receive state, the LNA is enabled. When the device is in the Receive state, CSN needs to be driven low as shown in Figure 3: Pin control RX state on page 12. When the device is in Transmit state, the transmit path is enabled and the receive path is disabled. In Transmit state, the PA is enabled. The device features a configurable TX output power, see TX power control on page 13 for details. Note: Enabling multiple states simultaneously is not supported. UICR Program state enables programming of default settings for TX power control to UICR EFUSE (one time programmable memory). UICR Program state is accessed from Program state by writing specific values to register CONFREG1. Registers CONFREG2 and CONFREG3 are where bit programming definition and triggering of UICR EFUSE programming can take place. See UICR programming on page 13 for more details about UICR programming. The SPI register interface is described in detail in SPI interface on page 15. Receive Transmit TX_EN = 1 RX_EN = 0 RX_EN = 0 TX_EN = 0 RX_EN = 1 TX_EN = 0 Program PDN = 1 VDD > 1.7 V PDN = 0 PowerDown PDN = 0 CONFREG1.KEY = Leave Figure 2: State diagram 4446_194 v1.0 1. CONFREG1.UICR_EN = Enable 2. CONFREG1.KEY = Enter 10 UICR Program Device control State Symbol Description Power-down PD The device is in Power-down state. Program PG The device can be configured and set to other states. UICR program UICR User defined initialization values for POUTA_SEL, POUTA_UICR, POUTB_SEL, and POUTB_UICR can be configured to UICR. Receive RX The RX path is enabled. CSN = 0 Transmit TX The TX path is enabled. Table 4: Operating states description 5.2 Antenna control ANT_SEL selects the antenna interface used during RX or TX. Antenna interface control is specified in the following table. State ANT_SEL Description Power-down X Antenna switches disabled (i.e. isolating) Program X Antenna switches disabled (i.e. isolating) UICR program X Antenna switches disabled (i.e. isolating) 0 ANT1 enabled, ANT2 disabled 1 ANT1 disabled, ANT2 enabled 0 ANT1 enabled, ANT2 disabled 1 ANT1 disabled, ANT2 enabled Receive Transmit Table 5: Antenna switch control with ANT_SEL in different states 5.3 State transition timing Settling time requirements when switching between operational states are defined in the following table. When using SPI control, the maximum settling time is defined from the falling edge of SPI clock cycle 16. For more details on SPI, see SPI interface on page 15. Note: GPIO control is faster than SPI control. 4446_194 v1.0 11 Device control Symbol Parameter Note Max. Unit TPD→PG Settling time from state PD to PG Triggered by PDN 17.5 µs TPG→TRX Settling time from state PG to TX or Triggered by RX_EN, TX_EN, or RX through SPI register control 10.5 µs TTRX→PG Power-off time when changing from RX or TX to PG Triggered by RX_EN, TX_EN, or through SPI register control 3 µs TPG→PD Settling time from state PG to PD Triggered by PDN 10 µs Table 6: Settling times When the device is in the Receive state, CSN needs to be driven low. An example of RX timing using an RX_EN pin-based configuration is shown in the following figure. Figure 3: Pin control RX state The following figure shows the Receive state configured using SPI. Figure 4: SPI control RX state The following figure shows the Transmit state configured through pin. Figure 5: Pin control TX state The following figure shows the Transmit state configured using SPI. 4446_194 v1.0 12 Device control Figure 6: SPI control TX state 5.4 TX power control The output power for the Transmit state can be configured using either pin control or the SPI interface. Note: Gain should not be changed while the device is in the Transmit state. To configure the output power through pins, MODE can be used to set TX power control to one of two preset values. Preset values are used to update the TX_Gain value when MODE control changes in the Program state. The same functionality can be achieved by writing to the MODE bit in CONFREG0. Custom preset values can be stored in UICR and selected as default. The following table presents the TX_Gain initialization functionality. The SPI interface can also be used to control the output power. Before entering the Transmit state, TX Gain is configured by writing the gain value over SPI to register CONFREG0 TX_Gain field. SPI write will always overwrite the initialization value. The Gain word can be set in the same SPI write cycle as TX is enabled from the Program state. Changing MODE or the MODE bit in CONFREG0 will always trigger a reload of a default value to TX_Gain. Setting any of these will load POUTB. Clearing any of these will load POUTA. The default value will also be used even if a new value is loaded to TX_Gain during the SPI write cycle changing the MODE bit. The following table shows TX power control with MODE control and corresponding preset values of TX_Gain in program state. MODE POUTA_SEL POUTB_SEL TX_Gain Description 0 0 X POUTA_PROD Chip production default value used 1 X 0 POUTB_PROD Chip production default value used 0 1 X POUTA_UICR End-user default value used 1 X 1 POUTB_UICR End-user default value used Table 7: TX power control 5.5 UICR programming The UICR Program state enables the automated programming sequence for UICR EFUSE cell. 4446_194 v1.0 13 Device control The automated programming sequence can be utilized in the following manner. 1. Apply VDD supply voltage using the specifications set in the following table. 2. 3. 4. 5. 6. 7. Parameter Min. Max. VDD 3.45 V 3.60 V TOP 0°C 85°C Table 8: EFUSE programming conditions Enable UICR Program state by writing Enable to field UICR_EN in register CONFREG1. Enter UICR Program state by writing Enter to field KEY in register CONFREG1. Write desired configuration values for POUTB_SEL and POUTB_UICR to register CONFREG3. Write desired configuration values for POUTA_SEL and POUTA_UICR and write a 1 to WR_UICR in register CONFREG2. Wait for 0.5 ms to guarantee successful programming. Reset the circuit by setting PDN to 0 and then back to 1. The programmed values are now set for register CONFREG2 and CONFREG3. The device can be set to UICR mode to verify programmed values by reading registers CONFREG2 and CONFREG3. 4446_194 v1.0 14 6 SPI interface The data transitions for slave in and out (MOSI and MISO) happen on the falling edge of the serial clock (SCK). All SPI transfers are two bytes long. Input data is sampled on the rising edge of SCK, starting with the first rising edge. Therefore, it is required that the first bit is stable on the first rising clock edge of SCK. Common definitions for SPI bus are CPOL = 0 and CPHA = 0. In other words, SPI mode 0. The serial data frame is 16 bits long and consists of three parts in the following transmission order: command (Cmd), address, and data. All fields are sent on MOSI line MSB first. In the event of a write operation, a command is 2 bits long, an address is 6 bits long, followed by 8 bits of data. CSN is active low and it is assumed that it is set to 0 at least half an SCK cycle before the first rising edge of SCK, and then again to logical 1 earliest after half a cycle of 16th SCK falling edge. The following commands are used: • READ, b10 – This command allows reading of registers. The register address to read from is sent after the command. The read data will be clocked out to the MISO line during the data part of the SPI frame. • WRITE, b11 – This command allows writing to registers. The last 8 bits sent on the MOSI line will be written to a register pointed with 6-bit address field. The write command has writeback property. When a register is accessed by the write command to update its value, the previous register value will be written to MISO line in serial format MSB first. SPI timing specification presents the required timings between CSN signal and SCK edge. The following figure shows a configuration example for SPI when writing to register CONFREG0. The WRITE command b11 is written to the command field. The first bit on the MOSI line shall be set to its value (in this case to 1) before the first rising edge of SCK occurs, since Cmd is read on the rising edge of the first and second SCK cycle. SCK rising edges 3 to 8 are used to read the address field and 9 to 16 read the data field. Register CONFREG0 writeback data is written on the MISO line starting on the falling edge of cycle 8 so that cycle 9 to 16 rising edges can be used to read in MISO data on the Master side. Guaranteed settling time for the first read bit before the cycle 9 falling edge can be found in SPI timing specification. Functionality of the read operation is similar to writeback, meaning that read data is written to the MISO line starting on the cycle 8 falling edge when the read command is given in the Cmd field. An overview of register address space and accessibility of registers in different operation states is found in SPI timing. The detailed register map is given in the Register interface on page 20. Figure 7: SPI write configuration example 4446_194 v1.0 15 SPI interface Register Function Accessible via SPI in the following states CONFREG0 TX state control and TX gain control in Program state PG, RX, TX, UICR CONFREG1 RX state control and RX gain control in Program state PG, RX, TX, UICR CONFREG2, CONFREG3 UICR programming interface registers UICR PARTNUMBER, HW_REVISION[7:4] Part number, hardware revision PG HW_ID0, HW_ID1 Hardware ID PG Table 9: Register overview and accessibility in different operation states 4446_194 v1.0 16 7 Electrical specification The device is calibrated at 25°C to VDD = 3.0 V. Unless otherwise stated, the following conditions apply: • VDD = 3.0 V • ZL = 50 Ω • PIN_TRX = 0 dBm 7.1 Electrical specification 7.1.1 Current consumption Symbol Description Min. Typ. Max. Units IPD State: PD 45 nA IPG State: PG 0.7 mA IRX State: RX 2.9 mA ITX_10dBm State: TX 38 mA 110 mA POUT = 10 dBm ITX_20dBm State: TX POUT = 20 dBm 7.1.2 RX Symbol Description Min. f Operating frequency range 2360 Typ. Max. Units 2500 GRX Gain 13 MHz dB NFRX Noise figure 2.7 dB IMD3-50dBm Two tone IMD at -50 dBm -109 dBm -75 dBm Two tone CW, f0: 2440 MHz, f1: +/- 3 MHz, f2: +/- 6 MHz IMD3-30dBm Two tone IMD at -30 dBm Two tone CW, f0: 2440 MHz, f1: +/- 3 MHz, f2: +/- 6 MHz H2RX Harmonic 2nd (CW, -10 dBm) -20 dBm H3RX Harmonic 3rd (CW, -10 dBm) -17 dBm S11_ANTdB ANT port input reflection (over input frequency, 50 Ω) -7 dB S22_TRXdB TRX port output reflection (over input frequency, 50 Ω) -12.0 PMAX,RX Maximum output power (at TRX, PIN = 0 dBm) 2.5 5.0 dBm Typ. Max. Units 2500 MHz dB 7.1.3 TX Symbol Description Min. f Operating frequency range 2360 PSAT Saturated output power; GFSK/OQPSK modulation 21.5 dBm GTX Power Gain 20 dB 4446_194 v1.0 17 Electrical specification Symbol Description Tcarrier Carrier switching time Min. Typ. Max. Units 1 µs POUT from -30 dBm to +20 dBm PSPUR2MHz In-band spurious emissions 2 MHz (GFSK/OQPSK) -26 dBm PSPUR3MHz In-band spurious emissions 3 MHz (GFSK/OQPSK) -36 dBm H2, H3 Harmonic, 2nd, 3rd; RBW = 1.0 MHz -42 dBm S11_TRXdB Input reflection at TRX pin (over input frequency range, 50 -10 dB Ω) VSWRSTB Unconditionally stable - VSWRRGN No permanent damage (load 10:1, all phase angles) PAE Power Added Efficiency 32 % 7.1.4 SPI timing specification Symbol Description Min. Typ. Max. Units TSCK SCK clock period (50% duty cycle) 112 125 TCSN-SCK1 CSN lead time 62.5 ns 62.5 ns 125 ns 30 ns ns Time from CSN set to 0 to first rising edge at SCK TSCK16-CSN CSN trail time Time from 16th falling edge at SCK to CSN set to 1 TCSN CSN idle time Time required between consecutive transmissions TS_MISO MISO settling time Guaranteed settling margin for MISO before 9th rising edge at SCK 7.2 Typical characteristics The following figure shows the TX output power control behavior for typical conditions. Figure 8: TX gain control behavior 4446_194 v1.0 18 Electrical specification The following figure shows the relationship between TX gain and current consumption. Figure 9: TX gain and current consumption The following figure shows the TX gain over operating frequency for typical conditions, with TX gain set to 20 dB. Figure 10: TX gain over operating frequency 4446_194 v1.0 19 8 Register interface 8.1 Registers Base address Peripheral Instance Description Configuration 0x00000000 REGIF REGIF Register interface Table 10: Instances Register Offset Description CONFREG0 0x0 Configuration register 0 CONFREG1 0x1 Configuration register 1 CONFREG2 0x2 Configuration register 2 CONFREG3 0x3 Configuration register 3 PARTNUMBER 0x14 HW_REVISION 0x15 HW_ID0 0x16 HW_ID1 0x17 Table 11: Register overview 8.1.1 CONFREG0 Address offset: 0x0 Configuration register 0 Bit number 7 6 5 4 3 2 1 0 ID C C C C C B A Reset 0x00 ID Access Field A RW TX_EN B C 0 0 0 0 0 0 0 0 Value ID Value Description Disable 0 TX mode disabled Enable 1 TX mode enabled 0 0 TX_Gain = POUTA 1 1 TX_Gain = POUTB TX enable RW MODE Select preset value of TX output power. RW TX_GAIN TX gain control (0: minimum, 31: maximum) EFUSE value loaded at reset. Initialized with value from POUTA or POUTB. See CONFREG2 and CONFREG3. 8.1.2 CONFREG1 Address offset: 0x1 Configuration register 1 4446_194 v1.0 20 Register interface Bit number 7 6 5 4 3 2 1 0 ID E E E E Reset 0x00 0 0 0 0 0 0 0 0 ID Access Field A RW RX_EN C E Value ID Value Disable 0 RX mode disabled Enable 1 RX mode enabled Disable 0 Enable 1 Enter 15 Set to 0xF when enabling UICR program mode Leave 0 Set to 0x0 when leaving UICR program mode C A Description RX enable RW UICR_EN UICR program mode enable RW KEY UICR program mode enter/leave key 8.1.3 CONFREG2 Address offset: 0x2 Configuration register 2 Bit number 7 6 5 4 3 2 1 0 ID D Reset 0x00 ID Access Field A RW POUTA_UICR B RW POUTA_SEL B A A A A A 0 0 0 0 0 0 0 0 Value ID Value Description User defined initialization value for POUTA (0: minimum - PA disabled, 31: maximum) D 0 0 TX_Gain initialized with POUTA_PROD (20 dBm +/- 0.5 dB) 1 1 TX_Gain initialized with POUTA_UICR 0 0 EFUSE idle 1 1 EFUSE write RW WR_UICR Write UICR memory 8.1.4 CONFREG3 Address offset: 0x3 Configuration register 3 Bit number 7 6 5 4 3 2 1 0 ID B A A A A A Reset 0x00 ID Access Field A RW POUTB_UICR 0 0 0 0 0 0 0 0 Value ID Value Description User defined initialization value for POUTB (0: minimum - PA disabled, 31: maximum) B RW POUTB_SEL 0 0 TX_Gain initialized with POUTB_PROD (10 dBm +/- 1.5 dB) 1 1 TX_Gain initialized with POUTB_UICR 8.1.5 PARTNUMBER Address offset: 0x14 4446_194 v1.0 21 Register interface Bit number 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0xFF 1 1 1 1 1 1 1 1 ID Access Field A R Value ID Value 21540 0x0C Description PARTNUMBER Part identification number nRF21540 8.1.6 HW_REVISION Address offset: 0x15 Bit number 7 6 5 4 3 2 1 0 ID B B B B Reset 0xFF 1 1 1 1 1 1 1 1 ID Access Field B R Value ID Value Description HW_REVISION HW revision code QD 0x2 QFN16 8.1.7 HW_ID0 Address offset: 0x16 Bit number 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0xFF 1 1 1 1 1 1 1 1 ID Access Field A R Value ID Value Description HW_ID0 Hardware ID, MSB AAF0 0x01 8.1.8 HW_ID1 Address offset: 0x17 Bit number 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0xFF 1 1 1 1 1 1 1 1 ID Access Field A R Value ID Value AAF0 0x9B Description HW_ID1 4446_194 v1.0 Hardware ID, LSB 22 9 Hardware and layout 9.1 Pin assignments The pin assignment figure and tables describe the pinouts for the device. There are also recommendations for how the GPIO pins should be configured, in addition to any usage restrictions. Figure 11: QFN16 pin assignments, top view 4446_194 v1.0 23 Hardware and layout Pin number Pin name Type Description 1 VSS Power Ground RF I/O First antenna interface RF I/O Second antenna interface Digital IN TX power mode control Power Supply voltage Power Supply voltage Digital IN RX mode enable Digital IN Antenna select Digital IN TX mode enable RF IO Transceiver interface Digital IN Power-down, active low Digital IN SPI clock 2 3 4 5 6 7 8 9 10 11 12 ANT1 ANT2 MODE VDD VDD RX_EN ANT_SEL TX_EN TRX PDN SCK Connect to VSS if SPI interface is not used 13 MOSI Digital IN SPI data in Connect to VSS if SPI interface is not used 14 MISO Digital OUT SPI data out Leave unconnected if SPI interfaces is not used 15 CSN Digital IN SPI chip select, active low Connect to VDD if SPI interface is not used 16 DAP VSS VSS Power Ground Power Ground Table 12: Pin assignments 9.2 Mechanical specifications The mechanical specifications for the package shows the dimensions in millimeters. 9.2.1 QFN 4 x 4 mm package Dimensions in millimeters for the QFN 4 x 4 mm package. 4446_194 v1.0 24 Hardware and layout Figure 12: QFN 4 x 4 mm package A A1 Min. 0.8 0 Nom. 0.85 0.035 Max. 0.9 0.05 A3 b D E 0.25 0.203 0.3 4 4 0.35 D2 E2 e 2.55 2.55 2.65 2.65 2.75 2.75 0.65 9.3 Reference circuitry The reference circuitry schematic shows the application schematic. 4 7 8 9 U1 MODE RX_EN ANT_SEL TX_EN VDD VDD ANT1 RF_I C1 TRX 10 6 5 2 nRF21540 11 12 13 14 15 ANT1 L1 1.9nH TRX 1.0pF PDN SCK MOSI MISO CSN VDD_nRF C6 100nF PDN SCK MOSI MISO CSN ANT2 VSS VSS VSS 3 ANT2 L2 1.9nH C7 10µF RF_O1 C2 1.2pF C3 N.C. C4 1.2pF C5 N.C. RF_O2 1 16 17 nRF21540-QDAA Figure 13: Reference circuitry schematic The following table lists the recommended and tested component types and values. 4446_194 v1.0 25 L 0.35 Table 13: QFN dimensions in millimeters MODE RX_EN ANT_SEL TX_EN K 0.4 0.45 Hardware and layout Designator Value Description Footprint C1 1.0 pF Capacitor, NP0, ±5% 0201 C2, C4 1.2 pF Capacitor, NP0, ±5% 0201 C3, C5 N.C. C6 100 nF Capacitor, X7S, ±10% 0201 C7 10 µF Capacitor, X7S, ±20% 0603 L1, L2 1.9 nH High frequency chip inductor ±5% 0201 U1 nRF21540-QDAA Radio front-end /range extender for 2.4 GHz QFN-16 0201 Table 14: Bill of material for QFN16 4446_194 v1.0 26 10 Recommended operating conditions The operating conditions are the physical parameters that the chip can operate within. Symbol Parameter Notes Min. Nom. Max. Units VDD Main supply voltage/battery Functional range 1.7 3.0 3.6 V VIH Digital input high SPI, PDN, ANT_SEL 0.7 VVDD VVDD V VIL Digital input low SPI, PDN, ANT_SEL VVSS 0.3 VVDD V FSCK SPI clock frequency Exceeding may cause SPI malfunction CMISO MISO load capacitance TOP Operating Board temperature, 1 mm temperature range from the package ZL Load impedance 8 Exceeding may cause SPI read malfunction -40 +25 50 Table 15: Recommended operating conditions 4446_194 v1.0 27 8.9 MHz 50 pF +105 °C Ω 11 Absolute maximum ratings Maximum ratings are the extreme limits to which the chip can be exposed to for a limited amount of time without permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time may affect the reliability of the device. Pin Note Min. Max. Unit VDD Supply voltage 0 3.6 V VSS Supply voltage 0 V VI/O Digital I/O pin voltage -0.3 VDD + 0.3 V VDD ≤ 3.6 V PIN_TRX +5 dBm +15 dBm Min. Max. Unit -40 125 °C 260 °C RF I/O pin input power CW, Transmit mode PIN_ANT RF I/O pin input power CW, Receive/Program mode Table 16: Pin voltage Note Storage temperature Reflow soldering temperature IPC/JEDEC J-STD-020 MSL Moisture sensitivity level ESD HBM Human Body Model 1 kV ESD CDM Charged Device Model 2 kV Table 17: Environmental 4446_194 v1.0 28 12 Ordering information This chapter contains information on IC marking, ordering codes, and container sizes. 12.1 Package marking The nRF21540 package is marked as shown in the following figure. N 2 1 5 4 0 Figure 14: Package marking 12.2 Box labels The following figures show the box labels used for nRF21540. PART NO.: (1P) TRACE CODE: (1T) TRACE CODE QUANTITY: TOTAL QUANTITY: (Q) Pb Figure 15: Inner box label 4446_194 v1.0 29 e3 Ordering information FROM: TO: PART NO: (1P) CUSTOMER PO NO: (K) Pb SALES ORDER NO: (14K) SHIPMENT ID.: 2K QUANTITY: (Q) COUNTRY OF ORIGIN.: 4L CARTON NO: x/n DELIVERY NO.: (9K)