SiT5356
1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision
Super-TCXO
Description
Features
The SiT5356 is a ±100 ppb precision MEMS Super-TCXO
that is fully compliant to Telcordia GR-1244-CORE Stratum
3 oscillator specifications. Engineered for best dynamic
performance, the SiT5356 is ideal for high reliability
telecom, wireless and networking, industrial, precision
GNSS and audio/video applications.
◼
Leveraging SiTime’s unique DualMEMS® temperature
sensing and TurboCompensation® technologies, the
SiT5356 delivers the best dynamic performance for timing
stability in the presence of environmental stressors such as
air flow, temperature perturbation, vibration, shock, and
electromagnetic interference. This device also integrates
multiple on-chip regulators to filter power supply noise,
eliminating the need for a dedicated external LDO.
◼
The SiT5356 offers three device configurations that can be
ordered using Ordering Codes for:
1) TCXO with non-pullable output frequency,
2) VCTCXO allowing voltage control of output frequency,
3) DCTCXO enabling digital control of output frequency
using an I2C interface, pullable to 5 ppt (parts per
trillion) resolution.
The SiT5356 can be factory programmed for any
combination of frequency, stability, voltage, and pull range.
Programmability enables designers to optimize clock
configurations while eliminating long lead times and
customization costs associated with quartz devices where
each frequency is custom built.
Refer to Manufacturing Guideline for proper reflow profile
and PCB cleaning recommendations to ensure best
performance.
Block Diagram
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Any frequency from 1 MHz to 60 MHz in 1 Hz steps
Factory programmable options for short lead time
Best dynamic stability under airflow, thermal shock
▪ ±100 ppb stability across temperature
▪ ±1 ppb/C typical frequency slope (ΔF/ΔT)
▪ 1.5e-11 ADEV at 10 second averaging time
-40°C to +105°C operating temperature
No activity dips or micro jumps
Resistant to shock, vibration and board bending
On-chip regulators eliminate the need for external LDOs
Digital frequency pulling (DCTCXO) via I 2C
▪ Digital control of output frequency and pull range
▪ Up to ±3200 ppm pull range
▪ Frequency pull resolution down to 5 ppt
2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage
LVCMOS or clipped sinewave output
RoHS and REACH compliant
Pb-free, Halogen-free, Antimony-free
Applications
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4G/5G radio, Small cell
IEEE1588 boundary and grandmaster clocks
Carrier-grade routers and switches
Synchronous Ethernet
Optical transport – SONET/SDH, OTN, Stratum 3
DOCSIS 3.x remote PHY
GPS disciplined oscillators
Precision GNSS systems
Test and measurement
Related products for automotive applications.
For aerospace and defense applications SiTime
recommends using only Endura™ SiT5346.
5.0 mm x 3.2 mm Package Pinout
SDA / NC
OE / VC / NC
1
9
VDD
SCL / NC
2
8
NC
NC
3
7
NC
GND
4
6
CLK
10
5
A0 / NC
Figure 2. Pin Assignments (Top view)
(Refer to Table 13 for Pin Descriptions)
Figure 1. SiT5356 Block Diagram
Rev 1.08
1 January 2023
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Ordering Information
The part number guide illustrated below is for reference only, in which boxes identify order codes having more than one option.
To customize and build an exact part number, use the SiTime Part Number Generator. To validate the part number, use the
SiTime Part Number Decoder.
Part
Family
TCXO
VCTCXO
DCTCXO
Silicon
Revision
Letter
Package Size
Pin 1 Function – TCXO mode only
"F": 5.0 mm x 3.2 mm
"E": Output Enable
"N": No Connect
SiT5356AC - FQ - 33 E 0 - 19.123456 T
SiT5356AC - FQ - 33 V T - 19.123456 T
SiT5356AC - FQG33 J R - 19.123456 T
Temperature Range
Packaging
"I": Industrial, -40 to 85°C
"C": Extended Commercial, -20 to 70°C
"E": Extended Industrial, -40 to 105°C
"T": 12 mm Tape & Reel, 3 ku reel
"Y": 12 mm Tape & Reel, 1 ku reel
"X": 12 mm Tape & Reel, 250 u reel
(blank): bulk[2]
Output Waveform
"-": LVCMOS[1]
"C": Clipped Sinewave
Frequency
Frequency Stability
Pull Range – DCTCXO mode only
"Q": for ±0.1 ppm
"P": for ±0.2 ppm
"N": for ±0.25 ppm
"T": ±6.25 ppm
"R": ±10 ppm
"Q": ±12.5 ppm
"M": ±25 ppm
"B": ±50 ppm
"C": ±80 ppm
"E": ±100 ppm
"F": ±125 ppm
1.000000 MHz to 60.000000 MHz
I2C Address Mode – DCTCXO mode only
“0”, “1”, “2”, “3”, “4”, “5”, “6”, “7”, “8”, “9”, “A”, “B”,
“C”, “D”, “E”, “F”: Order code representing hex
value of I2C address. When the I2C address is
factory programmed using this code, pin A0 is no
connect (NC).
"G":
"H":
"X":
"L":
"Y":
"S":
"Z":
"U":
±150 ppm
±200 ppm
±400 ppm
±600 ppm
±800 ppm
±1200 ppm
±1600 ppm
±3200 ppm
Pin 1 Function – DCTCXO mode only
"I": Output Enable
"J": No Connect, software OE control
“G”: I2C pin addressable mode. Address is set by
the logic on A0 pin.
Supply Voltage
"25": 2.5 V ±10%
"28": 2.8 V ±10%
"30": 3.0 V ±10%
"33": 3.3 V ±10%
Notes:
1. “-“ corresponds to the default rise/fall time for LVCMOS output as specified in Table 1 (Electrical Characteristics). Contact SiTime for other rise/fall time
options for best EMI or driving multiple loads. For differential outputs, contact SiTime.
2. Bulk is available for sampling only.
Rev 1.08
Page 2 of 41
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
TABLE OF CONTENTS
Description ................................................................................................................................................................................... 1
Features....................................................................................................................................................................................... 1
Applications ................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................. 1
5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1
Ordering Information .................................................................................................................................................................... 2
Electrical Characteristics.............................................................................................................................................................. 4
Device Configurations and Pin-outs ........................................................................................................................................... 10
Pin-out Top Views............................................................................................................................................................... 10
Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 11
Waveforms................................................................................................................................................................................. 13
Timing Diagrams ........................................................................................................................................................................ 14
Stability Diagrams ...................................................................................................................................................................... 14
Typical Performance Plots ......................................................................................................................................................... 15
Architecture Overview ................................................................................................................................................................ 19
Frequency Stability ............................................................................................................................................................. 19
Output Frequency and Format ............................................................................................................................................ 19
Output Frequency Tuning ................................................................................................................................................... 19
Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 20
Device Configurations ................................................................................................................................................................ 20
TCXO Configuration ........................................................................................................................................................... 20
VCTCXO Configuration ...................................................................................................................................................... 21
DCTCXO Configuration ...................................................................................................................................................... 22
VCTCXO-Specific Design Considerations ................................................................................................................................. 23
Linearity .............................................................................................................................................................................. 23
Control Voltage Bandwidth ................................................................................................................................................. 23
FV Characteristic Slope KV ................................................................................................................................................. 23
Pull Range, Absolute Pull Range ........................................................................................................................................ 24
DCTCXO-Specific Design Considerations ................................................................................................................................. 25
Pull Range and Absolute Pull Range .................................................................................................................................. 25
Output Frequency ............................................................................................................................................................... 26
I2C Control Registers .......................................................................................................................................................... 28
Register Descriptions.......................................................................................................................................................... 28
Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 28
Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 29
Register Address: 0x02. DIGITAL PULL RANGE CONTROL[18] ........................................................................................ 30
Serial Interface Configuration Description .......................................................................................................................... 31
Serial Signal Format ........................................................................................................................................................... 31
Parallel Signal Format ........................................................................................................................................................ 32
Parallel Data Format ........................................................................................................................................................... 32
I2C Timing Specification ...................................................................................................................................................... 34
I2C Device Address Modes ................................................................................................................................................. 35
Schematic Example ............................................................................................................................................................ 36
Dimensions and Patterns ........................................................................................................................................................... 37
Layout Guidelines ...................................................................................................................................................................... 38
Manufacturing Guidelines .......................................................................................................................................................... 38
Additional Information ................................................................................................................................................................ 39
Revision History ......................................................................................................................................................................... 40
Rev 1.08
Page 3 of 41
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output loa d unless otherwise
stated. Typical values are at 25°C and 3.3 V Vdd.
Table 1. Output Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Frequency Coverage
Nominal Output Frequency Range
F_nom
1
–
60
MHz
Temperature Range
Operating Temperature Range
T_use
-20
–
+70
°C
Extended Commercial, ambient temperature
-40
–
+85
°C
Industrial, ambient temperature
-40
–
+105
°C
Extended Industrial, ambient temperature
Frequency Stability – Stratum 3+ Grade
–
±0.1
ppm
Referenced to (max frequency + min frequency)/2 over the
rated temperature range, in TCXO, DCTCXO, or VCTCXO
(VCTCXO with ±6.25 ppm pull range, Vc=Vdd/2)
–
–
±0.3
ppm
Initial frequency at 25°C at 48 hours after 2 reflows
–
±0.5
±2.5
ppb
Vdd ±5%
F_load
–
±0.05
±0.4
ppb
LVCMOS output, 15 pF ±10%. Clipped sinewave output,
10 kΩ || 10 pF ±10%
ΔF/ΔT
–
±0.9
±2
ppb/°C
0.5°C/min temperature ramp rate, -20 to 85°C
–
±1
±3.5
ppb/°C
0.5°C/min temperature ramp rate, -40 to -20°C
–
±0.9
±3.3
ppb/°C
0.5°C/min temperature ramp rate, 85 to 105°C
–
±0.008
±0.02
ppb/s
0.5°C/min temperature ramp rate, -20 to 85°C
–
±0.01
±0.03
ppb/s
0.5°C/min temperature ramp rate, -40 to -20°C
–
±0.008
±0.028
ppb/s
0.5°C/min temperature ramp rate, 85 to 105°C
F_24_Hold
–
–
±0.15
ppm
Inclusive of frequency variation due to temperature, ±10%
supply variation, ±1.5 pF load variation and 24-hour aging
F_hys
–
±25
±42
ppb
-40 to 105°C, 0.5°C/min ramp rate, defined as ±ΔF/2 as
shown in Figure 19, contact SiTime for lower hysteresis
–
±15
±27
ppb
-40 to 85°C, 0.5°C/min ramp rate, defined as ±ΔF/2 as
shown in Figure 19, contact SiTime for lower hysteresis
–
±10
±20
ppb
-20 to 70°C, 0.5°C/min ramp rate, defined as ±ΔF/2 as
shown in Figure 19, contact SiTime for lower hysteresis
F_stab
–
Initial Tolerance
F_init
Supply Voltage Sensitivity
F_Vdd
Output Load Sensitivity
Frequency vs. Temperature Slope
Frequency Stability over
Temperature
Dynamic Frequency Change during
Temperature Ramp
24-hour holdover stability
Hysteresis Over Temperature
F_dynamic
One-Day Aging
F_1d
–
±0.5
±2.0
ppb
At 85°C, after 30-days of continued operation. Aging is
measured with respect to day 31.
One-Year Aging
F_1y
–
±57
±230
ppb
5-Year Aging
F_5y
–
±73
±320
ppb
At 85°C, after 2-days of continued operation. Aging is
measured with respect to day 3.
10-Year Aging
F_10y
–
±80
±360
ppb
20-Year Aging
F_20y
–
±87
±400
ppb
Allan deviation
ADEV
–
1.5e-11
–
–
10 second averaging time [3]
Frequency Stability – Stratum 3 Grade
Frequency Stability over
Temperature
F_stab
–
–
±0.2
ppm
–
–
±0.25
ppm
Referenced to (max frequency + min frequency)/2 over the
rated temperature range. Vc=Vdd/2 for VCTCXO
Initial Tolerance
F_init
–
–
±1
ppm
Initial frequency at 25°C at 48 hours after 2 reflows
Supply Voltage Sensitivity
F_Vdd
–
±3.0
±6.5
ppb
Vdd ±5%
Output Load Sensitivity
F_load
–
±0.3
±1.1
ppb
LVCMOS output, 15 pF ±10%. Clipped sinewave output,
10 kΩ || 10 pF ±10%
ΔF/ΔT
–
±6.4
±10
ppb/°C
Dynamic Frequency Change during
Temperature Ramp
F_dynamic
–
±0.05
±0.08
ppb/s
0.5°C/min temperature ramp rate
24-hour holdover stability
F_24_Hold
–
–
±0.28
ppm
Inclusive of frequency variation due to temperature, ±10%
supply variation, ±1.5 pF load variation and 24-hour aging
F_1d
–
±3
±5
ppb
At 25°C, after 30-days of continued operation. Aging is
measured with respect to day 31
One-Year Aging
F_1y
–
±1
–
ppm
20-Year Aging
F_20y
–
±2
–
ppm
At 25°C, after 2-days of continued operation. Aging is
measured with respect to day 3
F_tot_20y
–
–
±4.6
ppm
Frequency vs. Temperature Slope
One-Day Aging
20-Year Total Stability
Rev 1.08
Page 4 of 41
-40 to 105°C
Complies with Stratum 3 per GR-1244-CORE. Actual
performance is better
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Table 1. Output Characteristics (continued)
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
LVCMOS Output Characteristics
DC
45
–
55
%
Rise/Fall Time
Tr, Tf
0.8
1.2
1.9
ns
Output Voltage High
VOH
90%
–
–
Vdd
IOH = +3 mA
Output Voltage Low
VOL
–
–
10%
Vdd
IOL = -3 mA
Z_out_c
–
17
–
Ohms
Impedance looking into output buffer, Vdd = 3.3 V
–
17
–
Ohms
Impedance looking into output buffer, Vdd = 3.0 V
–
18
–
Ohms
Impedance looking into output buffer, Vdd = 2.8 V
–
19
–
Ohms
Impedance looking into output buffer, Vdd = 2.5 V
Duty Cycle
Output Impedance
10% - 90% Vdd
Clipped Sinewave Output Characteristics
Output Voltage Swing
V_out
0.8
–
1.2
V
Clipped sinewave output, 10 kΩ || 10 pF ±10%
Rise/Fall Time
Tr, Tf
–
3.5
4.6
ns
20% - 80% Vdd, F_nom = 19.2 MHz
ms
Time to first pulse, measured from the time Vdd reaches
90% of its final value. Vdd ramp time = 100 µs from 0 V to
Vdd
Start-up Characteristics
Start-up Time
Output Enable Time
Time to Rated Frequency Stability
T_start
–
2.5
3.5
T_oe
–
–
680
ns
F_nom = 10 MHz. See Timing Diagrams section below
T_stability
–
5
45
ms
Time to first accurate pulse within rated stability, measured
from the time Vdd reaches 90% of its final value.
Vdd ramp time = 100 µs
Note:
3. Measured 2 hours after startup in a temperature chamber with a constant temperature in still air.
Table 2. DC Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Supply Voltage
Supply Voltage
Vdd
2.25
2.5
2.75
V
2.52
2.8
3.08
V
2.7
3.0
3.3
V
2.97
3.3
3.63
V
Contact SiTime for 2.25 V to 3.63 V continuous supply
voltage support
Current Consumption
Current Consumption
OE Disable Current
Rev 1.08
Idd
I_od
–
44
53
mA
F_nom = 19.2 MHz, No Load, TCXO and DCTCXO modes
–
48
57
mA
F_nom = 19.2 MHz, No Load, VCTCXO mode
–
43
51
mA
OE = GND, output weakly pulled down. TCXO, DCTCXO
–
47
55
mA
OE = GND, output weakly pulled down. VCTCXO mode
Page 5 of 41
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Table 3. Input Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Input Characteristics – OE Pin
Input Impedance
Z_in
75
–
–
kΩ
Input High Voltage
VIH
70%
–
–
Vdd
Input Low Voltage
VIL
–
–
30%
Vdd
Internal pull up to Vdd
Frequency Tuning Range – Voltage Control or I2C mode
Pull Range
Absolute Pull Range[3]
PR
APR
±6.25
–
–
ppm
VCTCXO mode. Contact SiTime for ±12.5 and ±25 ppm
±6.25
±10
±12.5
±25
±50
±80
±100
±125
±150
±200
±400
±600
±800
±1200
±1600
±3200
–
–
ppm
DCTCXO mode
±5.31
–
–
ppm
±0.1 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
±3.05
–
–
ppm
±0.2 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
±3.00
–
–
ppm
±0.25 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
Upper Control Voltage
VC_U
90%
–
–
Vdd
VCTCXO mode
Lower Control Voltage
VC_L
–
–
10%
Vdd
VCTCXO mode
Control Voltage Input Impedance
VC_z
8
–
–
MΩ
VCTCXO mode
Control Voltage Input Bandwidth
VC_bw
–
10
–
kHz
VCTCXO mode. Contact SiTime for other bandwidth
options
1.0
%
Frequency Control Polarity
F_pol
Pull Range Linearity
PR_lin
Positive
–
0.5
VCTCXO mode
VCTCXO mode
I2C Interface Characteristics, 200 Ohm, 550 pF (Max I2C Bus Load)
Bus Speed
F_I2C
≤ 400
kHz
-40 to 105°C
≤ 1000
kHz
-40 to 85°C
Input Voltage Low
VIL_I2C
–
–
30%
Vdd
DCTCXO mode
Input Voltage High
VIH_I2C
70%
–
–
Vdd
DCTCXO mode
Output Voltage Low
VOL_I2C
–
–
0.4
V
DCTCXO mode
IL
0.5
–
24
µA
0.1 VDD< VOUT < 0.9 VDD. Includes typical leakage current
from 200 kΩ pull resister to VDD. DCTCXO mode
CIN
–
–
5
pF
DCTCXO mode
Input Leakage current
Input Capacitance
Note:
4. APR = PR – initial tolerance – 20-year aging – frequency stability over temperature. Refer to Table 17 for APR with respect to other pull range options.
Rev 1.08
Page 6 of 41
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Table 4. Jitter & Phase Noise – LVCMOS, -40°C to 85°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.48
ps
F_nom = 10 MHz, Integration bandwidth = 12 kHz to 5 MHz
–
0.31
0.48
ps
F_nom = 50 MHz, Integration bandwidth = 12 kHz to 20 MHz
RMS Period Jitter
T_jitt_per
–
0.8
1.1
ps
F_nom = 10 MHz, population 10 k
Peak Cycle-to-Cycle Jitter
T_jitt_cc
–
6
9
ps
F_nom = 10 MHz, population 1 k, measured as absolute
value
1 Hz offset
–
-80
-74
dBc/Hz
10 Hz offset
–
-108
-102
dBc/Hz
100 Hz offset
–
-127
-123
dBc/Hz
1 kHz offset
–
-148
-145
dBc/Hz
10 kHz offset
–
-154
-151
dBc/Hz
100 kHz offset
–
-154
-150
dBc/Hz
1 MHz offset
–
-167
-163
dBc/Hz
5 MHz offset
–
-168
-164
dBc/Hz
–
-112
-105
dBc
Phase Noise
T_spur
Spurious
F_nom = 10 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
F_nom = 10 MHz, 1 kHz to 5 MHz offsets
Table 5. Jitter & Phase Noise – Clipped Sinewave, -40°C to 85°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.45
ps
F_nom = 19.2 MHz, Integration bandwidth = 12 kHz to 5 MHz
–
0.31
0.48
ps
F_nom = 60 MHz, Integration bandwidth = 12 kHz to 20 MHz
Phase Noise
1 Hz offset
–
-74
-68
dBc/Hz
10 Hz offset
–
-102
-97
dBc/Hz
100 Hz offset
–
-121
-117
dBc/Hz
1 kHz offset
–
-142
-140
dBc/Hz
10 kHz offset
–
-148
-146
dBc/Hz
100 kHz offset
–
-149
-145
dBc/Hz
1 MHz offset
–
-162
-158
dBc/Hz
5 MHz offset
–
-164
-159
dBc/Hz
–
-109
-104
dBc
Spurious
Rev 1.08
T_spur
Page 7 of 41
F_nom = 19.2 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
F_nom = 19.2 MHz, 1 kHz to 5 MHz offsets
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Table 6. Jitter & Phase Noise – LVCMOS, -40°C to 105°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.48
ps
F_nom = 10 MHz, Integration bandwidth = 12 kHz to 5 MHz
–
0.31
0.50
ps
F_nom = 50 MHz, Integration bandwidth = 12 kHz to 20 MHz
RMS Period Jitter
T_jitt_per
–
0.8
1.1
ps
F_nom = 10 MHz, population 10 k
Peak Cycle-to-Cycle Jitter
T_jitt_cc
–
6
9
ps
F_nom = 10 MHz, population 1 k, measured as absolute value
Phase Noise
1 Hz offset
–
-80
-74
dBc/Hz
10 Hz offset
–
-108
-102
dBc/Hz
100 Hz offset
–
-127
-123
dBc/Hz
1 kHz offset
–
-148
-145
dBc/Hz
10 kHz offset
–
-154
-151
dBc/Hz
100 kHz offset
–
-154
-150
dBc/Hz
1 MHz offset
–
-167
-162
dBc/Hz
5 MHz offset
–
-168
-163
dBc/Hz
–
-112
-101
dBc
F_nom = 10 MHz, 1 kHz to 5 MHz offsets, Vdd = 2.5 V
–
-112
-106
dBc
F_nom = 10 MHz, 1 kHz to 5 MHz offsets,
Vdd = 2.8 V, 3.0 V, 3.3 V
Spurious
T_spur
F_nom = 10 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
Table 7. Jitter & Phase Noise – Clipped Sinewave, -40°C to 105°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.46
ps
F_nom = 19.2 MHz, Integration bandwidth = 12 kHz to 5 MHz
–
0.31
0.50
ps
F_nom = 60 MHz, Integration bandwidth = 12 kHz to 20 MHz
Phase Noise
1 Hz offset
–
-74
-68
dBc/Hz
10 Hz offset
–
-102
-97
dBc/Hz
100 Hz offset
–
-121
-117
dBc/Hz
1 kHz offset
–
-142
-140
dBc/Hz
10 kHz offset
–
-148
-146
dBc/Hz
100 kHz offset
–
-149
-145
dBc/Hz
1 MHz offset
–
-162
-158
dBc/Hz
5 MHz offset
–
-164
-159
dBc/Hz
–
-109
-103
dBc
Spurious
Rev 1.08
T_spur
Page 8 of 41
F_nom = 19.2 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
F_nom = 19.2 MHz, 1 kHz to 5 MHz offsets
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Table 8. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Test Conditions
Storage Temperature
Continuous Power Supply Voltage Range (Vdd)
Human Body Model (HBM) ESD Protection
JESD22-A114
Soldering Temperature (follow standard Pb-free soldering guidelines)
Value
Unit
-65 to 125
°C
-0.5 to 4
V
2000
V
260
°C
130
°C
Input Voltage, Maximum
Any input pin
Vdd + 0.3
V
Input Voltage, Minimum
Any input pin
-0.3
V
Junction Temperature[5]
Note:
5. Exceeding this temperature for an extended period of time may damage the device.
Table 9. Thermal Considerations[6]
Package
JA[7] (°C/W)
JC, Bottom (°C/W)
Ceramic 5.0 mm x 3.2 mm
54
15
Note:
6. Measured in still air. Refer to JESD51 for θJA and θJC definitions.
7. Devices soldered on a JESD51 2s2p compliant board.
Table 10. Maximum Operating Junction Temperature[8]
Max Operating Temperature (ambient)
Maximum Operating Junction Temperature
70°C
80°C
85°C
95°C
105°C
115°C
Note:
8. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 11. Environmental Compliance
Value
Unit
Mechanical Shock Resistance
Parameter
MIL-STD-883F, Method 2002
30000
g
Mechanical Vibration Resistance
MIL-STD-883F, Method 2007
70
g
Temperature Cycle
JESD22, Method A104
–
–
Solderability
MIL-STD-883F, Method 2003
–
–
Moisture Sensitivity Level
MSL1 @260°C
–
–
Rev 1.08
Test Conditions
Page 9 of 41
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Device Configurations and Pin-outs
Table 12. Device Configurations
I2C Programmable Parameters
Configuration
Pin 1
Pin 5
TCXO
OE/NC
NC
–
–
VCTCXO
VC
NC
DCTCXO
OE/NC
A0/NC
Frequency Pull Range, Frequency Pull Value, Output Enable control
Pin-out Top Views
OE/NC
1
NC
9
VDD
VC
1
2
8
NC
NC
NC
3
7
NC
GND
4
6
CLK
10
5
SDA
NC
NC
OE / NC
1
NC
SCL
7
NC
6
CLK
9
VDD
2
8
NC
3
GND
4
10
5
9
VDD
2
8
NC
NC
3
7
NC
GND
4
6
CLK
5
A0 / NC
NC
Figure 4. VCTCXO
NC
Figure 3. TCXO
10
Figure 5. DCTCXO
Table 13. Pin Description
Pin
1
2
Symbol
OE/NC/VC
SCL / NC [11]
I/O
Internal Pull-up/Pull Down
Resistor
3
NC
4
GND
5
A0 / NC [11]
H : specified frequency output
L: output is high impedance. Only output driver is disabled
OE – Input
100 kΩ Pull-Up
NC[11] – No Connect
–
H or L or Open: No effect on output frequency or other device functions
VC – Input
–
Control Voltage in VCTCXO Mode
SCL – Input
200 kΩ Pull-Up
No Connect
[11]
Function
[9]
I2C serial clock input
H or L or Open: No effect on output frequency or other device functions
No Connect
–
H or L or Open: No effect on output frequency or other device functions
Power
–
Connect to ground
Device I2C address when the address selection mode is via the A0 pin.
This pin is NC when the I2C device address is specified in the ordering
code.
A0 Logic Level I2C Address
0
1100010
1
1101010
A0 – Input
100 kΩ Pull-Up
NC – No Connect
–
H or L or Open: No effect on output frequency or other device functions.
Output
–
LVCMOS, or clipped sinewave oscillator output
7
NC
[11]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
8
NC [11]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
9
VDD
Power
–
Connect to power supply[1010]
SDA / NC [11]
SDA – Input/Output
200 kΩ Pull Up
10
NC – No Connect
–
6
CLK
I2C Serial Data
H or L or Open: No effect on output frequency or other device functions
Notes:
9. In OE mode for noisy environments, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use
the NC option.
10. A 0.1 μF capacitor in parallel with a 10 μF capacitor are required between VDD and GND. The 0.1 μF capacitor is recommended to place close to the
device, and place the 10 μF capacitor less than 2 inches away.
11. All NC pins can be left floating and do not need to be soldered down.
Rev 1.08
Page 10 of 41
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs
VDD
CLK
9
+
7
10
10µF
5
1
2
3
4
15pF
7
6
10
10µF
-
(including probe
and fixture
capacitance)
8
0.1µF
Power
Supply
Test Point
CLK
9
+
6
0.1µF
Power
Supply
-
8
VDD
Test Point
5
1
2
3
10pF
10kΩ
(including probe
and fixture
resistance and
capacitance)
4
Vdd
Vdd
OE Function
OE Function
Figure 6. LVCMOS Test Circuit (OE Function)
VDD
CLK
9
+
8
7
VDD
Test Point
10
5
10µF
1
2
3
15pF
4
7
6
10pF
10
10µF
-
(including probe
and fixture
capacitance)
8
0.1µF
Power
Supply
Test Point
CLK
9
+
6
0.1µF
Power
Supply
-
Figure 7. Clipped Sinewave Test Circuit (OE Function)
for AC and DC Measurements
10kΩ
5
1
2
3
(including probe
and fixture
resistance and
capacitance)
4
Control
Voltage
Control
Voltage
VC Function
VC Function
Figure 9. Clipped Sinewave Test Circuit (VC Function)
for AC and DC Measurements
Figure 8. LVCMOS Test Circuit (VC Function)
VDD
CLK
9
+
7
VDD
6
10
10µF
1
5
2
3
4
15pF
(including probe
and fixture
capacitance)
Any state
or floating
Rev 1.08
6
1
5
2
3
4
10pF
10kΩ
(including probe
and fixture
resistance and
capacitance)
Any state
or floating
NC Function
Figure 10. LVCMOS Test Circuit (NC Function)
7
10
10µF
-
8
0.1µF
Power
Supply
Test Point
CLK
9
+
0.1µF
Power
Supply
-
8
Test Point
NC Function
Figure 11. Clipped Sinewave Test Circuit (NC Function)
for AC and DC Measurements
Page 11 of 41
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs (continued)
VDD
9
+
8
7
6
A0/NC
0.1µF
Power
Supply
10
10µF
-
Test Point
CLK
5
1
SDA[11]
2
Any state
or floating
NC
Function
3
15pF
(including probe
and fixture
capacitance)
4
SCL
Figure 12. LVCMOS Test Circuit (I2C Control), DCTCXO mode for AC and DC Measurements
VDD
9
+
8
7
A0/NC
6
0.1µF
Power
Supply
10
10µF
-
Test Point
CLK
1
SDA[11]
10pF
5
2
Any state
or floating
NC
Function
3
10kΩ
(including probe
and fixture
resistance and
capacitance)
4
SCL
Figure 13. Clipped Sinewave Test Circuit (I2C Control), DCTCXO mode for AC and DC Measurements
VDD
CLK
Test Point
9
+
-
8
7
6
A0/NC
0.1µF
Power
Supply
10pF
10
10µF
1
5
2
3
4
10kΩ
(including probe
and fixture
resistance and
capacitance)
Any state
or floating
NC Function
Figure 14. Clipped Sinewave Test Circuit for Phase Noise Measurements, Applies to All Configurations
(NC Function shown for example only)
Note:
12. SDA is open-drain and may require pull-up resistor if not present in I2C test setup.
Rev 1.08
Page 12 of 41
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Waveforms
tr
tf
90 % Vdd
50 % Vdd
10 % Vdd
High Pulse
(TH)
Low Pulse
(TL)
Period
Figure 15. LVCMOS Waveform Diagram[13]
tr
tf
80 % Vout
50 % Vout
Vout
20 % Vout
High Pulse
(TH)
Low Pulse
(TL)
Period
Figure 16. Clipped Sinewave Waveform Diagram[13]
Note:
13. Duty Cycle is computed as Duty Cycle = TH/Period.
Rev 1.08
Page 13 of 41
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Timing Diagrams
90% Vdd
Vdd
Vdd
50% Vdd
T_start
Vdd Pin
Voltage
OE Voltage
CLK Output
T_oe
CLK Output
HZ
HZ
T_start: Time to start from power-off
T_oe: Time to re-enable the clock output
Figure 18. OE Enable Timing (OE Mode Only)
Figure 17. Startup Timing
Stability Diagrams
Figure 19. Illustration of hysteresis, where ΔF is max
frequency difference between up and down cycles
across temperature
Rev 1.08
Page 14 of 41
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Typical Performance Plots
Breezy Air
Still Air
Breezy Air
Still Air
TDEV (s)
Allan Deviation
1E-09
1E-10
1E-11
1E-12
0.033
1E-11
1
10
100
1000
0.33
3.3
Still Air
ITU-T G.8262, EEC2
Frequency deviation (ppb)
MTIE (s)
1E-08
1E-09
1E-10
1E-11
3.3
33
330
2.5 V
100
1E-07
0.33
3300
0
-50
-100
-40
Figure 22. MTIE (0.1 Hz loop bandwidth, ±0.1 ppm) [14]
2.5 V
-20
0
Frequency deviation (ppm)
Frequency vs. Temperature
Slope (ppb/°C)
3.3 V
0.5
-0.5
-1.5
-2.5
-20
0
20
40
60
80
20
40
Temperature (°C)
60
80
100
Figure 23. Frequency vs Temperature (±0.1 ppm), 105°C
1.5
-40
3.3 V
50
Observation interval (s)
2.5
330
Figure 21. TDEV (0.1 Hz loop bandwidth, ±0.1 ppm) [14]
Figure 20. ADEV (±0.1 ppm) [14]
Breezy Air
33
Averaging time (s)
Time (s)
10
8
6
4
2
0
-2
-4
-6
-8
-10
0.3
100
Temperature (°C)
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
Control Voltage (V)
Figure 24. Freq. vs. Temp. Slope (ΔF/ΔT), ±0.1 ppm device
Figure 25. VCTCXO frequency pull characteristic
5
50
4
40
3
30
Frequency drift (ppb)
Aging rate (ppb/day)
ITU-T G.8262, EEC2
1E-08
1E-10
2
1
0
-1
-2
-3
20
10
0
-10
-20
-30
-40
-4
-50
-5
30
35
40
45
Day
50
55
60
Figure 26. 1-day aging rate after 30 days, 0.1 ppm device
Rev 1.08
Page 15 of 41
30
40
50
60
Day
Figure 27. Frequency drift after 30 days [15]
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Typical Performance Plots (continued)
2.5 V
3.3 V
2.5 V
1.5
Frequency sensitivity (ppb)
Frequency sensitivity (ppb)
0.06
0.04
0.02
0
-0.02
-0.04
3.3 V
1
0.5
0
-0.5
-1
-1.5
-0.06
-10
-5
0
5
-10
10
Load variation (%)
Figure 28. Load sensitivity (±0.1 ppm )
2.5 V
2.8 V
-5
0
5
10
Power supply voltage variation (%)
3.0 V
Figure 29. VDD sensitivity (±0.1 ppm)
3.3 V
2.5 V
1.25
55
2.8 V
3.0 V
3.3 V
1.20
Rise time (ns)
Duty cycle (%)
53
51
49
47
1.15
1.10
1.05
1.00
0.95
0.90
45
10
20
30
40
50
10
60
20
Frequency (MHz)
2.5 V
3.0 V
3.3 V
2.5 V
46
45
44
43
42
41
40
10
2.8 V
3.0 V
3.3 V
20
30
40
50
51
50
49
48
47
46
45
44
60
10
20
Frequency (MHz)
2.5 V
500
2.8 V
30
40
50
60
Frequency (MHz)
Figure 32. IDD TCXO (LVCMOS)
Figure 33. IDD VCTCXO (LVCMOS)
3.0 V
3.3 V
2.5 V
3.3 V
1.90
Period Jitter (ps RMS)
Phase Jitter (fs RMS)
60
52
47
400
300
200
100
0
1.70
1.50
1.30
1.10
0.90
0.70
0.50
10
20
30
40
50
60
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
Figure 34. RMS Phase Jitter, DCTCXO, TCXO (LVCMOS)
Rev 1.08
50
Figure 31. Rise Time (LVCMOS)
Current consumption (mA)
Current consumption (mA)
2.8 V
40
Frequency (MHz)
Figure 30. Duty Cycle (LVCMOS)
48
30
Page 16 of 41
Figure 35. RMS Period Jitter (LVCMOS)
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Typical Performance Plots (continued)
2.5 V
2.8 V
3.0 V
2.5 V
3.3 V
47
Phase Jitter (fs RMS)
Current consumption (mA)
2.8 V
46
45
44
43
42
41
10
300
200
100
20
30
40
50
0
60
10
20
30
Frequency (MHz)
60
2.5 V
2.8 V
3.0 V
3.3 V
3.80
3.60
3.40
3.20
3.00
2.80
2.60
-5
-3.75 -2.5 -1.25
0
1.25
2.5
3.75
5
6.25
10
15
20
25
DCTCXO pull (ppm)
2.5 V
2.8 V
30
35
40
45
50
55
60
Frequency (MHz)
Figure 38. DCTCXO frequency pull characteristic
3.0 V
Figure 39. Rise Time (Clipped Sinewave)
3.3 V
2.5 V
2.8 V
3.0 V
3.3 V
50
Current consumption (mA)
45.5
Current consumption (mA)
50
Figure 37. RMS Phase Jitter, VCTCXO (LVCMOS)
Rise Time (ns)
Frequency deviation (ppm)
6.25
5
3.75
2.5
1.25
0
-1.25
-2.5
-3.75
-5
-6.25
-6.25
40
Frequency (MHz)
Figure 36. IDD DCTCXO (LVCMOS)
45.0
44.5
44.0
43.5
49
48
47
46
45
44
43
43.0
10
15
20
25
30
35
40
45
50
55
10
60
15
20
25
Frequency (MHz)
2.5 V
2.8 V
30
35
40
45
50
55
60
Frequency (MHz)
Figure 40. IDD TCXO (Clipped Sinewave)
3.0 V
Figure 41. IDD VCTCXO (Clipped Sinewave)
3.3 V
2.5 V
Current consumption (mA)
500
Phase Jitter (fs RMS)
3.3 V
400
40
400
300
200
100
2.8 V
3.0 V
3.3 V
46.5
46.0
45.5
45.0
44.5
44.0
43.5
43.0
0
10
20
30
40
50
60
Frequency (MHz)
10
15
20
25
30
35
40
45
50
55
60
Frequency (MHz)
Figure 42. RMS Phase Jitter, DCTCXO, TCXO (Clip Sine)
Rev 1.08
3.0 V
500
48
Page 17 of 41
Figure 43. IDD DCTCXO (Clipped Sinewave)
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Typical Performance Plots (continued)
2.8 V
3.0 V
2.5 V
3.3 V
55
400
53
Duty cycle (%)
Phase Jitter (fs RMS)
2.5 V
500
300
200
2.8 V
3.0 V
3.3 V
51
49
47
100
45
0
10
20
30
40
50
60
10
Frequency (MHz)
15
20
25
30
35
40
45
50
55
60
Frequency (MHz)
Figure 44. RMS Phase Jitter, VCTCXO (Clipped Sine)
Figure 45. Duty Cycle (Clipped Sinewave)
Note:
14. Measured 24 hours after start up in a temperature chamber with constant temperature.
15. Plotted with respect to the frequency measurement at the end of the 30th day.
Rev 1.08
Page 18 of 41
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Architecture Overview
Functional Overview
Based on SiTime’s innovative Elite Platform®, the SiT5356
delivers exceptional dynamic performance, i.e. resilience to
environmental stressors such as shock, vibration, and fast
temperature transients. Underpinning the Elite platform are
SiTime’s unique DualMEMS® temperature sensing
architecture and TurboCompensation® technologies.
The SiT5356 is designed for maximum flexibility with an
array of factory programmable options, enabling system
designers to configure this precision device for optimal
performance in a given application.
DualMEMS is a noiseless temperature compensation
scheme. It consists of two MEMS resonators fabricated on
the same die substrate. The TempFlat® MEMS resonator
is designed with a flat frequency characteristic over
temperature whereas the temperature sensing resonator is
by design sensitive to temperature changes. The ratio of
frequencies between these two resonators provides an
accurate reading of the resonator temperature with 20 µK
resolution.
By placing the two MEMS resonators on the same die, this
temperature sensing scheme eliminates any thermal lag
and gradients between resonator and temperature sensor,
thereby overcoming an inherent weakness of legacy quartz
TCXOs.
The DualMEMS temperature sensor drives a state-of-theart CMOS temperature compensation circuit. The
TurboCompensation design, with >100 Hz compensation
bandwidth, achieves a dynamic frequency stability that is
far superior to any quartz TCXO. The digital temperature
compensation enables additional optimization of
frequency stability and frequency slope over temperature
within any chosen temperature range for a given system
design.
The Elite platform also incorporates a high resolution, low
noise frequency synthesizer along with the industry
standard I2C bus. This unique combination enables system
designers to digitally control the output frequency in steps
as low as 5 ppt and over a wide range up to ±3200 ppm.
Frequency Stability
The SiT5356 comes in three factory-trimmed stability
grades that are optimized for different applications. Both
Stratum 3+ and Stratum 3 devices are compliant with
Stratum 3 stability of ±4.6 ppm over 20 years.
Table 14. Stability Grades vs. Ordering Codes
Frequency Slope
(ΔF/ΔT)
Frequency Stability
Over Temperature
Ordering
Code
Stratum 3+
±3.5 ppb/C
±0.1 ppm
Q
Stratum 3
±10 ppb/C
±0.2 ppm
P
±0.25 ppm
N
Grade
◼
Stratum 3+ grade with ΔF/ΔT of ±3.5 ppb/C is
engineered to provide significantly better performance
than legacy quartz TCXOs in time and phase
synchronization applications such as IEEE1588, small
cells, and 5G C-RAN (cloud RAN).
◼
Stratum 3 grade is designed to replace classic
Stratum 3 TCXOs in applications such as SyncE with
better dynamic performance and shorter lead time.
Output Frequency and Format
The SiT5356 can be factory programmed for an output
frequency without sacrificing lead time or incurring an
upfront customization cost typically associated with customfrequency quartz TCXOs.
The device supports both LVCMOS and clipped sinewave
output. Ordering codes for the output format are shown below:
Table 15. Output Formats vs. Ordering Codes
For more information regarding the Elite platform and its
benefits please visit:
◼ SiTime's breakthroughs section
◼ TechPaper: DualMEMS Temperature Sensing Technology
◼ TechPaper: DualMEMS Resonator TDC
Output Format
Ordering Code
LVCMOS
“-“
Clipped Sinewave
“C”
Output Frequency Tuning
In addition to the non-pullable TCXO, the SiT5356 can also
support output frequency tuning through either an analog
control voltage (VCTCXO), or I2C interface (DCTCXO). The
I2C interface enables 16 factory programmed pull-range
options from ±6.25 ppm to ±3200 ppm. The pull range can
also be reprogrammed via I2C to any supported pull-range
value.
Refer to Device Configuration section for details.
Rev 1.08
Page 19 of 41
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Pin 1 Configuration (OE, VC, or NC)
Device Configurations
Pin 1 of the SiT5356 can be factory programmed to support
three modes: Output Enable (OE), Voltage Control (VC), or
No Connect (NC).
The SiT5356 supports 3 device configurations – TCXO,
VCTCXO, and DCTCXO. The TCXO and VCTCXO options
are directly compatible with the quartz TCXO and
VCTCXO.
The
DCTCXO
configuration
provides
performance enhancement by eliminating VCTCXO’s
sensitivity to control voltage noise with an I 2C digital
interface for frequency tuning.
Table 16. Pin Configuration Options
Pin 1 Configuration
Operating Mode
Output
OE
TCXO/DCTCXO
Active or High-Z
NC
TCXO/DCTCXO
Active
VC
VCTCXO
Active
When pin 1 is configured as OE pin, the device output is
guaranteed to operate in one of the following two states:
◼
Clock output with the frequency specified in the part
number when Pin 1 is pulled to logic high
◼
Hi-Z mode with weak pull down when pin 1 is pulled to
logic low.
When pin 1 is configured as NC, the device is guaranteed
to output the frequency specified in the part number at all
times, regardless of the logic level on pin 1.
In the VCTCXO configuration, the user can fine-tune the
output frequency from the nominal frequency specified in
the part number by varying the pin 1 voltage. The
guaranteed allowable variation of the output frequency is
specified as pull range. A VCTCXO part number must
contain a valid pull-range ordering code.
Figure 46. Block Diagram – TCXO
TCXO Configuration
The TCXO generates a fixed frequency output, as shown in
Figure 46. The frequency is specified by the user in the
frequency field of the device ordering code and then factory
programmed. Other factory programmable options include
supply voltage, output types (LVCMOS or clipped
sinewave), and pin 1 functionality (OE or NC).
Refer to the Ordering Information section at the end of the
datasheet for a list of all ordering options.
Rev 1.08
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
VCTCXO Configuration
A VCTCXO, shown in Figure 47, is a frequency control device
whose output frequency is an approximately linear function of
control voltage applied to the voltage control pin. VCTCXOs
have a number of use cases including the VCO portion of a
jitter attenuation/jitter cleaner PLL Loop.
Note that the output frequency of the VCTCXO is
proportional to the analog control voltage applied to
pin 1. Because this control signal is analog and directly
controls the output frequency, care must be taken to
minimize noise on this pin.
The SiT5356 achieves a 10x better pull range linearity of
250
nsec
FM+ (1 MHz)
>0
nsec
FM (400 KHz)
>0
nsec
SM (100 KHz)
>0
nsec
FM+
> 450
nsec
FM (400 KHz)
> 900
nsec
SM (100 KHz)
> 3450
nsec
tHOLD
tVD:AWK
tVD:DAT
Rev 1.08
NA (s-awk + s-data)/(m-awk/s-data)
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Table 24. Pin Selectable I2C Address Control[20]
I2C Device Address Modes
A0
Pin 5
There are two I2C address modes:
I2C Address
0
1100010
1
1101010
Notes:
20. Table 24 is only valid for the DCTCXO device option which supports
I2C control and A0 Device Address Control Pin.
Table 23. Factory Programmed I2C Address Control[19]
I2C Address Ordering Code
Device I2C Address
0
1100000
1
1100001
2
1100010
3
1100011
4
1100100
5
1100101
6
1100110
7
1100111
8
1101000
9
1101001
A
1101010
B
1101011
C
1101100
D
1101101
E
1101110
F
1101111
Notes:
19. Table 23 is only valid for the DCTCXO device option which supports
I2C Control.
Rev 1.08
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Schematic Example
Figure 60. DCTCXO schematic example
Rev 1.08
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Dimensions and Patterns
Package Size – Dimensions (Unit: mm)
Recommended Land Pattern (Unit: mm)
Rev 1.08
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Layout Guidelines
◼
◼
◼
Manufacturing Guidelines
The SiT5356 uses internal regulators to minimize the
impact of power supply noise. For further reduction
of noise, it is essential to use two bypass capacitors
(0.1 μF and 10 μF). Place the 0.1 μF capacitor as
close to the VDD pin as possible, typically within
1 mm to 2 mm. Place the 10 μF capacitor within
2 inches of the device VDD and VSS pins.
It is also recommended to connect all NC pins to the
ground plane and place multiple vias under the GND
pin for maximum heat dissipation.
The SiT5356 Super-TCXOs are precision timing devices.
Proper PCB solder and cleaning processes must be
followed to ensure best performance and long-term
reliability.
◼
No Ultrasonic or Megasonic Cleaning: Do not subject
the SiT5356 to an ultrasonic or megasonic cleaning
environment. Otherwise, permanent damage or long-term
reliability issues to the device may result.
◼
No external cover. Unlike legacy quartz TCXOs, the
SiT5356 is engineered to operate reliably, without
performance degradation in the presence of ambient
disturbers such as airflow and sudden temperature
changes. Therefore, the use of an external cover
typically required by quartz TCXOs is not needed.
◼
Reflow profile: For mounting these devices to the PCB,
IPC/JEDEC J-STD-020 compliant reflow profile must be
used. Device performance is not guaranteed if soldered
manually or with a non-compliant reflow profile.
◼
PCB cleaning: After the surface mount (SMT)/reflow
process, solder flux residues may be present on the PCB
and around the pads of the device. Excess residual solder
flux may lead to problems such as pad corrosion,
elevated leakage currents, increased frequency aging, or
other performance degradation. For optimal device
performance and long-term reliability, thorough cleaning
to remove all the residual flux and drying of the PCB is
required as shortly after the reflow process as possible.
Water soluble flux is recommended. In addition, it is
highly recommended to avoid the use of any “no clean”
flux. However, if the reflow process necessitates the use
of “no clean” flux, then utmost care should be taken to
remove all residual flux between SiTime device and the
PCB. Note that ultrasonic PCB cleaning should not be
used with SiTime oscillators.
◼
For additional manufacturing guidelines and marking/
tape-reel instructions, refer to SiTime Manufacturing
Notes.
For additional layout recommendations, refer to the
Best Design Layout Practices.
Rev 1.08
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Additional Information
Table 25. Additional Information
Document
Description
Download Link
ECCN #: EAR99
Five character designation used on the commerce
Control List (CCL) to identify dual use items for
export control purposes.
—
HTS Classification Code:
8542.39.0000
A Harmonized Tariff Schedule (HTS) code developed
by the World Customs Organization to classify/define
internationally traded goods.
—
Evaluation Boards
SiT6722EB Evaluation Board User Manual
https://www.sitime.com/support/user-guides
Demo Board
SiT6702DB Demo Board User Manual
https://www.sitime.com/support/user-guides
Time Machine II
MEMS oscillator programmer
http://www.sitime.com/support/time-machine-oscillator-programmer
Time Master Web-based
Configurator
Web tool to establish proper programming
https://www.sitime.com/time-master-web-based-configurator
Manufacturing Notes
Tape & Reel dimension, reflow profile and other
manufacturing related info
https://www.sitime.com/support/resource-library/manufacturing-notessitime-products
Qualification Reports
RoHS report, reliability reports, composition reports
http://www.sitime.com/support/quality-and-reliability
Performance Reports
Additional performance data such as phase noise,
current consumption and jitter for selected frequencies
http://www.sitime.com/support/performance-measurement-report
Termination Techniques
Termination design recommendations
http://www.sitime.com/support/application-notes
Layout Techniques
Layout recommendations
http://www.sitime.com/support/application-notes
Rev 1.08
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
Revision History
Table 26. Revision History
Version
Release Date
Change Summary
0.1
0.15
10 May 2016
4 August 2016
0.16
0.2
0.4
12 September 2016
21 September 2016
19 December 2016
0.5
21 July 2017
0.51
20 August 2017
0.52
24 November 2017
First release, advanced information
Replaced QFN package with SOIC-8 package
Added 10 µF bypass cap requirement
Updated test circuits to reflect both new bypass cap requirement and SOIC-8 package
Update Table 1 (Electrical Characteristics)
Updated test circuit diagrams
Revised Table 1 (Electrical Characteristics)
Added DCTCXO mode
Added I2C information
Added I2C
Added 5.0 mm x 3.2 mm package information
Updated Table 1 (Electrical Characteristics)
Changed to preliminary
Updated 5.0 mm x 3.2 mm package dimensions
Updated test circuits
Updated Table 1 (Electrical Characteristics)
Updated part ordering info
Misc. corrections
Updated the Thermal Characteristics table; added more on Manufacturing Guideline section
0.55
5 February 2018
0.60
1.0
1 March 2018
26 June 2018
1.01
1.02
1.03
3 July 2018
4 July 2018
31 July 2018
1.04
1.05
1.06
3 August 2018
15 August 2018
27 November 2018
1.07
10 May 2020
1.08
1 January 2023
Rev 1.08
Added View labels to Package Drawings
Updated the frequency vs. output type changes to 60 MHz
Updated links and notes
Added 105°C support, updated Ordering Information
Updated Electrical Characteristics tables.
Added Performance Plots.
Improved readability; fixed bad hyperlinks.
Updated I2C specifications, Table 3 (Input Characteristics).
Updated Mechanical Shock Resistance, Table 11 (Environmental Compliance).
Added test circuit for clipped sinewave phase noise.
Revised spurious phase noise specification. Updated package outline drawing.
Updated conditions for one day and one year aging specs.
Various formatting updates.
Revised phase noise specifications.
Fixed revision-number typo in footer from 1.3 to 1.5
Formatting updates
Corrected typos in package drawing dimensions
Added nominal value for LVCMOS output impedance
Increased Mechanical Shock Resistance to 30000g
Added “X” order code for 250u Tape and Reel
Improved 24 hour holdover stability specification for 0.2 and 0.25 ppm parts
Improved I2C bus frequency specification
Updated Manufacturing Guidelines to recommend water soluble flux
Corrected typos for write/read I2C polarity
Clarified PCB cleaning instructions
Added link for SiT6702DB
Added ECCN and HTS codes
Reduced initial tolerance for Stratum 3+ grade
Updated typical performance plot for load sensitivity
Formatting updates
Added note for Theta Ja
Changed conditions for 24-hour holdover stability spec
Added Allan deviation spec and updated typical plot
Updated DCTCXO Delay and Settling Time table
Added 5 and 10 year aging specs for Stratum 3+ grade
Added max and min aging specs for 1 and 20 years for Stratum 3+ grade, and changed ambient temperature to 85°C
Slightly reduced minimum pull range specs and updated Tables 17 and 18 for Stratum 3+ grade
Added max and min hysteresis specs for Stratum 3+ grade, clarified conditions with related figure
Clarified 24-hour holdover stability spec condition
Added max and min input voltage to Absolute Maximum Limits table
Updated output impedance typical spec
Updated ΔF/ΔT and F_dynamic min and max specs
Clarified Initial Tolerance specification condition
Relabeled “First Pulse Accuracy” parameter to “Time to Rated Frequency Stability” for clarity
Tightened F_dynamic for Stratum 3+ from -40 to -20°C
Revised Parallel Data Format section description and figures
Updated company disclaimer, links, references and icons
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SiT5356 1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3 Elite Platform Precision Super-TCXO
SiTime Corporation, 5451 Patrick Henry Drive, Santa Clara, CA 95054, USA | Phone: +1-408-328-4400 | Fax: +1-408-328-4439
© SiTime Corporation 2016-2023. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liabi lity for any loss, damage
or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect
or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or
(iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress.
Disclaimer: SiTime makes no warranty of any kind, express or implied, with regard to this material, and specifically disclaims any and all express or implied warranties, either in fact or by
operation of law, statutory or otherwise, including the implied warranties of merchantability and fitness for use or a particular purpose, and any implied warranty arising from course of dealing
or usage of trade, as well as any common-law duties relating to accuracy or lack of negligence, with respect to this material, any SiTime product and any product documentation. This product
is not suitable or intended to be used in a life support application or component, to operate nuclear facilities, in military or aerospace applications, or in other mission critical applications
where human life may be involved or at stake. All sales are made conditioned upon compliance with the critical uses policy set forth below.
CRITICAL USE EXCLUSION POLICY
BUYER AGREES NOT TO USE SITIME'S PRODUCTS FOR ANY APPLICATION OR IN ANY COMPONENTS: USED IN LIFE SUPPORT DEVICES, TO OPERATE NUCLEAR
FACILITIES, FOR MILITARY OR AEROSPACE USE, OR IN OTHER MISSION CRITICAL APPLICATIONS OR COMPONENTS WHERE HUMAN LIFE OR PROP ERTY MAY BE
AT STAKE.
For aerospace and defense applications, SiTime recommends using only Endura™ ruggedized products.
SiTime owns all rights, title and interest to the intellectual property related to SiTime's products, including any software, firmware, copyright, patent, or trademark. The sale of SiTime products does
not convey or imply any license under patent or other rights. SiTime retains the copyright and trademark rights in all documents, catalogs and plans supplied pursuant to or ancillary to the sale
of products or services by SiTime. Unless otherwise agreed to in writing by SiTime, any reproduction, modification, translation, compilation, or representation of this material shall be strictly
prohibited.
Rev 1.08
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