GT24C02A
Advanced
GT24C02A
2-WIRE 2K Bits
Serial EEPROM
Copyright © 2014 Giantec Semiconductor Inc. (Giantec). All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time without
notice. Giantec products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment,
aerospace or military, or other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance
and optimization on the functionality and etc. Giantec assumes no liability arising out of the application or use of any information, products or services described herein. Customers
are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products.
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GT24C02A
Table of Contents
1.
2.
3.
4.
Features ..................................................................................................................................................................................................... 3
General Description............................................................................................................................................................................. 3
Functional Block Diagram ................................................................................................................................................................ 4
Pin Configuration .................................................................................................................................................................................. 5
4.1 8-Pin SOIC, TSSOP, MSOP and PDIP ............................................................................................................................. 5
4.2 8-Lead UDFN and XDFN.................................................................................................................................................. 5
4.3 5-Pin SOT23 ..................................................................................................................................................................... 5
4.4 Pin Definition .................................................................................................................................................................... 5
4.5 Pin Descriptions................................................................................................................................................................ 6
5. Device Operation .................................................................................................................................................................................. 7
5.1 2-WIRE Bus ...................................................................................................................................................................... 7
5.2 The Bus Protocol .............................................................................................................................................................. 7
5.3 Start Condition .................................................................................................................................................................. 7
5.4 Stop Condition .................................................................................................................................................................. 7
5.5 Acknowledge .................................................................................................................................................................... 7
5.6 Reset ................................................................................................................................................................................ 7
5.7 Standby Mode................................................................................................................................................................... 7
5.8 Device Addressing ............................................................................................................................................................ 7
5.9 Write Operation ................................................................................................................................................................ 7
5.10 Read Operation .............................................................................................................................................................. 8
5.11 Diagrams ........................................................................................................................................................................ 9
5.12 Timing Diagrams........................................................................................................................................................... 12
6. Electrical Characteristics .............................................................................................................................................................. 13
6.1 Absolute Maximum Ratings ............................................................................................................................................ 13
6.2 Operating Range ............................................................................................................................................................ 13
6.3 Capacitance.................................................................................................................................................................... 13
6.4 DC Electrical Characteristic ............................................................................................................................................ 14
6.5 AC Electrical Characteristic ............................................................................................................................................ 15
7. Ordering Information ........................................................................................................................................................................ 16
8. Top Markings......................................................................................................................................................................................... 17
8.1 SOIC Package ................................................................................................................................................................ 17
8.2 TSSOP Package ............................................................................................................................................................ 17
8.3 UDFN Package............................................................................................................................................................... 17
8.4 MSOP Package .............................................................................................................................................................. 17
8.5 XDFN Package ............................................................................................................................................................... 18
8.6 PDIP Package ................................................................................................................................................................ 18
8.7 SOT23 Package ............................................................................................................................................................. 18
9. Package Information ......................................................................................................................................................................... 19
9.1 SOIC............................................................................................................................................................................... 19
9.2 TSSOP ........................................................................................................................................................................... 20
9.3 UDFN ............................................................................................................................................................................. 21
9.4 MSOP ............................................................................................................................................................................. 22
9.5 XDFN.............................................................................................................................................................................. 23
9.6 PDIP ............................................................................................................................................................................... 24
9.7 SOT23 .............................................................................................................................. Error! Bookmark not defined.
10. Revision History ................................................................................................................................................................................ 26
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GT24C02A
1. Features
2
–
TM
Two-Wire Serial Interface, I C
Compatible
Page write mode
–
Bi-directional data transfer protocol
Partial page writes allowed
Wide-voltage Operation
Self timed write cycle: 5 ms (max.)
–
Noise immunity on inputs, besides Schmitt trigger
High-reliability
VCC = 1.7V to 5.5V
Speed: 400 KHz (1.7V) and 1 MHz (2.5V~5.5V)
Standby current (max.): 1 A, 1.7V
Read current (max.): 0.5 mA, 5.5V
Write current (max.): 0.5 mA, 5.5V
ESD Protection > 4000V
Hardware Data Protection
Industrial grade
–
Packages: SOIC, TSSOP, UDFN, MSOP, XDFN,
Write Protect Pin
Sequential & Random Read Features
Memory organization: 2Kb (256 x 8)
Page Size: 16 bytes
–
–
Endurance: 1 million cycles
Data retention: 100 years
PDIP and SOT23
Lead-free, RoHS, Halogen free, Green
2. General Description
The GT24C02A is an industrial standard electrically
function via WP pin to cease from overwriting the data
erasable programmable read only memory (EEPROM)
stored inside the memory array.
device that utilizes the industrial standard 2-wire interface
In order to refrain the state machine entering into a wrong
for communications. The GT24C02A contains a memory
state during power-up sequence or a power toggle off-on
array of 2K bits (256x8), which is organized in 16-byte per
condition, a power on reset circuit is embedded. During
page.
power-up, the device does not respond to any instructions
The EEPROM operates in a wide voltage range from 1.7V
until the supply voltage (VCC) has reached an acceptable
to 5.5V, which fits most application. The product provides
stable level above the reset threshold voltage. Once VCC
low-power operations and low standby current. The device
passes the power on reset threshold, the device is reset
is offered in Lead-free, RoHS, halogen free or Green
and enters into the Standby mode. This would also avoid
package. The available package types are 8-pin SOIC,
any inadvertent Write operations during power-up stage.
TSSOP, UDFN, MSOP, XDFN, PDIP and SOT23.
During power-down process, the device will enter into
The GT24C02A is compatible to the standard 2-wire bus
standby mode, once VCC drops below the power on reset
protocol. The simple bus consists of Serial Clock (SCL) and
threshold voltage. In addition, the device will be in standby
Serial Data (SDA) signals. Utilizing such bus protocol, a
mode after receiving the Stop command, provided that no
Master device, such as a microcontroller, can usually
internal write operation is in progress. Nevertheless, it is not
control one or more Slave devices, alike this GT24C02A.
recommended to send a command until the VCC reaches its
The bit stream over the SDA line includes a series of bytes,
operating level.
which identifies a particular Slave device, an instruction, an
address within that Slave device, and a series of data, if
appropriate. The GT24C02A also has a Write Protect
.
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GT24C02A
3. Functional Block Diagram
8
SDA
5
SCL
6
WP
7
X DECODER
VCC
HIGH VOLTAGE
GENERATOR
TIMING &
CONTROL
CONTROL LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
1
A1
2
A2
3
WORD ADDRESS
COUNTER
ACK
Y DECODER
CLOCK
DI
GND 4
nMOS
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EEPROM ARRAY
DATA REGISTER
DO
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GT24C02A
4. Pin Configuration
4.1 8-Pin SOIC, TSSOP, MSOP and PDIP
4.2 8-Lead UDFN and XDFN
Top View
Top View
A0
1
8
VCC
A0
1
8
VCC
A1
2
7
WP
A1
2
7
WP
A2
3
6
SCL
A2
3
6
SCL
GND
4
5
SDA
GND
4
5
SDA
4.3 5-Pin SOT23
Top View
SCL
1
GND
2
SDA
3
5
WP
4
VCC
4.4 Pin Definition
Pin Name
I/O
A0
I
Device Address Input
A1
I
Device Address Input
A2
I
Device Address Input
GND
-
Ground
SDA
I/O
SCL
I
Serial Clock Input
WP
I
Write Protect Input
VCC
-
Power Supply
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Definition
Serial Address and Data input and Data out put
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GT24C02A
4.5 Pin Descriptions
SCL
the inputs are defaulted to zero.
This input clock pin is used to synchronize the data transfer
WP
to and from the device.
WP is the Write Protect pin. While the WP pin is connected
SDA
to the power supply of GT24C02A, the entire array
The SDA is a bi-directional pin used to transfer addresses
becomes Write Protected (i.e. the device becomes Read
and data into and out of the device. The SDA pin is an open
only). When WP is tied to Ground or left floating, the normal
drain output and can be wired with other open drain or open
write operations are allowed.
collector outputs. However, the SDA pin requires a pull-up
VCC
resistor connected to the power supply.
Supply voltage
A0, A1, A2
GND
The A0, A1 and A2 are the device address inputs.
Ground of supply voltage
Typically, the A0, A1, and A2 pins are for hardware
addressing and a total of 8 devices can be connected on a
single bus system. When A0, A1, and A2 are left floating,
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GT24C02A
5. Device Operation
The GT24C02A serial interface supports communications
2
loss), or needs to be terminated mid-stream. The reset is
using industrial standard 2-wire bus protocol, such as I C.
initiated when the Master device creates a Start condition.
5.1 2-WIRE Bus
To do this, it may be necessary for the Master device to
The two-wire bus is defined as Serial Data (SDA), and
monitor the SDA line while cycling the SCL up to nine times.
Serial Clock (SCL). The protocol defines any device that
(For each clock signal transition to High, the Master checks
sends data onto the SDA bus as a transmitter, and the
for a High level on SDA.)
receiving devices as receivers. The bus is controlled by
5.7 Standby Mode
Master device that generates the SCL, controls the bus
While in standby mode, the power consumption is minimal.
access, and generates the Start and Stop conditions. The
The GT24C02A enters into standby mode during one of the
GT24C02A is the Slave device.
following conditions: a) After Power-up, while no Op-code is
5.2 The Bus Protocol
sent; b) After the completion of an operation and followed
Data transfer may be initiated only when the bus is not busy.
by the Stop signal, provided that the previous operation is
During a data transfer, the SDA line must remain stable
not Write related; or c) After the completion of any internal
whenever the SCL line is high. Any changes in the SDA line
write operations.
while the SCL line is high will be interpreted as a Start or
5.8 Device Addressing
Stop condition.
The Master begins a transmission on by sending a Start
The state of the SDA line represents valid data after a Start
condition, then sends the address of the particular Slave
condition. The SDA line must be stable for the duration of
devices to be communicated. The Slave device address is 8
the High period of the clock signal. The data on the SDA line
bits format as shown in Figure. 5-5.
may be changed during the Low period of the clock signal.
The four most significant bits of the Slave address are fixed
There is one clock pulse per bit of data. Each data transfer
(1010) for GT24C02A.
is initiated with a Start condition and terminated by a Stop
The next three bits, A0, A1 and A2, of the Slave address are
condition.
specifically related to EEPROM. Up to eight GT24C02A
5.3 Start Condition
units can be connected to the 2-wire bus.
The Start condition precedes all commands to the device
The last bit of the Slave address specifies whether a Read
and is defined as a High to Low transition of SDA when SCL
or Write operation is to be performed. When this bit is set to
is High. The EEPROM monitors the SDA and SCL lines and
1, Read operation is selected. While it is set to 0, Write
will not respond until the Start condition is met.
operation is selected.
5.4 Stop Condition
After the Master transmits the Start condition and Slave
The Stop condition is defined as a Low to High transition of
address byte appropriately, the associated 2-wire Slave
SDA when SCL is High. All operations must end with a Stop
device, GT24C02A, will respond with ACK on the SDA line.
condition.
Then GT24C02A will pull down the SDA on the ninth clock
5.5 Acknowledge
cycle, signaling that it received the eight bits of data.
After a successful data transfer, each receiving device is
The GT24C02A then prepares for a Read or Write operation
required to generate an ACK. The Acknowledging device
by monitoring the bus.
pulls down the SDA line.
5.9 Write Operation
5.6 Reset
5.9.1 Byte Write
The GT24C02A contains a reset function in case the 2-wire
In the Byte Write mode, the Master device sends the Start
bus transmission on is accidentally interrupted (e.g. a power
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GT24C02A
condition and the Slave address information (with the R/W
completed the Write operation, an ACK will be returned and
set to Zero) to the Slave device. After the Slave generates
the host can then proceed with the next Read or Write
an ACK, the Master sends the byte address that is to be
operation.
written into the address pointer of the GT24C02A. After
5.10 Read Operation
receiving another ACK from the Slave, the Master device
Read operations are initiated in the same manner as Write
transmits the data byte to be written into the address
operations, except that the (R/W) bit of the Slave address is
memory location. The GT24C02A acknowledges once more
set to ―1‖. There are three Read operation options: current
and the Master generates the Stop condition, at which time
address read, random address read and sequential read.
the device begins its internal programming cycle. While this
5.10.1 Current Address Read
internal cycle is in progress, the device will not respond to
any request from the Master device.
The GT24C02A contains an internal address counter which
maintains the address of the last byte
accessed,
5.9.2 Page Write
incremented by one. For example, if the previous operation
The GT24C02A is capable of 16-byte Page-Write operation.
is either a Read or Write operation addressed to the
A Page-Write is initiated in the same manner as a Byte
address location n, the internal address counter would
Write, but instead of terminating the internal Write cycle
increment to address location n+1. When the EEPROM
after the first data word is transferred, the Master device
receives the Slave Addressing Byte with a Read operation
can transmit up to 15 more bytes. After the receipt of each
(R/W bit set to ―1‖), it will respond an ACK and transmit the
data word, the EEPROM responds immediately with an
8-bit data byte stored at address location n+1. The Master
ACK on SDA line, and the four lower order data word
should not acknowledge the transfer but should generate a
address bits are internally incremented by one, while the
Stop condition so the GT24C02A discontinues transmission.
higher order bits of the data word address remain constant.
If 'n' is the last byte of the memory, the data from location '0'
If a byte address is incremented from the last byte of a page,
will be transmitted. (Refer to Figure 5-8. Current Address
it returns to the first byte of that page. If the Master device
Read Diagram.)
should transmit more than 16 bytes prior to issuing the Stop
5.10.2 Random Address Read
condition, the address counter will ―roll over,‖ and the
previously written data will be overwritten. Once all 16 bytes
are received and the Stop condition has been sent by the
Master, the internal programming cycle begins. At this point,
all received data is written to the GT24C02A in a single
Write cycle. All inputs are disabled until completion of the
internal Write cycle.
Selective Read operations allow the Master device to select
at random any memory location for a Read operation. The
Master device first performs a 'dummy' Write operation by
sending the Start condition, Slave address and byte
address of the location it wishes to read. After the
GT24C02A acknowledges the byte address, the Master
device resends the Start condition and the Slave address,
5.9.3 Acknowledge (ACK) Polling
this time with the R/W bit set to one. The EEPROM then
The disabling of the inputs can be used to take advantage
responds with its ACK and sends the data requested. The
of the typical Write cycle time. Once the Stop condition is
Master device does not send an ACK but will generate a
issued to indicate the end of the host's Write operation, the
Stop condition. (Refer to Figure 5-9. Random Address Read
GT24C02A initiates the internal Write cycle. ACK polling
Diagram.)
can be initiated immediately. This involves issuing the Start
5.10.3 Sequential Read
condition followed by the Slave address for a Write
operation. If the EEPROM is still busy with the Write
operation, no ACK will be returned. If the GT24C02A has
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Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
GT24C02A sends the initial byte sequence, the Master
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GT24C02A
device now responds with an ACK indicating it requires
address n+1,n+2 ... etc. The address counter increments by
additional data from the GT24C02A. The EEPROM
one automatically, allowing the entire memory contents to
continues to output data for each ACK received. The Master
be serially read during sequential Read operation. When
device terminates the sequential Read operation by pulling
the memory address boundary of the array is reached, the
SDA High (no ACK) indicating the last data word to be read,
address counter ―rolls over‖ to address 0, and the device
followed by a Stop condition. The data output is sequential,
continues to output data. (Refer to Figure 5-10. Sequential
with the data from address n followed by the data from
Read Diagram).
5.11 Diagrams
Figure 5-1. Typical System Bus Configuration
VCC
SDA
SCL
Master
Transmitter/Receiver
GT24CXX
Figure 5-2. Output Acknowledge
SCL from Master
1
8
9
Data Output from
Transmitter
TAA
Data Output from
Receiver
TDH
ACK
SDA
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STOP
CONDITION
SCL
START
CONDITION
Figure 5-3. Start and Stop Conditions
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GT24C02A
Figure 5-4. Data Validity Protocol
Data Change
SCL
Data Stable
Data Stable
SDA
Figure 5-5. Slave Address
Bit
7
6
5
4
3
2
1
0
1
0
1
0
A2
A1
A0
R/W
Figure 5-6. Byte Write
S
T
A
R
T
Device
Address
SDA
Bus
Activity
W
R
I
T
E
Byte Address
A
C
K
M
S
B
S
T
O
P
Data
A
C
K
A
C
K
L
S
B
R/W
Figure 5-7. Page Write
S
T
A
R
T
W
R
I
T
E Byte Address(n)
A
A
C
C
K
K
Device
Address
SDA
Bus
Activity
M
S
B
Data(n+1)
A
C
K
Data(n+15)
A
C
K
A
C
K
L
S
B
R/W
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Data(n)
S
T
O
P
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GT24C02A
Figure 5-8. Current Address Read
S
T
A
R
T
R
E
A
D
Device
Address
S
T
O
P
Data
A
C
K
SDA
Bus
Activity
M
S
B
L
S
B
N
O
A
C
K
R/W
Figure 5-9. Random Address Read
S
T
A
R
T
Device
Address
SDA
Bus
Activity
W
R
I
T
E
Byte
Address(n)
A
C
K
M
S
B
S
T
A
R
T
Device
Address
A
C
K
R
E
A
D
S
T
O
P
Data n
A
C
K
N
O
L
S
B
R/W
A
C
K
DUMMY WRITE
Figure 5-10. Sequential Read
Device
Address
SDA
Bus
Activity
R
E
A
D
Data Byte n
A
C
K
Data Byte n+1
A
C
K
S
T
O
Data Byte n+x P
Data Byte n+2
A
C
K
A
C
K
N
O
R/W
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A
C
K
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GT24C02A
5.12 Timing Diagrams
Figure 5-11. Bus Timing
TR
TF
THIGH
TLOW
TSU:STO
SCL
TSU:STA
THD:STA
TSU:DAT
THD:DAT
TBUF
SDAIN
TAA
TDH
SDAOUT
TSU:WP THD:WP
WP
Figure 5-12. Write Cycle Timing
SCL
SDA
ACK
Word n
TWR
STOP
Condition
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START
Condition
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GT24C02A
6. Electrical Characteristics
6.1 Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
VS
Supply Voltage
-0.5 to + 6.5
V
VP
Voltage on Any Pin
-0.5 to + 6.5
V
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
IOUT
Output Current
5
mA
Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
6.2 Operating Range
Range
Ambient Temperature (TA)
VCC
Industrial
–40°C to +85°C
1.7V to 5.5V
Note: Giantec offers Industrial grade for Commercial applications (0C to +70C).
6.3 Capacitance
Symbol
Parameter[1,2]
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
pF
CI/O
Input / Output Capacitance
VI/O = 0V
8
pF
Notes:
[1]
Tested initially and after any design or process changes that may affect these parameters and not 100% tested.
Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V
[2]
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GT24C02A
6.4 DC Electrical Characteristic
Industrial: TA = –40°C to +85°C, VCC = 1.7V ~ 5.5V
Symbol
Parameter
[1]
VCC
Test Conditions
Min.
Max.
Unit
1.7
5.5
V
VCC
Supply Voltage
VIH
Input High Voltage
0.7*VCC
VCC+1
V
VIL
Input Low Voltage
-1
0.3* VCC
V
ILI
Input Leakage Current
5V
—
2
μA
ILO
Output Leakage Current
5V
—
2
μA
VIN = VCC max
VOL1
Output Low Voltage
1.7V
IOL = 0.15 mA
—
0.2
V
VOL2
Output Low Voltage
2.5V
IOL = 2.1 mA
—
0.4
V
ISB1
Standby Current
1.7V
VIN = VCC or GND
0.2
1
μA
ISB2
Standby Current
2.5V
VIN = VCC or GND
0.3
1
μA
ISB3
Standby Current
5.5V
VIN = VCC or GND
0.5
1
μA
1.7V
Read at 400 KHz
—
0.15
mA
2.5V
Read at 1 MHz
—
0.2
mA
5.5V
Read at 1 MHz
—
0.5
mA
1.7V
Write at 400 KHz
—
0.3
mA
2.5V
Write at 1 MHz
—
0.4
mA
5.5V
Write at 1 MHz
—
0.5
mA
ICC1
ICC2
Read Current
Write Current
Note: The parameters are characterized but not 100% tested.
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GT24C02A
6.5 AC Electrical Characteristic
Industrial: TA = –40°C to +85°C, Supply voltage = 1.7V to 5.5V
Symbol
Parameter
[1] [2]
1.7VVCC
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