TDC-GP30YD 1K

Datasheet DS000391 TDC-GP30 System-Integrated Solution for Ultrasonic Flow Meters (Volume 1: General Data and Frontend Description) v5-00 • 2020-Mai-05 This product, formerly soled by ams AG, and before that by acam-messelectronics GmbH, is now owned and sold by ScioSence B.V.. This commercial transfer does not affect the technical specification or quality oft he product. UFC TDC-GP30 Copyrights & Disclaimer Copyright ScioSense B.V., High Tech Campus 10, 5656 AE Eindhoven, The Netherlands. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ScioSense B.V. are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ScioSense B.V. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ScioSense B.V. reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ScioSense B.V. for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by ScioSense B.V. for each application. This product is provided by ScioSense B.V. “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ScioSense B.V. shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ScioSense B.V. rendering of technical or other services. RoHS Compliant & ScioSense Green Statement RoHS Compliant: The term RoHS compliant means that ScioSense B.V. products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ScioSense Green (RoHS compliant and no Sb/Br): ScioSense Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ScioSense B.V. knowledge and belief as of the date that it is provided. ScioSense B.V. bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ScioSense B.V. has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ScioSense B.V. and ScioSense B.V. suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release Support / Contact For direct sales, distributor and sales representative contacts, visit the ScioSense web site at: www.sciosense.com For technical support you can contact the ScioSense support team: customersupport@sciosense.com or by phone +49-7244-74190. Ultrasonic Flow Converter Vol. 1 TDC-GP30 Notational Conventions Throughout the GP30 documentation, the following stile formats are used to support efficient reading and understanding of the documents: ▪ Hexadecimal numbers are denoted by a leading 0x, e.g. 0xAF = 175 as decimal number. Decimal numbers are given as usual. ▪ Binary numbers are denoted by a leading 0b, e.g. 0b1101 = 13. The length of a binary number can be given in bit (b) or Byte (B), and the four bytes of a 32b word are denoted B0, B1, B2 and B3 where B0 is the lowest and B3 the highest byte. ▪ Abbreviations and expressions which have a special or uncommon meaning within the context of GP30 application are listed and shortly explained in the list of abbreviations, see following page. They are written in plain text. Whenever the meaning of an abbreviation or expression is unclear, please refer to the glossary at the end of this document. ▪ Variable names for hard coded registers and flags are in bold. Meaning and location of these variables is explained in the datasheet (see registers CR, SRR and SHR). ▪ Variable names which represent memory or code addresses are in bold italics. Many of these addresses have a fixed value inside the ROM code, others may be freely defined by software. Their meaning is explained in the firmware and ROM code description, and their physical addresses can be found in the header files. These variable names are defined by the header files and thus known to the assembler as soon as the header files are included in the assembler source code. Note that different variable names may have the same address, especially temporary variables. ▪ 1 Physical variables are in italics (real times, lengths, flows or temperatures). Ultrasonic Flow Converter Vol. 1 TDC-GP30 Abbrevations AM CD CPU CR CRC DIFTOF, DIFTOF_ALL DR FEP FDB FHL FW FWC FWD FWD-RAM GPIO Hit HSO INIT IO I2C LSO MRG NVRAM, NVM PI PP PWR R RAA RAM RI ROM ROM code SHR SPI SRAM SRR SUMTOF Task TDC TOF, TOF_ALL TS TM UART USM V ref X,Y,Z ZCD Amplitude measurement Configuration Data Central Processing Unit Configuration Register Cyclic Redundancy Check Difference of up and down ->TOF Debug Register Frontend Processing Frontend data buffer First hit level (physical value V FHL ) Firmware, software stored on the chip Firmware Code Firmware Data Firmware Data memory General purpose input/output Stands for a detected wave period High speed oscillator Initialization process of ->CPU or -> FEP Input/output Inter-Integrated Circuit bus Low speed oscillator Measurement Rate Generator Programmable Non-Volatile Memory Pulse interface Post Processing Pulse width ratio RAM address pointer of the CPU, can also stand for the addressed register Random Access Area Random Access Memory Remote Interface Read Only Memory Hard coded routines in ROM System Handling Register Serial Peripheral Interface Static RAM Status & Result Register Sum of up and down TOF Process, job Time-to-digital-converter Time of Flight Task Sequencer Temperature measurement Universal Asynchronous Receiver & Transmitter Ultrasonic measurement Reference voltage Internal registers of the CPU Zero cross detection, physical level V ZCD For details see the glossary in section 9. 2 www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 Vol. 1 Content 1 2 3 4 5 6 7 8 Overview .............................................................................................................................. 1-3 1.1 Key Features ................................................................................................................. 1-3 1.2 Block diagram ............................................................................................................... 1-4 1.3 Ordering Numbers ......................................................................................................... 1-4 Characteristics & Specifications ............................................................................................ 2-1 2.1 Electrical Characteristics ............................................................................................... 2-1 2.2 Timings ......................................................................................................................... 2-5 2.3 Pin Description .............................................................................................................. 2-9 2.4 Package Drawings ...................................................................................................... 2-11 Flow and Temperature Measurement .................................................................................. 3-13 3.1 Measuring principle ..................................................................................................... 3-13 3.2 Ultrasonic Measurement .............................................................................................. 3-17 3.3 Temperature Measurement .......................................................................................... 3-21 3.4 Chip level calibrations ................................................................................................. 3-26 Special Service Functions ..................................................................................................... 4-1 4.1 Watchdog ...................................................................................................................... 4-1 4.2 Time Stamp (RTC) ........................................................................................................ 4-1 4.3 Backup .......................................................................................................................... 4-1 4.4 Clock Management ........................................................................................................ 4-1 4.5 Power Supply ................................................................................................................ 4-4 4.6 Voltage Measurement.................................................................................................... 4-6 Remote Port Interfaces ......................................................................................................... 5-1 5.1 SPI Interface ................................................................................................................. 5-1 5.2 UART Interface ............................................................................................................. 5-1 5.3 Remote Communication (Opcodes) ............................................................................... 5-3 5.4 Opcodes ....................................................................................................................... 5-3 General Purpose IO Unit ....................................................................................................... 6-1 6.1 Pulse Interface .............................................................................................................. 6-2 6.2 EEPROM Interface ........................................................................................................ 6-5 Memory Organization & CPU ................................................................................................. 7-1 7.1 Program Area ................................................................................................................ 7-3 7.2 Random Access Area (RAA) .......................................................................................... 7-4 7.3 Configuration Registers ............................................................................................... 7-10 7.4 System Handling Register ........................................................................................... 7-21 7.5 Status Registers .......................................................................................................... 7-28 Applications .......................................................................................................................... 8-1 8.1 GP30-DEMO Board ....................................................................................................... 8-1 8.2 GP30 Typical Configuration ........................................................................................... 8-2 TDC-GP30_DS000391_5-00 www.sciosense.com 1-1 Ultrasonic Flow Converter Vol. 1 TDC-GP30 9 Glossary ............................................................................................................................... 9-1 10 Miscellaneous ..................................................................................................................... 10-1 10.1 Bug Report .................................................................................................................. 10-1 10.2 Last Changes from 0.4 to current version 5 .................................................................. 10-1 1-2 www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 Vol. 1 1 Overview TDC-GP30 is the next generation in acam’s development for ultrasonic flow converters. The objectives of the TDC-GP30 development are as follows: ▪ Easy-to-adapt two-chip solution for ultrasonic heat and water meters (GP30 + simple µP) ▪ Single-chip solution for many industrial applications or pure flow meter parts ▪ All flow and temperature calculations are done by GP30 ▪ External µP needed only for interfaces (e.g. LCD, wireless, etc.) and other general-purpose tasks ▪ Integrated standard pulse interface enables one-to-one replacement of mechanical meters by GP30 based single-chip heat and water meters – customer µP and software remains unchanged. All in all, the TDC-GP30 is the next step in ultrasonic flow metering. It drastically simplifies the design of ultrasonic heat and water meters and is the necessary step for compact energy -saving ultrasonic water meters. The ultra-low-current capabilities allow the use of standard 2/3 AA or AA lithium thionyl chloride batteries at 6-8 Hz measuring frequency even in the water meter version. The TDC-GP30 is a system-on-chip approach that allows you to perform all measurement tasks in one IC. 1.1 Key Features ▪ High performance + ultra-low power 32-Bit CPU with ▪ 128 * 32 bit NVRAM (non-volatile RAM) for user firmware parameter & data ▪ 4k * 8 bit NVRAM (non-volatile RAM) for user firmware program code ▪ 4k * 8 bit ROM for system task code and special flow library code ▪ Capability of MID-compliant flow & temperature calculation, GP30-supported ▪ Flexible interfaces, SPI, UART, pulse (flow only) ▪ Advanced high-precision analog part ▪ Transducers can be connected directly to GP30, no external components required ▪ Amplitude measurements of receiving signal for secure bubble, aging and empty spool piece detection ▪ Up to 31 multi-hits for flow measurement yield the highest accuracy ▪ High update rates with very low power consumption of for example 6 µA at 8 Hz, including flow and temperature calculations, measure rate adopted to the flow ▪ Very low space and component requirements TDC-GP30_DS000391_5-00 www.sciosense.com 1-3 Ultrasonic Flow Converter Vol. 1 TDC-GP30 1.2 Block diagram Figure 1-1: Block diagram Vcc: 2.5...3.6 V 4/8 MHz 32.768 kHz quartz ceramic 10u 100u 10R A) Supervisor Clock Management Voltage Regulator Measure Rate Generator & Task Sequencer Ultrasonic Frontend PT1000 PT1000 680n Temperature Frontend 1k Remote Interface RAM & Register Time-to-Digital-Converter (TDC) Transducer 1...4 MHz D) User Interfaces Voltage Measurement System Tasks & Flow Library User-FW Program & ACAM-FW Program ROM (4k * 8) NVRAM (4k * 8) User-FW Data NVRAM (128*32) CPU 32 Bit SPI / UART SPI / UART Pulse Interface Pulse DIR EEPROM Interface SCL SDA General Purpo se IO Unit GPIOs 100n C0G B) Frontend C) Post processing Main functional blocks of TDC-GP30: A) Supervisor: Timing and voltage control B) Frontend: TOF and sensor temperature measurements C) Post processing: CPU operations, including initialization and firmware operations D) User interfaces: Chip communication over SPI or UART, Pulse interface and GPIOs 1.3 Ordering Numbers Part Number Firmware Material ID Packing Qty. T&R TDC-GP30YA 1K no 502030011 1000 TDC-GP30YA 3K no 502030004 3000 TDC-GP30YA-F01 1K yes, F01 502030013 1000 TDC-GP30YA-F01 3K yes, F01 502030007 3000 TDC-GP30YD 1K no 502030010 1000 TDC-GP30YD 3K no 502030003 3000 TDC-GP30YD-F01 1K yes, F01 502030012 1000 TDC-GP30YD-F01 3K yes, F01 502030005 3000 This product is RoHS-compliant and does not contain any Pb. 1-4 www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 Vol. 1 2 Characteristics & Specifications 2.1 Electrical Characteristics Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Electrical Characteristics” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2-1 Absolute maximum ratings Symbol Parameter Min Max Units VCC Supply voltage VCC vs. GND -0.3 4.0 V All other pins -0.3 VCC + 0.6 V Tamb Ambient temperature -40 +125 °C Tstrg Storage temperature -55 +150 °C Tbody Body temperature JEDEC J-STD-020 260 °C ESD ESD rating (HBM), each pin ±2 kV Table 2-2 Recommended operating conditions Symbol Parameter Conditions Min. Typ. Max. Unit VCC Supply voltage main supply voltage 2.5 3.0 3.6 V VDD18 Core supply Internally derived from VCC and regulated 1.65 1.80 1.92 V fLSO Low speed oscillator (LSO) frequency fHSO High-speed oscillator (HSO) frequency 32.768 kHz For Standard transducers, max. 2 MHz, 3.6 4 4.4 MHz For 4 MHz transducers, not in combination with UART 7.2 8 8.8 MHz Other frequencies in the range from 2 MHz to 8 MHz may be possible with limitations fSPI SPI Interface Clock Frequency fTOF TOF measurement frequency tcycle Measurement cycle time TDC-GP30_DS000391_5-00 SPI communication 𝑓𝑇𝑂𝐹 = 1 (𝑇𝑂𝐹_𝑅𝐴𝑇𝐸 ∗ 𝑡𝑐𝑦𝑐𝑙𝑒 ) LSB = 976.5625 µs www.sciosense.com 0.004 1…8 10 MHz 80 Hz 4000 ms 2-1 Ultrasonic Flow Converter Vol. 1 TDC-GP30 Table 2-3 DC Characteristics (VCC = 3.0 V, Tj = -40 to +85 °C) Symbol Parameter IStandby Supply current only 32 kHz, Standby mode Conditions Min. Typ. Max. Unit only 32 kHz oscillator running @ 25 °C, VCC = 3.6 V = 3.0 V 3.6 2.2 µA µA VCC = 3.6 V = 3.0 V off 80 65 Pulse 10: Low Speed Clock 11: Ultrasonic Fire Burst BIT2 b00 1:0 GP0_DIR: Direction of General Purpose Port 0 00: Output 01: Input Pull Up 10: Input Pull Down 11: Input High Z BIT2 b01 7.3.4 CR_UART (UART Interface) Bit 31:16 7-12 Vol. 1 0x0C3 Description UART_CRC_POLY: CRC Polynom Register CR_UART[Bit 16] has to be set 1, mandatory Format Reset UINT [15:0] h1021 15 UART_CRC_ORDER 0: UART CRC in unreversed order 1: UART CRC in reversed order BIT b0 14 UART_CRC_INIT_VAL 0: UART CRC Initial Value = 0x0000 1: UART CRC Initial Value = 0x1111 BIT b1 13 UART_CRC_MODE, if operating in flow meter mode 0: UART CRC with default settings 1: UART CRC with configured settings For initial communication or operating in time conversion mode UART_CRC_MODE in SHR_RC has to be used. BIT b1 12 UART_WUP_EN 0: Wake Up Command disabled 1: Wake Up Command enabled BIT b0 www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 Bit Vol. 1 Format Reset UART_HBR: UART High Baud Rate If any High Baud Mode enabled: 00: 19200 Baud 01: 38400 Baud 10: 57600 Baud 11: 115200 Baud BIT2 b01 9 UART_HB_MODE: UART High Baud Mode 0: High Baud Rate only controlled by remote controller 1: High Baud Rate enabled for UART Data Message BIT b1 8 UART_IRQ_CLR_MODE: UART Interrupt Clear Mode 0: UART Remote Interrupt has to be cleared by remote controller 1: UART Remote Interrupt automatically cleared by GP30 BIT b0 11:10 Description 7:4 UART_DATA_MSG_ADR Start of address block of automatic data message (upper four bit of actual start address) UINT [3:0] 0 3:0 UART_DATA_MSG_LEN 0: Automatic Data Message disabled 1-15: Length of automatic data message UINT [3:0] 0 Format Reset 7.3.5 CR_IEH (Interrupt & Errorhandling) 0x0C4 Bit Description 31 CPU_BLD_CS: Checksum Execution after bootloader 0: Checksum execution after bootloader disabled 1: Checksum execution after bootloader enabled BIT b0 CPU_GPT: General Purpose Timer, triggers General Purpose Handling for CPU via Task Sequencer 000: 1h 001: 2h 010: 4h 011: 6h 100: 8h 101: 12h 110: 24h 111: 48h BIT 0 27 Has to be set 0 BIT b0 26 CPU_REQ_EN_GPH: CPU Request Enable, General Purpose Handling triggered by General Purpose Timer 0: disabled 1: enabled BIT2 b00 25 not used BIT b0 24 CPU_REQ_EN_PP: CPU Request Enable, Post Processing If enabled, PP_EN in CR_MRG_TS has also be set. BIT b0 23 IRQ_EN_ERR_FLAG: Interrupt Request Enable, Error Flag BIT b1 22 IRQ_EN_DBG_STEP_FNS: Interrupt Request Enable, Debug Step Finished BIT b1 21 IRQ_EN_FW: Interrupt Request Enable, Firmware BIT b1 30:28 TDC-GP30_DS000391_5-00 www.sciosense.com 7-13 Ultrasonic Flow Converter Bit Description 20 TDC-GP30 Format Reset IRQ_EN_FW_S: Interrupt Request Enable , Firmware, synchronized with task sequencer BIT b1 19 IRQ_EN_CHKSUM_FNS: Interrupt Request Enable, Checksum generation finished BIT b1 18 IRQ_EN_BLD_FNS: Interrupt Request Enable, Bootload finished BIT b1 17 IRQ_EN_TRANS_FNS: Interrupt Request Enable, FW Transaction finished BIT b1 16 IRQ_EN_TSQ_FNS: Interrupt Request Enable, Task Sequencer finished BIT b1 15 EF_EN_CS_FWA_ERR: Error Flag Enable, FWA Checksum Error BIT b0 14 EF_EN_CS_FWU_ERR: Error Flag Enable, FWU Checksum Error BIT b0 13 EF_EN_CS_FWD2_ERR: Error Flag Enable, FWD2 Checksum Error BIT b0 12 EF_EN_CS_FWD1_ERR: Error Flag Enable, FWD1 Checksum Error BIT b0 11 Not used 10 EF_EN_E2P_ACK_ERR: Error Flag Enable, EEPROM Acknowledge Error BIT b0 9 EF_EN_TSQ_TMO: Error Flag Enable, Task Sequencer Timeout BIT b0 8 EF_EN_TM_SQC_TMO: Error Flag Enable, Temperature Sequence Timeout BIT b0 7 EF_EN_USM_SQC_TMO: Error Flag Enable, Ultrasonic Sequence Timeout BIT b0 6 EF_EN_LBD_ERR: Error Flag Enable, Low Battery Detect Error BIT b0 5 EF_EN_ZCC_ERR: Error Flag Enable, Zero Cross Calibration Error BIT b0 4 EF_EN_TM_SC: Error Flag Enable, Temperature Measurement Short Circuit BIT b0 3 EF_EN_TM_OC: Error Flag Enable, Temperature Measurement Open Circuit BIT b0 2 EF_EN_AM_TMO: Error Flag Enable, Amplitude Measurement Timeout BIT b0 1 EF_EN_TOF_TMO: Error Flag Enable, TOF Timeout BIT b0 0 EF_EN_TDC_TMO: Error Flag Enable, TDC Timeout BIT b0 7.3.6 CR_CPM (Clock- & Power-Management) Bit 31:24 Description 0x0C5 Format Reset Not used 23 BF_SEL: Base Frequency Select 0: 50 Hz T(BF_SEL) = 20 ms 1: 60 Hz T(BF_SEL) = 16.66 ms BIT b0 22 TSV_UPD_MODE: Time stamp update mode 0: Timestamp updated by TSV_UPD in SHR_EXC 1: Timestamp automatically update with every second BIT b0 UINT [5:0] 0 21:16 7-14 Vol. 1 LBD_TH: Low battery detection threshold, can be used for VCC measurement 1 LSB: 25 mV LBD_TH = 0: 2.13 V LBD_TH = 63: 3.70 V www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 Bit Vol. 1 Format Reset VM_RATE: VCC Voltage measurement rate 000: VCC Voltage measurement disabled 001: VCC Voltage measurement every measure cycle trigger 010: VCC Voltage measurement every 2. sequence cycle trigger 011: VCC Voltage measurement every 5. sequence cycle trigger 100: VCC Voltage measurement every 10. sequence cycle trigger 101: VCC Voltage measurement every 20. sequence cycle trigger 110: VCC Voltage measurement every 50. sequence cycle trigger 111: VCC Voltage measurement every 100. sequence cycle trigger BIT3 b000 GPH_MODE: General Purpose Handling Mode 0: General Purpose Handling invoked without High Speed Clock 1: General Purpose Handling invoked with High Speed Clock BIT b0 HSC_RATE: High-Speed Clock Calibration Rate 000: Clock Calibration disabled 001: Clock Calibration every measure cycle trigger 010: Clock Calibration every 2. measurement cycle trigger 011: Clock Calibration every 5. measurement cycle trigger 100: Clock Calibration every 10. measurement cycle trigger 101: Clock Calibration every 20. measurement cycle trigger 110: Clock Calibration every 50. measurement cycle trigger 111: Clock Calibration every 100. measurement cycle trigger BIT3 b000 HS_CLK_SEL: High-Speed Clock Select, if operating in flow meter mode 0: if 4 MHz clock source is used 1: if 8 MHz clock source is used For initial communication or operating in time conversion mode HS_CLK_SEL in SHR_RC has to be used. BIT b1 7:5 HBR_TO: High-Speed Clock Timeout if High Baud rate enabled 000: 10 ms 001: 20 ms 010: 30 ms 011: 40 ms 100: 60 ms 101: 80 ms 110: 100 ms 111: 120 ms BIT3 b001 4:2 HS_CLK_ST: High-Speed Clock Settling Time 000: On Request, Settling Time 74 µs 001: On Request, Settling Time 104 µs 010: On Request, Settling Time 135 µs 011: On Request, Settling Time 196 µs 100: On Request, Settling Time 257 µs 101: On Request, Settling Time 379 µs 110: On Request, Settling Time 502 µs 111: On Request, Settling Time ~5000 µs BIT3 b110 1:0 Has to be set 00 BIT2 b00 15:13 12 11:9 8 7.3.7 Description CR_MRG_TS (Measure Rate Generator & Task Sequencer) Bit 31:24 Description 0x0C6 Format Not used TDC-GP30_DS000391_5-00 www.sciosense.com 7-15 Reset Ultrasonic Flow Converter Bit Description 23 TDC-GP30 Format Reset TS_START_MODE: Task Sequencing Start Mode 0: Task Sequencing first starts when remote interface isn’t busy 1: Task Sequencing starts independent of remote busy state BIT b0 22:20 TS_CST: Checksum Timer 000: Checksum timer disabled 001: 1h 010: 2h 011: 6h 100: 24h 101: 48h 110: 96h 111: 168h This function is not executed when TOF_RATE = 1 and TM_RATE = 1 is set at the same time. BIT3 b000 19:17 Has to be set 000 BIT3 0 16 BG_PLS_MODE: Bandgap pulse mode 0: Bandgap in self-pulsed mode 1: Bandgap synchronized pulsed by Task sequencer BIT b1 15 PP_MODE: Post processing mode (only if post processing is enabled) 0: Post processing requested with every task sequencer trigger 1: Post processing only requested if a measurement task is requested BIT b0 14 PP_EN: Post processing enable, used by CPU, if operating in flow meter mode 0: Post processing disabled 1: Post processing enabled If enabled, CPU_REQ_EN_PP in CR_IEH has also be set. BIT b0 13 TS_RESTART_EN: Task Sequencer Restart Enable 0: No automatic restart of task sequencer if not in IDLE 1: Task Sequencer automatically restarts with next measure cycle trigger if not in IDLE BIT b1 UINT [12:0] 0 Format Reset 12:0 7.3.8 MR_CT: Measure rate cycle time 0: Measure rate generator disabled 1 – 8191: Cycle time = MR_CT * 976.5625 µs = MR_CT * 1 ms (LP_MODE = 1), (LP_MODE = 0) CR_TM (Temperature Measurement) Bit 31:24 7-16 Vol. 1 Description 0x0C7 Not used 23 TM_FAKE_NO: Number of Fake measurements 0: 2 fake measurements 1: 8 fake measurements BIT b0 22 TM_DCH_SEL: TM Discharge Select 0: 512 µs 1: 1024 µs BIT b0 www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 Bit Vol. 1 Format Reset 21:20 TM_LD_DLY: Temperature Measurement Load Delay 00: Recommended, no delay needed 01: 10: 11: BIT2 b00 19:18 TM_PORT_ORDER: TM Measurement Port Order 00: Measurement always in default port order 01: Measurement always in reversed order 10: 1. measurement: default order / 2. measurement: reversed order 11: 1. measurement: reversed order / 2. measurement: default order BIT2 b00 17 TM_PORT_MODE: Port Mode 0: Inactive ports pulled to GND while measurement 1: Inactive ports set to HighZ while measurement (only for extern measurement) BIT b0 16 TM_PORT_NO: Number of Ports 0: 1 ports, 1 external sensor 1: 2 ports, 2 external sensors (only for extern 2-wire measurement) BIT b0 15 TM_WIRE_MODE: Temperature Measurement Wire Mode 0: 2 Wire 1: 4 Wire (only for extern measurement) BIT b0 TM_MODE: Temperature Measurement Mode 00: Extern 01: Intern 1x: Toggling between Extern/Intern BIT2 b00 BIT3 b000 UINT [9:0] 0 Format Reset 14:13 12:10 Description TM_PAUSE: Pause time between 2 temperature measurements 000: no pause, only one measurement performed * 001: not allowed 010: Pause time = 0.25 * T(BF_SEL) ms 011: Pause time = 0.5 * T(BF_SEL) ms 100: Pause time = 1.0 * T(BF_SEL) ms 101: Pause time = 1.5 * T(BF_SEL) ms 110: Pause time = 2.0 * T(BF_SEL) ms 111: Pause time = 2.5 * T(BF_SEL) ms * In case no pause is selected it is recommended to disable the error flags EF_EN_TM_SQC_TMO 9:0 7.3.9 TM_RATE: Temperature Measurement Rate 0: Temperature Measurement disabled 1-1023: Rate of Temperature Measurement related to sequencer cycle trigger CR_USM_PRC (Ultrasonic Measurement Processing) Bit 31:18 Description 0x0C8 Not used TDC-GP30_DS000391_5-00 www.sciosense.com 7-17 Ultrasonic Flow Converter Bit Vol. 1 TDC-GP30 Format Reset 17:16 USM_TO: Timeout 00: 128 µs 01: 256 µs 10: 1024 µs 11: 4096 µs BIT2 b00 15:8 USM_NOISE_MASK_WIN: Defines the window as long any signal (e.g. noise) is masked on receive path. Starting time refers to rising edge of 1st fire pulse. End time defines switching point between firing and receiving state of transducer interface. Offset: -0.4 µs 1 LSB: 1 µs UINT [7:0] 0 7:6 Has to be set 00 BIT2 b00 5:4 USM_DIR_MODE: Ultrasonic Measurement Direction Mode 00: Always starting firing via Fire Buffer Up 01: Always starting firing via Fire Buffer Down 1x: Toggling direction with every ultrasonic measurement BIT2 b00 BIT3 b000 3 2:0 Description Not used USM_PAUSE: Pause time between 2 ultrasonic measurements 000: no pause, only 1 measurement performed * 001: not allowed 010: Pause time = 0.25 * T(BF_SEL) ms 011: Pause time = 0.5 * T(BF_SEL) ms 100: Pause time = 1.0 * T(BF_SEL) ms 101: Pause time = 1.5 * T(BF_SEL) ms 110: Pause time = 2.0 * T(BF_SEL) ms 111: Pause time = 2.5 * T(BF_SEL) ms * In case no pause is selected it is recommended to disable the error flags EF_EN_USM_SQC_TMO 7.3.10 CR_USM_FRC (Ultrasonic Measurement Fire & Receive Control) Bit 31:27 26 25:21 20 7-18 Description 0x0C9 Format Reset TI_GM_MODE: Gas Meter Mode 0: Gas Meter Mode disabled 1: Gas Meter Mode enabled BIT b1 TI_PATH_EN: Transducer Interface Path Enable, if Gas Meter Mode is enabled [4]: Enable analog switches in both US buffer [3]: Enable precharge transistors in both US buffer [2]: Enable pulldown transistors in both US buffer [1]: Enable receive path transistors as defined in TI_PATH_SEL [0]: Enable fire buffer as defined in TI_PATH_SEL BIT5 b0000 0 TI_ERA_EN: External receive amplifier 0: External receive amplifier disabled 1: External receive amplifier enabled BIT b0 Not used www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 Bit Vol. 1 Format Reset 19:18 TI_PATH_SEL: Transducer interface path select 00: No fire buffer & no receive path selected 01: Fire buffer 1 (350Ω) & receive path 1 selected 10: Fire buffer 2 (550Ω) & receive path 2 selected 11: Both Fire Buffers (214Ω) & both Receive Paths selected BIT2 b00 17:15 ZCC_RATE: Zero Cross Calibration Rate 000: Zero cross calibration via task sequencer disabled 001: Zero cross calibration every measure cycle trigger 010: Zero cross calibration every 2. measurement cycle trigger 011: Zero cross calibration every 5. measurement cycle trigger 100: Zero cross calibration every 10. measurement cycle trigger 101: Zero cross calibration every 20. measurement cycle trigger 110: Zero cross calibration every 50. measurement cycle trigger 111: Zero cross calibration every 100. measurement cycle trigger BIT3 b000 ZCD_FHL_POL: First Hit Level polarity 0: Positive, first hit level above zero cross level 1: Negative, first hit level below zero cross level BIT 0 14 Description 13:7 FPG_FP_NO: Number of fire pulses UINT [6:0] 0 6:0 FPG_CLK_DIV: Fire pulse generator clock divider (1 .. 127) Frequency = High Speed Clock divided by (FPG_CLK_DIV + 1) 0: divided by 2 1: divided by 2 2: divided by 3 …. 127: divided by 128 BIT7 0 Format Reset 7.3.11 CR_USM_TOF (Ultrasonic Measurement Time of Flight) Bit Description 0x0CA 31:16 Not used 15:14 TOF_EDGE_MODE: Time of Flight, Edge Mode 00: Time measurement on positive edge of TOF Hit 01: Time measurement on negative edge of TOF Hit 10: Edge for TOF hit toggling after every measurement cycle 11: Edge for TOF hit toggling after every 2. measurement cycle BIT2 b00 13 TOF_HITS_TO_FDB: TOF Hits stored to frontend data buffer 0: Only TOF sum of all values is stored to Frontend Data Buffer 1: TOF sum of all values and the first 8 TOF values are stored to Frontend Data Buffer BIT 0 UINT [4:0] 0 12:8 TOF_HIT_NO: Number of TOF hits taken for TDC measurement 0: not allowed 1: 1 Hit 2: 2 Hits …. 31: 31 Hits TDC-GP30_DS000391_5-00 www.sciosense.com 7-19 Ultrasonic Flow Converter Bit Description Vol. 1 TDC-GP30 Format Reset 7:6 TOF_HIT_IGN: Number of hits ignored between two TOF hits taken for TDC measurement 00: 0 Hits 01: 1 Hit 10: 2 Hits 11: 3 Hits BIT2 b00 5:1 TOF_START_HIT_NO: Defines number of detected hits after first hit which is defined as the starting TOF hit for TDC measurement 0: 0 Hits not allowed because start hit cannot be first hit 1: 1 Hits not recommended due to instability after first hit 2: 2 Hits …. 31: 31 Hits UINT [4:0] 0 BIT 0 Format Reset PWD_EN: Enables pulse width detection 0: Pulse width detection disabled 1: Pulse width detection enabled BIT 0 14:12 AMC_RATE: Amplitude measurement calibration rate 000: AM Calibration disabled 001: AM Calibration with every amplitude measurement 010: AM Calibration with every 2. amplitude measurement 011: AM Calibration with every 5. amplitude measurement 100: AM Calibration with every 10. amplitude measurement 101: AM Calibration with every 20. amplitude measurement 110: AM Calibration with every 50. amplitude measurement 111: AM Calibration with every 100. amplitude measurement BIT3 b000 11:9 Has to be set 111 Sets timeout for AM to 128µs BIT3 0 UINT [4:0] 0 BIT 0 0 7.3.12 TOF_START_HIT_MODE: Selects mode for TOF start hit 0: Start hit for TOF measurement defined by TOF_START_HIT_NO 1: Start hit for TOF measurement defined by TOF_START_HIT_DLY CR_USM_AM (Ultrasonic Measurement Amplitude Measurement) Bit 31:16 15 8:4 Description 0x0CB Not used AM_PD_END: Amplitude Measurement, Peak Detection End, defined by number of detected hits 0: not allowed 1: after 1. detected Hit 2: after 2. detected Hit …. 30: after 30. detected Hit 31: not allowed Recommended condition: AM_PD_END PI_TPW 7.4.5 SHR_PI_IU_TIME (Pulse Interface Internal Update Time Distance) Bit Description 31:16 Not used 15:0 PI_IU_TIME: Time between 2 Internal Updates 1 LSB: 976.5625 μs (LP_MODE = 1) 1 LSB: 1 ms (LP_MODE = 0) 0x0D6 Mandatory condition: PI_IU_TIME > 2 and PI_IU_TIME > PI_TPW 7-22 www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 7.4.6 Vol. 1 SHR_PI_IU_NO (Pulse Interface Number of Auto Updates) Bit 31:8 0x0D7 Description Format Reset UINT [7:0] 0 Format Reset UINT [18:0] 0 Format Reset UINT [9:0] 0 Not used PI_IU_NO: Number of Internal Updates between 2 General Updates 7:0 7.4.7 Recommended condition for uniformed pulse generation: (PI_IU_NO + 1) * PI_IU_TIME = TOF_RATE * MR_CT SHR_TOF_START_HIT_DLY (TOF Start Hit Delay) 0x0D8 Bit Description 31:19 Not used 18:0 TOF_START_HIT_DLY: Delay window after which next detected hit is defined to TOF start hit. Starting time of delay window refers to rising edge of 1st fire pulse 1 LSB: 7.8125 ns (HS_CLK: 4 MHz) 3.90625 ns (HS_CLK: 8 MHz) 7.4.8 SHR_ZCD_LVL (Zero Cross Detection Level) Bit 31:10 9:0 7.4.9 Description 0x0D9 Not used ZCD_LVL: Zero Cross Detection Level 1 LSB: ~ 0.88 mV SHR_FHL_U (First Hit Level Up) Bit Description 31:8 Not used 7:0 ZCD_FHL_U: First Hit Level Up 1 LSB ~ 0.88 mV 7.4.10 Bit SHR_FHL_D (First Hit Level Down) Description 31:8 Not used 7:0 ZCD_FHL_D: First Hit Level Down 1 LSB ~ 0.88 mV 7.4.11 0x0DA Format Reset UINT [7:0] 0 Format Reset UINT [7:0] 0 0x0DB SHR_CPU_REQ (CPU Requests) 0x0DC This register is automatically cleared when the CPU stops operation, typically due to a stop command. All bits are typically triggered by the task sequencer, the error handling, a general purpose pin or the remote control. TDC-GP30_DS000391_5-00 www.sciosense.com 7-23 Ultrasonic Flow Converter Vol. 1 TDC-GP30 For test or debugging purposes it is also possible to write directly to these registers. Bits have to be cleared by the system program code or the user program code. Bit Format Reset 5 CPU_REQ_FW_INIT: CPU Request Firmware Initialization 0: Firmware Initialization not requested 1: Firmware Initialization requested Initially triggered by Bootloader BIT-T b0 4 CPU_REQ_GPH: CPU Request General Purpose Handling 0: General Purpose Handling in CPU not requested 1: General Purpose Handling in CPU requested - Synchronously triggered via Task Sequencer by any General Purpose Request BIT-T b0 3 not used BIT-T b0 2 CPU_REQ_PP: CPU Request Post Processing User 0: Post Processing in CPU not requested 1: Post Processing in CPU requested - Synchronously triggered by Task Sequencer if enabled BIT-T b0 1 CPU_REQ_CHKSUM: CPU Request Build Checksum 0: Build Checksum in CPU not requested 1: Configuration Compare in CPU requested - Synchronously triggered via Task Sequencer by Checksum Timer - Asynchronously triggered by Remote Controller - Initially triggered by Bootloader BIT-T b0 0 CPU_REQ_BLD_EXC: CPU Request Bootloader Execute 0: Bootloader Subroutine in CPU not requested 1: Bootloader Subroutine in CPU requested Initially triggered by Task Sequencer after system reset BIT-T b0 31:6 7.4.12 Description Not used SHR_EXC (Executables) 0x0DD Executables implemented as self-clearing bits. Bit 7-24 Description Format Reset 31:16 Not used 15 Not used SCB 0 14 GPH_TRIG: General Purpose Handling Trigger 0: No action 1: Triggers General Purpose Handling for CPU via Task Sequencer SCB 0 13 GPR_REQ_CLR: General Purpose Request Clear 0: No action 1: Clears general purpose request via remote interface SCB 0 12 COM_REQ_CLR: Communication Request Clear 0: No action 1: Clears communication request via remote interface SCB 0 www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 Vol. 1 Bit Description 11 7.4.13 Format Reset FW_IRQ: FW Interrupt Request 0: No action 1: Interrupt Request triggered by FW SCB 0 10 FW_IRQ_S: FW Interrupt Request, synchronized with task sequencer 0: No action 1: Interrupt Request triggered by FW and synchronized with task sequencer SCB 0 9 ZCC_RNG_CLR: Zero Cross Calibration Range Clear 0: No action 1: Clears Zero Cross Calibration Range SCB 0 8 Not used Has to be set 0 SCB 0 7 E2P_CLR: E2P Clear 0: No action 1: Clears E2P interface SCB 0 6 BG_REFRESH: Bandgap Refresh 0: No action 1: Bandgap Refresh SCB 0 5 PI_UPD: Pulse Interface Update 0: No action 1: Updates Pulse Interface SCB 0 4 TSV_UPD: Time Stamp Value Update 0: No action 1: Update Time Stamp Value SCB 0 3 TSC_CLR: Time Stamp Clear 0: No action 1: Clears Time Stamp Counter SCB 0 2 FES_CLR: Frontend Status Clear 0: No action 1: Clears Frontend Status Register SRR_FEP_STF SCB 0 1 EF_CLR: Error Flag Clear 0: No action 1: Clears Error Flag Register SRR_ERR_FLAG SCB 0 0 IF_CLR: Interrupt Flag Clear 0: No action 1: Clears Interrupt Flag Register SRR_IRQ_FLAG SCB 0 SHR_RC (Remote Control) 0x0DE The remote control register is implemented with radio buttons and self-clearing bits. It is used when operating in time conversion mode accessed by remote control. Radio buttons have the advantage in that single states of the register settings can be changed without knowing the complete state of the register. This saves a pre-reading of the register when operating in remote mode. To change a dedicated bit write a 1 to this one and a 0 to all others. TDC-GP30_DS000391_5-00 www.sciosense.com 7-25 Ultrasonic Flow Converter Bit Description TDC-GP30 Format Reset 20 FWD_RECALL: Recalls Firmware Data 0: No action 1: Starts recalling of Firmware Data from Flash to SRAM Execution needs to be enabled by SHR_FW_TRANS_EN SCB 0 19 FWC_RECALL: Recalls Firmware Program Code 0: No action 1: Starts recalling of Firmware Program Code from Flash to SRAM Execution needs to be enabled by SHR_FW_TRANS_EN SCB 0 18 FW_ERASE: Erases User Firmware Program Code & Firmware Data 0: No action 1: Starts erasing User Firmware Program Code & Data Execution needs to be enabled by SHR_FW_TRANS_EN SCB 0 17 FW_STORE_LOCK: Stores & Lock User Firmware Program Code & Firmware Data 0: No action 1: Starts storing & locking of User Firmware Program Code & Data Execution needs to be enabled by SHR_FW_TRANS_EN SCB 0 16 FW_STORE: Stores User Firmware Program Code & Firmware Data 0: No action 1: Starts storing of Firmware User Program Code & Data Execution needs to be enabled by SHR_FW_TRANS_EN SCB 0 RB b01 RB b01 RB b01 RB b01 31:21 7-26 Vol. 1 not used 15:14 not used 13:12 FWD1_MODE: Firmware Data 1 Mode 00: No Change of FWD1_MODE state (WO) 01: FWD1 Read disabled when GP30 will be protected 10: FWD1 Read enabled when GP30 will be protected 11: No Change of FWD1_MODE state (WO) 11:10 BG_MODE: Bandgap Mode 00: No Change of BG_MODE state 01: Bandgap controlled as configured 10: Bandgap always on 11: No Change of BG_MODE state 9:8 HSO_MODE: High Speed Oscillator Mode 00: No Change of HSO_MODE state (WO) 01: HSO controlled as configured 10: HSO always on 11: No Change of HSO_MODE state (WO) 7:6 DBG_EN: Debug Enable 00: No Change of DBG_EN state 01: Debug Mode disabled 10: Debug Mode enabled 11: No Change of DBG_EN state www.sciosense.com (WO) (WO) (WO) (WO) TDC-GP30_DS000391_5-00 TDC-GP30 Vol. 1 Bit Description 5:4 UART_CRC_MODE: UART CRC Mode 00: No Change of UART_CRC_MODE state (WO) 01: UART_CRC_MODE default 10: UART_CRC_MODE as configured 11: No Change of DBG_EN state 3:2 Format Reset RB b01 RB b10 RB b01 Format Reset BIT32 hAF0A _7435 (WO) HS_CLK_SEL: High Speed Clock Select. 00: No Change of HS_CLK_SEL state (WO) 01: If 4 MHz clock source, has to be initially configured after reset 10: If 8 MHz clock source 11: No Change of HS_CLK_SEL state (WO) Note: In the typical case of a 4 MHz reference, the user actively has to change the default setting to b01 after a power on or watchdog rest. 1:0 7.4.14 Bit 31:0 CFG_OK: GP30 Configuration OK 00: No Change of CFG_OK state 01: GP30 not properly configured 10: GP30 properly configured 11: No Change of CFG_OK state (WO) (WO) SHR_FW_TRANS_EN (Firmware Transaction Enable) Description FW_TRANS_EN: Firmware Transaction Enable Code to enable transactions of firmware into NVRAMs: h50F5_B8CA Write only register Status of this register can be checked in FW_TRANS_EN in register SRR_MSC_STF TDC-GP30_DS000391_5-00 www.sciosense.com 0x0DF 7-27 Ultrasonic Flow Converter Vol. 1 TDC-GP30 7.5 Status Registers 7.5.1 SRR_IRQ_FLAG (Interrupt Flags) Bit 31:8 Description Format Reset Not used 7 ERR_FLAG: At least 1 error flag is set BIT b0 6 DBG_STEP_END: Debug Step Ended BIT b0 5 FW_IRQ: Firmware Interrupt Request BIT b0 4 FW_IRQ_S: Firmware Interrupt Request, synchronized with task sequencer BIT b0 3 CHKSUM_FNS: Checksum Subroutine Finished BIT b0 2 BLD_FNS: Bootloader Finished BIT b0 1 FW_TRANS_FNS: Firmware Transaction Finished BIT b0 0 TSQ_FNS: Task Sequencer Finished BIT b0 Format Reset 7.5.2 SRR_ERR_FLAG (Error Flags) Bit 31:16 7-28 0x0E0 0x0E1 Description Not used 15 EF_CS_FWA_ERR: Error Flag FWA Checksum BIT b0 14 EF_CS_FWU_ERR: Error Flag FWU Checksum BIT b0 13 EF_CS_FWD2_ERR: Error Flag FWD2Checksum BIT b0 12 EF_CS_FWD1_ERR: Error Flag FWD1Checksum BIT b0 11 Not used BIT b0 10 EF_E2P_ACK_ERR: Error Flag EEPROM Acknowledge BIT b0 9 EF_TSQ_TMO: Error Flag Task Sequencer Timeout BIT b0 8 EF_TM_SQC_TMO: Error Flag Temperature Sequence Timeout BIT b0 7 EF_USM_SQC_TMO: Error Flag Ultrasonic Sequence Timeout BIT b0 6 EF_LBD_ERR: Error Flag Low Battery Detect BIT b0 5 EF_ZCC_ERR: Error Flag Zero Cross Calibration BIT b0 4 EF_TM_SC_ERR: Error Flag Temperature Measurement Short Circuit BIT b0 3 EF_TM_OC_ERR: Error Flag Temperature Measurement Open Circuit BIT b0 2 EF_AM_TMO: Error Flag Amplitude Measurement Timeout BIT b0 1 EF_TOF_TMO: Error Flag TOF Timeout BIT b0 0 EF_TDC_TMO: Error Flag TDC Timeout BIT b0 www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 7.5.3 Vol. 1 SRR_FEP_STF (Frontend Processing Status Flags) Bit 31:10 Description 0x0E2 Format Reset Not used 9 US_AMC_UPD: Ultrasonic Update for AMC measurement 0: No update in frontend buffer 1: Updated value in AMC area of frontend buffer BIT b0 8 US_AM_UPD: Ultrasonic Update for AM measurement 0: No update in frontend buffer 1: Updated value in AM area of frontend buffer BIT b0 7 US_TOF_EDGE: TOF Measurement Edge 0: Positive Edge 1: Negative Edge BIT b0 6 US_TOF_UPD: Ultrasonic Update for TOF measurement 0: No update in frontend buffer 1: Updated value in TOF area of frontend buffer BIT b0 5 US_D_UPD: Ultrasonic Update in Down direction 0: No update in frontend buffer 1: Updated value in ultrasonic down area of frontend buffer BIT b0 4 US_U_UPD: Ultrasonic Update in Up direction 0: No update in Frontend Buffer 1: Updated value in ultrasonic up area of frontend buffer BIT b0 3 TM_ST: Temperature Measurement Subtask 0: Temperature Measurement with 1 subtask 1: Temperature Measurement with 2 subtasks BIT b0 2 TM_MODE: Temperature Measurement Mode 0: External Measurement 1: Internal Measurement BIT b0 1 TM_UPD: Temperature Measurement Update 0: No update in Frontend Buffer 1: Updated value in Temp Measure related Frontend Buffer BIT b0 0 HCC_UPD: High-Speed Clock Calibration Update 0: No update in SRR_HCC_VAL 1: Updated value in SRR_HCC_VAL BIT b0 Format Reset 7.5.4 SRR_GPI (General Purpose In) Bit 31:12 Description 0x0E3 Not used 11 LS_CLK_S: Low Speed Clock, synchronized to CPU Clock BIT 10 NVM_RDY: NVRAM Ready BIT 9 UART_SEL: UART Select BIT 8 LP_MODE: Low Power Mode. Equals the signal on pin LP_MODE during operation. Note: Signal goes low during startup after power on, including firmware initialization. BIT 7 not used TDC-GP30_DS000391_5-00 www.sciosense.com 7-29 Ultrasonic Flow Converter Bit Description 6:0 GPI: General Purpose In 7.5.5 TDC-GP30 Format Reset BIT7 0 SRR_HCC_VAL (High-Speed Clock Calibration Value) Bit Description 31:26 Not used 25:0 HCC_VAL: High-Speed Clock Calibration Value Measures the time of 4 LS_CLK periods: 122.07 µs 1 LSB: 250 ns / 216 (if fHS_CLK = 4 MHz) 1 LSB: 125 ns / 216 (if fHS_CLK = 8 MHz) 7.5.6 0x0E4 Format Reset UINT [25:0] 0 SRR_VCC_VAL (VCC Value) Bit 31: 6 5:0 7.5.7 Description Description Not used 17:0 TS_HOUR: Timestamp Hours 1 LSB: 1h SRR_TS_MIN_SEC (Time Stamp Minutes & Seconds) Bit Format Reset UINT [5:0] 0 Format Reset UINT [17:0] 0 Format Reset VCC_VAL: Measured value of VCC voltage 1 LSB: 25 mV VCC_VAL = 0: 2.13 V VCC_VAL = 63: 3.70 V 31:18 7.5.8 0x0E5 Not used SRR_TS_HOUR (Time Stamp Hours) Bit Description 0x0E6 0x0E7 31:16 Not used 15:8 TS_MIN: Timestamp Minutes 1 LSB: 1min Range (0-59) UINT [7:0] 0 7:0 TS_SEC: Timestamp Seconds 1 LSB: 1sec Range (0-59) UINT [7:0] 0 7.5.9 SRR_TOF_CT (Time of Flight, Cycle Time) Bit 31:13 7-30 Vol. 1 Description 0x0E8 Format Not used www.sciosense.com TDC-GP30_DS000391_5-00 Reset TDC-GP30 Bit 12:0 7.5.10 Vol. 1 Description TOF_CT: TOF Cycle Time Cycle Time = TOF_CT * 976.5625 µs = TOF_CT * 1 ms Not used 11:0 TS_TIME: Task Sequencer Time Current Time = TS_TIME * 976,5625 µs = TS_TIME* 1 ms 7.5.11 31:16 0 Format Reset UINT [11:0] 0 Format Reset (LP_MODE = 1), (LP_MODE = 0) SRR_MSC_STF (Miscellaneous Status Flags) Bit UINT [12:0] 0x0E9 Description 31:12 Reset (LP_MODE = 1), (LP_MODE = 0) SRR_TS_TIME (Task Sequencer time) Bit Format Description 0x0EA Not used 15 WD_DIS: Watchdog Disabled BIT b0 14 E2P_BSY: E2P Busy BIT b0 13 E2P_ACK: EEPROM Acknowledge BIT b0 12 HSO_STABLE: High Speed Oscillator Stable BIT b0 11 Not used BIT b0 10 CST_REQ: Request by Checksum Timer BIT b0 9 Not used BIT b0 8 Not used BIT b0 7 GPH_REQ: General Purpose Request by GPH_TRIG in SHR_EXC BIT b0 6 GPT_REQ: General Purpose Request by GP Timer BIT b0 5 GPR_REQ: General Purpose Request by remote interface BIT b0 4 COM_REQ: Communication Request by remote interface BIT b0 3 FWD1_RD_EN: FWD1 Read Enabled BIT b0 2 FW_UNLOCKED: FW Unlocked BIT b0 1 FW_STORE_ALL: FW Store All BIT b0 0 FW_TRANS_EN: FW Transaction Enabled BIT b0 Format Reset 7.5.12 Bit 31:8 SRR_E2P_RD (EEPROM Read Data) Description 0x0EB not used TDC-GP30_DS000391_5-00 www.sciosense.com 7-31 Ultrasonic Flow Converter Bit Description 7:0 E2P_DATA: EEPROM Read Data Read Data from external EEPROM connected via EEPROM interface 7.5.13 Bit Description 11:0 FWU_RNG: FW User Range Number of FW Code addresses which are reserved for FW User Code starting at address 0. 31:0 7.5.15 Bit 31:0 7.5.16 Bit 6:0 Format Reset BIT8 0 0x0EC Not used Bit TDC-GP30 SRR_FWU_RNG (FW User Range) 31:12 7.5.14 7-32 Vol. 1 SRR_FWU_REV (FW User Revision) Description Format Reset UINT [11:0] 0 Format Reset BIT32 0 Format Reset BIT32 0 0x0ED FWU_REV: FW User Revision Last 4 Bytes in FW User Code Range, reserved for revision. SRR_FWA_REV (FW ACAM Revision) Description FWA_REV: FW ACAM Revision 4 Bytes in FW ACAM Code Range, reserved for revision. SRR_LSC_CV (Low Speed Clock Count Value) Description LSC_CV: Low Speed Clock Count Value www.sciosense.com 0x0EE 0x0EF Format Reset BIT7 0 TDC-GP30_DS000391_5-00 TDC-GP30 Vol. 1 8 Applications 8.1 GP30-DEMO Board For Ultrasonic Heat/Water Meter with 2-Wire Temperature Measurement The following diagram shows the complete schematics of a heat meter front end. For details refer to the GP30-DEMO-KIT datasheet. Figure 8-1 Complete schematics of the GP30 DEMO board: Temperature Hot VCC AS1360 4 MHz 100n 100n VCC LP_MODE US_UP GND US_DOWN PTREF 25 560k XOUT_4MHZ SSN_GPIO2 SSN MOSI MOSI_GPIO3 For test only SCK_RXD SCK / RX MISO / TX MISO_TXD INT 32.768kHz 10p 10M XOUT_32KHZ UART_SEL GPIO0 GPIO1 VCC XIN_32KHZ 680n XIN_4MHZ VDD18_IN 17 US_VREF FIRE_DOWN VCC PTCOLDA 8 9 FIRE_UP PTCOLDB 24 VDD18_OUT 4R7 100u PTHOTB 1 7 GP30YD 1503 VDD18_IN 16 PTWCOMB INTN_DIR VDD18 32 100u CLOAD 1k PTWCOMA 4u7 Vout PTHOTA Vin 10p GPIO TDC-GP30_DS000391_5-00 www.sciosense.com 8-1 SPI / UART 4R7 Pulse interface 47R Vin 3.6V Cold Ultrasonic Flow Converter Vol. 1 TDC-GP30 8.2 GP30 Typical Configuration The following table shows a typical configuration as it is used in our example that simply calculates the DIFTOF and converts this to an output via the pulse interface (DIF_over_PI.cfg). Table 8-1 Typical configuration Register Address Content Main settings CR_WD_DIS 0xC0 0xAF0A7435 Watchdog enabled CR_PI_E2P 0xC1 0x0034310A Pulse interface enabled, with update over PI_UPD… CR_GP_CTRL 0xC2 0x81111144 GPIO0 and GPIO1 set for pulse interface; pulls ups activated on inputs to avoid floating gates CR_UART 0xC3 0x00001000 Not used CR_IEH 0xC4 0x011F03FF Various triggers for interrupt and error are set CR_CPM 0xC5 0x00280AE8 Voltage measurement disabled. 4 MHz high speed clock, calibrated every 20 th sequence, settling time 135µs CR_MRG_TS 0xC6 0x00016080 Back timer and checksum timer disabled, bandgap synchronized, MR_CT = 253 (~247ms) CR_TM 0xC7 0x00F99400 Temperature measurement off CR_USM_PRC 0xC8 0x00002824 Ultrasonic measurement, 20ms between TOF_UP and TOF_DOWN, toggling direction, noise window 40.6 µs, 128 µs timeout CR_USM_FRC 0xC9 0x03E48C83 25 pulses at 1 MHz CR_USM_TOF 0xCA 0x00000C10 First hit mode, starting with 9 th hit, 12 hits, no ignored ones, positive edges CR_USM_AM 0xCB 0x0000DE81 Amplitude measurement with every TOF for 8 hits, calibration every 20 th CR_TRIM1 0xCC 0x84A0C47C Trim bits as recommended CR_TRIM2 0xCD 0x401700CF Trim bits as recommended CR_TRIM3 0xCE 0x00270808 Trim bits as recommended SHR_TOF_RATE 0xD0 0x00000001 TOF rate = 1 SHR_TOF_START_HIT_DLY 0xD8 0x00000000 Start hit delay window = 0 (not active) SHR_ZCD_FHL_U 0xDA 0x00000055 First hit level up = 85 (~ 74.8 mV) SHR_ZCD_FHL_D 0xDB 0x00000055 First hit level down = 85 (~ 74.8 mV) 8-2 www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 Vol. 1 9 Glossary Terms AM Backup Bootloader Burst Calibration CD Comparator Meaning GP30 interpretation Amplitude measurement This is a peak measurement of the received signal amplitude. It can be configured to be executed in different time frames, which allows to pick the overall signal maximum (to control the signal level), or to measure only the peak of a selected number of ->wave periods. The latter allows for a more detailed receive signal analysis. Permanent storage of a GP30 is prepared for an external data backup, foreseen over the data copy built-in I2C-bus, which permits write and read with an external EEPROM. In principle, a user may also utilize the ->GPIOs for his own interface implementation for external backup. System routine that Typically after a system reset, first time when the ->TS calls the initializes CPU >CPU, the bootloader routine is called. If the -> Firmware is operation released, the bootloader loads the chip configuration from FWD into CR and does other hardware initialisations like reading firmware revision numbers and calculation of checksums. Analog signal containing For a flow measurement, a ->fire burst, that means a fixed number of a number of ->wave ->wave periods of the measurement frequency, is send over a periods ->transducer into the flow medium. After some travel time (see >TOF), a receive burst appears at the opposed transducer, which is detected as a number of ->hits. Note that the peak amplitude of the receive burst must not exceed -> V ref to avoid negative voltages. Parameter adjustment to In GP30, different calibration processes are implemented and compensate variations needed for high quality measurements: ->Firmware calibrations: Flow and temperature calibration, but also the ->FHL adjustment are under full control of the firmware. Half-automated calibrations: ->AM calibration and ->HSO calibration are based on dedicated measurements, initiated by the ->TS on demand. The actual calibrations need further evaluation by the firmware. Fully hard-coded calibrations: these calibrations need no interaction from firmware. One example is ->ZCD level calibration, which only needs to be initiated by the ->TS frequently. Another example is >TDC calibration which happens automatically before each measurement. Configuration Data 16 x (up to) 32b words of ->flash memory for configuration of the chip, address range 0x16C - 0x17A (->NVRAM). Is copied to ->CR for actual usage. CPU Device that compares two input signals Central Processing Unit CR Configuration Register CRC Cyclic Redundancy Check C0G DIFTOF, DIFTOF_ALL Difference of up and down ->TOF TDC-GP30_DS000391_5-00 See ->ZCD-comparator 32b processor (Harvard architecture type) for general data processing. The CPU has a fixed instruction set and acts directly on its three input- and result-registers ->X,Y and Z as well as on addressed RAM. The fourth register of the CPU is the ->RAM address pointer R. Instructions for the CPU are read as -> FWC or >ROM code at an address given by the ->program counter. The chip actually uses for its hardware configuration a copy of the >CD into the CR address range 0x0C0 - 0x0CF (see ->direct mapped registers). Method for checksum calculation to control data integrity, employed in GP30 for ->UART communication. Material of a ceramic capacitor with a very low temperature drift of capacity The difference between up and down ->TOF is the actual measure for flow speed. (see also ->SUMTOF). DIFTOF_ALL is the DIFTOF using ->TOF_ALL results, averaged over all TOF ->hits. www.sciosense.com 9-1 Ultrasonic Flow Converter Terms Direct mapped registers Meaning Registers with direct hardware access DR Debug Register FEP FDB Frontend Processing Frontend data buffer FHL, V FHL First hit level Fire, fire burst, fire buffer Firmware Send signal ->burst Flow meter mode Operation mode of GP30 as full flow meter system Frontend Main measurement circuit block FWC Firmware Code FWD Firmware Data FWD-RAM Firmware Data memory GPIO General purpose input/output 9-2 Program code (in a file) for chip operation Vol. 1 TDC-GP30 GP30 interpretation These register cells are not part of some fixed memory block, they rather have individual data access. This makes them suitable for hardware control. See ->SHR, ->SRR, ->CR and ->DR. Labels have the according prefix. Internal registers of the ->CPU, mapped to the RAA address range 0x0F8 – 0x0FB in debug mode. Task of the ->TS where frontend measurements are performed Part of the -> RAM where the -> frontend temporarily stores its latest measurement results (-> RAA address range from 0x80 up to maximally 0x9B) Voltage level similar to the ->ZCD level, but shifted away from Zero level, for save detection of a first ->hit. The FHL determines, which of the ->wave periods of the receive -> burst is detected as first hit. It thus has a strong influence on ->TOF and must be well controlled, in order to achieve comparable TOF measurements. The measurement signal on sending side is called fire burst, its output amplifier correspondingly fire buffer. The program code can be provided by acam or by the customer, or a combination of both. The complete program code becomes the >FWC (firmware code) when stored in the ->NVRAM. The term firmware is in general used for all firmware programs, no matter if they make up the complete FWC or not. In flow meter mode, the TDC-GP30 also performs further evaluation of ->TOF results, to calculate physical results like flow and temperature. To do this, it uses a ->firmware running on its internal CPU. See for comparison -> time conversion mode This part of the GP30 chip is the main measurement device, containing the analog measurement interface (including the -> TDC). The frontend provides measurement results which are stored in the >FDB. Firmware code denotes the complete content of the ->NVRAM’s 4kB section (address range 0x0000 to 0x 0FFF). The difference to the term ->firmware is on the one hand that firmware means the program in the file. On the other hand, a particular firmware may provide just a part of the complete FWC. FWC is addressed by the CPU’s program counter, it is not available for direct read processes like RAM. The firmware configuration and calibration data, to be stored in the >FWD-RAM 128 x 32b words of ->NVRAM (built as volatile ->SRAM and non-volatile flash memory). The FWD-RAM is organized in two address ranges, FWD1 (-> RAM addresses 0x100 0x11F) and FWD2 (RAM addresses 0x120 – 0x17F). Main purpose is calibration and configuration Due to its structure, FWD-RAM can be used like usual ->RAM by the firmware. But note that with every data recall from flash memory the contents of the SRAM cells get overwritten. GP30 has up to 7 GPIO pins which can be configured by the user. Some of them can be configured as ->PI or ->I2C-interface. www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 Vol. 1 Terms Hit Meaning Stands for a detected wave period HSO High speed oscillator INIT Initialization process of ->CPU or -> FEP IO I2C Input/output Inter-Integrated Circuit bus Low speed oscillator LSO MRG Measurement Rate Generator NVRAM, NVM Programmable NonVolatile Memory PI Pulse interface PP Post Processing TDC-GP30_DS000391_5-00 GP30 interpretation The receive ->burst is typically a signal which starts with ->wave periods of the measurement frequency at increasing signal levels. While the first of these wave periods are too close to noise for a reliable detection, later signal wave periods with high level can be detected safely by the ->ZCD-comparator. The comparator converts the analog input signal into a digital signal, which is a sequence of hits. To detect the first hit at an increased signal level, away from noise, the input signal is compared to the ->FHL. After the first hit, the level for comparison is immediately reduced to the ->ZCD level, such that all later hits are detected at zero crossing (note that the ZCD level is defined to zero with respect to the receive signal, it is actually close to -> V ref or another userdefined level). Different hits are denoted according to their usage: ▪ Hit (in general) stands for any detected ->wave period. ▪ First hit is actually the first hit in a ->TOF measurement (not the first wave period!) ▪ TOF hits means all hits which are evaluated for ->TOF measurements. Note that typically the first hit is not a TOF hit. ▪ Start hit is the first TOF hit. This is typically not the first hit, but (according to configuration) some well-defined later hit. Minimum the 3 rd hit has to set as Start hit. ▪ Stop hit is the last TOF hit. It is also defined by configuration and should not be too close to the end of the receive ->burst. ▪ Ignored hits are all hits which are not evaluated for the TOF measurement: All hits between first hit and start hit, as well any hit between TOF hits or after the stop hit. The 4 or 8 MHz oscillator of the GP30. In usual operation only switched on when needed, to reduce energy consumption. This is the time base for ->TDC measurements. The HSO is typically less accurate that the ->LSO. It should be frequently ->calibrated against the LSO to obtain the desired absolute accuracy of the ->TDC. In GP30 terminology, INIT processes don’t reset registers or digital IOs, while -> reset does at least one of it. Several different INIT processes are implemented, see chapter “Reset hierarchy” for details. Connections to the outside world for input or output Standard serial bus for communication with external chips. Implemented in GP30 only in part for EEPROM data exchange. The 32768 Hz crystal oscillator of the GP30. This oscillator controls the main timing functions (->MRG and ->TS, real time clock). The measurement rate generator controls the cyclic ->tasks of GP30 by setting task requests in a rate defined by configuration (->CR). When the MRG is activated, it periodically triggers the ->TS for initiating the actual ->tasks. GP30 contains two sections of programmable non-volatile memory: One section of 4kB ->FWC memory, and another of ->FWD-RAM (FWD1:-> RAM addresses 0x100 - 0x11F and FWD2: RAM addresses 0x120 – 0x17F), in total 128 x 32b words. It is organized as a volatile SRAM part which is directly accessed from outside, and a non-volatile flash memory part. Standard 2-wire interface for flow output of a water meter. Typically outputs one pulse per some fixed water volume (e.g. one pulse per 0.1 l ), while the other wire signals the flow direction. Permits standalone operation and is fully compatible to mechanical water meters. Processing activities of the -> CPU, typically after frontend processing (e.g. a measurement) , initiated by –>TS www.sciosense.com 9-3 Ultrasonic Flow Converter Terms Program counter Meaning Pointer to the current code address of the ->CPU PWR Pulse width ratio R RAM address pointer of the CPU RAA Random Access Area RAM Random Access Memory Address of a cell in the RAA range RAM address Register Memory cell for dedicated data storage Reset Reset of the chip RI Remote Interface ROM Read Only Memory ROM code Hard coded routines in ROM Serial Clock Serial Data System Handling Register SCL SDA SHR SPI SRAM SRR 9-4 Vol. 1 TDC-GP30 GP30 interpretation The program counter addresses the currently evaluated ->FWC or >ROM-code cell during ->CPU operation The program counter always starts at 0xF000, when any CPU action is requested. If any kind of firmware code execution is requested, the program counter is continued at 0x0000 (for FW initialization, post processing or general purpose handling). Width of the pulse following the first ->hit, related to the pulse width at the start hit. This width indicates the position of the ->FHL relative to the level of the detected ->wave period and thus gives some information on detection safety (small value means FHL is close to the peak amplitude and the desired wave period may be missed due to noise; large value indicates the danger that an earlier wave period may reach FHL level and trigger the first hit before the desired wave period). The ->CPU acts on the data of the ->X-,Y- and Z-register and on one single RAM cell. The pointer R defines the address of the current RAM cell. Address range from 0x000 to 0x1FF covering the ->RAM addresses. Memory cells within this address range can all be read, most of them can also be written (except ->SRR and ->DR). The RAA covers memory cells of different technology: ->RAM (including ->FDB), ->FWD-RAM ( including ->CD), ->direct mapped registers (->SHR, ->SRR, ->CR and ->DR). 176 x 32b words of volatile memory, used by ->FDB and -> Firmware. Address range 0x000 to 0x0AF A RAM address is used by the firmware or over ->RI to point to a memory cell for data storage or retrieval. Note that RAM addresses cover not only actual RAM, but all cells in the RAA range. Address range from 0x000 to 0x1FF Memory cells are typically called register when they contain flags or configuration bits, or when they have a single dedicated purpose (see ->CPU, ->CR, ->SHR and ->SRR). GP30 has different processes and commands that can call resets and initializations at different levels. Some of them refresh ->CR or GPIO state, others just (re-) initialize CPU or frontend. The latter are rather denoted ->INIT. See chapter “Reset hierarchy” for details. Interface for communication with a remote controller (see ->SPI and ->UART) 4kB of fixed memory, contains hard coded routines for general purpose and parts of acam’s ->firmware (ROM code). Address range 0xF000 – 0xFFFF. The ROM code is addressed by the CPU’s program counter, it is not available for direct read processes like RAM. See -> ROM. Serial clock of EEPROM interface Serial data of EEPROM interface Registers that directly control chip operation. The data & flags of system handling registers have a dynamic character. They are typically updated by post processing, but have to be initially configured before measurement starts. Serial Peripheral Standard interface for communication of the GP30 with an external Interface master controller (alternative to ->UART). Static RAM GP30 does not use any dynamic RAM, in fact all RAM in GP30 is static RAM. However, the term “SRAM” is in particular used for the RAM-part of the ->NVRAM. Status & Result Register The SRR-registers describe the current state of the chip. They are set by the chip hardware and contain error and other condition flags, timing information and so on. www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 Terms SUMTOF, SUMTOF_ALL Vol. 1 Meaning Sum of up and down TOF GP30 interpretation The sum of up and down ->TOF is a measure for the speed of sound in the medium, which can be used for temperature calculation. SUMTOF_ALL is the SUMTOF using ->TOF_ALL results, averaged over all TOF ->hits. Supervisor Functional block of The supervisor of TDC-GP30 controls chip operation and timing GP30 that controls through the measurement rate generator (->MRG) and the task voltage and timing sequencer (–>TS). It also covers voltage control and adjustment functions as well as the main oscillators -> LSO and ->HSO Task Process, job The term task is used for a process which aims at fulfilling some fixed purpose, separate from other tasks with different goals. Typical tasks in GP30 are ->TOF measurement, temperature measurement (-> TM), post processing (-> PP), remote communication and voltage measurement. Time Remotely controlled In time conversion mode, the TDC-GP30 mainly acts as a ->TOF conversion operation of GP30 measurement system. It may operate self-controlled or remotely mode controlled, but it does no further result evaluation. This operation mode is similar to the typical usage of the acam chips GP21 and GP22. For comparison see ->Flow meter mode TDC Time-to-digital-converter The core measurement device of GP30. Measures times between a start- and a stop-signal at high accuracy and high resolution. The internal fast time base of the TDC is automatically ->calibrated against the ->HSO before each measurement. TOF, TOF_ALL Time of Flight Basic measurement result for an ultrasonic flow meter: The time between send and receive ->burst (with some offset, depending on >hit detection). Measurements of TOF are done in flow direction (down TOF) and in the opposite direction (up TOF). GP30 also provides the sum of all TOF ->hits in the values TOF_ALL. TS Task Sequencer The task sequencer arranges and initiates the ->tasks which are requested by the ->MRG in one measurement cycle or which are initiated remotely. TM Temperature This task means a temperature measurement using sensors, in measurement contrast to temperatures which are calculated results from a TOF measurement (see -> SUMTOF) Transducer Electromechanical Transducers for flow measurements are piezoelectric devices that conversion device convert an electrical signal into ultrasound and reverse. They are usually matched to the flow medium (e.g. water). GP30 can connect directly to the send and receive transducer. UART Universal Asynchronous Standard interface for communication of the GP30 with an external Receiver & Transmitter master controller (alternative to ->SPI). USM Ultrasonic measurement The principle of an ultrasonic flow meter is to measure ->TOFs of ultrasound in flow direction and against it, and to calculate the flow from the result. See also ->transducer. Reference voltage V ref The analog interface of GP30 refers to V ref , a nominal voltage for -> V ZCD of typically 0.7V. This makes it possible to receive a DC-free AC-signal with a single supply voltage. Up to the level of V ref , negative swings of the receive signal are avoided. Zero cross detection This voltage level represents the virtual zero line for the receive V ZCD level >burst. It is normally close to -> V ref , just differing by the offset of the ->ZCD-comparator. Needs frequent ->calibration to compensate the slowly changing offset. Optionally, this voltage can be configured differently in SHR_ZCD… through the firmware. Watchdog, Reset timer for chip re- The watchdog of GP30 ->resets the chip (including ->CR refresh) if watchdog clear initialization no watchdog clear (->firmware command clrwdt) within 13.2s (typically) is executed. This is a safety function to interrupt hang-up situations. It can be disabled for remote control, when no firmware clears the watchdog automatically. TDC-GP30_DS000391_5-00 www.sciosense.com 9-5 Ultrasonic Flow Converter Terms Wave period X-, Y- and Zregister ZCD ZCDComparator 9-6 Vol. 1 TDC-GP30 Meaning GP30 interpretation One period of the signal A period of typically 1us length for a 1 MHz measurement frequency. wave This may be a digital pulse, for example when sending, or a more sinusoidal wave when receiving. Fire or receive ->bursts are sequences of wave periods. Input- and result The ->CPU acts on these ->registers for data input and result output. registers of the CPU Zero cross detection All ->hits following the first hit are detected when the received signal crosses a voltage level V ZCD , defined as zero with respect to the receive ->burst. In contrast, the first hit is detected when the received signal crosses the different voltage level V FHL (->FHL). ->comparator for ->hit The ZCD-comparator in GP30 detects ->hits in the received -> burst detection signal by comparing the received signal level to a given reference voltage (see also -> FHL, ->ZCD and ->hit). www.sciosense.com TDC-GP30_DS000391_5-00 TDC-GP30 Vol. 1 10 Miscellaneous 10.1 Bug Report 10.1.1 Communication Request Flag Error description COM_REQ bit in SRR_MSC_STF register might be set back in an uncontrolled manner, depending on the communication. In consequence, GP30 allows only a single response to a remote communication request. Work around Avoid any further communication after sending a remote command request (RC_COM_REQ), until the interrupt is set. Users have to reset the flag COM_REQ_CLR (bit 12) in register SHR_EXC. In TDC-GP30-F01 with firmware versions A1.A2.11.04 the bit is reset by the firmware. 10.2 Last Changes from 0.4 to current version 5 05.05.2020 SHR_FHL_xx format changed from SINT to UINT ScioSense contacts replacing ams AG / acam-messelectronic GmbH 1.3 Ordering numbers extended TDC-GP30_DS000391_5-00 www.sciosense.com 10-1 ScioSense B.V. High Tech Campus 10 5656 AE Eindhoven The Netherlands info@sciosense.com www.sciosense.com Tel. +31 40 851 6435 Tel. +40 7244 7419 0