W83312SN

Nuvoton Bus Termination Regulator W83312SN W83312SN -Table of Content1. GENERAL DESCRIPTION .............................................................................................................. 1 2. FEATURES ...................................................................................................................................... 1 3. BLOCK DIAGRAM ........................................................................................................................... 2 4. PIN CONFIGURATION AND TYPICAL APPLICATION CIRCUIT .................................................. 2 5. PIN DESCRIPTION .......................................................................................................................... 3 6. FUNCTIONAL DESCRIPTION ........................................................................................................ 4 7. ELECTRICAL CHARACTERISTIC .................................................................................................. 7 8. TYPICAL OPERATING WAVEFORMS ........................................................................................... 9 9. PACKAGE DIMENSION ................................................................................................................ 22 10. ORDERING INFORMATION.......................................................................................................... 23 11. TOP MARKING SPECIFICATION ................................................................................................. 23 12. REVISION HISTORY ..................................................................................................................... 24 -I- Publication Date: Mar., 2010 Revision A5 W83312SN 1. GENERAL DESCRIPTION The W83312SN is a linear regulator which provides a power achieves peak 3.0Amp bidirectional sinking and sourcing capability for a high speed bus terminator application. The chip simply implements a stable power supply which tracks half of input power dynamically for bus terminator with a single chip. The W83312SN is promoted with small footprint 8-SOP 150mil power package. With W83312SN design, a high integration, high performance, and cost-effective solution are promoted. 2. FEATURES 2.1. 2.2. 2.3. General z Memory Termination Regulator for DDR1, DDR2, DDR3 and Low Power DDR3 z Sink and Source 3A Peak Current z Integrated Power MOSFET z Adjustable V OUT by External Resistors z Low External Component Count z Low Output Voltage Offset z Current Limit Protection z Over Temperature Protection z -40°C to 85°C Ambient Operating Temperature Range Package z SOP-8 150mil with Exposed Pad Package z Lead Free (ROHS Compliant) and Halogen Free Applications z Desktop PCs, Notebooks, and Workstations z Graphics Card Memory Termination z Set Top Boxes, Digital TVs and Printers z Active Termination Buses z DDR1, DDR2 and DDR3 Memory Systems -1- Publication Date: Mar., 2010 Revision A5 W83312SN 3. BLOCK DIAGRAM VIN VCNTL Current Limit Protection Control VREF VOUT Logic GND Thermal Shutdown 4. PIN CONFIGURATION AND TYPICAL APPLICATION CIRCUIT VIN 1 8 NC GND 2 7 NC VREF 3 6 VCNTL VOUT 4 5 NC W83312SN (Top View) -2- Publication Date: Mar., 2010 Revision A5 W83312SN VDDQ=2.5V/1.8V/1.5V VCNTL=3.3V/5V C CNTL C IN R1 VIN VCNTL VREF Enable C SS R2 VTT = VDDQ x R2 / (R1+R2) VOUT GND C OUT Typical Application Circuits 5. PIN DESCRIPTION SYMBOL VIN PIN 1 I/O FUNCTION I Main power input pin which supplies current to output pin. For lower power dissipation consideration, using VDDQ (Supply voltage for DRAM) as power source is recommended. Internal reference voltage source. Generally, VREF tracks VDDQ/2 for DDR application. VREF 3 I Using voltage dividing resistors and capacitor as low pass filter for noise immunity and output voltage soft start is recommended. If using an N-MOSFET as shutdown function, please make sure the sinking current capability can pull down VREF under 0.2V. VOUT 4 O Voltage output pin which is regulated to track VREF voltage. VCNTL 6 I Power for internal control logic circuitry. A ceramic decoupling capacitor with 1uF is required. GND 2 NC 5, 7, 8 Ground. Connect to negative terminal of the output capacitor. No connection. -3- Publication Date: Mar., 2010 Revision A5 W83312SN 6. FUNCTIONAL DESCRIPTION 6.1 VTT Sink/Source Regulator The W83312SN is a sink/source tracking Double Data Rate (DDR) termination regulator specifically designed for low input voltage, low cost and low external component count systems where space is a key application parameter. The W83312SN integrates a high performance, low dropout linear regulator that is capable of both sinking and sourcing current. 6.2 General Regulator The W83312SN could also serves as a general linear regulator. The W83312SN accepts an external reference voltage at VREF pin and provides output voltage regulated to this reference voltage as shown in Fig.6-1, where VOUT=VEXT x R2/ (R1+R2) VIN VCNTL=3.3V/5V VEXT C CNTL R1 C IN R2 C SS VIN VCNTL VREF VOUT = VEXT x R2 / (R1+R2) VOUT GND C OUT Fig. 6-1 The W83312SN supports wide VREF voltage input range, making it versatile and idea for many types of low power LDO applications. The dropout voltage is the input voltage minus output voltage that produces 2% decrease in output voltage, where VIN MIN =V DROPOUT + VOUT The output voltage range depends on VCNTL voltage and output loading which means higher VCNTL voltage can support higher output voltage and higher output loading. Fig.6-2 and Table 6-1 show that the relationships among VOUT, V DROPOUT and IOUT when VCNTL=5V. For example, if VOUT=3.4V, the maximum output loading is 1.5A with 0.25V dropout voltage and the minimum VIN is 3.65V. The Max column in the table means the minimum dropout voltage needed in worst conditions. Choose suitable VIN voltage to obtain better efficiency. VCNTL=5V Parameter Dropout Voltage -4- Typ. Max IOUT=1A, 0.6V≦ VOUT ≦3.4V Conditions 0.15 0.3 IOUT=1.5A, 0.6V≦ VOUT ≦3.4V 0.25 0.5 IOUT=2A, 0.6V≦ VOUT ≦3.2V 0.35 0.7 IOUT=2.5A, 0,8V≦ VOUT ≦3V 0.5 1 Unit V Publication Date: Mar., 2010 Revision A5 W83312SN VOUT vs. Dropout Voltage, VCNTL=5V 0.6 Dropout Voltage (V) 0.5 IOUT=1A IOUT=2A 0.4 IOUT=1.5A IOUT=2.5A 0.3 0.2 0.1 0 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 Table 6-1 VOUT (V) Fig.show 6-2 that the relationships among VOUT, V DROPOUT and IOUT when Fig.6-3 and Table 6-2 VCNTL=3.3V. VOUT vs. Dropout Voltage, VCNTL=3.3V 0.6 Dropout Voltage (V) 0.5 IOUT=1A IOUT=1.5A IOUT=2A IOUT=2.5A VCNTL=3.3V Parameter Conditions Typ. Max IOUT=1A, 0.6V≦ VOUT ≦1.8V 0.35 0.7 IOUT=1.5A, 0.6V≦ VOUT ≦1.6V 0.35 0.7 IOUT=2A, 0.6V≦ VOUT≦ 1.6V 0.6 1.2 IOUT=2.5A, 0.8V≦ VOUT≦ 1.4V 0.45 0.9 Unit 0.4 0.3 Dropout Voltage 0.2 0.1 0 0.6 0.8 1 1.2 1.4 1.6 1.8 VOUT (V) V Table 6-2 Fig. 6-3 6.3 Shutdown Function When the external reference voltage at VREF pin is under shutdown threshold, the internal regulator will be turned off and VOUT is at High-Z state. 6.4 Over Current Protection The W83312SN provides a current limit circuitry, which monitors the output current and controls NMOS’s gate voltage to limit the output current at 3.5A, typically. 6.5 Over Temperature Protection The W83312SN monitors its junction temperature. If the device junction temperature exceeds its threshold value, typically 165°C, the VOUT is shut off. The shutdown is a non-latch protection. 6.6 Thermal Design Since the W83312SN is a linear regulator, the VOUT current flows in both source and sink directions, thereby dissipating power from the device. When the device is sourcing current, the -5- Publication Date: Mar., 2010 Revision A5 W83312SN voltage difference between VIN and VOUT times I OUT current becomes the power dissipation as shown in below equation. P DISS_SOURCE = (VIN-VOUT) x I OUT_SOURCE In this case, if VIN is connected to an alternative power supply lower than the VDDQ voltage, overall power loss can be reduced. For the sink phase, VOUT voltage is applied across the internal LDO regulator and the power dissipation, P DISS_SINK can be calculated by below equation. P DISS_SINK = VOUT x I OUT_SINK Because the device does not sink and source current at the same time and the I OUT current may vary rapidly with time, the actual power dissipation should be the time average of the above dissipations over the thermal relaxation duration of the system. Another source of power consumption is the current used for the internal current control circuitry form VCNTL supply and the VIN supply. This can be estimate as 10mW or less during normal operating conditions. The power must be effectively dissipated from the package. Maximum power dissipation allowed by the package is calculated by below equation. P PKG = [ T J(MAX) – T A(MAX) ] / θ JA , where z T J(MAX) is +125°C z T A(MAX) is the maximum ambient temperature in the system z θ JA is the thermal resistance form junction to ambient 6.7 Input Capacitor Depending on the trace impedance between the VIN bulk power supply to the device, a transient increase of source current is supplied mostly by the charge from the VIN input capacitor. Use a 100uF (or greater) capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is used at VOUT. 6.8 Output Capacitor For stable operation, the total capacitance of the VOUT terminal must be greater than 100uF. Attach two or more capacitors in parallel to minimize the effect of equivalent series resistance (ESR) and equivalent series inductance (ESL). 6.9 Layout Consideration Consider the following points before starting the W83312SN layout design. Fig. 6-4 shows the suggestion of minimum land pattern. Fig. 6-5 shows the recommended PCB layout. Using “dog bone” copper patterns on the top layer can increase efficiency of heat dissipating. z The input bypass capacitor for VIN should be placed as close as possible to the pin with short and wide connections. z The output capacitor for VOUT should be placed close to the pin with short and wide connection in order to avoid ESR and/or ESL trace inductance. z In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directly to the package’s thermal pad. The wide traces of component and the side copper connected to the thermal land pad help to dissipate heat. The thermal land connected to the ground plane could also be used to help dissipation. -6- Publication Date: Mar., 2010 Revision A5 W83312SN 75 VCNTL Ground C CNTL For heat dissipatin 130 219 Ground 95 Unit: mil (Not to scale) C IN C OUT VIN VOUT 24 50 Fig. 6-4 7. 7.1 Fig. 6-5 ELECTRICAL CHARACTERISTIC Absolute Maximum Ratings (Note1) RATING UNIT Input Voltage ITEM VIN SYMBOL -0.3 to 7 V Control Logic Input Voltage VCNTL -0.3 to 7 V Reference Voltage VREF -0.3 to 5 V ±2 kV Machine Mode ±200 V Latch-Up ±100 mA -65 to 150 °C Human Body Mode Electrostatic discharge protection (Note2) Storage Temperature Range 7.2 Thermal Information ITEM Power Dissipation, P D @ T A =25°C RATING UNIT Internal Limited W 75 °C/W Package Thermal Resistance, ESOP8, θ JA 7.3 Recommended Operating Conditions ITEM SYMBOL MIN MAX 1.2 5.5 3 5.5 0.6 3.3 Sourcing 0 2.5 Sinking 0 2.5 Sourcing 0 3.0 Sinking 0 3.0 VIN Input Voltage VCNTL VREF Continuous Output Current Peak Output Current -7- UNIT V V A A Publication Date: Mar., 2010 Revision A5 W83312SN Operating Temperature Range Junction Temperature Range (Note3) -40 85 °C -40 125 °C Electrical Characteristics 7.4 Typicals and limits appearing in normal type apply for Tj = 25°C. Limits appearing in Boldface type apply over the entire junction temperature range for operation, -40 ° C to 85 ° C (Note4). VCNTL= 3.3V/5V, VIN=2.5V/1.8V/1.5V, VREF=1.25V/0.9V/0.75V, C OUT =100uF, all voltage outputs unloaded (unless otherwise noted). PARAMETER SYMBOL TEST CONDITION MIN TYP MAX I OUT =0A, VCNTL=3.3V 0.5 0.7 I OUT =0A, VCNTL=5V 0.7 1 I OUT =0A, VCNTL=3.3V 0.3 0.5 I OUT =0A, VCNTL=5V 0.3 0.5 VREF < 0.2V, VCNTL=3.3V 60 90 VREF < 0.2V, VCNTL=5V 60 90 UNITS Input VCNTL Operating Current VIN Operating Current VCNTL Quiescent Current in Shutdown Mode VIN Quiescent Current in Shutdown Mode VREF Leakage Current I CNTL I VIN I SD_CNTL mA mA uA I SD_VIN VREF < 0.2V -1 0 1 uA I IH VREF=3.3V -1 0 1 I IL VREF=0V -1 0 1 I OUT =0A -5 5 I OUT =0 → +2.5A (Note5) -20 20 I OUT =0 → -2.5A (Note5) -20 20 In any VIN ±3 ±3.5 ±4.5 A 150 165 175 °C uA Output (DDR1 / DDR2 / DDR3) Output Offset Voltage (VREFVOUT) V OS Load Regulation (VREF-VOUT) ∆V L mV mV Protection Current Limit Thermal Shutdown Temperature Thermal Shutdown Hysteresis I LIM T SD 3.3V < VCNTL < 5V ∆T SD 3.3V < VCNTL < 5V (Note6) °C 30 VREF Shutdown Mode Shutdown Threshold V IH Enable V IL Disable 0.6 V 0.2 Note1. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Note2. Devices are ESD sensitive. Handling precaution recommended. Note3. At elevated temperatures, devices must be de-rated based on thermal resistance. The device in the ESOP-8 package must be de-rated at θ JA =75˚C/W junction to ambient with minimum PCB footprint. -8- Publication Date: Mar., 2010 Revision A5 W83312SN Note4. Limits are 100% production tested at 25˚C. Limits over operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate average outgoing quality level. Note5. VOUT load regulation is tested by using a 10ms period and 50% duty cycle current pulse. Note6. The maximum allowable power dissipation is a function of the maximum junction temperature, T J(MAX) , the junction to ambient thermal resistance, θ JA , and the ambient temperature, T A . exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal shutdown. Ensured by design, no production tested. 8. TYPICAL OPERATING WAVEFORMS VIN=2.5V, VCNTL=3.3V, VOUT=1.25V @ 3A Sourcing VIN=2.5V, VCNTL=5V, VOUT=1.25V @ 3A Sourcing VIN=2.5V, VCNTL=3.3V, VOUT=1.25V @ 2.5A Sourcing VIN=2.5V, VCNTL=5V, VOUT=1.25V @ 2.5A Sourcing -9- Publication Date: Mar., 2010 Revision A5 W83312SN VIN=1.8V, VCNTL=3.3V, VOUT=0.9V @ 3A Sourcing VIN=1.8V, VCNTL=3.3V, VOUT=0.9V @ 2.5A Sourcing VIN=1.8V, VCNTL=5V, VOUT=0.9V @ 3A Sourcing VIN=1.8V, VCNTL=5V, VOUT=0.9V @ 2.5A Sourcing VIN=1.5V, VCNTL=3.3V, VOUT=0.75V @ 3A Sourcing VIN=1.5V, VCNTL=3.3V, VOUT=0.75V @ 2.5A Sourcing -10- Publication Date: Mar., 2010 Revision A5 W83312SN VIN=1.5V, VCNTL=5V, VOUT=0.75V @ 3A Sourcing VIN=1.2V, VCNTL=3.3V, VOUT=0.6V @ 3A Sourcing VIN=1.5V, VCNTL=5V, VOUT=0.75V @ 2.5A Sourcing VIN=1.2V, VCNTL=3.3V, VOUT=0.6V @ 2.5A Sourcing -11- Publication Date: Mar., 2010 Revision A5 W83312SN VIN=1.2V, VCNTL=5V, VOUT=0.6V @ 3A Sourcing VIN=1.2V, VCNTL=5V, VOUT=0.6V @ 2.5A Sourcing VIN=2.5V, VCNTL=3.3V, VOUT=1.25V @ 3A Sinking VIN=2.5V, VCNTL=3.3V, VOUT=1.25V @ 2.5A Sinking VIN=2.5V, VCNTL=5V, VOUT=1.25V @ 3A Sinking VIN=2.5V, VCNTL=5V, VOUT=1.25V @ 2.5A Sinking -12- Publication Date: Mar., 2010 Revision A5 W83312SN VIN=1.8V, VCNT3O.9V @ 3A Sinking VIN=1.8V, VCNTL=5V, VOUT=0.9V @ 3A Sinking VIN=1.5V, VCNTL=3.3V, VOUT=0.75V @ 3A Sinking VIN=1.8V, VCNTL=3.3V, VOUT=0.9V @ 2.5A Sinking VIN=1.8V, VCNTL=5V, VOUT=0.9V @ 2.5A Sinking VIN=1.5V, VCNTL=3.3V, VOUT=0.75V @ 2.5A Sinking -13- Publication Date: Mar., 2010 Revision A5 W83312SN VIN=1.5V, VCNTL=5V, VOUT=0.75V @ 3A Sinking VIN=1.5V, VCNTL=5V, VOUT=0.75V @ 2.5A Sinking VIN=1.2V, VCNTL=3.3V, VOUT=0.6V @ 3A Sinking VIN=1.2V, VCNTL=3.3V, VOUT=0.6V @ 2.5A Sinking VIN=1.2V, VCNTL=5V, VOUT=0.6V @ 3A Sinking VIN=1.2V, VCNTL=5V, VOUT=0.6V @ 2.5A Sinking -14- Publication Date: Mar., 2010 Revision A5 W83312SN VIN=2.5V, VCNTL=3.3V, VOUT=1.25V, VOUT short to GND VIN=2.5V, VCNTL=5V, VOUT=1.25V, VOUT short to GND VIN=2.5V, VCNTL=3.3V, VOUT=1.25V, VOUT short to VIN VIN=2.5V, VCNTL=5V, VOUT=1.25V, VOUT short to VIN -15- Publication Date: Mar., 2010 Revision A5 W83312SN VIN=1.8V, VCNTL=3.3V, VOUT=0.9V, VOUT short to GND VIN=1.8V, VCNTL=5V, VOUT=0.9V, VOUT short to GND VIN=1.8V, VCNTL=3.3V, VOUT=0.9V, VOUT short to VIN VIN=1.8V, VCNTL=5V, VOUT=0.9V, VOUT short to VIN VIN=1.5V, VCNTL=3.3V, VOUT=0.75V, VOUT short to GND VIN=1.5V, VCNTL=5V, VOUT=0.75V, VOUT short to GND -16- Publication Date: Mar., 2010 Revision A5 W83312SN VIN=1.5V, VCNTL=3.3V, VOUT=0.75V, VOUT short to VIN VIN=1.5V, VCNTL=5V, VOUT=0.75V, VOUT short to VIN VIN=1.2V, VCNTL=3.3V, VOUT=0.6V, VOUT short to GND VIN=1.2V, VCNTL=5V, VOUT=0.6V, VOUT short to GND VIN=1.2V, VCNTL=3.3V, VOUT=0.6V, VOUT short to VIN VIN=1.2V, VCNTL=5V, VOUT=0.6V, VOUT short to VIN -17- Publication Date: Mar., 2010 Revision A5 W83312SN VCNTL Current vs. Temperature 590 570 570 550 550 VCNTL Current (uA) VCNTL Current (uA) VCNTL Current vs. Temperature 590 530 510 490 470 450 DDR1 @ VCNTL=3.3V DDR1 @ VCNTL=5V 430 -20 0 20 40 60 510 490 470 450 DDR2 @ VCNTL=3.3V DDR2 @ VCNTL=5V 430 410 -40 530 80 100 120 410 -40 -20 0 Temperature (°C) 590 570 570 550 550 530 510 490 470 DDR3 @ VCNTL=3.3V 430 410 -20 0 20 40 60 60 80 100 120 530 510 490 470 450 430 DDR3 @ VCNTL=5V -40 40 VCNTL Current vs. Temperature VCNTL Current (uA) VCNTL Current (uA) VCNTL Current vs. Temperature 590 450 20 Temperature (°C) 80 100 120 Temperature (°C) -18- LP DDR @ VCNTL=3.3V LP DDR @ VCNTL=5V 410 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 Publication Date: Mar., 2010 Revision A5 W83312SN VIN Current vs. Temperature VIN Current vs. Temperature 220 320 DDR1 @ VCNTL=3.3V DDR1 @ VCNTL=5V 280 260 240 220 DDR2 @ VCNTL=3.3V DDR2 @ VCNTL=5V 210 VIN Current (uA) VIN Current (uA) 300 200 200 190 180 170 160 180 -40 -20 0 20 40 60 80 150 100 120 -40 Temperature (°C) VIN Current vs. Temperature 0 20 40 60 80 Temperature (°C) 100 120 VIN Current vs. Temperature 160 190 DDR3 @ VCNTL=3.3V DDR3 @ VCNTL=5V 150 VIN Current (uA) 180 VIN Current (uA) -20 170 160 150 140 130 120 140 130 -40 -20 0 20 40 60 80 LP DDR @ VCNTL=3.3V LP DDR @ VCNTL=5V 110 100 120 -40 -20 0 Temperature (°C) Turn On/Off Threshold vs. Temperature 20 40 60 80 Temperature (°C) 100 120 VCNTL Shutdown Current vs. Temperature 0.5 70 0.45 Voltage (V) 0.3 0.25 0.2 Turn On @ VCNTL=3.3V Turn On @ VCNTL=5V Turn Off @ VCNTL=3.3V Turn Off @ VCNTL=5V 0.15 0.1 0.05 VCNTL Current (uA) 0.4 0.35 65 60 55 VCNTL=3.3V 50 VCNTL=5V 0 45 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 -40 -19- -20 0 20 40 60 80 Temperature (°C) 100 120 Publication Date: Mar., 2010 Revision A5 W83312SN DDR1 Current Limit vs. Temperature 5 Source @ VCNTL=3.3V Source @ VCNTL=5V Sink @ VCNTL=3.3V Sink @ VCNTL=5V 4 Source @ VCNTL=3.3V Source @ VCNTL=5V Sink @ VCNTL=3.3V Sink @ VCNTL=5V 4.5 Current (A) 4.5 Current (A) DDR2 Current Limit vs. Temperature 5 3.5 3 4 3.5 3 2.5 2.5 2 2 -40 -20 0 20 40 60 80 -40 -20 100 120 0 Temperature (°C) 5 5 Source @ VCNTL=3.3V Source @ VCNTL=5V Sink @ VCNTL=3.3V Sink @ VCNTL=5V 4.5 Current (A) Current (A) 4 40 60 80 100 120 LP DDR Current Limit vs. Temperature DDR3 Current Limit vs. Temperature 4.5 20 Temperature (°C) 3.5 3 4 Source @ VCNTL=3.3V Source @ VCNTL=5V Sink @ VCNTL=3.3V Sink @ VCNTL=5V 3.5 3 2.5 2.5 2 2 -40 -20 0 20 40 60 80 -40 -20 100 120 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) -20- Publication Date: Mar., 2010 Revision A5 W83312SN Normalized VOFFSET vs. Temperature 5.00 4.00 3.00 VOFFSET (mV) VOFFSET (mV) Normalized VOFFSET vs. Temperature 5.00 4.00 3.00 2.00 1.00 0.00 -1.00 -2.00 -3.00 -4.00 -5.00 DDR1 @ VCNTL=3.3V DDR1 @ VCNTL=5V -40 -20 0 20 40 60 80 2.00 1.00 0.00 -1.00 -2.00 -3.00 DDR2 @ VCNTL=3.3V DDR2 @ VCNTL=5V -4.00 -5.00 100 120 -40 Temperature (°C) 20 40 60 80 100 120 Normalized VOFFSET vs. Temperature 5.00 4.00 VOFFSET (mV) VOFFSET (mV) 0 Temperature (°C) Normalized VOFFSET vs. Temperature 5.00 4.00 3.00 2.00 1.00 0.00 -1.00 -2.00 -3.00 -4.00 -5.00 -20 DDR3 @ VCNTL=3.3V DDR3 @ VCNTL=5V -40 -20 0 20 40 60 80 3.00 2.00 1.00 0.00 -1.00 -2.00 -3.00 LP DDR @ VCNTL=3.3V LP DDR @ VCNTL=5V -4.00 -5.00 100 120 -40 -20 Temperature (°C) -21- 0 20 40 60 80 100 120 Temperature (°C) Publication Date: Mar., 2010 Revision A5 W83312SN 9. PACKAGE DIMENSION SOP8-EP (150mil) -22- Publication Date: Mar., 2010 Revision A5 W83312SN ¾ TAPING SPECIFICATION Note: W83312SN L/F size is D1-3 & E1-3 dimension SOP8-EP Package 10. ORDERING INFORMATION Part Number Supplied as Production Flow T Shape: 2,500 units/T&R Commercial, -40°C to +85°C Package Type W83312SN 8PIN SOP8-EP (Green Package) 11. TOP MARKING SPECIFICATION W83312SN 752ABBX 1st Line: Nuvoton logo 2nd Line: W83312SN (Part number) 3rd line: Tracking code z 752: packages assembled in Year 2007, week 52 z A: assembly house ID z BB: Internal use only z X: the IC version (A means A; B means B & C means C…etc.) -23- Publication Date: Mar., 2010 Revision A5 W83312SN 12. REVISION HISTORY VERSION DATE PAGE A1 11/28/2008 All A2 12/29/2008 4, 5, 7 DESCRIPTION New Create Update the linear regulator chart & VIN Recommended Range 1. Updated operating temperature range A3 8/1/2009 All 2. Updated 6.2 General Regulator 3. Updated Typical Operating Waveforms A4 1/29/2010 6 A5 3/31/2010 6,20 Correct Typo, add PCB Layout Suggestion 1. Add suggestion land pattern 2. Update the SOP8-EP package outline Important Notice Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. -24- Publication Date: Mar., 2010 Revision A5