Data Sheet
ADA4098-1/ADA4098-2
50 V, 1 MHz, 165 µA per Channel, Robust, Over-The-Top, Precision Op Amps
FEATURES
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GENERAL DESCRIPTION
Ultrawide common-mode input range: −VS − 0.1 V to −VS + 70 V
Wide power supply voltage range: +3 V to +50 V (to ±25 V for
PSRR)
Low power supply current: 165 µA per channel (typical)
Low input offset voltage: ±35 µV maximum
Low input offset voltage drift: ±0.5 µV/°C maximum (B grade)
Low input voltage noise
► 1/f noise corner: 6 Hz typical
► 400 nV p-p typical at 0.1 Hz to 10 Hz
► 17 nV/√Hz typical at 100 Hz
High speed
► GBP: 1.05 MHz typical for fTEST = 2.5 kHz
► Slew rate: 0.85 V/µs typical at ΔVOUT = 25 V
Low power supply current shutdown: 20 µA maximum
Low input offset current: ±700 pA maximum
Large signal voltage gain: 126 dB minimum for ΔVOUT = 3.5 V
CMRR: 120 dB minimum at VCM = −0.1 V to +70 V
PSRR: 123 dB minimum at VSY = +3 V to ±25 V
Input overdrive tolerant with no phase reversal
±3 kV HBM and ±1.25 kV FICDM
Wide temperature range: −55°C to +150°C (H grade)
The ADA4098-1 and ADA4098-2 are single/dual robust, precision,
rail-to-rail input and output operational amplifiers (op amps) with
inputs that operate from −VS to +VS and beyond, which is referred
to in this data sheet as Over-The-Top™. The devices feature offset
voltages of 5 V
f = 100 Hz
f = 100 Hz, VCM > 5 V
H Grade
±0.05
Typ
Max
Unit
±35
±90
±15
±35
±100
µV
µV
±40
±200
±135
±40
±200
±200
±0.5
±0.7
±10
12
14.8
1
±20
±20
±40
±200
±135
±40
±200
±250
±0.8
±0.7
±25
12
15
1
µV
µV
µV
µV
µV
µV
µV/°C
nA
nA
µA
µA
µA
10
±700
±15
±0.15
±0.2
µA
pA
nA
µA
µA
dB
+70
400
6
17
20
0.15
1.8
±0.1
±0.35
3.5
1.5
8
0.001
±350
±0.05
120
134
122
±20
±20
10
±700
±5
±0.15
±0.2
140
150
Min
109
116
110
−0.1
126
120
112
106
140
134
+70
150
122
400
6
17
20
0.15
1.8
dB
dB
dB
V
dB
dB
dB
dB
nV p-p
Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
Rev. A | 3 of 33
Data Sheet
ADA4098-1/ADA4098-2
SPECIFICATIONS
Table 1.
B Grade
Parameter
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product (GBP)
Phase Margin
1% Settling Time
0.1% Settling Time
Total Harmonic Distortion Plus
Noise (THD + N)
Channel Separation
INPUT CHARACTERISTICS
Input Resistance
Over-The-Top
Input Capacitance
SHDN AND SHDNx PINS
Input Logic Low
Input Logic High
Response Time
Pull-Down Current
OUTPUT CHARACTERISTICS
Output Voltage Swing Low
Output Voltage Swing High
Short-Circuit Current
Output Pin Leakage During
Shutdown
Test Conditions/Comments
Min
Typ
ΔVOUT = 2 V
TMIN < TA < TMAX
Test frequency (fTEST) = 2.5 kHz
TMIN < TA < TMAX
0.15
0.1
0.9
0.9
0.4
ΔVOUT = ±2 V
ΔVOUT = ±2 V
f = 10 kHz, VOUT = 1 V p-p, RL =
10 kΩ, bandwidth = 80 kHz
f = 1 kHz, RL = 2 kΩ
Differential mode
Common mode
Differential mode, VCM > 5 V
Common mode, VCM > 5 V
Differential mode
Common mode
Amplifier active, SHDN and SHDNx
pin voltage (VSHDN) < −VS + 0.5 V,
TMIN < TA < TMAX
Amplifier shutdown, VSHDN > −VS +
1.5 V, TMIN < TA < TMAX
Amplifier active to shutdown
Amplifier shutdown to active
VSHDN = −VS + 0.5 V, TMIN < TA <
TMAX
VSHDN = −VS + 1.5 V, TMIN < TA <
TMAX
Overdrive voltage (VOD)4 = 30 mV, no
load
TMIN < TA < TMAX
VOD = 30 mV, sink current (ISINK) =
10 mA
TMIN < TA < TMAX
VOD = 30 mV, no load
TMIN < TA < TMAX
VOD = 30 mV, source current
(ISOURCE) = 10 mA
TMIN < TA < TMAX
ISOURCE
TMIN< TA < TMAX
ISINK
TMIN < TA < TMAX
VSHDN = −VS + 1.5 V
TMIN < TA < TMAX
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H Grade
Max
Min
Typ
0.15
0.1
0.9
0.9
0.4
Unit
55
14
18
0.01
55
14
18
0.01
V/µs
V/µs
MHz
MHz
Degrees
µs
µs
%
115
115
dB
1
>1
7
>250
1
3
1
>1
7
>250
1
3
MΩ
GΩ
kΩ
MΩ
pF
pF
1.05
1.05
−VS + 0.5
−VS + 1.5
−VS + 0.5
−VS + 1.5
2.5
30
0.6
V
V
3
2.5
30
0.6
3
µs
µs
µA
0.3
2.5
0.3
2.5
µA
20
45
20
45
mV
260
50
360
260
55
360
mV
mV
450
15
30
1100
mV
mV
mV
mV
1650
±100
mV
mA
mA
mA
mA
nA
±10
µA
2.5
900
435
15
25
1100
2.5
900
1500
24
15
35
25
Max
40
24
12
35
20
50
±0.01
±100
±10
40
50
±0.01
Rev. A | 4 of 33
Data Sheet
ADA4098-1/ADA4098-2
SPECIFICATIONS
Table 1.
B Grade
Parameter
POWER SUPPLY
Maximum Operating Voltage5
VSY Range
Supply Current per Channel
PSRR
THERMAL SHUTDOWN6
Temperature
Hysteresis
Operating Temperature
Test Conditions/Comments
Min
Guaranteed by Power Supply
Rejection Ratio (PSRR)
Amplifier active
TMIN < TA < TMAX
Amplifier shutdown, VSHDN = −VS +
1.5 V
TMIN < TA < TMAX
VSY = +3 V to ±25 V
TMIN < TA < TMAX
Typ
H Grade
Max
50
50
3
165
12
Min
Typ
3
175
242
20
165
12
22.5
123
120
145
Junction temperature (TJ)
123
120
175
20
TA
−40
Max
Unit
50
50
V
V
175
250
20
µA
µA
µA
22.5
µA
dB
dB
145
175
20
+125
−55
+150
°C
°C
°C
1
Thermoelectric voltages present in the high speed production test limit the measurement accuracy of this parameter. The limits shown in Table 1 are determined by test
capability and are not necessarily indicative of actual device performance.
2
Offset voltage drift is guaranteed through lab characterization and is not production tested.
3
Test accuracy is limited by high speed production test equipment repeatability. Bench measurements indicate that the input offset current in Over-The-Top configuration is
typically controlled to under 50 nA at +25°C and 100 nA over the −55°C < TA < +150°C temperature range.
4
VOD is +30 mV for VOUT high and −30 mV for VOUT low.
5
Maximum operating voltage is limited by the time-dependent dielectric breakdown (TDDB) of the on-chip capacitor oxides. The amplifiers tolerate temporary transient
overshoot up to the specified absolute maximum rating, but the dc supply voltage must be limited to the maximum operating voltage.
6
Thermal shutdown is lab characterized only and is not tested in production.
±15 V SUPPLY
VCM = 0 V, SHDN pin (ADA4098-1) and SHDNx pins (ADA4098-2 10-lead LFCSP) are open, RL = 499 kΩ to ground, and TA = 25°C, unless
otherwise noted.
Table 2.
B Grade
Parameter
Test Conditions/Comments
DC PERFORMANCE
VOS1
Input Offset Voltage Drift2
Input Bias Current (IB)
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
TMIN < TA < TMAX
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
IOS
Typ
Max
±15
±40
±90
±40
±90
±0.5
±0.7
±10
±0.7
±10
±0.7
±5
±0.7
±5
±15
±0.1
±0.35
±0.35
±0.35
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
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Min
H Grade
±0.35
Min
Typ
Max
Unit
±15
±40
±100
±40
±100
±0.8
±0.7
±25
±0.7
±25
±0.7
±15
±0.7
±15
µV
µV
µV
µV
µV/°C
nA
nA
nA
nA
nA
nA
nA
nA
±15
±0.1
±0.35
±0.35
±0.35
±0.35
Rev. A | 5 of 33
Data Sheet
ADA4098-1/ADA4098-2
SPECIFICATIONS
Table 2.
B Grade
Parameter
Test Conditions/Comments
Min
Typ
CMRR
VCM = −14.75 V to +13.25 V
TMIN < TA < TMAX
VCM = −15.1 V to +13.25 V
TMIN < TA < TMAX
VCM = −15.1 V to +55 V
TMIN < TA < TMAX
Guaranteed by CMRR tests
ΔVOUT = 25 V
TMIN < TA < TMAX
ΔVOUT = 25 V, RL = 10 kΩ
TMIN < TA < TMAX
118
116
117
102
120
110
−15.1
134
126
117
108
135
Common-Mode Input Range
AOL
NOISE PERFORMANCE
Input Voltage Noise
Over-The-Top
Input Current Noise
Over-The-Top
DYNAMIC PERFORMANCE
Slew Rate
GBP
Phase Margin
1% Settling Time
0.1% Settling Time
THD + N
Channel Separation
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
SHDN AND SHDNx PINS
Input Logic Low
Input Logic High
Response Time
Pull-Down Current
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f = 0.1 Hz to 10 Hz
1/f noise corner
f = 100 Hz
f = 100 Hz, VCM > +VS
f = 100 Hz
f = 100 Hz, VCM > +VS
ΔVOUT = 25 V
TMIN < TA < TMAX
fTEST = 2.5 kHz
TMIN < TA < TMAX
H Grade
Max
135
140
+55
150
120
Min
Typ
118
116
117
100
120
108
−15.1
134
123
117
106
135
400
6
17
20
0.15
1.8
0.35
0.2
0.9
0.9
ΔVOUT = ±2 V
ΔVOUT = ±2 V
f = 10 kHz, VOUT = 1 V p-p, RL =
10 kΩ, bandwidth = 80 kHz
f = 1 kHz, RL = 2 kΩ
Differential mode
Common mode
Differential mode
Common mode
Amplifier active, VSHDN < −VS + 0.5
V
Amplifier shutdown, VSHDN > −VS + −VS + 1.5
1.5 V
Amplifier active to shutdown
Amplifier shutdown to active
VSHDN = −VS + 0.5 V, TMIN < TA <
TMAX
VSHDN = −VS + 1.5 V, TMIN < TA <
TMAX
0.85
0.35
0.2
0.9
0.9
Max
Unit
dB
dB
dB
dB
dB
dB
V
dB
dB
dB
dB
135
140
+55
150
120
400
6
17
20
0.15
1.8
nV p-p
Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
0.85
57
14
18
0.01
57
14
18
0.01
V/µs
V/µs
MHz
MHz
Degrees
µs
µs
%
115
115
dB
1
>1
1
3
1
>1
1
3
MΩ
GΩ
pF
pF
1.05
1.05
−VS + 0.5
−VS + 0.5
−VS + 1.5
2.5
30
0.6
0.3
V
V
3
2.5
30
0.6
3
µs
µs
µA
2.5
0.3
2.5
µA
Rev. A | 6 of 33
Data Sheet
ADA4098-1/ADA4098-2
SPECIFICATIONS
Table 2.
B Grade
Parameter
OUTPUT CHARACTERISTICS
Output Voltage Swing Low
Output Voltage Swing High
Short-Circuit Current
POWER SUPPLY
Maximum Operating Voltage4
VSY Range
Supply Current per Channel
PSRR
THERMAL SHUTDOWN5
Temperature
Hysteresis
Operating Temperature
Test Conditions/Comments
VOD3 = 30 mV, no load
TMIN < TA < TMAX
VOD = 30 mV, ISINK = 10 mA
TMIN < TA < TMAX
VOD = 30 mV, no load
TMIN < TA < TMAX
VOD = 30 mV, ISOURCE = 10 mA
TMIN < TA < TMAX
ISOURCE
TMIN < TA < TMAX
ISINK
TMIN < TA < TMAX
Min
20
45
50
360
435
15
25
1100
1500
2.5
900
Guaranteed by PSRR
3
Amplifier active
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
Amplifier shutdown, VSHDN = −VS +
1.5 V
TMIN < TA < TMAX
VSY = 3 V to 50 V
123
TMIN < TA < TMAX
120
TJ
TA
Max
260
24
15
35
20
H Grade
Typ
34
195
17
50
50
205
272
215
292
24
Typ
Max
Unit
20
45
55
360
450
15
30
1100
1650
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
mA
mA
50
50
205
295
215
315
24
V
V
µA
µA
µA
µA
µA
27
µA
dB
dB
260
2.5
900
24
12
35
20
50
185
Min
34
50
3
185
195
17
27
145
123
120
175
20
−40
145
175
20
+125
−55
+150
°C
°C
°C
1
Thermoelectric voltages present in the high speed production test limit the measurement accuracy of this parameter. The limits shown in Table 2 are determined by test
capability and are not necessarily indicative of actual device performance.
2
Offset voltage drift is guaranteed through lab characterization and is not production tested.
3
VOD is +30 mV for VOUT high and −30 mV for VOUT low.
4
Maximum operating voltage is limited by the TDDB of the on-chip capacitor oxides. The amplifiers tolerate temporary transient overshoot up to the specified absolute
maximum rating and the dc supply voltage must be limited to the maximum operating voltage.
5
Thermal shutdown is lab characterized only and is not tested in production.
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Rev. A | 7 of 33
Data Sheet
ADA4098-1/ADA4098-2
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage1
Transient
Continuous
Power Dissipation (PD)
Differential Input Voltage
±IN Pin Voltage
Continuous
Survival
±IN Pin Current
SHDN and SHDNx Pin Voltage 2
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
TJ
Rating
60 V
50 V
See Figure 3
±80 V
−10 V to +80 V
−20 V to +80 V
15 mA
−0.3 V to +60 V
−65°C to +150°C
−55°C to +150°C
300°C
175°C
1
Maximum supply voltage is limited by the TDDB of the on-chip capacitor oxides. The amplifiers tolerate temporary transient overshoot up to the specified
transient maximum rating. The continuous operating supply voltage must be
limited to no more than 50 V.
2
SHDN is Pin 5 on the ADA4098-1. SHDNx refers to SHDN1 and SHDN2 (Pin 5
and Pin 6, respectively) on the ADA4098-2 (10-lead LFCSP).
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating
only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
Junction temperatures (TJ) exceeding 125°C promotes accelerated
aging. The ADA4098-1 and ADA4098-2 demonstrate ±25 V supply
operation beyond 1000 hours at TA = 150°C.
MAXIMUM POWER DISSIPATION
The maximum safe PD on the devices is limited by the associated
rise in either case temperature (TC) or TJ on the die. At approximately TC = 150°C, which is the glass transition temperature, the
properties of the plastic changes. Exceeding this temperature limit,
even temporarily, may change the stresses that the package exerts
on the die, which permanently shifts the parametric performance
of the ADA4098-1 and ADA4098-2. Exceeding TJ = 175°C for an
extended period may result in changes in the silicon devices and
may potentially cause failure of the devices.
The PD on the package is the sum of the quiescent power dissipation and the power dissipated in the package due to the output load
drive. The quiescent power is expressed as VSY × ISY, where ISY is
the quiescent current.
the associated voltage drop across the devices. RMS voltages and
currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA. Additional metal that is directly in contact with the package leads from
metal traces through vias, ground, and power planes reduces θJA.
Figure 3 shows the maximum PD vs. TA for the single and dual
6-lead TSOT packages on a JEDEC standard, 4‑layer board, with
−VS connected to a pad that is thermally connected to a printed
circuit board (PCB) plane. θJA values are approximations.
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and operating
environment. Careful attention to PCB thermal design is required.
θJA is the junction to ambient thermal resistance.
Table 4. Thermal Resistance
Package Type
θJA
Unit
UJ-6
R-8
RM-8
05-08-1699
192
120
163
43
°C/W
°C/W
°C/W
°C/W
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Field induced charged device model (FICDM) per ANSI/ESDA/JEDEC JS-002.
The PD due to the load drive depends on the application. The PD
due to load drive is calculated by multiplying the load current by
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Rev. A | 8 of 33
Data Sheet
ADA4098-1/ADA4098-2
ABSOLUTE MAXIMUM RATINGS
ESD CAUTION
ESD Ratings for ADA4098-1/ADA4098-2
Table 5. ADA4098-1 6-Lead TSOT, ADA4098-2 8-Lead SOIC_N, ADA4098-2
8-Lead MSOP, ADA4098-2 10-Lead LFCSP
ESD Model
Withstand Threshold (kV)
Class
HBM
FICDM
±3
±1.25
2
3
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ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Rev. A | 9 of 33
Data Sheet
ADA4098-1/ADA4098-2
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration for ADA4098-1 6-Lead TSOT
Table 6. Pin Function Descriptions for ADA4098-1 6-Lead TSOT
Pin No.
Mnemonic
Description
1
2
VOUT
−VS
3
4
5
+IN
−IN
SHDN
6
+VS
Amplifier Output.
Negative Power Supply. In single-supply applications, the −VS pin is normally soldered to a low impedance ground plane. In split-supply
applications, bypass the −VS pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the −VS pin as possible.
Noninverting Input of the Amplifier.
Inverting Input of the Amplifier.
Op Amp Shutdown. The threshold for shutdown is approximately 1 V above the negative supply. If the SHDN pin is hard tied to the −VS pin
or floating, the amplifier is active. If the SHDN pin is asserted high (VSHDN > −VS + 1.5 V), the amplifier is placed in a shutdown state, and the
output of the amplifier goes to a high impedance state. If the SHDN pin is left floating, it is recommended to connect a small capacitor of 1 nF
between the SHDN pin and the −VS pin to prevent signals from the −IN pin from capacitively coupling to the SHDN pin.
Positive Power Supply. Bypass the +VS pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the +VS pin as
possible.
Figure 5. Pin Configuration for ADA4098-2 8-Lead SOIC_N and 8-Lead MSOP
Table 7. Pin Function Descriptions for ADA4098-2 8-Lead SOIC_N and 8-Lead MSOP
Pin No.
Mnemonic
Description
1
VOUT1
Amplifier Output, Channel 1.
2
−IN1
Inverting Input of the Amplifier, Channel 1.
3
+IN1
Noninverting Input of the Amplifier, Channel 1.
4
−VS
Negative Power Supply. In single-supply applications, the −VS pin is normally soldered to a low impedance ground plane. In
split-supply applications, bypass the −VS pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the
−VS pin as possible.
5
−IN2
Inverting Input of the Amplifier, Channel 2.
6
+IN2
Noninverting Input of the Amplifier, Channel 2.
7
VOUT2
Amplifier Output, Channel 2.
8
+VS
Positive Power Supply. Bypass the +VS pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the
+VS pin as possible.
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Rev. A | 10 of 33
Data Sheet
ADA4098-1/ADA4098-2
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 6. Pin Configuration for ADA4098-2 10-Lead LFCSP
Table 8. Pin Function Descriptions for ADA4098-2 10-Lead LFCSP
Pin No.
Mnemonic
Description
1
2
3
4
VOUT1
−IN1
+IN1
−VS
5
SHDN1
6
SHDN2
7
8
9
10
−IN2
+IN2
VOUT2
+VS
Amplifier Output, Channel 1.
Inverting Input of the Amplifier, Channel 1.
Noninverting Input of the Amplifier, Channel 1.
Negative Power Supply. In single-supply applications, the −VS pin is normally soldered to a low impedance ground plane. In
split-supply applications, bypass the −VS pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the
−VS pin as possible.
Op Amp Shutdown, Channel 1. The threshold for shutdown is approximately 1 V above the negative supply. If the SHDN1 pin is
hard tied to the −VS pin or floating, the amplifier is active. If the SHDN1 pin is asserted high (VSHDN > −VS + 1.5 V), the amplifier
is placed in a shutdown state, and the output of the amplifier goes to a high impedance state. If the SHDN1 pin is left floating, it is
recommended to connect a small capacitor of 1 nF between the SHDN1 pin and the −VS pin to prevent signals from the −INx pins
from capacitively coupling to the SHDN1 pin.
Op Amp Shutdown, Channel 2. The threshold for shutdown is approximately 1 V above the negative supply. If the SHDN2 pin is
hard tied to the −VS pin or floating, the amplifier is active. If the SHDN2 pin is asserted high (VSHDN > −VS + 1.5 V), the amplifier
is placed in a shutdown state, and the output of the amplifier goes to a high impedance state. If the SHDN2 pin is left floating, it is
recommended to connect a small capacitor of 1 nF between the SHDN2 pin and the −VS pin to prevent signals from the −INx pins
from capacitively coupling to the SHDN2 pin.
Inverting Input of the Amplifier, Channel 2.
Noninverting Input of the Amplifier, Channel 2.
Amplifier Output, Channel 2.
Positive Power Supply. Bypass the +VS pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the
+VS pin as possible.
Exposed Pad. Connect the exposed pad to −VS.
EPAD
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Rev. A | 11 of 33
Data Sheet
ADA4098-1/ADA4098-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. Supply Current vs. Supply Voltage
Figure 10. Shutdown Supply Current vs. Supply Voltage
Figure 8. Supply Current vs. Temperature Across Various Supply Voltages
Figure 11. Typical Distribution of Input Offset Voltage, VSY = 5 V
Figure 9. Supply Current vs. VSHDN with Respect to −VS
Figure 12. Typical Distribution of Input Offset Voltage with VSY = ±15 V
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Rev. A | 12 of 33
Data Sheet
ADA4098-1/ADA4098-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 13. Typical Distribution of Input Offset Voltage with VSY = ±25 V
Figure 16. Midsupply Offset Voltage vs. Temperature with VSY = ±25 V
Figure 14. Midsupply Offset Voltage vs. Temperature with VSY = 5 V
Figure 17. Midsupply Input Bias Current vs. Temperature with VSY = 5 V
Figure 15. Midsupply Offset Voltage vs. Temperature with VSY = ±15 V
Figure 18. Midsupply Input Bias Current vs. Temperature with VSY = ±15 V
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Rev. A | 13 of 33
Data Sheet
ADA4098-1/ADA4098-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 19. Offset Voltage vs. Temperature with VCM = 6 V, Over-The-Top
Figure 22. Input Bias Current vs. Temperature with VSY = 5 V, Over-The-Top
Figure 20. Offset Voltage vs. Temperature with VCM = 70 V
Figure 23. Midsupply Input Bias Current vs. Temperature Across Various
Supply Voltages
Figure 21. Over-The-Top Input Bias Current vs. Temperature with VCM = 6 V
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Figure 24. Offset Voltage vs. Temperature Across Various Supply Voltages
Rev. A | 14 of 33
Data Sheet
ADA4098-1/ADA4098-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 25. Offset Voltage vs. Input Common-Mode Voltage over the Input
Common-Mode Range
Figure 28. Offset Voltage vs. Input Common-Mode Voltage for Ground
Sensing Applications
Figure 26. Offset Voltage vs. Input Common-Mode Voltage from Normal
Operation to Over-The-Top Operation
Figure 29. Input Bias Current vs. Input Common-Mode Voltage for Ground
Sensing Applications
Figure 27. Input Bias Current vs. Input Common-Mode Voltage from Normal
Operation to Over-The-Top Operation
Figure 30. Input Bias Current vs. Input Common-Mode Voltage
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Rev. A | 15 of 33
Data Sheet
ADA4098-1/ADA4098-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 31. Supply Current vs. Minimum Supply Voltage
Figure 34. ΔOffset Voltage vs. VOUT
Figure 32. Offset Voltage vs. Minimum Supply Voltage
Figure 35. ΔOffset Voltage vs. VOUT (5 kΩ Load)
Figure 33. Offset Voltage vs. Supply Voltage
Figure 36. SHDN Pin Current vs. VSHDN with Respect to −VS over Various
Temperatures
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Rev. A | 16 of 33
Data Sheet
ADA4098-1/ADA4098-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 37. Output Voltage Low (VOL) and Output Voltage High (VOH) vs.
Temperature
Figure 38. Gain Bandwidth vs. Temperature
Figure 40. Noninverting Small Signal Frequency Response (RF Is the
Feedback Resistor, RG Is the Gain Setting Resistor, and VIN Is the Input
Voltage)
Figure 41. Inverting Small Signal Frequency Response
Figure 39. Loop Gain and Phase vs. Frequency
Figure 42. Voltage Noise Density vs. Frequency for a Unity-Gain
Configuration
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Rev. A | 17 of 33
Data Sheet
ADA4098-1/ADA4098-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 46. THD + N vs. Frequency over Load
Figure 43. 0.1 Hz to 10 Hz Noise
Figure 47. THD + N vs. Output Amplitude
Figure 44. Unity-Gain Small Signal Step Response (CLOAD Is the Load
Capacitor)
Figure 48. THD + N vs. Output Amplitude and Load
Figure 45. Unity-Gain Large Signal Step Response
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Rev. A | 18 of 33
Data Sheet
ADA4098-1/ADA4098-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 49. CMRR vs. Frequency
Figure 51. Output Impedance vs. Frequency
Figure 50. PSRR vs. Frequency
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Rev. A | 19 of 33
Data Sheet
ADA4098-1/ADA4098-2
THEORY OF OPERATION
The ADA4098-1 and ADA4098-2 are robust, voltage feedback
amplifiers that combine unity-gain stability with low offset, low offset
drift, and 17 nV/√Hz of input voltage noise. Figure 54 shows a simplified schematic of the devices. The ADA4098-1 and ADA4098-2
have two input stages: a common emitter differential input stage
consisting of the Q1 and Q2 PNP transistors that operate with the
inputs biased between −VS and 1.25 V below +VS, and a common
base input stage that consists of the Q3 to Q6 PNP transistors
that operate when the common-mode input is biased >+VS − 1.25
V. These input stages result in two distinct operating regions, as
shown in Figure 52.
For common-mode input voltages that are approximately 1.25 V
below the +VS supply, where Q1 and Q2 are active (see Figure
52), the common emitter PNP input stage is active and the input
bias current is typically 20 V below −VS, at the cost of stability
and added thermal noise. The input stage of the ADA4098-1 and
ADA4098-2 incorporates phase reversal protection to prevent the
output from phase reversing for inputs below −VS. The ADA4098-1
and ADA4098-2 op amps do not have clamping diodes between
the inputs and can be differentially overdriven up to 80 V without
damage, inducing parametric shifts, or drawing appreciable input
current. Figure 56 summarizes the input fault types that can be
applied to the ADA4098-1 and ADA4098-2 without compromising
input integrity.
OVER-THE-TOP OPERATION
CONSIDERATIONS
When the ADA4098-1 and ADA4098-2 input common-modes are
biased near or >+VS supply, the amplifiers operate in the Over-TheTop configuration. The differential input pair that controls amplifier
operation is the common base pair, Q3 to Q6 (see Figure 54).
Input bias currents change from
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