Product
Document
Published by
ams OSRAM Group
TMD2725
ALS, and Small Aperture Proximity
Sensor Module
General Description
The device features advanced proximity measurement and
digital ambient light sensing (ALS). The package has been
designed to accommodate a single small aperture approach.
The slim module incorporates an IR LED and factory calibrated
LED driver. The proximity detection feature provides object
detection (e.g. mobile device screen to user’s ear) by
photodiode detection of reflected IR energy (sourced by the
integrated LED). Detect/release events are interrupt driven, and
occur when proximity result crosses upper and/or lower
threshold settings. The proximity engine features offset
adjustment registers to compensate for unwanted IR energy
reflection at the sensor. Proximity results are further improved
by automatic ambient light subtraction. The ALS detection
feature provides photopic light intensity data. The ALS
photodiode has UV and IR blocking filters and a dedicated data
converter producing 16-bit data. This architecture allows
applications to accurately measure ambient light which
enables devices to calculate illuminance to control display
backlight.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of TMD2725, ALS, and Small Aperture
Proximity Sensor Module are listed below:
Figure 1:
Added Value of Using TMD2725
Benefits
Features
• Small aperture requirements
• 1.055mm emitter to detector distance
• Single device integrated optical solution
•
•
•
•
•
• Accurate ambient light sensing
• Photopic Ambient Light Sensor (ALS)
• UV / IR blocking filters
• Programmable gain and integration time
• Reduced power consumption
• 1.8V power supply with 1.8V I²C bus
ams Datasheet
[v1-13] 2018-Feb-23
ALS + proximity
2mm x 3.65mm x 1mm
Integrated IR LED
Power management features
I²C fast mode interface compatible
Page 1
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TMD2725 − General Description
Applications
The TMD2725 applications include:
• Ambient light sensing
• Single hole proximity sensing
• Mobile phone touch screen disable
Block Diagram
The functional blocks of this device are shown below:
Figure 2:
Functional Blocks of TMD2725
LEDK/LDR
Optically
Isolated
IR
LED
PGND
Proximity LED
Current Sink
Prox ADC
LEDA
Prox Data
Prox Control
SCL
Lower
Upper
Prox Integration
Wait Control
ALS Thresholds
Lower
I²C Interface
Prox Thresholds
SDA
Upper
ALS Control
Photopic
IR
ALS ADC
ALS Data
IR ADC
IR Data
Interrupt Out /
Threshold Status
INT
VDD
TMD2725
Page 2
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VSS
ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Pin Assignments
Pin Assignments
Figure 3:
Pin Diagram of TMD2725
9''
966
6'$
,17
6&/
3*1'
/('$
/('./LDR
Figure 4:
Pin Description of TMD2725 (8-Pin Module)
Description
Pin Number
Pin Name
1
VDD
Supply voltage
2
SDA
I²C serial data I/O terminal
3
SCL
I²C serial clock input terminal
4
LEDA
5
LEDK/LDR
6
PGND
7
INT
Interrupt. Open drain output (active low)
8
VSS
Ground. All voltages are referenced to GND
ams Datasheet
[v1-13] 2018-Feb-23
LED anode
This test point is the junction of the LED cathode and internal
current source. Do not connect.
Ground for LED current sink and digital core
Page 3
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TMD2725 − Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated under Electrical
Characteristics is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 5:
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Comments
Electrical Parameters
VDD
Supply Voltage to Ground
-0.3
2.2
V
LEDA
LED Voltage to PGND
-0.3
3.6
V
VIO
Digital I/O terminal voltage
-0.3
3.6
V
IIO
SDA, INT Output terminal
current
-1
20
mA
Electrostatic Discharge
Input Current
(latch up immunity)
JEDEC JESD78D
± 100
mA
ESDHBM
Electrostatic Discharge
HBM JS-001-2014
± 2000
V
ESDCDM
Electrostatic Discharge
CDM JEDEC JESD22-C101F
± 500
V
ISCR
Class II
Temperature Ranges and Storage Conditions
TSTRG
Storage Temperature Range
TBODY
Package Body Temperature
RHNC
Relative Humidity
(non-condensing)
MSL
Moisture Sensitivity Level
Page 4
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-40
85
5
3
°C
260
°C
85
%
IPC/JEDEC J-STD-020
The reflow peak soldering
temperature (body temperature)
is specified according to
IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity
Classification for Non-hermetic
Solid State Surface Mount
Devices.”
Maximum floor life time 168 hours
ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Electrical Characteristics
Electrical Characteristics
All limits are guaranteed. The parameters with min and max
values are guaranteed with production tests or SQC (Statistical
Quality Control) methods.
Figure 6:
Recommended Operating Conditions
Parameter
Min
Typ
Max
Unit
VDD supply range
1.7
1.8
2.0
V
VLEDA, Supply voltage range (1)
3.0
3.3
3.6
V
TA, Operating free-air temperature(2)
-30
85
°C
Note(s):
1. The minimum required supply voltage on the LED anode (VLEDA) is the sum of the LED's VF and the voltage drop from the LDR pin
to PGND pin. The minimum required VLEDA can be lowered to 2.8V if the LED's forward current doesn't exceed 102mA (PLDRIVE
value of 16 or less).
2. While the device is operational across the temperature range, performance will vary with temperature. Operational characteristics
are at 25°C, unless otherwise noted.
Figure 7:
Operating Characteristics, VDD = 1.8V, TA = 25°C (unless otherwise noted)
Symbol
fOSC
IDD
Parameter
Conditions
Min
Oscillator frequency
Supply Current (1)
VOL
INT, SDA output low voltage
ILEAK
Leakage current, SDA,SCL,INT
Typ
Max
8.107
MHz
Active ALS State
(PON=AEN=1, PEN=0) (2)
80
150
Idle State
(PON=1,AEN=PEN=0) (3)
30
60
Sleep State (4)
0.7
5
6mA sink current
Unit
μA
0.6
V
-5
5
μA
VIH
SCL, SDA input high voltage
1.26
3.3
V
VIL
SCL, SDA input low voltage
0
0.54
V
TActive
Time from power-on to ready
to receive I²C commands
1.5
ms
Note(s):
1. Values are shown at the VDD pin and do not include current through the IR LED.
2. This parameter indicates the supply current during periods of ALS integration. If Wait is enabled (WEN=1), the supply current is
lower during the Wait period.
3. Idle state occurs when PON=1 and all functions are not enabled.
4. Sleep state occurs when PON = 0 and I²C bus is idle. If Sleep state has been entered as the result of operational flow, SAI = 1, PON
will remain high.
ams Datasheet
[v1-13] 2018-Feb-23
Page 5
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TMD2725 − Typical Operating Characteristics
Typical Operating
Characteristics
Figure 8:
Optical Characteristics, VDD = 1.8V, TA = 25°C (unless otherwise noted)
Clear Channel
Parameter
Conditions
Unit
Min
Re
Irradiance responsivity
Settings:
AGAIN = 16x
ATIME = 400ms
Typ
λD = 465 nm LED, 53.8 μW/cm2
58
λD = 530 nm LED, 43.9 μW/cm2
490
λD = 620 nm LED, 37.5 μW/cm2
405
Warm White LED, 45.6 μW/cm2
363
Warm White LED, 45.6 μW/cm2
14025
λD = 950 nm LED, 21.1 μW/cm2
16500
Max
Count/
(μW/cm2)
18975
Counts
Count/
(μW/cm2)
8
Figure 9:
ALS Optical Characteristics, VDD = 1.8V, TA = 25°C (unless otherwise noted)
Parameter
Conditions
Integration time step size
Dark ADC count value
Gain Scaling, relative to 1x
gain setting
ADC noise
Page 6
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Ee = 0 μW/ cm2
AGAIN: 64x
ATIME = 100ms (0x23)
Min
Typ
Max
Unit
2.72
2.82
2.94
ms
0
1
3
Counts
AGAIN = 1x
1
AGAIN = 4x
4
AGAIN = 16x
16
AGAIN = 64x
66
AGAIN = 128x
140
AGAIN = 16x
0.005
x
% full scale
ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Typical Operating Characteristics
Figure 10:
Proximity Optical Characteristics, VDD = 1.8V, TA = 25°C (unless otherwise noted)
Parameter
Conditions
Min
Typ
Max
Unit
Part to part variation (1)
Conditions:
PGAIN = 2 (4x)
PLDRIVE = 8 (54mA)
PPULSE = 15 (16 pulses)
PPULSE_LEN = 1 (8μs)
d=23mm round target
30mm target distance
75
100
125
%
Response, absolute
Basic proximity measurement (2)
Conditions:
PGAIN = 2 (4x),
PLDRIVE = 16 (102mA)
PPULSE = 15 (16 pulses)
PPULSE_LEN = 2 (16μs)
Target material:
90% reflective surface of Kodak
gray card
Target Size: 100mm x 100mm
Target Distance: 100mm
128
160
192
Response, no target
PGAIN = 2 (4x)
ILEDDRIVE = 16 (102mA)
PPULSE = 16 (17 Pulses)
Pulse Length = 2 (16μS)
Noise/Signal (3)
PGAIN = 2 (4x)
IRLEDDRIVE = 8 (54mA)
PPULSE = 15 (16 pulses)
PPULSE_LEN = 1 (8μs)
d=23mm round target
30mm target distance
Counts
0
20
1.2
%
Note(s):
1. Production tested result is the average of 5 readings expressed relative to a calibrated response.
2. Representative result by characterization.
3. Production tested result is the average of 20 readings divided by the maximum proximity value 255.
ams Datasheet
[v1-13] 2018-Feb-23
Page 7
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TMD2725 − Typical Operating Characteristics
Figure 11:
Spectral Responsivity
120%
Photopic
Normalized Responsivity
100%
IR
80%
60%
40%
20%
0%
300
400
500
600
700
800
900
1000
1100
Wavelength (nm)
Figure 12:
ALS Responsivity vs Angular Displacement
100%
Normalized Response (%)
90%
Green LED
Photopic Ch
80%
70%
60%
50%
40%
30%
20%
10%
0%
-90
-75
-60
-45
-30
-15
0
15
30
45
60
75
90
Angle of Incident Light (°)
Page 8
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ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Typical Operating Characteristics
Figure 13:
ALS Linearity
TMD2725 Linearity Response, 2700 K LED, 50ms
100000
Gain Corrected ALS Count
Best Linear Fit
10000
ADC Counts
1000
100
10
1
0.01
0.1
1
10
0.1
100
1000
10000
Illuminance(Lux)
Figure 14:
Proximity Operation of TMD2725
Proximity Operating Range using six 90mA pulses, while varying Gain and Pulse Length
Proximity Count (0 - 255 Range)
250
200
150
100
50
0
0
5
10
15
20
25
30
40
50
60
70
80
90
100
110
120
130
140
150
Distance to Target in mm
4μs, 1X Gain
8μs, 2X Gain
16μs, 4X Gain
32μs, 8X Gain
Proximity Operation: By varying Gain, LED drive current, number of LED pulses and LED pulse duration the
proximity detection range can be adjusted.
ams Datasheet
[v1-13] 2018-Feb-23
Page 9
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TMD2725 − Detailed Description
Detailed Description
Proximity
Proximity results are affected by three fundamental factors: the
integrated IR LED emission, IR reception, and environmental
factors, including target distance and surface reflectivity.
The IR reception signal path begins with IR detection from a
photodiode and ends with the 8-bit proximity result in PDATA
register. Signal from the photodiode is amplified, and offset
adjusted to optimize performance. Offset correction or
cross-talk compensation is accomplished by adjustment to the
POFFSET register.
The analog circuitry of the device applies the offset value as a
subtraction to the signal accumulation; therefore a positive
offset value has the effect of decreasing the results.
Ambient Light Sensing, ALS
The ALS reception signal path begins as photodiodes receive
filtered light and ends with the 16-bit results in the
PHOTOPICL/H and ALS_IRL/H registers. The Photopic
photodiode is filtered with a UV and IR filter. The ALS_IR
photodiode is filtered to receive only IR. Signal from the
photodiodes simultaneously accumulate for a period of time
set by the value in ATIME before the results are available. Gain
is adjustable from 1x to 64x to facilitate operation over a wide
range of lighting conditions. Custom LUX equations are used to
calculate the amount of ambient light, as well as, determine the
light type (e.g. LED, fluorescent, incandescent, etc.) using the
two ALS results.
I²C Characteristics
The device uses I²C serial communication protocol for
communication. The device supports 7-bit chip addressing and
both standard and fast clock frequency modes with a chip
address of 0x39. Read and Write transactions comply with the
standard set by Philips (now NXP).
Internal to the device, an 8-bit buffer stores the register address
location of the desired byte to read or write. This buffer
auto-increments upon each byte transfer and is retained
between transaction events (I.e. valid even after the master
issues a STOP command and the I²C bus is released). During
consecutive Read transactions, the future/repeated I²C Read
transaction may omit the memory address byte normally
following the chip address byte; the buffer retains the last
register address + 1.
Page 10
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ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Detailed Description
I²C Write Transaction
A Write transaction consists of a START, CHIP-ADDRESS WRITE,
REGISTER-ADDRESS, DATA BYTE(S), and STOP. Following each
byte (9TH clock pulse) the slave places an ACKNOWLEDGE/
NOT-ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is
transmitted by the slave, the master may issue a STOP.
I²C Read Transaction
A Read transaction consists of a START, CHIP-ADDRESS WRITE,
REGISTER-ADDRESS, START, CHIP-ADDRESS READ, DATA
BYTE(S), and STOP. Following all but the final byte the master
places an ACK on the bus (9TH clock pulse). Termination of the
Read transaction is indicated by a NACK being placed on the
bus by the master, followed by STOP.
Alternately, if the previous I²C transaction was a Read, the
internal register address buffer is still valid, allowing the
transaction to proceed without “re”-specifying the register
address. In this case the transaction consists of a START,
CHIP-ADDRESS READ, DATA BYTE(S), and STOP. Following all but
the final byte the master places an ACK on the bus (9 TH clock
pulse). Termination of the Read transaction is indicated by a
NACK being placed on the bus by the master, followed by STOP.
The I²C bus protocol was developed by Philips (now NXP). For
a complete description of the I²C protocol, please review the
NXP I²C design specification at:
http://www.i2c-bus.org/references/
Timing Diagrams
Figure 15:
I²C Timing
ams Datasheet
[v1-13] 2018-Feb-23
Page 11
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TMD2725 − Principles of Operation
Principles of Operation
System State Machine
An internal state machine provides system control of the ALS,
proximity detection, and power management features of the
device. At power up, an internal power-on-reset initializes the
device and puts it in a lowpower Sleep state. When a write on
I²C bus to the Enable register (0x80) PON bit is set, the device
transitions to the Idle state. If PON is disabled, the device will
return to the Sleep state to save power. Otherwise, the device
will remain in the Idle state until a Proximity or ALS function is
enabled. Once enabled, the device will execute the ALS,
Proximity and Wait states in sequence as indicated in Figure 16
and Figure 17. Upon completion, the device will automatically
begin a new ALS-Prox-Wait cycle as long as PON and either PEN
or AEN remain enabled. If the Prox or ALS function generates
an interrupt and the Sleep-After-Interrupt (SAI) feature is
enabled, the device will transition to the Sleep state and remain
in a low-power mode until an I²C command is received clearing
the interrupts in the STATUS register. See Interrupts for
additional information.
Page 12
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ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Principles of Operation
Figure 16:
Detailed State Diagram
Oscillator Off
(SLEEP)
az-done = 0 (reset)
no
pon
An I2C Write to az-nth-iteration register, except of the value 00h(disable-az),
resets az-done independent of actual cntrl-state.
In consequence, a new autozero calibration will be started in advance to the
next ALS integration cycle.
yes
Oscillator On
(IDLE)
no
no
aen | pen
start-offset-calib
Run Proximity
Offset Calibration
yes
yes
no
aen
pen
no
yes
yes
yes
az-done
Run Proximity
Integration
no
Run Autozero
Calibration
aen | pen
no
yes
az-done = 1
no
wen
yes
no
aen
aen==1 &&
az-done==0
no
yes
yes
Run ALS
Integration
~aen
wtime-done = 0
Run Autozero
Calibration
Run WTIME timer
aen==0
aborts ALS
~wen |
(~aen & ~pen)
az-done = 1
wtime-done = 1
az-done = 0, if az-nth
iterations passed since
last AZ calibration.
(refer to note 1
for exceptions)
autozero calibration is
executed in parallel to
running WTIME timer
az-done &
wtime-done
wen==0 | (aen==0 & pen==0)
aborts WTIME timer
yes
ams Datasheet
[v1-13] 2018-Feb-23
Page 13
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TMD2725 − Principles of Operation
Figure 17:
Simplified State Diagram
CNTRL Typical Flow
rev 1v0, 24.08.2016
Az_nth_iteration is assumed 0x7f – Run
Autozero once before 1st ALS integration
This makes the flow chart simpler, and this is the
more usual case
Oscillator Off
(SLEEP)
no
pon=1
yes
Run Proximity
Offset Calibration
Oscillator On
(IDLE)
aen=0 & pen=0
no
yes
yes
start-offset-calib
no
no
aen=1
yes
aen=1 & pen=x
no
yes
no
1st ALS iteration
yes
Run Autozero
Calibration
no
aen=0
aborts ALS
Run ALS
Integration
yes
pen=1
aen=0 & pen=1
no
yes
Run Proximity
Integration
wen=1
yes
wen=0 | (aen=0 & pen=0)
aborts WTIME timer
Page 14
Document Feedback
Run WTIME timer
ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Register Description
Register Description
Register Overview
Figure 18:
Register Overview
Address
Register Name
R/W
0x80
ENABLE
R/W
Enables states and functions
0x00
0x81
ATIME
R/W
ALS integration time
0x00
0x82
PRATE
R/W
Proximity sampling time
0x1F
0x83
WTIME
R/W
Wait time
0x00
0x84
AILTL
R/W
ALS interrupt low threshold low byte
0x00
0x85
AILTH
R/W
ALS interrupt low threshold high byte
0x00
0x86
AIHTL
R/W
ALS interrupt high threshold low byte
0x00
0x87
AIHTH
R/W
ALS interrupt high threshold high byte
0x00
0x88
PILT
R/W
Proximity interrupt low threshold
0x00
0x8A
PIHT
R/W
Proximity interrupt high threshold
0x00
0x8C
PERS
R/W
Interrupt persistence filters
0x00
0x8D
CFG0
R/W
Configuration register zero
0x80
0x8E
PCFG0
R/W
Proximity configuration register zero
0x4F
0x8F
PCFG1
R/W
Proximity configuration register one
0x80
0x90
CFG1
R/W
Configuration register one
0x00
0x91
REVID
R
Revision ID
0x20
0x92
ID
R
Device ID
0xE4
0x93
STATUS
R
Device status register
0x00
0x94
PHOTOPICL
R
Photopic channel data low byte
0x00
0x95
PHOTOPICH
R
Photopic channel data high byte
0x00
0x96
ALS_IRL
R
IR channel data low byte
0x00
0x97
ALS_IRH
R
IR channel data high byte
0x00
0x9C
PDATA
R
Proximity channel data
0x00
0x9E
REVID2
R
Auxiliary ID
0x00
0x9F
CFG2
R/W
Configuration register two
0x04
0xAB
CFG3
R/W
Configuration register three
0x4C
ams Datasheet
[v1-13] 2018-Feb-23
Register Function
Reset Value
Page 15
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TMD2725 − Register Description
Address
Register Name
R/W
Register Function
Reset Value
0xC0
POFFSETL
R/W
Proximity offset magnitude
0x00
0xC1
POFFSETH
R/W
Proximity offset sign
0x00
0xD6
AZ_CONFIG
R/W
Autozero configuration
0x7F
0xD7
CALIB
R/W
Calibration start
0x00
0xD9
CALIBCFG
R/W
Calibration configuration
0x50
0xDC
CALIBSTAT
R/W
Calibration status
0x00
0xDD
INTENAB
R/W
Interrupt enables
0x00
Note(s):
1. Address 0x98 and 0x99 will contain the results for the IR photodiode when controlled by the Green/IR MUX.
Register Access:
R = Read Only
W = Write Only
R/W = Read or Write
SC = Self Clearing after access
Page 16
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ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Register Description
Detailed Register Description
Enable Register (Address 0x80)
Figure 19:
Enable Register
Addr: 0x80
Enable
Bit
Bit Name
Default
Access
Bit Description
7:4
RESERVED
0000
RW
Reserved.
3
WEN
0
RW
This bit activates the wait feature. Active high.
2
PEN
0
RW
This bit activates the proximity detection. Active high.
1
AEN
0
RW
This bit actives the ALS function. Active high.
*Set AEN=1 and PON=1 in the same command to
ensure auto-zero function is run prior to the first
measurement.
0
PON
0
RW
This field activates the internal oscillator and ADC
channels. Active high.
Before activating AEN or PEN, preset each applicable operating
mode registers and bits.
ams Datasheet
[v1-13] 2018-Feb-23
Page 17
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TMD2725 − Register Description
ATIME Register (Address 0x81)
Figure 20:
ATIME Register
Addr: 0x81
Bit
Bit Name
ATIME
Default
Access
Bit Description
ALS value that specifies the integration time in 2.78ms
intervals. 0x00 indicates 2.8ms. The maximum ALS value
depends on the integration time. For every 2.78ms, the
maximum value increases by 1024. This means that to
be able to reach ALS full scale, the integration time has
to be at least 64*2.8ms.
7:0
ATIME
0x00
RW
Value
Integration
Cycles
Integration
Time
Maximum
ALS Value
0x00
1
2.8ms
1023
0x01
2
5.6ms
2047
…
…
…
…
0x3F
64
180ms
65535
…
…
…
…
0xFF
256
719ms
65535
The ATIME register controls the integration time of the ALS
ADCs. The timer is implemented with a down counter with 0x00
as the terminal count. The timer is clocked at a 2.8ms nominal
rate. Loading 0x00 will generate a 2.8ms integration time,
loading 0x01 will generate a 5.6ms integration time, and so
forth. The RC oscillator runs at 8MHz nominal rate. This gets
divided by 11 to generate the integration clock of 727kHz. One
count in ATIME (nominal 2.8ms) are 2.78ms. This is 2048
integration clock cycles: 125ns*11*8*256=2.8ms.
PTIME Register (Address 0x82)
Figure 21:
PTIME Register
Addr: 0x82
PTIME
Bit
Bit Name
Default
Access
7:0
PTIME
0x1F
RW
Page 18
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Bit Description
This register defines the duration of 1 Prox Sample,
which is (PTIME + 1)*88μs.
ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Register Description
WTIME Register (Address 0x83)
Figure 22:
WTIME Register
Addr: 0x83
Bit
Bit Name
WTIME
Default
Access
Bit Description
Value that specifies the wait time between ALS cycles in
2.78ms increments.
7:0
WTIME
0x00
RW
Value
Increments
Wait Time
0x00
1
2.8ms (33.8ms)
0x01
2
5.6ms (67.6ms)
…
…
…
0x3F
64
180ms (2.16s)
…
…
…
0xFF
256
719ms (8.65s)
The wait timer is implemented using a down counter.
Wait time = (value +1) x 2.8ms. If WLONG is enabled then
Wait time = (value +1) x 2.8ms. x 12.
AILTL Register (Address 0x84)
Figure 23:
AILTL Register
Addr: 0x84
AILTL
Bit
Bit Name
Default
Access
Bit Description
7:0
AILTL
0x00
RW
This register sets the low byte of the LOW ALS threshold.
The photopic channel is compared against low-going 16-bit
threshold value set by AILTL and AILTH.
ams Datasheet
[v1-13] 2018-Feb-23
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TMD2725 − Register Description
AILTH Register (Address 0x85)
Figure 24:
AILTH Register
Addr: 0x85
AILTH
Bit
Bit Name
Default
Access
7:0
AILTH
0x00
RW
Bit Description
This register sets the high byte of the LOW ALS
threshold.
The photopic channel is compared against low-going 16-bit
threshold value set by AILTL and AILTH.
The contents of the AILTH and AILTL registers are combined and
treated as a sixteen bit threshold value. If the value generated
by the photopic channel is below the AILTL/H threshold and the
APERS value is reached, the AINT bit is asserted. If AIEN is set,
then the INT pin will also assert.
When setting the 16-bit ALS threshold AILTL must be written
first, immediately follow by AILTH. Internally, the lower 8-bits
are buffered until the upper 8-bits are written. As the upper
8-bits are written both the high and low bytes are
simultaneously latched as a 16-bit value.
AIHTL Register (Address 0x86)
Figure 25:
AIHTL Register
Addr: 0x86
AIHTL
Bit
Bit Name
Default
Access
7:0
AIHTL
0x00
RW
Bit Description
This register sets the low byte of the HIGH ALS
threshold.
The photopic channel is compared against high-going 16-bit
threshold value set by AIHTL and AIHTH.
The contents of the AIHTH and AIHTL registers are combined
and treated as a sixteen bit threshold value. If the value
generated by the photopic channel is above the AIHTL/H
threshold and the APERS value is reached, the AINT bit is
asserted. If AIEN is set, then the INT pin will also assert. When
setting the 16-bit ALS threshold AIHTL must be written first,
immediately follow by AIHTH. Internally, the lower 8-bits are
buffered until the upper 8-bits are written. As the upper 8-bits
are written both the high and low bytes are simultaneously
latched as a 16-bit value.
Page 20
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ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Register Description
AIHTH Register (Address 0x87)
Figure 26:
AIHTH Register
Addr: 0x87
AIHTH
Bit
Bit Name
Default
Access
7:0
AIHTH
0x00
RW
Bit Description
This register sets the high byte of the HIGH ALS
threshold.
The photopic channel is compared against high-going 16-bit
threshold value set by AIHTL and AIHTH.
The contents of the AIHTH and AIHTL registers are combined
and treated as a sixteen bit threshold value. If the value
generated by the photopic channel is above the AIHTL/H
threshold and the APERS value is reached, the AINT bit is
asserted. If AIEN is set, then the INT pin will also assert.
When setting the 16-bit ALS threshold AIHTL must be written
first, immediately follow by AIHTH. Internally, the lower 8-bits
are buffered until the upper 8-bits are written. As the upper
8-bits are written both the high and low bytes are
simultaneously latched as a 16-bit value.
PILT Register (Address 0x88)
Figure 27:
PILT Register
Addr: 0x88
PILT
Bit
Bit Name
Default
Access
7:0
PILT
0x00
RW
Bit Description
This register sets the Proximity ADC channel low
threshold.
The proximity channel is compared against low-going 8-bit
threshold value set by PILT.
If the value generated by the Proximity channel is below the
PILT threshold and the PPERS value is reached, the PINT bit is
asserted. If PIEN is set, then the INT pin will also assert.
ams Datasheet
[v1-13] 2018-Feb-23
Page 21
Document Feedback
TMD2725 − Register Description
PIHT Register (Address 0x8A)
Figure 28:
PIHT Register
Addr: 0x8A
PIHT
Bit
Bit Name
Default
Access
7:0
PIHT
0x00
RW
Bit Description
This register sets the Proximity ADC channel high
threshold.
The proximity channel is compared against high-going 8-bit
threshold value set by PIHT.
If the value generated by the Proximity channel is above the
PIHT threshold and the PPERS value is reached, the PINT bit is
asserted. If PIEN is set, then the INT pin will also assert.
PERS Register (Address 0x8C)
Figure 29:
PERS Register
Addr: 0x8C
Bit
Bit Name
PERS
Default
Access
Bit Description
This register sets the Proximity persistence filter.
Value
7:4
PPERS
Page 22
Document Feedback
0000
Interrupt
0
Every Proximity Cycle
1
Any value outside PILT/PIHT thresholds
2
2 consecutive proximity values out of range
3
3 consecutive proximity values out of range
…
….
15
15 consecutive proximity values out of range
RW
ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Register Description
Addr: 0x8C
Bit
Bit Name
PERS
Default
Access
Bit Description
This register sets the ALS persistence filter.
3:0
APERS
0000
RW
0
Every ALS Cycle
1
Any value outside ALS thresholds
2
2 consecutive ALS values out of range
3
3 consecutive ALS values out of range
4
5 consecutive ALS values out of range
5
10 consecutive ALS values out of range
6
15 consecutive ALS values out of range
7
20 consecutive ALS values out of range
…
…
13
50 consecutive ALS values out of range
14
55 consecutive ALS values out of range
15
60 consecutive ALS values out of range
The frequency of consecutive proximity channel results outside
of threshold limits are counted; this count value is compared
against the PPERS value. If the counter is equal to the PPERS
value an interrupt is asserted. Any time a proximity channel
result is inside the threshold values the counter is cleared.
The frequency of consecutive photopic channel results outside
of threshold limits are counted; this count value is compared
against the APERS value. If the counter is equal to the APERS
setting an interrupt is asserted. Any time a photopic channel
result is inside the threshold values the counter is cleared.
ams Datasheet
[v1-13] 2018-Feb-23
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TMD2725 − Register Description
CFG0 Register (Address 0x8D)
Figure 30:
CFG0 Register
Addr: 0x8D
CFG0
Bit
Bit Name
Default
Access
Bit Description
7:3
Reserved
10000
RW
This field must be set to the default value.
2
WLONG
0
RW
When Wait Long is asserted the wait period as set by
WTIME is increased by a factor of 12.
1:0
Reserved
00
RW
This field must be set to the default value.
The wait timer is implemented using a down counter.
Wait time = (value +1) x 2.8ms. If WLONG is enabled then
Wait time = (value +1) x 2.8ms x 12.
Page 24
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ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Register Description
PCFG0 Register (Address 0x8E)
Figure 31:
PCFG0 Register
Addr: 0x8E
Bit
Bit Name
PCFG0
Default
Access
Bit Description
Proximity Pulse Length
7:6
PPULSE_LEN
01
Value
Pulse Length
0
4μs
1
8μs
2
16μs
3
32μs
RW
Maximum Number of Pulses in a single proximity cycle.
5:0
PPULSE
001111
RW
Value
Maximum Number of Pulses
0
1
1
2
2
3
…
…
63
64
The PPULSE_LEN field sets the width of all IR LED pulses within
the proximity cycle. Longer pulses result in increased proximity
range and typically result in less electrical noise generated in
the analog front end. However, a setting of 8μs is recommended
because less cumulative noise is generated during a proximity
cycle.
The PPULSE field sets the maximum number of IR LED pulses
that may occur in a proximity cycle. The proximity engine will
automatically continue to add IR LED pulses, up to the value set
in PPULSE or if a near-saturation condition occurs.
The dynamic range of the sensor is automatically adjusted to
detect distant targets as well as prevent saturation from close
targets.
This operation also reduces power consumption because
proximity integration period is automatically shortened when
a target is either to close or far from the sensor.
ams Datasheet
[v1-13] 2018-Feb-23
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TMD2725 − Register Description
PCFG1 Register (Address 0x8F)
Figure 32:
PCFG1 Register
Addr: 0x8F
Bit
Bit Name
PCFG1
Default
Access
Bit Description
This field sets the gain of the proximity IR sensor.
7:6
5
PGAIN
Reserved
10
0
Gain
Value
Bit Field
1x
0
00b
2x
1
01b
4x
2
10b
8x
3
11b
RW
RW
Reserved
This field sets the drive strength of the IR LED current.
Values are approximate; actual current through LED is
factory trimmed to normalize IR intensity.
4:0
PLDRIVE
00000
Value
LED Current
0
6mA
1
12mA
RW
iLED = 6(PLDRIVE +1) mA
Page 26
Document Feedback
30
186mA
31
192mA
ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Register Description
CFG1 Register (Address 0x90)
Figure 33:
CFG1 Register
Addr: 0x90
CFG1
Bit
Bit Name
Default
Access
7:2
Reserved
000000
RW
Bit Description
Reserved
This field sets the gain of the ALS sensor.
1:0
AGAIN
00
Value
Gain
0
1x
1
4x
2
16x
3
64x
RW
REVID Register (Address 0x91)
Figure 34:
REVID Register
Addr: 0x91
REVID
Bit
Bit Name
Default
Access
Bit Description
7:3
Reserved
00100
RO
Reserved
2:0
REV_ID
000
RO
Device revision number
ID Register (Address 0x92)
Figure 35:
ID Register
Addr: 0x92
ID
Bit
Bit Name
Default
Access
Bit Description
7:2
ID
111001
RO
Device type identification.
1:0
Reserved
00
RO
Reserved
ams Datasheet
[v1-13] 2018-Feb-23
Page 27
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TMD2725 − Register Description
Status Register (Address 0x93)
Figure 36:
Status Register
Addr: 0x93
Status Register
Bit
Bit Name
Default
Access
Bit Description
7
ASAT
0
R, SC
The Analog Saturation flag signals that the ALS results
may be unreliable due to saturation of the AFE.
6
PSAT
0
R, SC
The Proximity Saturation flag indicates that an ambientor reflective-saturation event occurred during a
previous proximity cycle.
5
PINT
0
R, SC
The Proximity Interrupt flag indicates that proximity
results have exceeded thresholds and persistence
settings.
4
AINT
0
R, SC
The ALS Interrupt flag indicates that ALS results
(photopic channel) have exceeded thresholds and
persistence settings.
3
CINT
0
R, SC
The Calibration Interrupt flag indicates that calibration
has completed.
2
Reserved
0
R, SC
Reserved
1
PSAT_REFLECTIVE
0
R, SC
The Reflective Proximity Saturation Interrupt flag
signals that the AFE has saturated during the IR LED
active portion of proximity integration.
0
PSAT_AMBIENT
0
R, SC
The Ambient Proximity Saturation Interrupt flag signals
that the AFE has saturated during the IR LED inactive
portion of proximity integration.
All flags in this register can be cleared by setting the bit high.
Alternatively, if the CFG3.int_read_clear bit is set, then simply
reading this register automatically clears all eight flags.
PHOTOPICL Register (Address 0x94)
Figure 37:
PHOTOPICL Register
Addr: 0x94
PHOTOPICL
Bit
Bit Name
Default
Access
7:0
PHOTOPICL
0x00
RO
Page 28
Document Feedback
Bit Description
This register contains the low byte of the 16-bit
photopic channel data.
ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Register Description
PHOTOPICH Register (Address 0x95)
Figure 38:
PHOTOPICH Register
Addr: 0x95
PHOTOPICH
Bit
Bit Name
Default
Access
Bit Description
7:0
PHOTOPICH
0x00
RO
This register contains the high byte of the 16-bit
photopic channel data.
ALS_IRL Register (Address 0x96)
Figure 39:
ALS_IRL Register
Addr: 0x96
ALS_IRL
Bit
Bit Name
Default
Access
Bit Description
7:0
ALS_IRL
0x00
RO
This register contains the low byte of the 16-bit
IR channel data.
ALS_IRH Register (Address 0x97)
Figure 40:
ALS_IRH Register
Addr: 0x97
ALS_IRH
Bit
Bit Name
Default
Access
Bit Description
7:0
ALS_IRH
0x00
RO
This register contains the high byte of the 16-bit
IR channel data.
PDATA Register (Address 0x9C)
Figure 41:
PDATA Register
Addr: 0x9C
PDATA
Bit
Bit Name
Default
Access
Bit Description
7:0
PDATA
0x00
RO
This register contains the 8-bit proximity channel data.
ams Datasheet
[v1-13] 2018-Feb-23
Page 29
Document Feedback
TMD2725 − Register Description
REVID2 Register (Address 0x9E)
Figure 42:
REVID2 Register
Addr: 0x9E
REVID2
Bit
Bit Name
Default
Access
Description
7:4
Reserved
0000
RO
Reserved
3:0
REVID2
0000
RO
Package Identification
CFG2 Register (Address 0x9F)
Figure 43:
CFG2 Register
Addr: 0x9F
CFG2
Bit
Bit Name
Default
Access
Bit Description
7:5
Reserved
000
RW
Reserved
4
AGAINMAX
0
RW
This bit adjusts the overall ALS gain factor. See
Figure 44 for recommended settings and
corresponding overall ALS gain factor.
3
Reserved
0
RW
Reserved
2
AGAINL
1
RW
This bit adjusts the overall ALS gain factor. See
Figure 44 for recommended settings and
corresponding overall ALS gain factor.
1:0
Reserved
00
RW
Reserved
The ALS gain can be adjusted using by setting the two AGAIN
bits as well as the AGAINL bit which yields an overall range
from ½ x to 128x.
Page 30
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ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Register Description
Figure 44:
AGAIN Range
AGAIN[1]
AGAIN[0]
AGAINMAX
AGAINL
Overall ALS Gain
0
0
0
0
½
0
0
0
1
1
0
1
0
1
4
1
0
0
1
16
1
1
0
1
64
1
1
1
1
128
CFG3 Register (Address 0xAB)
Figure 45:
CFG3 Register
Addr: 0xAB
CFG3
Bit
Bit Name
Default
Access
Bit Description
7
INT_READ_CLEAR
0
RW
If the Interrupt-Clear-by-Read bit is set, then all flag
bits in the STATUS register will be reset whenever
the STATUS register is read over I²C.
6:5
Reserved
10
RW
Reserved
The Sleep After Interrupt bit is used to place the
device into a low power mode upon an interrupt pin
assertion.
4
3:0
SAI
Reserved
ams Datasheet
[v1-13] 2018-Feb-23
0
1100
RW
RW
PON
SAI
INT
Oscillator
0
X
X
OFF
1
0
X
ON
1
1
1
ON
1
1
0
OFF
Reserved
Page 31
Document Feedback
TMD2725 − Register Description
The SAI bit sets the device operational mode following the
completion of an ALS or proximity cycle. If AINT and AIEN are
both set or if PINT and PIEN are both set, causing an interrupt
on the INT pin, and the SAI bit is set, then the oscillator will
deactivate. The Device will appear as if PON = 0, however, PON
will read as 1. The device can only be reactivated (oscillator
enabled) by clearing the interrupts in the STATUS register.
POFFSETL Register (Address 0xC0)
Figure 46:
POFFSETL Register
Addr: 0xC0
POFFSETL
Bit
Bit Name
Default
Access
Bit Description
7:0
POFFSETL
0x00
RW
This register contains the magnitude portion of
proximity offset adjust value.
Typically, optical and/or electrical crosstalk negatively
influence proximity operation and results. The
POFFSETL/POFFSETH registers provide a mechanism to remove
system crosstalk from the proximity data. POFFSETL and
POFFSETH contains the magnitude and sign of a value which
adjusts PDATA generated in the AFE. An offset value in the range
of ± 255 is possible.
POFFSETH Register (Address 0xC1)
Figure 47:
POFFSETH Register
Addr: 0xC1
POFFSETH
Bit
Bit Name
Default
Access
7:1
Reserved
0000000
RW
Reserved
0
POFFSET_SIGN
0
RW
This register contains the sign portion of
proximity offset adjust value.
Page 32
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Bit Description
ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Register Description
AZ_CONFIG Register (Address 0xD6)
Figure 48:
AZ_CONFIG Register
Addr: 0xD6
AZ_CONFIG
Bit
Bit Name
Default
Access
Description
7
Reserved
0
RW
Reserved.
6:0
AZ_NTH_
ITERATION
1111111
RW
Run autozero automatically before every nth ALS
cycle (00h = never, n = every nth ALS cycle, and
7Fh = only before the first ALS cycle).
CALIB Register (Address 0xD7)
Figure 49:
CALIB Register
Addr: 0xD7
CALIB
Bit
Bit Name
Default
Access
Bit Description
7:6
Reserved
00
RO
Reserved
5
ELECTRICAL_
CALIBRATION
0
RW
Selects proximity calibration type.
1 = electrical offset only.
0 = calibration compensates for electrical and
optical crosstalk.
4:1
Reserved
0000
RW
Reserved
0
START_OFFSET_
CALIB
0
RW
Set to 1 to start a calibration sequence.
Proximity response in systems with electrical and optical
crosstalk may be improved by using the calibration feature.
Optical crosstalk is caused when the photodiode receives a
small portion of the LED IR which was unintentionally reflected
by a surface other than the target. Electrical offset is caused by
electrical disturbance in the sensor AFE, and also influences the
proximity result. The calibration routine adjusts the value in
registers C0 and C1 until the proximity result is as close to
BINSRCH_TARGET as possible without becoming zero.
Optical and electrical calibration function identically, except
that during an electrical calibration the proximity photodiode
is disconnected from the AFE.
An electrical only calibration can be initiated by setting the
ELECTRICAL_CALIBRATION and START_OFFSET_CALB bits.
To perform an optical (and electrical) calibration do not set the
ELECTRICAL_CALIBRATION bit when setting the START_
OFFSET_CALIB. The CINT flag will assert after calibration has
ams Datasheet
[v1-13] 2018-Feb-23
Page 33
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TMD2725 − Register Description
finished.
Upon completion Proximity offset registers are automatically
loaded with calibration result.
CALIBCFG Register (Address 0xD9)
Figure 50:
CALIBCFG Register
Addr: 0xD9
Bit
Bit Name
CALIBCFG
Default
Access
Bit Description
Proximity Result Target
7:5
BINSRCH_
TARGET
010
Value
PDATA Target
0
0
1
1
2
3
3
7
4
15
5
31
6
63
7
127
RW
4
Reserved
1
RW
Reserved
3
AUTO_
OFFSET_ADJ
0
RW
The Proximity Auto Offset Adjust bit causes the value in
POFFSETL register to decrement when PDATA equals zero at the
completion of the proximity cycle.
The Proximity Averaging field defines the number of ADC
samples collected and averaged during a cycle which become
the proximity result.
2:0
PROX_AVG
Page 34
Document Feedback
000
RW
Value
Sample Size
0
Disable
1
2
2
4
3
8
4
16
5
32
6
64
7
128
ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Register Description
The binary search target field is used by the calibration feature
to set the baseline value for PDATA when no target is present.
For example, calibration of a device in open air, with no target,
and BINSEARCH_TARGET setting of 4 causes the PDATA value
will be approximately 15 counts. This feature is useful because
it forces PDATA result to always be above zero.
The PROX_AVG field sets the number of ADC samples that are
averaged to calculate the PDATA result.
CALIBSTAT Register (Address 0xDC)
Figure 51:
CALIBSTAT Register
Addr: 0xDC
CALIBSTAT
Bit
Bit Name
Default
Access
Bit Description
7:1
Reserved
0000000
RW
Reserved
0
CALIB_FINISHED
0
RW
This flag indicates that calibration has
finished. It can only be cleared by setting this
bit high.
INTENAB Register (Address 0xDD)
Figure 52:
INTENAB Register
Addr: 0xDD
INTENAB
Bit
Bit Name
Default
Access
7
ASIEN
0
RW
ALS Saturation Interrupt Enable
6
PSIEN
0
RW
Proximity Saturation Interrupt Enable
5
PIEN
0
RW
Proximity Interrupt Enable
4
AIEN
0
RW
ALS Interrupt Enable
3
CIEN
0
RW
Calibration Interrupt Enable
2:0
Reserved
000
RW
Reserved
ams Datasheet
[v1-13] 2018-Feb-23
Bit Description
Page 35
Document Feedback
TMD2725 − Application Information
Application Information
Schematic
Figure 53:
Typical Applications Circuit
VBUS
RINT = 10KΩ
RPU
TMD2725
R = 22Ω
SCL
SCL
VDD
SDA
SDA
VSS
INT
INT
LEDA
LEDK/LDR
PGND
4.7μF
1.8V
Bulk System
Capacitance
3.0V
10μF
Typical Applications Circuit: It is important to place the 4.7μF (VDD) and 10μF (LEDA) capacitors at the package
pins.
Page 36
Document Feedback
ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Application Information
PCB Layout
Figure 54:
Typical Applications Circuit
The dominant factor governing device performance is the
component placement, not necessarily component value. The
placement of the decoupling capacitor, C1, is the most critical.
Place the component on the same side of PCB as device as
shown in the figure above. Make connection as close as possible
to minimize series inductance and resistance. This is critical.
ams Datasheet
[v1-13] 2018-Feb-23
Page 37
Document Feedback
TMD2725 − Package Drawings & Markings
Package Drawings & Markings
Figure 55:
Package Drawings
/('$3(5785(
5
&/
&/
3,1,1',&$725
3$57 &/ 72$/6 &/
3$57 &/ 72352; &/
/(' &/ 72352; &/
$
%
&
;
0 & $ %
&/
;
;
0 & $ %
&/
;
;
;
RoHS
Green
Note(s):
1. All linear dimensions are in millimeters.
2. Contact finish is Au.
3. This package contains no lead (Pb).
4. This drawing is subject to change without notice.
Page 38
Document Feedback
ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Package Drawings & Markings
Figure 56:
Recommended PCB Layout
;
&/
;
&/
;
;
;
;
Note(s):
1. All dimensions are in millimeters.
2. Dimension tolerances are 0.05mm unless otherwise noted.
3. This drawing is subject to change without notice.
ams Datasheet
[v1-13] 2018-Feb-23
Page 39
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TMD2725 − Tape & Reel Information
Tape & Reel Information
Figure 57:
Tape and Reel Information
J
%
$
$
.
$
PD[
$$
PD[
%
%
[
XQZLQGLQJGLUHFWLRQHPSW\
%%
Note(s):
1. All linear dimensions are in millimeters.
2. For missing tolerances and dimensions, refer to EIA-481.
3. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
Page 40
Document Feedback
ams Datasheet
[v1-13] 2018-Feb-23
TMD2725 − Soldering & Storage Information
Soldering & Storage
Information
The module has been tested and has demonstrated an ability
to be reflow soldered to a PCB substrate. The solder reflow
profile describes the expected maximum heat exposure of
components during the solder reflow process of product on a
PCB. Temperature is measured on top of component. The
components should be limited to a maximum of three passes
through this solder reflow profile.
Figure 58:
Solder Reflow Profile
Profile Feature
Preheat/ Soak
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Temperature Min (Tsmin)
100 °C
150 °C
Temperature Max (Tsmax)
150 °C
200 °C
Time (ts) from (Tsmin to Tsmax)
60-120 seconds
60-120 seconds
Ramp-up rate (TL to TP)
3 °C/second max.
3 °C/second max.
Liquidous temperature (TL)
Time (tL) maintained above TL
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body temperature (TP)
For users TP must not exceed the
Classification temp of 235 °C
For suppliers TP must equal or
exceed the Classification temp
of 235 °C
For users TP must not exceed the
Classification temp of 260 °C
For suppliers TP must equal or
exceed the Classification temp of
260 °C
Time (tP) (1) within 5 °C of the
specified classification temperature
(Tc)
20 (1)seconds
30 (1)seconds
Ramp-down rate (TP to TL)
6 °C/second max.
6 °C/second max.
Time 25 °C to peak temperature
6 minutes max.
8 minutes max.
Note(s):
1. Tolerance for peak profile temperature (TP) is defined as a supplier minimum and a user maximum.
ams Datasheet
[v1-13] 2018-Feb-23
Page 41
Document Feedback
TMD2725 − Soldering & Storage Information
Figure 59:
Solder Reflow Profile Graph
Not to Scale – For Reference Only
TP
Max Ramp Up Rate = 3°C/s
Max Ramp Down Rate = 6°C/s
TL
TC - 5°C
tP
Temperature (°C)
tL
Tsmax
Preheat Area
Tsmin
25
Time (seconds)
Storage Information
Moisture Sensitivity Optical characteristics of the device can be
adversely affected during the soldering process by the release
and vaporization of moisture that has been previously
absorbed into the package. To ensure the package contains the
smallest amount of absorbed moisture possible, each device is
baked prior to being dry packed for shipping. Devices are dry
packed in a sealed aluminized envelope called a
moisture-barrier bag with silica gel to protect them from
ambient moisture during shipping, handling, and storage
before use.
Shelf Life
The calculated shelf life of the device in an unopened moisture
barrier bag is 12 months from the date code on the bag when
stored under the following conditions:
• Shelf Life: 12 months
• Ambient Temperature:
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