YT8010A

YT8010 Datasheet | Rev v0.1 tia lf or s in gu la to 2019 id en YT8010 Datasheet nf 100BASE-T1 PHY FOR AUTOMOTIVE ETHERNET co REV V0.1 苏州裕太车通 | motor-comm YT8010 Datasheet Revision History Revision Release Date Summary Draft 1.0 Update register table co nf id en tia lf or s in gu la to 0.1 2 YT8010 Datasheet Table of Content 內容 1. General Description .......................................................................................................................... 5 TARGET APPLICATIONS ...................................................................................................................... 5 2. Feature .................................................................................................................................................. 6 3 PIN assigment .................................................................................................................................... 7 YT8010 QFN36 6x6mm ....................................................................................................................... 7 Function Description ...................................................................................................................... 11 la 4 to Pin Descriptions ..................................................................................................................................... 8 in gu Application Diagram .......................................................................................................................... 11 100Base-t1 application................................................................................................................. 11 MII interface .......................................................................................................................................... 11 or s RMII interface ....................................................................................................................................... 11 Management interface ...................................................................................................................... 12 DAC.......................................................................................................................................................... 12 lf ADC.......................................................................................................................................................... 12 tia Adaptive equalizer .............................................................................................................................. 12 Echo-canceller ..................................................................................................................................... 13 en Clock recovery...................................................................................................................................... 13 id Link Monitor.......................................................................................................................................... 13 Polarity detection and auto correction ........................................................................................ 13 nf Operational Description ................................................................................................................ 14 Reset ........................................................................................................................................................ 14 co 5 PHY Address ......................................................................................................................................... 14 XMII interface ....................................................................................................................................... 14 MII........................................................................................................................................................ 14 RMII ..................................................................................................................................................... 15 RGMII .................................................................................................................................................. 16 REMII interface ................................................................................................................................ 17 SQI ........................................................................................................................................................... 18 3 YT8010 Datasheet Loopback mode................................................................................................................................... 18 Internal loopback:........................................................................................................................... 18 External loopback ........................................................................................................................... 19 Remote loopback ........................................................................................................................... 19 Master-slave configuration ............................................................................................................. 20 Interrupt ................................................................................................................................................. 20 Power saving ........................................................................................................................................ 20 to Application notes about sleep mode ........................................................................................... 21 Sleep negotiation process ................................................................................................................ 22 Register Overview ........................................................................................................................... 26 in gu 6 la Remote wakeup ................................................................................................................................... 25 MII Management Interface Clause 22 Register Programming............................................. 26 MII REGISTERS ............................................................................................................................. 26 Timing and AC Characteristics .................................................................................................... 49 8 Power Requirements ...................................................................................................................... 50 9 Mechanical and Thermal .............................................................................................................. 51 lf or s 7 tia RoHS-Compliant Packaging............................................................................................................ 51 Mechanical Information .................................................................................................................... 52 co nf id en 10 Ordering Information..................................................................................................................... 53 4 YT8010 Datasheet 1. GENERAL DESCRIPTION The MotorComm YT8010 is a single pair Ethernet physical layer transceiver (PHY) which implements the Ethernet physical layer portion of the 100BASE-T1 standard as defined by the IEEE 802.3bw task force. Ideally suited for a wide range of automotive applications, it is manufactured using a standard digital CMOS process and contains all the active circuitry required to implement the physical layer functions to transmit and receive data on a single balanced twisted pair. Based on cutting-edge DSP technology, combing adaptive equalizers, echo canceller, to phaselocked, ADCs, phase-locked loops, line drivers, encoders/decoders, echo cancelers and all other required support circuitry at a 100Mbps data rate to achieve robust performance and la exceed automotive electromagnetic interference (EMI) requirements in noisy environments with in gu very low power dissipation. The YT8010 is designed to be fully compliant with RGMII, RMII and MII interface specifications, allowing compatibility with industry-standard Ethernet media access controllers (MACs) and or s switch controllers. The YT8010 delivers the most comprehensive automotive technology solution required by OEM tia TARGET APPLICATIONS lf and Tier 1 suppliers, meeting AEC-Q100 Grade 1 temperature range. en • Automotive infotainment systems • Automotive diagnostics id • Advanced driver assist systems co nf • Body electronics 5 YT8010 Datasheet ⚫ 100BASE-T1 Transceiver single supply 100BASE-T1 IEEE 802.3bw ⚫ standards ⚫ for diagnosis ◼ Full duplex ◼ Rapid linkup time ⚫ Support auto cable detection and ⚫ MII/RMII/RGMII support ⚫ RMII/RGMII interface EMI enhancement ⚫ Support latency accommodation of ⚫ Jumbo frame support up to 16 kB ⚫ Polarity detection and auto/manual correction ⚫ Integrated twisted-pair termination resistors RGMII clock AEC-Q100 Grade 1 (-40~125°C) or s ⚫ Support IEEE 802.1AS ⚫ Support Remote Wake up 3.3V analog ⚫ Trace matched output impedance ⚫ Integrated low-pass filter ⚫ Support over Temperature warning. ⚫ Robust cable ESD tolerance ⚫ Package QFN 36, 6x6mm lf ⚫ tia supply. Advanced low-power management with en local wake-up support Automotive Cable Diagnostics support co nf id ⚫ MDI pins protected against ESD to 6kV HBM and 6kV IEC61000-4-2 working mode selection. ⚫ Internal/external/remote loopback mode to ◼ Integrated LDO regulator allowing a la ⚫ FEATURE in gu 2. 6 YT8010 Datasheet 3 PIN ASSIGMENT co nf id en tia lf or s in gu la to YT8010 QFN36 6X6MM 7 YT8010 Datasheet ⚫ = Output ⚫ I/O = Bidirectional ⚫ OD = Open-drain output ⚫ OT = Tristateable signal ⚫ B = Bias ⚫ PU = Internal pull-up ⚫ PD = Internal pull-down ⚫ SOR = Sample on reset ⚫ CS = Continuously sampled ⚫ ST = Schmitt trigger ⚫ XT = Crystal inputs/outputs pin type ⚫ D = Digital pin type ⚫ G = RGMII pin type ⚫ A = Analog pin type la I = Input or s in gu ⚫ to PIN DESCRIPTIONS Pin No. Symbol Type Description 1 MDC I; ST Management Data Clock. Only need to be effect during mdio operation. OVDD PWR, selected, RESET, MDIO, and LED pins are not 3.3V tia IO 2.5V or 3.3V for non-RGMII digital pads. When 2.5V is lf 2 tolerant. 6 Ana en LED_N/INT_N co 5 VSENSE id 4 VCNTL nf 3 XTAL_OUT Ana Vcontrol. Output point of an internal error amplifier. This pin shall be connected to the base of an external PNP power transistor. Vsense. Sensing point of the external power transistor. This pin shall be connected to the external 1.2V power. O,od LED_N/INT_N Dual function pin. This pin is a dual function pin. It is active low unless programmed through MDIO. O/XT 25 MHz Crystal Oscillator Output Pin. A continuous 25 MHz reference clock must be supplied to the chip by connecting a 25 MHz crystal between these two pins or by driving XTAL_IN with an external 25 MHz clock. When using a crystal, connect a loading capacitor from each pin to GND. When using an oscillator, leave XTAL_OUT unconnected. 7 XTAL_IN I/XT 25 MHz Crystal Oscillator Input Pin. 8 YT8010 Datasheet 8 VDD33_MAIN PWR, 3.3V power for the main core. I 9 RBIAS Ana Bias Resistor. A 2.4 kΩ±1% resistor is connected between the RBIAS pin and GND 10 AVDDL PWR, 1.2V power for the analog. I 11 VDD33_DAC PWR, 3.3V power for the DAC. I 12 TXP Ana Transmit/Receive Pairs . Differential data from copper media is transmitted and received on the single TRD± 13 TXN to signal pair. There are 50Ω internal terminations on each pin. Since this device incorporates voltage driven DAC, it Ana 14 WAKE la does not require a center-tap supply. I,pd WAKE. Active-high. When in sleep mode, transitioning in gu the WAKE pin from low to high will cause the PHY to exit the sleep mode. 15 VDD33_AUX PWR, 3.3V power for the auxiliaryr domain. This pin supplies I power to the passive signal detect circuitry and must 16 INH or s remain powered with 3.3V. O Inhibit. Output to be connected to the LDO supplying power to the PHY. When entering sleep mode, INH will lf be pulled low and will disable the LDO. When exit sleep mode, INH will be pulled high and will enable the LDO EN I,pd EN. This pin is used in conjunction with INH to enable tia 17 18 en sleep mode or to provide a local wakeup from sleep RX_DV/ IO,pd RXD[3]/ co 19 nf id Strapping[4] mode Receive Data Valid. Active-high. RX_DV indicates that a receive frame is in progress and that the data present on the RXD output pins is valid. Strapping[4]. Used as power on strapping[4] bit when reset is active. IO,pd Strapping[3] Receive Data Outputs. Byte-wide receive data output synchronous with the receive clock. RXD[3] is the most significant bit. Strapping[3]. Used as power on strapping[3] bit when reset is active. 20 RXD[2]/ Strapping[2] IO,pd Receive Data Outputs. Byte-wide receive data output synchronous with the receive clock. Strapping[2]. Used as power on strapping[2] bit when reset is active. 9 YT8010 Datasheet 21 22 OVDD_RGMII RXD[1]/ PWR, 2.5V or 3.3V for RGMII IO. This pin is internally shorted I with OVDD_RMII. IO,pd Receive Data Outputs. Byte-wide receive data output Strapping[1] synchronous with the receive clock. Strapping[1]. Used as power on strapping[1] bit when reset is active. 23 RXD[0]/ IO,pd Receive Data Outputs. Byte-wide receive data output Strapping[0] synchronous with the receive clock. RXD[0] is the less significant bit. Strapping[0]. Used as power on strapping[0] bit when 24 RXC to reset is active. IO,pu Receive Clock. 2.5M/25M output or input. This clock is la used to synchronize the receive data outputs RXD[3:0]. link mode. 25 26 OVDD_RMII TX_EN in gu The direction and frequency depend on MII mode and PWR, 2.5V or 3.3V for RGMII IO. This pin is internally shorted I with OVDD_RGMII. I,ST Transmit Enable. Active-high. When TX_EN is asserted, 27 TXD[3] or s the data on the TXD pins is encoded and transmitted. I,pd Transmit Data Input. Data is input synchronously with TXC clock. TXD[2] I,pd Transmit Data Input. Data is input synchronously with lf 28 TXC clock. TXD[1] I,pd Transmit Data Input. Data is input synchronously with tia 29 TXC clock. TXC I,pd IO,pd DVDDL co 32 nf id 31 TXD[0] en 30 Transmit Data Input. Data is input synchronously with TXC clock. Transmit Clock. 2.5M/25M/50M output or input. This clock is used to synchronize the transmit data inputs TXD[3:0]. The direction and frequency depend on MII mode and link mode. PWR, 1.2V input for digital core I 33 SYNC_IO IO,pd 802.1AS Frame Sync event/sync pulse input or output 34 SYNC_IN I, ST 802.1AS Frame Sync event/sync pulse input. 35 RESET_N I,pu RESET. Active-low, reset pin for chip. 36 MDIO IO,pu Management Data I/O. This serial input/output bit is used to read from and write to the MII registers. The data value on the MDIO pin is valid and latched on the rising edge of MDC. 10 YT8010 Datasheet 4 FUNCTION DESCRIPTION APPLICATION DIAGRAM 100BASE-T1 APPLICATION PHY SWITCH/MAC 100BASE-T1 RXD[3:0] MII/RMII/RGMII in gu la to TXD[3:0] CMC and Capacitive Coupling MII INTERFACE or s The Media Independent Interface (MII) is the digital data interface between the MAC and the physical layer that can be enabled when the device is functioning in 100BASE-T1 mode. The original MII transmit signals include TX_EN, TXC, TXD[3:0], and TX_ER. The receive signals include lf RX_DV, RXC, RXD[3:0], and RX_ER. The media status signals include CRS and COL. Due to pincount limitations, the YT8010 supports a subset of MII signals. This subset includes all MII signals id en tia except TX_ER, RX_ER, CRS and COL. nf RMII INTERFACE Reduced media-independent interface (RMII) is a standard which was developed to reduce the co number of signals required to connect a PHY to a MAC. If this interface is active, the number of data signal pins required to and from the MAC is reduced to half by clocking data on both the rising and falling edge of the transmit clock. 11 YT8010 Datasheet MANAGEMENT INTERFA CE The Status and Control registers of the device are accessible through the MDIO and MDC serial interface. The functional and electrical properties of this management interface comply with IEEE 802.3, Section 22 and also support MDC clock rates up to 25 MHz. DAC symbols. to The digital-to-analog converter (DAC) transmits PAM3, MLT3, and Manchester coded la The transmit DAC performs signal wave shaping that reduces electromagnetic interference (EMI). The transmit DAC uses voltage driven output with internal terminations and hence does not or s in gu require external components or magnetic supply for operation. ADC lf Each receive channel has its own analog-to-digital converter (ADC) that samples the incoming en tia data on the receive channel and feeds the output to the digital data path. id ADAPTIVE EQUALIZER nf The digital adaptive equalizer removes inter-symbol interference (ISI) created by the channel. co The equalizer accepts sampled data from the analog-to-digital converter (ADC) on each channel and produces equalized data. The coefficients of the equalizer are adaptive to accommodate varying conditions of cable quality and cable length. 12 YT8010 Datasheet ECHO-CANCELLER The echo impairment is caused on each channel because of the bidirectional transceiver in 100BASE-T1 mode. An echo canceller is added to remove this impairment from the ADC output. The echo canceler coefficients are adaptive to manage the varying echo impulse responses caused by different channels, transmitters, and environmental conditions. to CLOCK RECOVERY la The clock recovery block creates the transmit and receive clocks for 100BASE-T1 the two ends of the link perform loop timing. One end of the link is configured as the master, and the other is in gu configured as the slave. The master transmit and receive clocks are locked to the 25 MHz crystal input. The slave transmit and receive clocks are locked to the incoming receive data stream. lf or s Loop timing allows for the cancellation of echo. LINK MONITOR tia Description about link status in different working mode. en In 100BASE-T1 mode, after receiver synchronizes to link partner’s transmit signal and finishes local training process, local receive status will be good. Phy will monitor local receive status id continuously. Local receive status should be good for at least 1.8us in 100BASE-T1 mode, then link monitor enters link pass status. Accordingly, if Local receive status is bad then link monitor nf enters link fail status immediately. co Link status can be read in mii reg address 0x1h, bit2. POLARITY DETECTION A ND AUTO CORRECTION YT8010 can detect and correct two types of cable errors: swapping of pairs within the UTP cable and swapping of wires within a pair. 13 YT8010 Datasheet 5 OPERATIONAL DESCRIPTION RESET YT8010 have a hardware reset pin(RESET_N) which is low active. RESET_N should be active for at least 5us to make sure all internal logic is reset to a known state. Hardware reset should be applied after power up including wakeup from sleep mode. RESET_N is also used as enable for power on strapping. During RESET_N is active, YT8010 latches input value on RX_DV and RXD[3:0] as strapping[4:0]. Strapping[4:0] is used as configuration to information which provides flexibility in application without mdio access. YT8010 also provides two software reset control registers which are used to reset all internal la logic except some mdio configuration registers. For detailed information about what register will in gu be reset by software reset, please refer to register table. Configure bit 15 of lds mii register(address 0x0) or mii register(address 0x0) to 1 to enable software reset. These two bits or s are self-clear after reset process is done. PHY ADDRESS lf For YT8010, Strapping[4] is used to generate phy address. Phy address is Strapping[4]+1. For tia example, If strapping[4] is 1’b1, then phy address is 2. YT8010 and YT8050 always response to phy address 0. It also has another broadcast phy address en which is configurable through mdio. Bit[4:0] of extended register(address 0x0) is broadcast phy address and its default value is 5’b11111. Bit[5] of extended register(address 0x0) is enable id control for broadcast phy address and its default value is 1’b1. nf XMII INTERFACE co YT8010 support 4 kinds of MII related interfaces: MII, RMII, RGMII and REMII. MII The Media Independent Interface (MII) is the digital data interface between the MAC and the physical layer that can be enabled when the device is functioning in 100BASE-T1 mode. The original MII transmit signals include TX_EN, TXC, TXD[3:0], and TX_ER. The receive signals include RX_DV, RXC, RXD[3:0], and RX_ER. The media status signals include CRS and COL. Due to pincount limitations, the YT8010 supports a subset of MII signals. This subset includes all MII signals except TX_ER, RX_ER, CRS and COL. For 100M application, TXC and RXC are 25MHz; for 10M application, TXC and RXC are 2.5MHz. TXC and RXC are output in this case. 14 in gu la Figure . connection diagram of MII to YT8010 Datasheet RMII Reduced media-independent interface (RMII) is a standard which was developed to reduce the number of signals required to connect a PHY to a MAC. If this interface is active, the number or s of data signal pins required to and from the MAC is reduced to half by doubling clock speed compared to MII. It has 7 signals: REF_CLK, TX_EN, TXD[1:0], RX_DV and RXD[1:0]. In YT8010/YT8050, we use TXC as REF_CLK. For 100M application, REF_CLK is 50MHz; for 10M lf application, REF_CLK is still 50MHz, data will be duplicated for 10 times in 20ns cycles. YT8010/ tia supports two types of connection method; 1. RMII1 mode: This is fully conforming to RMII standard. YT8010/YT8050 can use clock from TXC as reference clock for pll. In this case, 25MHz en crystal at XI/XO is not needed. Configure bit 6 of extended register(address 0h50) to 1 to enable this feature. 2. RMII2 mode: TXC will be 50MHz output to MAC, this can save one 50MHz clock nf id source. co RXDV RXDV RXD[1:0] RXD[1:0] TXD[1:0] TXD[1:0] PHY MAC TXEN TXEN REF_CLK TXC XO XI 25MHz XTAL 50MHz XTAL Figure .connection diagram of RMII1(with 25MHz and 50MHz clock) 15 YT8010 Datasheet RXDV RXDV RXD[1:0] RXD[1:0] TXD[1:0] TXD[1:0] PHY MAC TXEN TXEN REF_CLK TXC XO XI 50MHz XTAL RXDV in gu la to Figure .connection diagram of RMII1(with 50MHz clock only) RXDV RXD[1:0] RXD[1:0] TXD[1:0] TXD[1:0] PHY MAC TXEN REF_CLK or s TXC XO TXEN XI lf 25MHz XTAL tia Figure .connection diagram of RMII2 en RGMII Reduced gigabit media independent interface is a subset of GMII which is used for gigabit id Ethernet. For 100M/10M application, RGMII is similar to MII. The only difference is that nf tx_er/rx_er is transmitted by tx_en/rx_dv on the falling edge of clock. TXD[3:0] and RXD[3:0] will be duplicated on both rising and falling edge of clock. For 100M application, TXC and RXC are co 25MHz; for 10M application, TXC and RXC are 2.5MHz. RXC RXC RXDV RXDV RXD[3:0] RXD[3:0] PHY MAC TXC TXC TXEN TXEN TXD[3:0] XO TXD[3:0] XI 25MHz XTAL 16 YT8010 Datasheet Figure .connection diagram of RGMII REMII INTERFACE Reverse media independent interface is the opposite of MII interface. The only difference is the direction of tx clock and rx clock. For MII, tx clock and rx clock are output; for REMII, tx clock and rx clock are input. REMII interface are used for back to back connection of two phys. RXC RXDV RXD[3:0] to MII TXC TXEN TXD[3:0] PHY PHY TXEN TXD[3:0] XI 25MHz XTAL RXDV RXD[3:0] or s XO RXC in gu TXC la REMII co nf id en tia lf Figure .connection diagram of REMII 17 YT8010 Datasheet SQI YT8010 provides a method to monitor quality of link. By reading extended register mse(address 0h1005), we can obtain SNR during following steps. Read register mse[14:0] b) Calculate SNR = 10*log10(32768/(3*mse)) c) Average over 200 readings A= avg(SNR) d) Rank the link quality iii. SQI = 3 when 15 < A < 18 iv. SQI = 2 when 15 < A < 18 v. SQI = 1 when 11 < A < 14 la SQI = 4 when 18 < A < 23 in gu ii. or s SQI = 5 when A > 23 en LOOPBACK MODE tia lf i. to a) id There are three loopback modes in YT8010. INTERNAL LOOP BACK: nf In Internal loopback mode, YT8010 feed transmit data to receive path in chip. co Configure bit 14 of mii register(address 0h0) to enable internal loopback mode. For 10Base-T and 100Base-Tx, YT8050 feeds digital dac data to adc directly. For HR10/HR100, YT8010 feeds digital pcs transmit data to pcs receiver directly. 18 YT8010 Datasheet DIGITAL PMATX PCS-TX 10Base-T/ 100Base-Tx MUX HR10/ HR100 MII RX PCS-RX TRX_P0 TRX_N0 ANALOG TRX_P1 DIGITAL PMARX MUX MII TX TRX_N1 to Figure . Internal loopback EXTERNAL LOOPBACK la In external loopback mode, YT8010 feed transmit data to receive path out of chip. For 100 TRX_P0/N0 unconnected. TRX_P0 TRX_N0 ANALOG TRX_P1 DIGITAL PMARX PCS-RX TRX_N1 tia lf MII RX DIGITAL PMATX PCS-TX or s MII TX in gu BASE-T1 configure bit 12 of extended register(address 0h4000) and just leave TRX_P0/N0 and en Figure . external loopback id REMOTE LOOPBACK In remote loopback mode, YT8010 feed MII receive data to transmit path in chip. Configure bit nf 11 of extended register(address 0h4000) and for TRX interface, just connect to link partner co normally. MII TX PCS-TX TRX_P0 DIGITAL PMATX TRX_N0 ANALOG TRX_P1 MII RX PCS-RX DIGITAL PMARX TRX_N1 Figure . external loopback 19 YT8010 Datasheet MASTER-SLAVE CONFIGURATION Master and slave configuration is from hardware strapping or in force mode, it comes from bit 3 of lds mii reg(address 0h0). INTERRUPT Interrupt shares same pin with LED. Interrupt function can be selected by configuring bit 14 of extended register(address 0h4001). la in gu Every interrupt has a corresponding mask bit and interrupt bit. to The polarity of interrupt is configurable by accessing bit 4 of mii reg(address 0h10). Please refer to mii register map(address 0h12, 0h13, 0h16 and 0h17) for detailed information. POWER SAVING or s YT8010 supports standby mode and sleep mode to save power. In standby mode, PHY turn off analog ADC, DAC, and PLL. All digital logic is gated except MDIO register access. INH pin is high and power supply is still on. The link is down in standby mode, lf YT8010 can recover from standby mode rapidly. Write bit 11 of mii address 0x0h to 1’b1 to enter tia standby mode. To exit standby mode, write the same bit to 1’b0. In standby mode, the power consumption of YT8010 is less than mw. en In sleep mode, PHY turn off all power supply except always on 3.3v supply. The only working block is analog INH generation circle and power detect circle. In this mode, INH pin is low. There id are three ways to enter sleep mode: nf 1. Pull down local EN pin from high. co 2. Write bit12 of extended 0x1007 register. 3. Use TC10 standard to control remote phy to enter sleep mode. There are also three ways to exit sleep mode: 1. Pull up local En pin from low. 2. Pull up local Wake pin from low. 20 YT8010 Datasheet 3. Inject wake up signal which amplitude at txp/txn for more than 100us to wake up phy remotely. Please refer to following chapter for detailed information about remote control. In sleep mode, the power consumption of YT8010 is lower than 50uw. APPLICATION NOTES ABOUT SLEEP MODE 3.3V Power Unit MCU EN Wake PHY or s INH in gu alwayson 3.3V la to 12V or higher figure. Hardware connection description (MCU don’t support Sleep and Wakeup function) lf When MCU don’t support sleep and wakeup function,YT8010 can take the responsibility of power control. If MCU decides to enter sleep mode,it can pull down EN pin or configure tia sleep_mode_en register through mdio, then INH goes down and power supply for MCU and phy will turn off except always on 3.3V power supply. The whole system can be wakeup 3.3V id Power Unit MCU co nf 12V or higher en remotely by injecting wakeup pulse on txp/txn or pulling up wake pin. alwayson 3.3V EN alwayson 3.3V INH PHY Wake figure. Hardware connection description (MCU support Sleep and Wakeup function) When MCU support sleep and wakeup function,INH pin only control the power supply of phy。If MCU decides to enter sleep mode，it can pull down En pin or configure sleep_mode_en register through mdio, then INH goes down and power supply for phy will 21 YT8010 Datasheet turn off except always on 3.3V power supply. MCU can pull up En/Wake pin to wakeup phy or phy will be wakeup remotely and send out a wake interrupt to MCU. Following is an example of INH control application. Only AVDD_PPD is connected to always on 3.3V power and other power pins are controlled by INH pin. 3.3V Power In Controllable PMU PMU Enable AVDD_PPD INH AVDD_HV_MAIN to 3.3V Power In in gu la AVDD_HV_TX OVDD OVDD_RGMII or s OVDD_RMII tia lf Figure. Power solution for INH control en SLEEP NEGOTIATION PR OCESS co nf id Following figure gives the state transition in sleep negotiation process。 22 YT8010 Datasheet STANDBY_MODE Sleep_fail