NSi6602
High Reliability Isolated Dual-Channel
Gate Driver
Datasheet (EN) 1.3
Product Overview
NSI6602 is a family of high reliability isolated dualchannel gate driver ICs which can be designed to drive
power transistor up to 2MHz switching frequency. Each
output could source 4A and sink 6A peak current with
fast 25ns propagation delay and 5ns maximum delay
matching.
The NSI6602 provides 2500Vrms isolation per UL1577 in
5*5mm LGA13 package, 3000Vrms isolation in SOIC-16
narrow package, and 5700Vrms isolation in SOIC-16 or
SOIC-14 wide package. System robustness is supported
by 150kV/us typical common-mode transient immunity
(CMTI).
The driver operates with a maximum supply voltage of
28V, while the input-side accepts from 2.7V to 5V supply
voltage. Under voltage lock-out (UVLO) protection is
supported by all the power supply voltage pins.
Safety Regulatory Approvals
UL recognition:
LGA13: 2500Vrms for 1 minute per UL1577
SOP16/SOP14(300mil): 5700Vrms for 1 minute per
UL1577
SOP16(150mil): 3000Vrms for 1 minute per UL1577
DIN VDE V 0884-11:2017-01
CSA component notice 5A
With all these excellent features, NSI6602 is suitable for
high reliability, power density and efficiency switching
power system.
CQC certification per GB4943.1-2011
Key Features
Isolated DC-DC and AC-to-DC power supplies in server,
telecom, and industry
Isolated dual channel driver
DC-to-AC solar inverters
Input side supply voltage: 2.7V to 5.5V
Motor drives and EV charging
Driver side supply voltage: up to 25V with UVLO
UPS and battery chargers
4A peak source and 6A peak sink output
Functional Block Diagram
High CMTI: ±150kV/us typical
Applications
25ns typical propagation delay
5ns maximum delay matching
6ns maximum pulse width distortion
Programmable deadtime
Accepts minimum input pulse width 20ns
Operation temperature: -40℃~125℃
Copyright © 2020, NOVOSENSE
Figure 0.1 NSI6602 Block Diagram
Page 1
NSi6602
Datasheet (EN) 1.3
INDEX
1.
PIN CONFIGURATION AND FUNCTIONS................................................................................................................................... 3
2.
ABSOLUTE MAXIMUM RATINGS.............................................................................................................................................. 4
3.
RECOMMENDED OPERATING CONDITIONS............................................................................................................................. 5
4.
THERMAL INFORMATION......................................................................................................................................................... 5
5.
SPECIFICATIONS........................................................................................................................................................................ 5
5.1.
5.2.
5.3.
5.4.
6.
ELECTRICAL CHARACTERISTICS.......................................................................................................................................... 5
SWITCHING CHARACTERISTICS.......................................................................................................................................... 7
TYPICAL PERFORMANCE CHARACTERISTICS......................................................................................................................7
PARAMETER MEASUREMENT INFORMATION..................................................................................................................11
HIGH VOLTAGE FEATURE DESCRIPTION..................................................................................................................................14
6.1.
6.2.
6.3.
7.
INSULATION CHARACTERISTICS....................................................................................................................................... 14
SAFETY-LIMITING VALUES................................................................................................................................................15
SAFETY-RELATED CERTIFICATIONS................................................................................................................................... 18
FUNCTION DESCRIPTION........................................................................................................................................................ 19
7.1. OVERVIEW........................................................................................................................................................................19
7.2. VDDI, VDDA/B, AND UNDER VOLTAGE LOCK OUT (UVLO)...............................................................................................19
7.3. TRUTH TABLES..................................................................................................................................................................20
7.4. PROGRAMMABLE DEADTIME (DT) PIN............................................................................................................................20
7.4.1.
TYING THE DT PIN TO VDDI...................................................................................................................................... 20
7.4.2.
DT PIN LEFT OPEN OR CONNECTED TO A PROGRAMMING RESISTOR BETWEEN DT AND GND PINS......................20
8.
APPLICATION NOTE.................................................................................................................................................................22
8.1.
8.2.
8.3.
9.
TYPICAL APPLICATION CIRCUIT........................................................................................................................................ 22
ESD PROTECTION............................................................................................................................................................. 21
LAYOUT CONSIDERATIONS...............................................................................................................................................22
PACKAGE INFORMATION........................................................................................................................................................ 23
10.
ORDERING INFORMATION..................................................................................................................................................27
11.
DOCUMENTATION SUPPORT.............................................................................................................................................. 27
12.
TAPE AND REEL INFORMATION.......................................................................................................................................... 28
13.
REVISION HISTORY.............................................................................................................................................................. 30
Copyright © 2020, NOVOSENSE
Page 2
NSi6602
Datasheet (EN) 1.3
1. Pin Configuration and Functions
Figure 1.1 NSI6602 LGA13 Package
Figure 1.2 NSI6602 SOW16/SOP16 Package
Figure 1.3 NSI6602 SOW14 Package
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Page 3
NSi6602
Datasheet (EN) 1.3
Table 1.1 NSI6602A Pin Configuration and Description
PIN NO.
SYMBOL
FUNCTION
LGA13
SOP16
SOP14
1
4
4
GND
Input-side ground reference.
2
1
1
INA
TTL/CMOS compatible input signal for channel A with internal pull down
to GND. It is recommended to connect this pin to GND if not used.
3
2
2
INB
TTL/CMOS compatible input signal for channel B with internal pull down
to GND. It is recommended to connect this pin to GND if not used.
4, 7
3, 8
3, 8
VDDI
Input-side supply voltage. It is recommended to place a bypass capacitor
from this pin to GND as close as possible.
5
5
5
DISABLE
Disables the isolator inputs and driver outputs if asserted high, enables if
asserted low or left open. It is recommended to connect this pin to GND
if not used.
6
6
6
DT
Programmable deadtime. Connect DT to VDDI allows the outputs to
overlap. Place a 1kΩ to 200kΩ resistor (RDT) between DT and GND to
adjusts deadtime following: tDT (ns) = 10 x RDT (kΩ). It is recommended to
parallel a low ESR capacitor, e.g., 2.2nF or above.
8
9
9
GNDB
Ground for output channel B
9
10
10
OUTB
Output gate driver for channel B
10
11
11
VDDB
Supply voltage for channel B
11
14
12
GNDA
Ground for output channel A
12
15
13
OUTA
Output gate driver for channel A
13
16
14
VDDA
Supply voltage for channel A
/
7,12,13
7
NC
Not connected
2. Absolute Maximum Ratings
Parameters
Input Side Supply Voltage
Output Side Supply Voltage
Input Signal Voltage
Output Signal Voltage
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Symbol
Min
Max
VDDI to GNDI
-0.3
6
V
VDDA to GNDA, VDDB to GNDB
-0.3
30
V
INA, INB, DIS, DT to GNDI
-0.3
VVDDI+0.3
V
INA, INB, DIS, DT to GNDI, Transient for 50ns
-5
VVDDI+0.3
V
OUTA to GNDA, OUTB to GNDB
-0.3
OUTA to GNDA, OUTB to GNDB, Transient for
200ns
-2
VVDDA+0.3
VVDDB+0.3
VVDDA+0.3
VVDDB+0.3
Unit
V
V
Page 4
NSi6602
Datasheet (EN) 1.3
Parameters
Channel A to Channel B Voltage
Symbol
Min
Max
Unit
GNDA to GNDB in LGA13 package
700
V
GNDA to GNDB in SOP16&SOW16 package
1500
V
GNDA to GNDB in SOW14 package
1850
V
Junction Temperature
TJ
-40
150
℃
Storage Temperature
Tstg
-65
150
℃
HBM (all pins)
-4000
4000
V
CDM
-1500
1500
V
Electrostatic discharge
3. Recommended Operating Conditions
Parameters
Symbol
Min
Max
Unit
Input Side Supply Voltage
VDDI to GNDI
3
5.5
V
Driver Side Supply Voltage
VDDA to GNDA,
VDDB to GNDB
7
25
V
Input Signal Voltage
INA, INB, DIS, DT
0
VVDDI
V
Junction Temperature
TJ
-40
150
℃
Ambient Temperature
Ta
-40
125
℃
Comments
4. Thermal Information
Parameters
Symbol
LGA13
Junction-to-ambient thermal resistance1)
RJA
209.5
Junction-to-case(top) thermal resistance2)
RJC（top）
Junction-to-top characterization parameter3)
Junction-to-board characterization parameter3)
SOW16/
SOP16
Unit
97.0
150.5
℃/W
48.4
23.3
21.2
℃/W
ΨJT
41.8
35.8
52.3
℃/W
ΨJB
31.9
39.0
55.6
℃/W
SOW14
1)
Standard JESD51-3 Low Effective Thermal Conductivity Test Board (1s) in an environment described in JESD51-2a.
2)
Standard JESD51-3 Low Effective Thermal Conductivity Test Board (1s) by transient dual interface test method described in
JESD51-14.
3)
Obtained by Simulating in an environment described in JESD51-2a.
5. Specifications
5.1. Electrical Characteristics
VDDI=3.3V or 5V, VDDA=VDDB=12V for NSI6602A/B, VDDA=VDDB=15V for NSI6602C, Ta=-40℃ to 125℃. Unless otherwise noted,
Typical values are at Ta=25℃
Parameter
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Symbol
Min
Typ
Max
Unit
Comments
Page 5
NSi6602
Datasheet (EN) 1.3
Parameter
Symbol
Min
Typ
Max
2
Unit
Comments
Input Side Supply
VDDI Quiescent Current
IVDDIQ
0.75
VDDI Operation Current
IVDDI
1.8
mA
INA=0, INB=0
mA
Input frequency
500kHz, COUTA/B=15pF
VDDI UVLO Rising Threshold
VVDDI_ON
2.35
2.55
2.75
V
VDDI UVLO Falling Threshold
VVDDI_OFF
2.15
2.35
2.55
V
VDDI UVLO Hysteresis
VVDDI_HYS
0.2
V
Output Side Supply
Output Side Supply Voltage
VVDDA, VVDDB
VDDA/B Quiescent Current, per Channel
IVDDAQ, IVDDBQ
1.6
VDDA/B Operation Current, per Channel
IVDDA, IVDDB
3.2
25
V
Minimum defined by
UVLO
2.5
mA
INA=0, INB=0,
VDDx=12V for 6V,8V
UVLO; VDDx=15V for
13V UVLO
mA
100pF, 500kHz,
VDDx=12V for 6V,8V
UVLO; VDDx=15V for
13V UVLO
NSI6602A (6V)
VDDA/B UVLO Rising Threshold
VVDDA_ON, VVDDB_ON
5.7
6.15
6.5
V
VDDA/B UVLO Falling Threshold
VVDDA_OFF, VVDDB_OFF
5.4
5.85
6.2
V
VDDA/B UVLO Hysteresis
VVDDA_HYS, VVDDB_HYS
VDDA/B UVLO Rising Threshold
VVDDA_ON, VVDDB_ON
8.1
8.5
8.9
V
VDDA/B UVLO Falling Threshold
VVDDA_OFF, VVDDB_OFF
7.6
8.0
8.4
V
VDDA/B UVLO Hysteresis
VVDDA_HYS, VVDDB_HYS
VDDA/B UVLO Rising Threshold
VVDDA_ON, VVDDB_ON
12.7
13.2
13.7
V
VDDA/B UVLO Falling Threshold
VVDDA_OFF, VVDDB_OFF
11.7
12.2
12.7
V
VDDA/B UVLO Hysteresis
VVDDA_HYS, VVDDB_HYS
1
V
Input Pin Pull Down Resistance, INA, INB,
RINA_PD, RINB_PD
100
kΩ
Input Pin Pull Down Resistance, DIS (EN)
RDIS_PD
100
kΩ
Logic High Input Threshold
VINA_H, VINB_H, VDIS_H
1.7
Logic Low Input Threshold
VINA_L, VINB_L, VDIS_L
0.3
V
0.5
NSI6602B (8V)
V
NSI6602C (13V)
Input Side Characteristic
Input Hysteresis
VINA_HYS, VINB_HYS,
VDIS_HYS
0.8
2
V
1.1
V
0.6
V
Output Side Characteristic
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NSi6602
Datasheet (EN) 1.3
Parameter
Symbol
Min
Typ
Logic High Output Voltage
VVDDA-VOUTA_H,
VVDDB-VOUTB_H
0.34
Logic Low Output Voltage
VOUTA_L, VOUTB_L
55
Output Sink Resistance
ROUTA_L, ROUTB_L
Output Source Resistance
Max
Unit
Comments
V
Iout = 100mA
mV
Iout = -100mA
0.55
Ω
Iout = 100mA
ROUTA_H, ROUTB_H
3.4
Ω
Iout = -100mA
Peak Output Sink Current
IOUTA-, IOUTB-
6
A
Peak Output Source Current
IOUTA+, IOUTB+
4
A
5.2. Switching Characteristics
VDDI=3.3V or 5V, VDDA=VDDB=12V for NSI6602A/B, VDDA=VDDB=15V for NSI6602C, Ta=-40℃ to 125℃.
Parameter
Minimum Pulse Width
Propagation Delay
Symbol
Min
tPWmin
tPDHL, tPDLH
10
Typ
Max
Unit
10
15
ns
25
35
ns
Comments
COUTA/B = 0 pF
Pulse Width Distortion |tPDLH-tPDHL|
tPWD
6
ns
Channel to Channel Delay Matching
tDMLH, tDMHL
5
ns
200
240
ns
tDT(ns)=10*R(kΩ); Test for R = 20kΩ
Programmed Deadtime
tDT
Output Rise Time (20% to 80%)
tR
7
16
ns
COUTA/B=1.8nF, verified by design
Output Fall Time (90% to 10%)
tF
6
12
ns
COUTA/B=1.8nF, verified by design
Shutdown Time from Disable True
tDIS
40
ns
Recovery Time from Disable False
tEN
40
ns
VDDI Power-up Time Delay
160
tstart_VDDI
8.5
15
us
INA or INB tied to VDDI
tstart_VDDA,
tstart_VDDB
18
30
us
INA or INB tied to VDDI
(Time from VDDI = VDDI_ON to OUTA/B
= INA/B)
VDDA/B Power-up Time Delay
(Time from VDDA/B = 2V to OUTA/B =
INA/B)
Common Mode Transient Immunity
CMTI
COUTA/B=1.8nF
100
150
kV/us
verified by design
5.3. Typical Performance Characteristics
VDDI = 3.3 V, VDDA=VDDB=12V for NSI6602A/B, VDDA=VDDB=15V for NSI6602C, TA = 25℃. Output has no load unless otherwise
noted.
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Page 7
NSi6602
Datasheet (EN) 1.3
Figure 5.1 VDDI Quiescent Current vs Temperature
Figure 5.2 VDDI Operating Current vs Temperature
Figure 5.3 VDDA/B Quiescent Current vs Temperature
Figure 5.4 VDDA/B Operating Current vs Temperature
Figure 5.5 VDDA/B Quiescent Current vs Supply Voltage
Figure 5.6 Output Resistance vs Temperature
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Page 8
NSi6602
Datasheet (EN) 1.3
Figure 5.7 Typical Rise Time & Fall Time vs Temperature
Figure 5.8 Output Peak Current vs VDDA/B Supply Voltage
Figure 5.9 VDDI UVLO Threshold vs Temperature
Figure 5.10 VDDI UVLO Hysteresis vs Temperature
Figure 5.11 6V VDDA/B UVLO Threshold vs Temperature
Figure 5.12 6V VDDA/B UVLO Hysteresis vs Temperature
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Page 9
NSi6602
Datasheet (EN) 1.3
Figure 5.13 8V VDDA/B UVLO Threshold vs Temperature
Figure 5.14 8V VDDA/B UVLO Hysteresis vs Temperature
Figure 5.15 INA/INB/DIS Threshold vs Temperature
Figure 5.16 INA/INB/DIS Hysteresis vs Temperature
Figure 5.17 Propagation Delay vs Temperature
Figure 5.18 Propagation Delay vs VDDA/B
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Page 10
NSi6602
Datasheet (EN) 1.3
Figure 5.19 Propagation Delay Matching vs Temperature
Figure 5.20 Pulse Width Distortion vs Temperature
Figure 5.21 Disable & Enable Time vs Temperature
Figure 5.22 Deadtime (RDT=20kΩ) vs Temperature
5.4. Parameter Measurement Information
Figure 5.23 Propagation Delay and Channel to Channel Delay Match Time, connect DT to VDDI
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NSi6602
Datasheet (EN) 1.3
Figure 5.24 Channel to Channel Delay Match Test Circuit
Figure 5.25 Disable Time and Enable Time
Figure 5.26 Deadtime, Determined by RDT
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Page 12
NSi6602
Datasheet (EN) 1.3
Figure 5.27 Common-Mode Transient Immunity Test Circuit
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Page 13
NSi6602
Datasheet (EN) 1.3
6. High Voltage Feature Description
6.1. Insulation Characteristics
Description
Test Condition
Symbol
Value
Unit
LGA 13
SOW16/14
SOP16
Min. External Air Gap (Clearance)
CLR
3.5
8
4
mm
Min. External Tracking (Creepage)
CPG
3.5
8
4
mm
Distance through the Insulation
DTI
32
CTI
>600
Comparative Tracking Index
DIN EN 60112 (VDE 0303-11)
Material Group
IEC 60112
um
V
I
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150Vrms
I to III
I to IV
I to IV
For Rated Mains Voltage ≤ 300Vrms
I to II
I to IV
I to III
For Rated Mains Voltage ≤ 600Vrms
I
I to IV
I to II
For Rated
1000Vrms
/
I to III
/
Mains
Voltage
≤
Insulation Specification per DIN VDE V 0884-11:2017-011)
Climatic Category
40/125/21
Pollution Degree
per DIN VDE 0110, Table 1
Maximum Working Isolation Voltage
AC voltage
2
VIOWM
560
1000
700
VRMS
792
1414
990
VDC
VIORM
792
1414
990
Vpeak
Vpd (m)
1188
/
1485
Vpeak
Vpd (m)
/
2652
/
Vpeak
Vini. a = VIOTM, Vpd(m) = VIORM × 1.3,
V pd (m)
1030
/
1287
Vpeak
tini = 60 sec, tm = 10 sec, qpd ≤ 5 pC
Vini. a = VIOTM, Vpd(m) = VIORM × 1.6,
V pd (m)
/
2263
/
Vpeak
tini = 60 sec, tm = 10 sec, qpd ≤ 5 pC
V pd (m)
950
1697
1188
Vpeak
DC voltage
Maximum
Voltage
Repetitive
Isolation
Input to Output Test Voltage, Method
B1
Vini. b = VIOTM, Vpd(m) = VIORM × 1.5,
tini = tm = 1 sec, qpd ≤ 5 pC,
100% production test
Vini. b = VIOTM, Vpd(m) = VIORM ×
1.875,
tini = tm =1 sec, qpd≤ 5 pC,
100% production test
Input to Output Test Voltage, Method
A.
After
Environmental
Tests
Subgroup 1
Input to Output Test Voltage, Method
A. After Input and Output Safety Test
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Vini. a = VIOTM, Vpd(m) = VIORM × 1.2,
Page 14
NSi6602
Datasheet (EN) 1.3
Description
Test Condition
Symbol
Maximum Transient Isolation Voltage
tini = 60 sec, tm = 10 sec, qpd ≤ 5 pC
t = 60 sec
VIOTM
3535
8000
4242
Vpeak
Maximum Surge Isolation Voltage
Test method per IEC62368-1,
VIOSM
3500
/
6000
Vpeak
/
6250
/
Vpeak
Subgroup 2 and Subgroup 3
Value
Unit
1.2/50us waveform, VTEST = 1.3 ×
VIOSM
Test method per IEC62368-1,
1.2/50us waveform, VTEST = 1.6 ×
VIOSM
Isolation Resistance
VIO = 500 V, Tamb = TS
RIO
VIO = 500 V, 100 ℃ ≤ Tamb ≤ 125 ℃
Isolation Capacitance
f = 1MHz
CIO
VTEST = 1.2 × VISO, t = 1 sec,
VISO
>109
Ω
>1011
Ω
1.2
pF
Insulation Specification per UL1577
Withstand Isolation Voltage
2500
5700
3000
Vrms
100% production test
1)
This coupler is suitable for “safe electrical insulation” only within the safety ratings. Compliance with the safety ratings shall be
ensured by means of suitable protective circuits.
6.2. Safety-Limiting Values
Basic isolation safety-limiting values as outlined in VDE-0884-11 of NSI6602x-xLAR (LGA13)
Description
Safety Supply Power
Safety Supply Current
Test Condition
Side
Value
Input
12
mW
Driver A, Driver B
293
mW
Total
598
mW
RθJA = 209.5 ℃ / W1), VDDA/B = 12V, TJ = 150 ℃ , TA =
25 ℃
Driver A, Driver B
24.4
mA
RθJA = 209.5 ℃ / W1), VDDA/B = 25V, TJ = 150 ℃ , TA =
25 ℃
Driver A, Driver B
11.7
mA
150
℃
RθJA = 209.5 ℃/W1), TJ = 150 ℃, TA = 25 ℃
Safety Temperature2)
Unit
1)
Calculate with the junction-to-air thermal resistance, RθJA, of LGA13 package (Thermal Information Table) which is that of a
device installed on a low effective thermal conductivity test board (1s) according to JESD51-3.
2)
The maximum safety temperature has the same value as the maximum junction temperature (TJ) specified for the device.
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NSi6602
Datasheet (EN) 1.3
Figure 6.1 NSI6602x-DLAR Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN VDE V 0884-11
Reinforced isolation safety-limiting values as outlined in VDE-0884-11 of NSI6602x-xSWxR (SOW16/SOW14)
Description
Safety Supply Power
Safety Supply Current
Test Condition
Side
Value
Input
12
mW
Driver A, Driver B
638
mW
Total
1288
mW
RθJA = 97 ℃/ W1), VDDA/B = 12V, TJ = 150 ℃, TA = 25 ℃
Driver A, Driver B
53.1
mA
RθJA = 97 ℃/ W1), VDDA/B = 25V, TJ = 150 ℃, TA = 25 ℃
Driver A, Driver B
25.5
mA
150
℃
RθJA = 97 ℃/W1), TJ = 150 ℃, TA = 25 ℃
Safety Temperature2)
Unit
1)
Calculate with the junction-to-air thermal resistance, RθJA, of SOW16/SOW14 package (Thermal Information Table) which is that
of a device installed on a low effective thermal conductivity test board (1s) according to JESD51-3.
2)
The maximum safety temperature has the same value as the maximum junction temperature (TJ) specified for the device.
Figure 6.2 NSI6602x-DSWR Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN VDE V 0884-11
Basic isolation safety-limiting values as outlined in VDE-0884-11 of NSI6602x-xSPNR (SOP16)
Description
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Test Condition
Side
Value
Unit
Page 16
NSi6602
Safety Supply Power
Safety Supply Current
Datasheet (EN) 1.3
Input
12
mW
Driver A, Driver B
409
mW
Total
830
mW
RθJA = 150.5 ℃/ W1), VDDA/B = 12V, TJ = 150 ℃, TA =
25 ℃
Driver A, Driver B
34.0
mA
RθJA = 150.5 ℃/ W1), VDDA/B = 25V, TJ = 150 ℃, TA =
25 ℃
Driver A, Driver B
16.3
mA
150
℃
RθJA = 150.5 ℃/W1), TJ = 150 ℃, TA = 25 ℃
Safety Temperature2)
1)
Calculate with the junction-to-air thermal resistance, RθJA, of SOP16 package (Thermal Information Table) which is that of a
device installed on a low effective thermal conductivity test board (1s) according to JESD51-3.
2)
The maximum safety temperature has the same value as the maximum junction temperature (TJ) specified for the device.
Figure 6.3 NSI6602x-DSWR Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN VDE V 0884-11
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Page 17
NSi6602
Datasheet (EN) 1.3
6.3. Safety-Related Certifications
The NSI6602x-xLAR(LGA13) are approved or pending approval by the organizations listed in table.
CUL
UL1577
Component
Recognition Program
Single Protection, 2500Vrms
Isolation voltage
VDE
CQC
Approved
under
CSA
Component
Acceptance
Notice 5A
DIN VDE V 0884-11: 201701
Certified by CQC11-4715432012
Single Protection,2500Vrms
Isolation voltage
Basic Insulation at
GB4943.1-2011
Basic insulation
VIORM=792VPEAK
VIOSM=3500VPEAK
VIOTM=3535VPEAK
File (pending)
File (pending)
File (pending)
File (pending)
The NSI6602x-xSWxR(SOW16/SOW14) are approved or pending approval by the organizations listed in table.
CUL
UL
1577
Component
Recognition Program
Single Protection, 5700Vrms
Isolation voltage
VDE
CQC
Approved
under
CSA
Component
Acceptance
Notice 5A
DIN VDE V 0884-11: 201701
Certified by CQC11-4715432012
Single Protection, 5700Vrms
Isolation voltage
Reinforced insulation at
GB4943.1-2011
Reinforced insulation
VIORM=1414VPEAK
VIOSM=6250VPEAK
VIOTM=8000VPEAK
E500602
E500602
Certification No. 40052820
CQC20001264939
The NSI6602x-xSPNR(SOP16) are approved or pending approval by the organizations listed in table.
CUL
UL
1577
Component
Recognition Program
Single Protection, 3000Vrms
Isolation voltage
VDE
CQC
Approved
under
CSA
Component
Acceptance
Notice 5A
DIN VDE V 0884-11(VDE V
0884-11):2017-01
Certified by CQC11-4715432012
Single Protection, 3000Vrms
Isolation voltage
Reinforced insulation at
GB4943.1-2011
Basic insulation
VIORM=990VPEAK
VIOSM=6000VPEAK
VIOTM=4242VPEAK
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Copyright © 2020, NOVOSENSE
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Page 18
NSi6602
Datasheet (EN) 1.3
7. Function Description
7.1. Overview
NSI6602 is a high reliability dual channel isolated gate driver which could be designed in variety switching power and motor drive
topologies. NSI6602 has some useful protections, such as under voltage lock-out (UVLO) for both input and output supply, a disable
pin, dead-time control, default low output as input is floating. The functional circuit block diagram is shown as below:
Figure 7.1 Functional Block Diagram
7.2. Under Voltage Lock Out (UVLO)
The NSI6602 has an internal under voltage lock out (UVLO) protection on both input and output supply circuit blocks. The driver
output is held low by an active clamp circuit when the supply voltage of VDDI or VDDA/VDDB is lower than VVDD_ON at power-up
status or lower than VVDD_OFF after power-up, regardless of the status of the input pins.
The VDDI and VDDA/B ULVO protections have hysteresis (VVDD_HYS) to prevent chatter noise from VDD supply and allow small drops in
supply power which are usually happened in startup.
Copyright © 2020, NOVOSENSE
Page 19
NSi6602
Datasheet (EN) 1.3
7.3. Input and Output Logic Table
When the device is power up, setting the DIS pin high can shut down both outputs simultaneously. Left open or grounding the DIS
pin can allow the device operating normally.
Table 7.1 Output status vs. Input and Power status
VDDI
status
VDDA/B
status
DIS
PU
PU
PU
IN
OUT
NOTE1)
A
B
A
B
L or O
L
H
L
H
PU
L or O
H
L
H
L
PU
PU
L or O
H
H
H
H
DT pin is pulled to VDDI.
PU
PU
L or O
H
H
L
L
DT is left open or programmed with RDT.
PU
PU
L or O
L
L
L
L
PU
PU
L or O
O
O
L
L
PU
PU
H
X
X
L
L
PU
PD
X
X
X
L
L
PD
PU
X
X
X
L
L
1)
If Deadtime function is used, output transits
to high after the deadtime expires.
PD= Power Down; PU= Power Up; H= Logic High; L= Logic Low; O= Left Open; X= Irrelevant.
7.4. Programmable Deadtime (DT pin)
7.4.1.Pulling the DT Pin to VDDI
This allows outputs match inputs completely and no deadtime is asserted.
7.4.2.DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
If the DT pin is left open, the deadtime duration (tDT) is set to
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