AZ1143-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Features
Consumer Electronics
Set Top Box
DVDRW Players
Graphics Cards
ESD Protect for Transition Minimized Differential
Signaling (TMDS) channels
Protects four I/O lines
Provide ESD protection for each line to
IEC 61000-4-2 (ESD) ±18kV (air), ±16kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 6A (8/20µ
µs)
For operating voltage of 3.3V and below
Ultra low capacitance : 0.45pF typical
Fast turn-on and Low clamping voltage
Array of ESD rated diodes with internal
equivalent TVS (Transient Voltage
Suppression) diode
Simplified layout for HDMI connectors
Solid-state silicon-avalanche and active circuit
triggering technology
Green part
Applications
High Definition Multi-Media Interface (HDMI)
1.3 & 1.4 and 2.0 version
DisplayPort interface
SATA and eSATA interface
USB3.0
V-By-One
LVDS interfaces
IEEE 1394 up to 3.2 Gb/s
Ethernet port: 10/100/1000 Mb/s
Desktop and Notebooks PCs
Description
AZ1143-04F is a design which includes ESD
rated diode arrays to protect high speed data
interfaces.
The AZ1143-04F
has
been
specifically designed to protect sensitive
components which are connected to data and
transmission lines from over-voltage caused by
Electrostatic Discharging (ESD), Electrical Fast
Transients (EFT), Lightning, and Cable
Discharge Event (CDE).
AZ1143-04F is a unique design which includes
ESD rated, ultra low capacitance steering diodes
and a unique design of clamping cell which is an
equivalent TVS diode in a single package. During
transient conditions, the steering diodes direct
the transient to either the internal ESD line or to
ground line. The internal unique design of
clamping cell prevents over-voltage on the
internal ESD line and on the I/O line, which is
protecting any downstream components.
AZ1143-04F may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4
(±15kV air, ±8kV contact discharge).
Circuit Diagram
1
2
4
Pin Configuration
5
3,8
Line-1
1
10 NC
Line-2
2
9
GND
3
Line-3
4
7
NC
Line-4
5
6
NC
8
NC
GND
DFN2510P10E (Top View)
Revision 2014/10/02
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AZ1143-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNITS
Peak Pulse Current (tp= 8/20µs)
IPP
6
A
Operating Voltage (I/O pin-GND)
VDC
(GND – 0.5) to 3.6
V
ESD per IEC 61000-4-2 (Air)
18
VESD
ESD per IEC 61000-4-2 (Contact)
Lead Soldering Temperature
TSOL
kV
16
260 (10 sec.)
o
C
Operating Temperature
TOP
-55 to +85
o
Storage Temperature
TSTO
-55 to +150
o
C
C
ELECTRICAL CHARACTERISTICS
PARAMETER
Reverse Stand-Off
Voltage
Channel Leakage
Current
Reverse Breakdown
Voltage
Forward Voltage
ESD Clamping
Voltage
ESD Dynamic
Turn-on Resistance
Channel Input
Capacitance
Channel to Channel
Input Capacitance
Revision 2014/10/02
SYMBOL
VRWM
ICH-Leak
VBV
VF
Vclamp
Rdynamic
CIN
CCROSS
CONDITIONS
MIN
TYP
Pin-1,-2,-4,-5 to pin-3,-8, T=25 oC
VPin-1,-2,-4,-5 = 3.3V, VPin-3,-8 = 0V,
T=25 oC
IBV = 1mA, T=25 oC, pin-1,-2,-4,-5 to
pin-3,-8
IF = 15mA, T=25 oC, pin-3,-8 to
pin-1,-2,-4,-5
IEC 61000-4-2 +6kV, T=25 oC,
Contact mode, any I/O pin to Ground
IEC 61000-4-2, 0~+6kV, T=25 oC,
Contact mode, any I/O pin to Ground
Vpin-3,-8 = 0V, VIN = 1.65V, f = 1MHz,
T=25 oC, any I/O pin to Ground
Vpin-3,-8 = 0V, VIN = 1.65V, f = 1MHz,
T=25 oC, between I/O pins
©2014-2015 Amazing Micro.
2
MAX
UNITS
3.3
V
1.0
µA
4.5
V
0.9
1.1
V
9
V
0.24
Ω
0.45
0.65
pF
0.05
0.1
pF
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AZ1143-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Typical Characteristics
Typical Variation of CIN vs. VIN
0.8
Input Capacitance (pF)
Input Capacitance (pF)
f = 1MHz, T=25 oC,
0.09
f = 1MHz, T=25 oC,
0.7
Typical Variation of CIO-to-IO vs. VIN
0.10
0.6
0.5
0.4
0.3
0.2
0.1
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.0
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
0.00
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
Input Voltage (V)
Input Voltage (V)
Insertion Loss S21 (IO-to-GND)
Analog Cross Talk
20
0
10
Analog Cross Talk (dB)
Insertion Loss (dB)
-3
-6
-9
-12
-15
-18
-21
-24
8.1GHz : -3dB
-27
-20
-30
-40
-50
-60
-70
-30
-80
1e+8
1e+9
1e+10
1e+8
Frequency (Hz)
Transmission Line Pulsing (TLP) Current (A)
0
-10
1e+9
1e+10
Frequency (Hz)
Transmission Line Pulsing (TLP) Measurement
18
16
14
V_pulse
12
Pulse from a
transmission line
TLP_I
10
100ns
+
TLP_V
8
DUT
-
6
4
I/O to GND
2
0
0
1
2
3
4
5
6
7
8
9
10
11
Transmission Line Pulsing (TLP) Voltage (V)
Revision 2014/10/02
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AZ1143-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Applications Information
The AZ1143-04F is designed to protect four
data lines from transient over-voltage (such as
ESD stress pulse). The device connection of
AZ1143-04F is shown in the Fig. 1. In Fig. 1, the
four protected data lines are connected to the
ESD protection pins (pin1, pin2, pin4, and pin5)
of AZ1143-04F. The ground pins (pin3 and pin8)
of AZ1143-04F are the negative reference pins.
I/O 1
line
data
line
I/O 1
I/O 2
I/O 2
Line-1
Line-2
GND
Line-3
Line-4
To
I/O-port
Connector
data
1
10
NC
2
9
NC
3
4
AZ1143-04F
To
I/O-port
Connector
These pins should be directly connected to the
GND rail of PCB (Printed Circuit Board). To get
minimum parasitic inductance, the path length
should keep as short as possible.
AZ1143-04F can provide ESD protection for
4 I/O signal lines simultaneously. If the number of
I/O signal lines is less than 4, the unused I/O pins
can be simply left as NC pins.
5
8
GND
7
NC
6
NC
I/O 3
I/O 3
I/O 4
data
line
data
line
To
Protected
IC
To
Protected
IC
I/O 4
Fig. 1 Data lines connection of AZ1143-04F.
B. Application
AZ1143-04F is designed for protecting high
speed I/O ports from over-voltage caused by
Electrostatic Discharging (ESD). Thus, a lot of
kinds of high speed I/O ports can be the
applications of AZ1143-04F, especially, the HDMI
port.
HDMI Protection for High and Low speed
signals
The HDMI Compliance Test Specification
(CTS) requires sink (receiver) ports maintain a
differential impedance of 100 Ohms +/- 15%.
ESD protection devices have an inherent
junction capacitance. Even a small amount of
added capacitance on a HDMI port will cause the
impedance of the differential pair to drop. Thus,
some form of compensation to the layout will be
required to bring the differential pairs back within
the required 100 Ohm +/- 15% range. The higher
the added capacitance, the more extreme the
modifications will need to be. If the added
capacitance is too high, compensation may not
even be possible. The AZ1143-04F presents
0.45pF capacitance to each differential signal
while being rated to handle >8kV ESD contact
discharges (>15kV air discharge) as outlined in
IEC 61000-4-2. Therefore, it is possible to make
Revision 2014/10/02
4
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AZ1143-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
none adjustment to the board layout parameters
to compensate for the added capacitance of the
AZ1143-04F. Figure 2 shows how to implement
the AZ1143-04F in a HDMI application.
The AZ1143-04F is designed for allowing the
traces to run straight through the device to
simplify the PCB layout. As shown in Figure 2,
the best way to design the PCB trace is using the
flow through layout. The solid line represents the
PCB trace. Note that the PCB traces are used to
connect the pin pairs for each line (pin 1 to pin 10,
pin 2 to pin 9, pin 4 to pin 7, pin 5 to pin 6). For
example, line 1 enters at pin 1 and exits at Pin 10
and the PCB trace connects pin 1 and 10
together. Lines 2, 3, and 4 have the same way of
connection. The ground pins (pin3 and pin8) of
AZ1143-04F are the negative reference pins.
These pins should be directly connected to the
GND plane of PCB. To get minimum parasitic
inductance, the path length should keep as short
as possible. In Figure 2, the none-TMDS
signals, DDC_CLK, DDC_DAT, CE_REMOTE,
and HOTPLUG_DET, can be protected with
another low cost part, e.g., AZC199-04S.
TMDS_D2+
NC
9
NC
8
GND
7
NC
5
6
NC
Line-1
1
10
NC
TMDS_GND
Line-2
2
9
NC
TMDS_D0-
GND
3
8
GND
TMDS_CK+
Line-3
4
7
NC
TMDS_GND
Line-4
5
6
NC
Line-1
1
TMDS_GND
Line-2
2
TMDS_D2-
GND
3
TMDS_D1+
Line-3
4
TMDS_GND
Line-4
TMDS_D0+
AZ1143-04F
10
TMDS_D2+
TMDS_D2-
TMDS_D1+
TMDS_D1-
AZ1143-04F
TMDS_D1TMDS_D0+
TMDS_D0-
TMDS_CK+
TMDS_CK-
TMDS_CKCE_REMOTE
CE_REMOTE
Via hole to GND
N/C
DDC_DAT
GND
GND
2
DDC_CLK
1
AZC199-04S
DDC_CLK
3
4
5
+5V
6
Via hole to +5V
+5V OUT
C=100nF
(optional)
HOTPLUG_DET
DDC_DAT
Via hole to GND
HOTPLUG_DET
HDMI
Connector
Fig. 2 HDMI Protection for High and Low speed signals.
Revision 2014/10/02
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AZ1143-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Fig. 3 shows the HDMI 2.0 (6 Gb/s) eye
diagrams with and without AZ1143-04F. Due to
ultra
low
capacitance
of
AZ1143-04F,
no
degradation is observed.
Without AZ1143-04F
With AZ1143-04F
Fig. 3 HDMI 2.0 (6 Gb/s) Eye Diagrams with and without AZ1143-04F.
Revision 2014/10/02
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AZ1143-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
PACKAGE OUTLINE
(DFN2510P10E)
TOP VIEW (unit in mm)
BOTTOM VIEW (unit in mm)
SIDE VIEW (unit in mm)
Symbol
A
A1
A3
D
E
D1
E1
b
e
L1
L2
b2
L
Revision 2014/10/02
Millimeters
min
max
0.40
0.55
0.00
0.05
0.152REF.
2.45
2.55
0.95
1.05
0.35
0.45
0.35
0.45
0.15
0.25
0.5 BSC
0.075 REF
0.05 REF
0.20
0.30
0.35
0.45
©2014-2015 Amazing Micro.
7
Inches
min
max
0.016
0.022
0.000
0.002
0.006 BSC
0.096
0.100
0.037
0.041
0.014
0.018
0.014
0.018
0.006
0.010
0.019 BSC
0.0029 REF
0.0019 REF
0.0079
0.012
0.014
0.018
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AZ1143-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
LAND LAYOUT
D
D1
Dimensions
B F
A
E
C
C1
Notes:
This LAND
LAYOUT
is
for
Index
Millimeter
Inches
A
0.875
0.034
B
0.20
0.008
C
0.50
0.02
C1
1.00
0.039
D
0.25
0.01
D1
0.4
0.016
E
0.675
0.027
F
1.55
0.061
reference
purposes only. Please consult your
manufacturing partners to ensure your
company’s PCB design guidelines are met.
MARKING CODE
Part Number
143XY
AZ1143-04F
(Green part)
143 = Device Code
X = Date Code
Y= Control Code
Marking Code
143XY
Note. Green means Pb-free, RoHS, and
Halogen free compliant.
Ordering Information
PN#
Material
Type
Reel size
MOQ/internal box
MOQ/carton
AZ1143-04F.R7G
Green
T/R
7 inch
4 reel= 12,000/box
6 box =72,000/carton
Revision 2014/10/02
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AZ1143-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port
Revision History
Revision
Modification Description
Revision 2014/06/16
Preliminary Release.
Revision 2014/10/02
Formal Release.
Revision 2014/10/02
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