NUC130LC1CN

NuMicro™ NUC130 Data Sheet ARM Cortex™-M0 32-BIT MICROCONTROLLER NuMicro™ Family NUC130 Data Sheet The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. -1- Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet Contents 1  2  GENERAL DESCRIPTION ......................................................................................................... 7  FEATURES ................................................................................................................................. 8  2.1  3  NuMicro™ NUC130 Features – Automotive Line............................................................ 8  PARTS INFORMATION LIST AND PIN CONFIGURATION .................................................... 12  3.1  NuMicro™ NUC130 Products Selection Guide ............................................................. 12  3.1.1  3.2  3.2.1  4  NuMicro™ NUC130/NUC140 Pin Diagram .....................................................................13  BLOCK DIAGRAM .................................................................................................................... 16  4.1  NuMicro™NUC130 Block Diagram ............................................................................... 16  4.1.1  5  NuMicro™ NUC130 Automotive Line Selection Guide....................................................12  Pin Configuration .......................................................................................................... 13  NuMicro™ NUC130 Block Diagram ................................................................................16  FUNCTIONAL DESCRIPTION.................................................................................................. 17  5.1  ARM® Cortex™-M0 Core .............................................................................................. 17  5.2  System Manager........................................................................................................... 19  5.2.1  5.2.2  5.2.3  5.2.4  5.2.5  5.2.6  5.3  Clock Controller ............................................................................................................ 28  5.3.1  5.3.2  5.3.3  5.3.4  5.3.5  5.3.6  5.4  Overview ........................................................................................................................37  Features .........................................................................................................................38  Real Time Clock (RTC)................................................................................................. 39  5.7.1  5.7.2  5.8  Overview ........................................................................................................................35  Features .........................................................................................................................36  PWM Generator and Capture Timer (PWM) ................................................................ 37  5.6.1  5.6.2  5.7  Overview ........................................................................................................................34  Features .........................................................................................................................34  I2C Serial Interface Controller (Master/Slave) (I2C) ...................................................... 35  5.5.1  5.5.2  5.6  Overview ........................................................................................................................28  Clock Generator .............................................................................................................30  System Clock and SysTick Clock ...................................................................................31  Peripherals Clock ...........................................................................................................32  Power Down Mode Clock ...............................................................................................32  Frequency Divider Output...............................................................................................33  General Purpose I/O (GPIO) ........................................................................................ 34  5.4.1  5.4.2  5.5  Overview ........................................................................................................................19  System Reset .................................................................................................................19  System Power Distribution .............................................................................................20  System Memory Map......................................................................................................21  System Timer (SysTick) .................................................................................................23  Nested Vectored Interrupt Controller (NVIC) ..................................................................24  Overview ........................................................................................................................39  Features .........................................................................................................................39  Serial Peripheral Interface (SPI) ................................................................................... 40  -2- Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.8.1  5.8.2  5.9  Timer Controller (TMR)................................................................................................. 41  5.9.1  5.9.2  5.10  Overview ......................................................................................................................54  Features .......................................................................................................................54  FLASH MEMORY CONTROLLER (FMC) ................................................................................ 55  6.1  Overview ....................................................................................................................... 55  6.2  7  Overview ......................................................................................................................53  Features .......................................................................................................................53  External Bus Interface (EBI) ......................................................................................... 54  5.18.1  5.18.2  6  Overview ......................................................................................................................52  Features .......................................................................................................................52  PDMA Controller (PDMA) ............................................................................................. 53  5.17.1  5.17.2  5.18  Overview ......................................................................................................................51  Features .......................................................................................................................51  Analog Comparator (CMP) ........................................................................................... 52  5.16.1  5.16.2  5.17  Overview ......................................................................................................................50  Features .......................................................................................................................50  Analog-to-Digital Converter (ADC) ............................................................................... 51  5.15.1  5.15.2  5.16  Overview ......................................................................................................................49  Features .......................................................................................................................49  I2S Controller (I2S)......................................................................................................... 50  5.14.1  5.14.2  5.15  Overview ......................................................................................................................48  Features .......................................................................................................................48  PS/2 Device Controller (PS2D)..................................................................................... 49  5.13.1  5.13.2  5.14  Overview ......................................................................................................................45  Features .......................................................................................................................47  Controller Area Network (CAN) .................................................................................... 48  5.12.1  5.12.2  5.13  Overview ......................................................................................................................42  Features .......................................................................................................................44  UART Interface Controller (UART) ............................................................................... 45  5.11.1  5.11.2  5.12  Overview ........................................................................................................................41  Features .........................................................................................................................41  Watchdog Timer (WDT)................................................................................................ 42  5.10.1  5.10.2  5.11  Overview ........................................................................................................................40  Features .........................................................................................................................40  Features........................................................................................................................ 55  ELECTRICAL CHARACTERISTICS......................................................................................... 56  7.1  Absolute Maximum Ratings .......................................................................................... 56  7.2  DC Electrical Characteristics ........................................................................................ 57  7.2.1  7.3  NuMicro™ NUC130/NUC140 DC Electrical Characteristics............................................57  AC Electrical Characteristics ........................................................................................ 62  7.3.1  7.3.2  External 4~24 MHz High Speed Oscillator .....................................................................62  External 4~24 MHz High Speed Crystal .........................................................................62  -3- Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 7.3.3  7.3.4  7.3.5  7.4  Analog Characteristics.................................................................................................. 64  7.4.1  7.4.2  7.4.3  7.4.4  7.4.5  7.4.6  7.4.7  8  9  External 32.768 kHz Low Speed Crystal ........................................................................63  Internal 22.1184 MHz High Speed Oscillator..................................................................63  Internal 10 kHz Low Speed Oscillator.............................................................................63  Specification of 12-bit SARADC .....................................................................................64  Specification of LDO and Power management...............................................................65  Specification of Low Voltage Reset ................................................................................66  Specification of Brown-Out Detector...............................................................................66  Specification of Power-On Reset (5 V) ...........................................................................66  Specification of Temperature Sensor .............................................................................67  Specification of Comparator ...........................................................................................67  7.5  Flash DC Electrical Characteristics .............................................................................. 68  7.6  SPI Dynamic Characteristics ........................................................................................ 69  PACKAGE DIMENSIONS ......................................................................................................... 71  8.1  100L LQFP (14x14x1.4 mm footprint 2.0mm) .............................................................. 71  8.2  64L LQFP (10x10x1.4mm footprint 2.0 mm) ................................................................ 72  8.3  48L LQFP (7x7x1.4mm footprint 2.0mm) ..................................................................... 73  REVISION HISTORY ................................................................................................................ 74  -4- Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet Figures Figure 3-1 NuMicro™ NUC100 Series selection code ................................................................... 12  Figure 3-2 NuMicro™ NUC130 LQFP 100-pin Pin Diagram .......................................................... 13  Figure 3-3 NuMicro™ NUC130 LQFP 64-pin Pin Diagram ............................................................ 14  Figure 3-4 NuMicro™ NUC130 LQFP 48-pin Pin Diagram ............................................................ 15  Figure 4-1 NuMicro™ NUC130 Block Diagram .............................................................................. 16  Figure 5-1 Functional Controller Diagram...................................................................................... 17  Figure 5-3 NuMicro™ NUC130 Power Distribution Diagram.......................................................... 20  Figure 5-4 Clock generator global view diagram ........................................................................... 29  Figure 5-5 Clock generator block diagram..................................................................................... 30  Figure 5-6 System Clock Block Diagram ....................................................................................... 31  Figure 5-7 SysTick Clock Control Block Diagram .......................................................................... 31  Figure 5-8 Clock Source of Frequency Divider .............................................................................. 33  Figure 5-9 Block Diagram of Frequency Divider ............................................................................ 33  Figure 5-10 I2C Bus Timing ............................................................................................................ 35  Figure 5-11 Timing of Interrupt and Reset Signal .......................................................................... 43  Figure 7-1 Typical Crystal Application Circuit ................................................................................ 63  Figure 7-2 SPI Master dynamic characteristics tiMINg .................................................................. 70  Figure 7-3 SPI Slave dynamic characteristics timing..................................................................... 70  -5- Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet Tables Table 1-1 Connectivity Supported Table.......................................................................................... 7  Table 5-1 Address Space Assignments for On-Chip Controllers................................................... 22  Table 5-2 Exception Model ............................................................................................................ 25  Table 5-3 System Interrupt Map..................................................................................................... 26  Table 5-4 Vector Table Format ...................................................................................................... 27  Table 5-5 Watchdog Timeout Interval Selection ............................................................................ 43  Table 5-6 UART Baud Rate Equation ............................................................................................ 45  Table 5-7 UART Baud Rate Setting Table ..................................................................................... 46  -6- Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 1 GENERAL DESCRIPTION The NuMicro™ NUC100 Series is 32-bit microcontrollers with embedded ARM® Cortex™-M0 core for industrial control and applications which need rich communication interfaces. The Cortex™-M0 is the newest ARM® embedded processor with 32-bit performance and at a cost equivalent to traditional 8-bit microcontroller. NuMicro™ NUC100 Series includes NUC100, NUC120, NUC130 and NUC140 product line. The NuMicro™ NUC130 Automotive Line with CAN function embeds Cortex™-M0 core running up to 50 MHz with 32K/64K/128K-byte embedded flash, 4K/8K/16K-byte embedded SRAM, and 4Kbyte loader ROM for the ISP. It also equips with plenty of peripheral devices, such as Timers, Watchdog Timer, RTC, PDMA, UART, SPI, I2C, I2S, PWM Timer, GPIO, LIN, CAN, PS/2, 12-bit ADC, Analog Comparator, Low Voltage Reset Controller and Brown-out Detector. Product Line UART SPI I2 C NUC100 ● ● ● NUC120 ● ● ● NUC130 ● ● ● NUC140 ● ● ● USB LIN CAN ● ● PS/2 I2 S ● ● ● ● ● ● ● ● ● ● ● ● Table 1-1 Connectivity Supported Table -7- Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 2 FEATURES The equipped features are dependent on the product line and their sub products. 2.1 NuMicro™ NUC130 Features – Automotive Line • Core – ARM® Cortex™-M0 core runs up to 50 MHz – One 24-bit system timer – Supports low power sleep mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority – Serial Wire Debug supports with 2 watchpoints/4 breakpoints • Build-in LDO for wide operating voltage ranges from 2.5 V to 5.5 V • Flash Memory 32K/64K/128K bytes Flash for program code 4KB flash for ISP loader Support In-system program (ISP) application code update 512 byte page erase for flash Configurable data flash address and size for 128KB system, fixed 4KB data flash for the 32KB and 64KB system – Support 2 wire ICP update through SWD/ICE interface – Support fast parallel programming mode by external programmer • SRAM Memory – – – – – – 4K/8K/16K bytes embedded SRAM – Support PDMA mode • PDMA (Peripheral DMA) • – Support 9 channels PDMA for automatic data transfer between SRAM and peripherals Clock Control Flexible selection for different applications Built-in 22.1184 MHz high speed OSC for system operation 1 % at +25 ℃ and VDD = 5 V ‹ Trimmed to ‹ Trimmed to 3 % at -40 ℃ ~ +85 ℃ and VDD = 2.5 V ~ 5.5 V – Built-in 10 kHz low speed OSC for Watchdog Timer and Wake-up operation – Support one PLL, up to 50 MHz, for high performance system operation – External 4~24 MHz high speed crystal input for precise timing operation – External 32.768 kHz low speed crystal input for RTC function and low power system operation • GPIO – – – – – – Four I/O modes: ‹ Quasi bi-direction ‹ Push-Pull output ‹ Open-Drain output ‹ Input only with high impendence TTL/Schmitt trigger input selectable I/O pin can be configured as interrupt source with edge/level setting High driver and high sink IO mode support -8- Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet • • • • • • Timer – Support 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter – Independent clock source for each timer – Provides one-shot, periodic, toggle and continuous counting operation modes – Support event counting function – Support input capture function Watchdog Timer – Multiple clock sources – 8 selectable time out period from 1.6ms ~ 26.0sec (depends on clock source) – WDT can wake-up from power down or idle mode – Interrupt or reset selectable on watchdog time-out RTC – Support software compensation by setting frequency compensate register (FCR) – Support RTC counter (second, minute, hour) and calendar counter (day, month, year) – Support Alarm registers (second, minute, hour, day, month, year) – Selectable 12-hour or 24-hour mode – Automatic leap year recognition – Support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second – Support wake-up function PWM/Capture – Built-in up to four 16-bit PWM generators provide eight PWM outputs or four complementary paired PWM outputs – Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one Dead-Zone generator for complementary paired PWM – Up to eight 16-bit digital Capture timers (shared with PWM timers) provide eight rising/falling capture inputs – Support Capture interrupt UART – Up to three UART controllers – UART ports with flow control (TXD, RXD, CTS and RTS) – UART0 with 64-byte FIFO is for high speed – UART1/2(optional) with 16-byte FIFO for standard device – Support IrDA (SIR) and LIN function – Support RS-485 9-bit mode and direction control. – Programmable baud-rate generator up to 1/16 system clock – Support PDMA mode SPI – Up to four sets of SPI controller – Master up to 32 MHz, and Slave up to 10 MHz (chip working @ 5V) – Support SPI master/slave mode – Full duplex synchronous serial data transfer – Variable length of transfer data from 1 to 32 bits – MSB or LSB first data transfer – Rx and Tx on both rising or falling edge of serial clock independently – 2 slave/device select lines when it is as the master, and 1 slave/device select line when it is as the slave – Support byte suspend mode in 32-bit transmission – Support PDMA mode – Support three wire, no slave select signal, bi-direction interface -9- Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet • I2C – – – – – – – – – 2 • IS Up to two sets of I2C device Master/Slave mode Bidirectional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer Programmable clocks allow versatile rate control Support multiple address recognition (four slave address with mask option) – Interface with external audio CODEC – Operate as either master or slave mode – Capable of handling 8-, 16-, 24- and 32-bit word sizes – Mono and stereo audio data supported – I2S and MSB justified data format supported – Two 8 word FIFO data buffers are provided, one for transmit and one for receive – Generates interrupt requests when buffer levels cross a programmable boundary – Support two DMA requests, one for transmit and one for receive • PS/2 Device Controller – Host communication inhibit and request to send detection – Reception frame error detection – Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention – Double buffer for data reception – S/W override bus • CAN 2.0 – Supports CAN protocol version 2.0 part A and B – Bit rates up to 1M bit/s – 32 Message Objects – Each Message Object has its won identifier mask – Programmable FIFO mode (concatenation of Message Object) – Maskable interrupt – Disabled Automatic Re-transmission mode for Time Triggered CAN applications – Support power down wake-up function • EBI (External bus interface) support (100-pin and 64-pin Package Only) – Accessible space: 64KB in 8-bit mode or 128KB in 16-bit mode – Support 8-/16-bit data width – Support byte write in 16-bit data width mode • ADC – – – – – – – 12-bit SAR ADC with 700K SPS Up to 8-ch single-end input or 4-ch differential input Single scan/single cycle scan/continuous scan Each channel with individual result register Scan on enabled channels Threshold voltage detection Conversion start by software programming or external input - 10 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet – Support PDMA mode • Analog Comparator – Up to two analog comparator – External input or internal bandgap voltage selectable at negative node – Interrupt when compare result change – Power down wake-up • One built-in temperature sensor with 1℃ resolution • Brown-Out detector – With 4 levels: 4.5 V/3.8 V/2.7 V/2.2 V – Support Brown-Out Interrupt and Reset option • Low Voltage Reset • – Threshold voltage levels: 2.0 V Operating Temperature: -40℃~85℃ • Packages: – – All Green package (RoHS) LQFP 100-pin / 64-pin / 48-pin - 11 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 3 PARTS INFORMATION LIST AND PIN CONFIGURATION 3.1 3.1.1 NuMicro™ NUC130 Products Selection Guide NuMicro™ NUC130 Automotive Line Selection Guide Part number APROM RAM Data Flash ISP Loader ROM Connectivity I/O I2S Comp. PWM Timer UART SPI I2C ADC RTC EBI ISP Package ICP USB LIN CAN NUC130LC1CN 32 KB 4 KB 4 KB 4 KB up to 35 4x32-bit 3 1 2 - 2 1 1 1 4 8x12-bit v - v LQFP48 NUC130LD2CN 64 KB 8 KB 4 KB 4 KB up to 35 4x32-bit 3 1 2 - 2 1 1 1 4 8x12-bit v - v LQFP48 NUC130LE3CN 128 KB 16 KB Definable 4 KB up to 35 4x32-bit 3 1 2 - 2 1 1 1 4 8x12-bit v - v LQFP48 NUC130RC1CN 32 KB 4 KB 4 KB 4 KB up to 49 4x32-bit 3 2 2 - 2 1 1 2 6 8x12-bit v v v LQFP64 NUC130RD2CN 64 KB 8 KB 4 KB 4 KB up to 49 4x32-bit 3 2 2 - 2 1 1 2 6 8x12-bit v v v LQFP64 NUC130RD3CN 128 KB 16 KB Definable 4 KB up to 49 4x32-bit 3 2 2 - 2 1 1 2 6 8x12-bit v v v LQFP64 NUC130VE3CN 128 KB 16 KB Definable 4 KB up to 80 4x32-bit 3 4 2 - 2 1 1 2 8 8x12-bit v v v LQFP100 NUC 1 0 0 - X X X X X ARM-Based 32-bit Microcontroller Temperature CPU core N: -40 E: -40 C: -40 ~ +85 ~ +105 ~ +125 1: Cortex-M0 5/7: ARM7 9: ARM9 Reserve Function RAM Size 1: 4K 2: 8K 3: 16K 0: Advance Line 2: USB Line 3: Automotive Line 4: Connectivity Line APROM Size A: 8K B: 16K C: 32K D: 64K E: 128K Package Type Y: QFN 36 L: LQFP 48 R: LQFP 64 V: LQFP 100 Figure 3-1 NuMicro™ NUC100 Series selection code - 12 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 3.2 Pin Configuration 3.2.1 NuMicro™ NUC130/NUC140 Pin Diagram 3.2.1.1 NuMicro™ NUC130 LQFP 100 pin AD8/ADC5/PA.5 76 50 PB.9/TM1/SPISS11 AD7/ADC6/PA.6 77 49 PB.10/TM2/SPISS01 AD6/ADC7/SPISS21/PA.7 78 48 PB.11/TM3/PWM4 VREF 79 47 PE.5/PWM5/T1EX AVDD 80 46 PE.6 SPISS20/PD.0 81 45 PC.0/SPISS00/I2SLRCLK SPICLK2/PD.1 82 44 PC.1/SPICLK0/I2SBCLK MISO20/PD.2 83 43 PC.2/MISO00/I2SDI MOSI20/PD.3 84 42 PC.3/MOSI00/I2SDO MISO21/PD.4 85 41 PC.4/MISO01 40 PC.5/MOSI01 39 PD.15/TXD2 38 PD.14/RXD2 37 PD.7/CANTX0 MOSI21/PD.5 86 AD5/CPN0/PC.7 87 AD4/CPP0/PC.6 88 AD3/CPN1/PC.15 89 AD2/CPP1/PC.14 90 36 PD.6/CANRX0 T0EX/INT1/PB.15 91 35 PB.3/CTS0/nWRH/T3EX XT1_OUT 92 34 PB.2/RTS0/nWRL/T2EX XT1_IN 93 33 PB.1/TXD0 /RESET 94 32 PB.0/RXD0 VSS 95 31 PE.7 VDD 96 30 PE.8 PS2DAT 97 29 PE.9 PS2CLK 98 28 PE.10 PVSS 99 27 PE.11 100 26 PE.12 STADC/TM0/PB.8 NUC130VxxCN LQFP 100-pin Figure 3-2 NuMicro™ NUC130 LQFP 100-pin Pin Diagram - 13 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet PA.4/ADC4/AD9 PA.3/ADC3/AD10 PA.2/ADC2/AD11 PA.1/ADC1/AD12 PA.0/ADC0 AVSS ICE_CK ICE_DAT PA.12/PWM0/AD13 PA.13/PWM1/AD14 PA.14/PWM2/AD15 PA.15/PWM3/I2SMCLK PC.8/SPISS10 PC.9/SPICLK1 PC.10/MISO10 PC.11/MOSI10 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro™ NUC130 LQFP 64 pin 48 3.2.1.2 AD8/ADC5/PA.5 49 32 PB.9/TM1 AD7/ADC6/PA.6 50 31 PB.10/TM2 AD6/ADC7/PA.7 51 30 PB.11/TM3/PWM4 AVDD 52 29 PE.5/PWM5/T1EX AD5/CPN0/PC.7 53 28 PC.0/SPISS00/I2SLRCLK AD4/CPP0/PC.6 54 27 PC.1/SPICLK0/I2SBCLK AD3/CPN1/PC.15 55 26 PC.2/MISO00/I2SDI AD2/CPP1/PC.14 56 25 PC.3/MOSI00/I2SDO T0EX/INT1/PB.15 57 24 PD.15/TXD2 XT1_OUT 58 23 PD.14/RXD2 XT1_IN 59 22 PD.7/CANTX0 /RESET 60 21 PD.6/CANRX0 NUC130RxxCN LQFP 64-pin 11 12 13 14 15 16 TXD1/PB.5 ALE/RTS1/PB.6 nCS/CTS1/PB.7 LDO VDD VSS 9 10 8 I2C0SCL/PA.9 I2C0SDA/PA.8 RXD1/PB.4 7 PB.0/RXD0 WR/I2C1SDA/PA.10 17 6 64 5 STADC/TM0/PB.8 X32I PB.1/TXD0 nRD/I2C1SCL/PA.11 18 4 63 3 PB.2/RTS0/nWRL/T2EX PVSS 2 PB.3/CTS0/nWRH/T3EX 19 AD1/CPO1/PB.13 AD0/CLKO/CPO0/ PB.12 X32O 20 62 1 61 INT0/PB.14 VSS VDD Figure 3-3 NuMicro™ NUC130 LQFP 64-pin Pin Diagram - 14 - Publication Release Date: Jan. 2, 2012 Revision V3.02 - 15 - 33 32 31 30 29 28 4 5 6 7 8 9 I2C1SCL/PA.11 I2C1SDA/PA.10 I2C0SCL/PA.9 I2C0SDA/PA.8 RXD1/PB.4 TXD1/PB.5 11 12 VDD VSS 25 26 27 34 3 X32I 10 35 2 X32O LDO 36 1 PA.15/PWM3/I2SMCLK PA.14/PWM2 PA.13/PWM1 PA.12/PWM0 ICE_DAT ICE_CK AVSS PA.0/ADC0 PA.1/ADC1 PA.2/ADC2 PA.3/ADC3 PA.4/ADC4 3.2.1.3 CLKO/CPO0/PB.12 NuMicro™ NUC130 Data Sheet NuMicro™ NUC130 LQFP 48 pin Figure 3-4 NuMicro™ NUC130 LQFP 48-pin Pin Diagram Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 4 BLOCK DIAGRAM 4.1 4.1.1 NuMicro™NUC130 Block Diagram NuMicro™ NUC130 Block Diagram Figure 4-1 NuMicro™ NUC130 Block Diagram - 16 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5 5.1 FUNCTIONAL DESCRIPTION ARM® Cortex™-M0 Core The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processor. The profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception return. Figure 5-1 shows the functional controller of processor. Cortex-M0 components Cortex-M0 processor Nested Vectored Interrupt Controller (NVIC) Interrupts Debug Cortex-M0 Processor Core Wakeup Interrupt Controller (WIC) Bus Matrix Breakpoint and Watchpoint Unit Debug Access Port (DAP) Debugger interface AHB-Lite interface Serial Wire or JTAG debug port Figure 5-1 Functional Controller Diagram The implemented device provides: z A low gate count processor that features: ‹ The ARMv6-M Thumb® instruction set ‹ Thumb-2 technology ‹ ARMv6-M compliant 24-bit SysTick timer ‹ A 32-bit hardware multiplier ‹ The system interface supports little-endian data accesses ‹ The ability to have deterministic, fixed-latency, interrupt handling ‹ Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling ‹ C Application Binary Interface compliant exception model. This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers - 17 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet ‹ z z z Low power sleep mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from interrupt sleep-on-exit feature NVIC that features: ‹ 32 external interrupt inputs, each with four levels of priority ‹ Dedicated Non-Maskable Interrupt (NMI) input. ‹ Support for both level-sensitive and pulse-sensitive interrupt lines ‹ Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support. Debug support ‹ Four hardware breakpoints. ‹ Two watchpoints. ‹ Program Counter Sampling Register (PCSR) for non-intrusive code profiling. ‹ Single step and vector catch capabilities. Bus interfaces: ‹ Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals and memory. ‹ Single 32-bit slave port that supports the DAP (Debug Access Port). - 18 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.2 System Manager 5.2.1 Overview System management includes these following sections: z System Resets z System Memory Map z System management registers for Part Number ID, chip reset and on-chip controllers reset , multi-functional pin control z System Timer (SysTick) z Nested Vectored Interrupt Controller (NVIC) z System Control registers 5.2.2 System Reset The system reset can be issued by one of the below listed events. For these reset event flags can be read by RSTSRC register. z The Power-On Reset z The low level on the /RESET pin z Watchdog Time Out Reset z Low Voltage Reset z Brown-Out Detector Reset z CPU Reset z System Reset System Reset and Power-On Reset all reset the whole chip including all peripherals. The difference between System Reset and Power-On Reset is external crystal circuit and ISPCON.BS bit. System Reset doesn’t reset external crystal circuit and ISPCON.BS bit, but Power-On Reset does. - 19 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.2.3 System Power Distribution In this chip, the power distribution is divided into three segments. z Analog power from AVDD and AVSS provides the power for analog components operation. z Digital power from VDD and VSS supplies the power to the internal regulator which provides a fixed 2.5 V power for digital operation and I/O pins. The outputs of internal voltage regulators, LDO and VDD33, require an external capacitor which should be located close to the corresponding pin. Analog power (AVDD) should be the same voltage level of the digital power (VDD). Figure 5-2 shows the power distribution of NuMicro™ NUC130. AVDD 12-bit SAR-ADC AVSS NUC130 Power Distribution Analog Comparator Low Voltage Reset Temperature Seneor Brown Out Detector FLASH Digital Logic Internal 22.1184 MHz & 10 kHz Oscillator LDO 2.5V POR50 IO cell VDD 5V to 2.5V LDO GPIO VSS POR25 X32I External 32.768 kHz Crystal X32O PVSS PLL 1uF Figure 5-2 NuMicro™ NUC130 Power Distribution Diagram - 20 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.2.4 System Memory Map NuMicro™ NUC100 Series provides 4G-byte addressing space. The memory locations assigned to each on-chip controllers are shown in the following table. The detailed register definition, memory space, and programming detailed will be described in the following sections for each onchip peripherals. NuMicro™ NUC100 Series only supports little-endian data format. Address Space Token Controllers Flash and SRAM Memory Space 0x0000_0000 – 0x0001_FFFF FLASH_BA FLASH Memory Space (128KB) 0x2000_0000 – 0x2000_3FFF SRAM Memory Space (16KB) SRAM_BA 0x6000_0000 – 0x6001_FFFF EXTMEM_BA External Memory Space (128KB) AHB Controllers Space (0x5000_0000 – 0x501F_FFFF) 0x5000_0000 – 0x5000_01FF GCR_BA System Global Control Registers 0x5000_0200 – 0x5000_02FF CLK_BA Clock Control Registers 0x5000_0300 – 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers 0x5000_4000 – 0x5000_7FFF GPIO_BA GPIO Control Registers 0x5000_8000 – 0x5000_BFFF PDMA_BA Peripheral DMA Control Registers 0x5000_C000 – 0x5000_FFFF FMC_BA Flash Memory Control Registers 0x5001_0000 – 0x5001_03FF External Bus Interface Control Registers EBI_BA APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF) 0x4000_4000 – 0x4000_7FFF WDT_BA Watchdog Timer Control Registers 0x4000_8000 – 0x4000_BFFF RTC_BA Real Time Clock (RTC) Control Register 0x4001_0000 – 0x4001_3FFF TMR01_BA Timer0/Timer1 Control Registers 0x4002_0000 – 0x4002_3FFF I2C0_BA I C0 Interface Control Registers 0x4003_0000 – 0x4003_3FFF SPI0_BA SPI0 with master/slave function Control Registers 0x4003_4000 – 0x4003_7FFF SPI1_BA SPI1 with master/slave function Control Registers 0x4004_0000 – 0x4004_3FFF PWMA_BA PWM0/1/2/3 Control Registers 0x4005_0000 – 0x4005_3FFF UART0_BA UART0 Control Registers 0x4006_0000 – 0x4006_3FFF USBD_BA USB 2.0 FS device Controller Registers 2 - 21 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet Address Space Token Controllers 0x400D_0000 – 0x400D_3FFF ACMP_BA Analog Comparator Control Registers 0x400E_0000 – 0x400E_FFFF ADC_BA Analog-Digital-Converter (ADC) Control Registers APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF) 0x4010_0000 – 0x4010_3FFF PS2_BA PS/2 Interface Control Registers 0x4011_0000 – 0x4011_3FFF TMR23_BA Timer2/Timer3 Control Registers 0x4012_0000 – 0x4012_3FFF I2C1_BA I C1 Interface Control Registers 0x4013_0000 – 0x4013_3FFF SPI2_BA SPI2 with master/slave function Control Registers 0x4013_4000 – 0x4013_7FFF SPI3_BA SPI3 with master/slave function Control Registers 0x4014_0000 – 0x4014_3FFF PWMB_BA PWM4/5/6/7 Control Registers 0x4015_0000 – 0x4015_3FFF UART1_BA UART1 Control Registers 0x4015_4000 – 0x4015_7FFF UART2_BA UART2 Control Registers 0x4018_0000 – 0x4018_3FFF CAN0_BA CAN0 Bus Control Registers 0x401A_0000 – 0x401A_3FFF I2S_BA 2 I2S Interface Control Registers System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers Table 5-1 Address Space Assignments for On-Chip Controllers - 22 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.2.5 System Timer (SysTick) The Cortex-M0 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_CVR) to zero, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to zero before enabling the feature. This ensures the timer will count from the SYST_RVR value rather than an arbitrary value when it is enabled. If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. This mechanism can be used to disable the feature independently from the timer enable bit. For more detailed information, please refer to the documents “ARM® Cortex™-M0 Technical Reference Manual” and “ARM® v6-M Architecture Reference Manual”. - 23 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.2.6 Nested Vectored Interrupt Controller (NVIC) Cortex-M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”. It is closely coupled to the processor kernel and provides following features: z Nested and Vectored interrupt support z Automatic processor state saving and restoration z Reduced and deterministic interrupt latency The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of the interrupts and most of the system exceptions can be configured to different priority levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. When any interrupts is accepted, the starting address of the interrupt service routine (ISR) is fetched from a vector table in memory. There is no need to determine which interrupt is accepted and branch to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal execution. Thus it will take less and deterministic time to process the interrupt request. The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the higher one without delay penalty. Thus it advances the real-time capability. For more detailed information, please refer to the documents “ARM® Cortex™-M0 Technical Reference Manual” and “ARM® v6-M Architecture Reference Manual”. - 24 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.2.6.1 Exception Model and System Interrupt Map Table 5-2 lists the exception model supported by NuMicro™ NUC100 Series. Software can set four levels of priority on some of these exceptions as well as on all interrupts. The highest userconfigurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”. Exception Name Vector Number Priority Reset 1 -3 NMI 2 -2 Hard Fault 3 -1 Reserved 4 ~ 10 Reserved SVCall 11 Configurable Reserved 12 ~ 13 Reserved PendSV 14 Configurable SysTick 15 Configurable Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable Table 5-2 Exception Model Vector Number Interrupt Number (Bit in Interrupt Registers) Interrupt Name Source IP Interrupt description 0 ~ 15 - - - System exceptions 16 0 BOD_OUT 17 1 WDT_INT WDT Watchdog Timer interrupt 18 2 EINT0 GPIO External signal interrupt from PB.14 pin 19 3 EINT1 GPIO External signal interrupt from PB.15 pin 20 4 GPAB_INT GPIO External signal interrupt from PA[15:0]/PB[13:0] 21 5 GPCDE_INT GPIO External interrupt from PC[15:0]/PD[15:0]/PE[15:0] 22 6 PWMA_INT PWM0~3 PWM0, PWM1, PWM2 and PWM3 interrupt 23 7 PWMB_INT PWM4~7 PWM4, PWM5, PWM6 and PWM7 interrupt 24 8 TMR0_INT TMR0 Timer 0 interrupt 25 9 TMR1_INT TMR1 Timer 1 interrupt Brown-Out Brown-Out low voltage detected interrupt - 25 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet Vector Number Interrupt Number (Bit in Interrupt Registers) Interrupt Name Source IP Interrupt description 26 10 TMR2_INT TMR2 Timer 2 interrupt 27 11 TMR3_INT TMR3 Timer 3 interrupt 28 12 UART02_INT UART0/2 29 13 UART1_INT UART1 30 14 SPI0_INT SPI0 SPI0 interrupt 31 15 SPI1_INT SPI1 SPI1 interrupt 32 16 SPI2_INT SPI2 SPI2 interrupt 33 17 SPI3_INT SPI3 SPI3 interrupt 2 UART0 and UART2 interrupt UART1 interrupt 34 18 I2C0_INT I C0 I2C0 interrupt 35 19 I2C1_INT I2C1 I2C1 interrupt 36 20 CAN0_INT CAN0 37 21 Reserved Reserved Reserved 38 22 Reserved Reserved Reserved 39 23 USB_INT USBD 40 24 PS2_INT PS/2 41 25 ACMP_INT ACMP Analog Comparator-0 or Comaprator-1 interrupt 42 26 PDMA_INT PDMA PDMA interrupt 43 27 I2S_INT I2S 44 28 PWRWU_INT CLKC Clock controller interrupt for chip wake-up from power down state 45 29 ADC_INT ADC ADC interrupt 46 30 Reserved 47 31 RTC_INT CAN0 interrupt USB 2.0 FS Device interrupt PS/2 interrupt 2 I S interrupt Reserved Reserved RTC Real time clock interrupt Table 5-3 System Interrupt Map - 26 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.2.6.2 Vector Table When any interrupts is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. The vector number on previous page defines the order of entries in the vector table associated with exception handler entry as illustrated in previous section. Vector Table Word Offset Description 0 Vector Number SP_main – The Main stack pointer Exception Entry Pointer using that Vector Number Table 5-4 Vector Table Format 5.2.6.3 Operation Description NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt SetEnable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the associated interrupt. NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. The Clear-Pending Register has no effect on the execution status of an Active interrupt. NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register supporting four interrupts). The general registers associated with the NVIC are all accessible from a block of memory in the System Control Space and will be described in next section. - 27 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.3 Clock Controller 5.3.1 Overview The clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and a clock divider. The chip will not enter power down mode until CPU sets the power down enable bit (PWR_DOWN_EN) and Cortex-M0 core executes the WFI instruction. After that, chip enter power down mode and wait for wake-up interrupt source triggered to leave power down mode. In the power down mode, the clock controller turns off the external 4~24 MHz high speed crystal and internal 22.1184 MHz high speed oscillator to reduce the overall system power consumption. - 28 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet Figure 5-3 Clock generator global view diagram - 29 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.3.2 Clock Generator The clock generator consists of 5 clock sources which are listed below: z One external 32.768 kHz low speed crystal z One external 4~24 MHz high speed crystal z One programmable PLL FOUT(PLL source consists of external 4~24 MHz high speed crystal and internal 22.1184 MHz high speed oscillator) z One internal 22.1184 MHz high speed oscillator z One internal 10 kHz low speed oscillator XTL32K_EN (PWRCON[1]) X32I External 32.768 kHz Crystal 32.768 kHz X32O XTL12M_EN (PWRCON[0]) 4~24 MHz XT_IN External 4~24 MHz Crystal PLL_SRC (PLLCON[19]) XT_OUT 0 OSC22M_EN (PWRCON[2]) 1 PLL PLL FOUT Internal 22.1184 MHz Oscillator 22.1184 MHz OSC10K_EN(PWRCON[3]) Internal 10 kHz Oscillator 10 kHz Figure 5-4 Clock generator block diagram - 30 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.3.3 System Clock and SysTick Clock The system clock has 5 clock sources which were generated from clock generator block. The clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is showed in Figure 5-5. HCLK_S (CLKSEL0[2:0]) 22.1184 MHz 10 kHz PLLFOUT 32.768 kHz 4~24 MHz 111 011 CPUCLK 010 HCLK 1/(HCLK_N+1) 001 HCLK_N (CLKDIV[3:0]) PCLK CPU AHB APB 000 CPU in Power Down Mode Figure 5-5 System Clock Block Diagram The clock source of SysTick in Cortex-M0 core can use CPU clock or external clock (SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block diagram is showed in Figure 5-6. STCLK_S (CLKSEL0[5:3]) 22.1184 MHz HCLK 4~24 MHz 32.768 kHz 4~24 MHz 1/2 111 1/2 011 1/2 010 STCLK 001 000 Figure 5-6 SysTick Clock Control Block Diagram - 31 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.3.4 Peripherals Clock The peripherals clock had different clock source switch setting which depends on the different peripheral. Please refer the CLKSEL1 and CLKSEL2 register description in 5.3.7. 5.3.5 Power Down Mode Clock When chip enters into power down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. Some clock sources and peripherals clock are still active in power down mode. For theses clocks which still keep active list below: z z Clock Generator ‹ Internal 10 kHz low speed oscillator clock ‹ External 32.768 kHz low speed crystal clock Peripherals Clock (When these IP adopt external 32.768 kHz low speed crystal or 10 kHz low speed oscillator as clock source) - 32 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.3.6 Frequency Divider Output This device is equipped a power-of-2 frequency divider which is composed by16 chained divideby-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider. The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]). When write 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When write 0 to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low state and stay in low state. Figure 5-7 Clock Source of Frequency Divider Figure 5-8 Block Diagram of Frequency Divider - 33 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.4 General Purpose I/O (GPIO) 5.4.1 Overview NuMicro™ NUC130/NUC140 has up to 80 General Purpose I/O pins can be shared with other function pins; it depends on the chip configuration. These 80 pins are arranged in 5 ports named with GPIOA, GPIOB, GPIOC, GPIOD and GPIOE. Each port equips maximum 16 pins. Each one of the 80 pins is independent and has the corresponding register bits to control the pin mode function and data. The I/O type of each of I/O pins can be configured by software individually as input, output, opendrain or quasi-bidirectional mode. After reset, the I/O type of all pins stay in quasi-bidirectional mode and port data register GPIOx_DOUT[15:0] resets to 0x0000_FFFF. Each I/O pin equips a very weakly individual pull-up resistor which is about 110 KΩ~300 KΩ for VDD is from 5.0 V to 2.5 V. 5.4.2 Features z Four I/O modes: ‹ Quasi bi-direction ‹ Push-Pull output ‹ Open-Drain output ‹ Input only with high impendence z TTL/Schmitt trigger input selectable z I/O pin can be configured as interrupt source with edge/level setting z High driver and high sink IO mode support - 34 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.5 I2C Serial Interface Controller (Master/Slave) (I2C) 5.5.1 Overview I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to the Figure 5-9 for more detail I2C BUS Timing. Figure 5-9 I2C Bus Timing The device’s on-chip I2C logic provides the serial interface that meets the I2C bus standard mode specification. The I2C port handles byte transfers autonomously. To enable this port, the bit ENS1 in I2CON should be set to '1'. The I2C H/W interfaces to the I2C bus via two pins: SDA and SCL. Pull up resistor is needed for I2C operation as these are open drain pins. When the I/O pins are used as I2C port, user must set the pins function to I2C in advance. - 35 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.5.2 Features The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus are: z Master/Slave mode z Bidirectional data transfer between masters and slaves z Multi-master bus (no central master) z Arbitration between simultaneously transmitting masters without corruption of serial data on the bus z Serial clock synchronization allows devices with different bit rates to communicate via one serial bus z Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer z Built-in a 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs up and timer-out counter overflows. z External pull-up are needed for high output z Programmable clocks allow versatile rate control z Supports 7-bit addressing mode z I2C-bus controllers support multiple address recognition ( Four slave address with mask option) - 36 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.6 PWM Generator and Capture Timer (PWM) 5.6.1 Overview NuMicro™ NUC130/NUC140 has 2 sets of PWM group supports total 4 sets of PWM Generators which can be configured as 8 independent PWM outputs, PWM0~PWM7, or as 4 complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM4, PWM5) and (PWM6, PWM7) with 4 programmable dead-zone generators. Each PWM Generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM downcounters for PWM period control, two 16-bit comparators for PWM duty control and one deadzone generator. The 4 sets of PWM Generators provide eight independent PWM interrupt flags which are set by hardware when the corresponding PWM period down counter reaches zero. Each PWM interrupt source with its corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators can be configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode to output PWM waveform continuously. When PCR.DZEN01 is set, PWM0 and PWM1 perform complementary PWM paired function; the paired PWM period, duty and dead-time are determined by PWM0 timer and Dead-zone generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3), (PWM4, PWM5) and (PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2, 4 and 6, respectively. To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and 16-bit comparator are implemented with double buffer. When user writes data to counter/comparator buffer registers the updated value will be load into the 16-bit down counter/ comparator at the time down counter reaching zero. The double buffering feature avoids glitch at PWM outputs. When the 16-bit period down counter reaches zero, the interrupt request is generated. If PWMtimer is set as auto-reload mode, when the down counter reaches zero, it is reloaded with PWM Counter Register (CNRx) automatically then start decreasing, repeatedly. If the PWM-timer is set as one-shot mode, the down counter will stop and generate one interrupt request when it reaches zero. The value of PWM counter comparator is used for pulse high width modulation. The counter control logic changes the output to high level when down-counter value matches the value of compare register. The alternate feature of the PWM-timer is digital input Capture function. If Capture function is enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc. Therefore user must setup the PWM-timer before enable Capture feature. After capture feature is enabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR) when input channel has a rising transition and latched PWM-counter to Capture Falling Latch Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is programmable by setting CCR0.CRL_IE0[1] (Rising latch Interrupt enable) and CCR0.CFL_IE0[2]] (Falling latch Interrupt enable) to decide the condition of interrupt occur. Capture channel 1 has the same feature by setting CCR0.CRL_IE1[17] and CCR0.CFL_IE1[18]. And capture channel 2 to channel 3 on each group have the same feature by setting the corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3, the PWM counter 0/1/2/3 will be reload at this moment. The maximum captured frequency that PWM can capture is confined by the capture interrupt latency. When capture interrupt occurred, software will do at least three steps, they are: Read - 37 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet PIIR to get interrupt source and Read CRLRx/CFLRx(x=0~3) to get capture value and finally write 1 to clear PIIR to zero. If interrupt latency will take time T0 to finish, the capture signal mustn’t transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0. For example: HCLK = 50 MHz, PWM_CLK = 25 MHz, Interrupt latency is 900 ns So the maximum capture frequency will is 1/900ns ≈ 1000 kHz 5.6.2 Features 5.6.2.1 PWM function features: 5.6.2.2 z PWM group has two PWM generators. Each PWM generator supports one 8-bit prescaler, one clock divider, two PWM-timers (down counter), one dead-zone generator and two PWM outputs. z Up to 16-bit resolution z PWM Interrupt request synchronized with PWM period z One-shot or Auto-reload mode PWM z Up to 2 PWM group (PWMA/PWMB) to support 8 PWM channels or 4 PWM paired channels Capture Function Features: z Timing control logic shared with PWM Generators z Support 8 Capture input channels shared with 8 PWM output channels z Each channel supports one rising latch register (CRLR), one falling latch register (CFLR) and Capture interrupt flag (CAPIFx) - 38 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.7 Real Time Clock (RTC) 5.7.1 Overview Real Time Clock (RTC) controller provides user the real time and calendar message. The clock source of RTC is from an external 32.768 kHz low speed crystal connected at pins X32I and X32O (reference to pin descriptions) or from an external 32.768 kHz low speed oscillator output fed at pin X32I. The RTC controller provides the time message (second, minute, hour) in Time Loading Register (TLR) as well as calendar message (day, month, year) in Calendar Loading Register (CLR). The data message is expressed in BCD format. It also offers alarm function that user can preset the alarm time in Time Alarm Register (TAR) and alarm calendar in Calendar Alarm Register (CAR). The RTC controller supports periodic Time Tick and Alarm Match interrupts. The periodic interrupt has 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by TTR (TTR[2:0]). When RTC counter in TLR and CLR is equal to alarm setting time registers TAR and CAR, the alarm interrupt flag (RIIR.AIF) is set and the alarm interrupt is requested if the alarm interrupt is enabled (RIER.AIER=1). Both RTC Time Tick and Alarm Match can cause chip wakeup from power down mode if wake-up function is enabled (TWKE (TTR[3])=1). 5.7.2 z Features There is a time counter (second, minute, hour) and calendar counter (day, month, year) for user to check the time z Alarm register (second, minute, hour, day, month, year) z 12-hour or 24-hour mode is selectable z Leap year compensation automatically z Day of week counter z Frequency compensate register (FCR) z All time and calendar message is expressed in BCD code z Support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second z Support RTC Time Tick and Alarm Match interrupt z Support wake-up chip from power down mode - 39 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.8 Serial Peripheral Interface (SPI) 5.8.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which operates in full duplex mode. Devices communicate in master/slave mode with 4-wire bi-direction interface. The NuMicro™ NUC130/NUC140 contains up to four sets of SPI controller performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller can be set as a master, it also can be configured as a slave device controlled by an off-chip master device. This controller supports a variable serial clock for special application and it also supports 2-bit transfer mode to connect 2 off-chip slave devices at the same time. The SPI controller also supports PDMA function to access the data buffer. 5.8.2 z Features Up to four sets of SPI controller z Support master or slave mode operation z Support 1-bit or 2-bit transfer mode z Configurable bit length up to 32-bit of a transfer word and configurable word numbers up to 2 of a transaction, so the maximum bit length is 64-bit for each data transfer z Provide burst mode operation, transmit/receive can be transferred up to two times word transaction in one transfer z Support MSB or LSB first transfer z 2 device/slave select lines in master mode, but 1 device/slave select line in slave mode z Support byte reorder function z Support byte or word suspend mode z Variable output serial clock frequency in master mode z Support two programmable serial clock frequencies in master mode z Support two channel PDMA request, one for transmitter and another for receiver z Support three wire, no slave select signal, bi-direction interface z The SPI clock rate can be configured to equal the system clock rate - 40 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.9 Timer Controller (TMR) 5.9.1 Overview The timer controller includes four 32-bit timers, TIMER0~TIMER3, which allows user to easily implement a timer control for applications. The timer can perform functions like frequency measurement, event counting, interval measurement, clock generation, delay timing, and so on. The timer can generate an interrupt signal upon timeout, or provide the current value during operation. 5.9.2 Features z 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter z Independent clock source for each timer z Provides one-shot, periodic, toggle and continuous counting operation modes z Time out period = (Period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit TCMP) z Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period of timer clock z 24-bit timer value is readable through TDR (Timer Data Register) z Support event counting function to count the event from external pin z Support input capture function to capture or reset counter value - 41 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.10 Watchdog Timer (WDT) 5.10.1 Overview The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports another function to wake-up chip from power down mode. The watchdog timer includes an 18-bit free running counter with programmable time-out intervals. Table 5-5 show the watchdog timeout interval selection and Figure 5-64 shows the timing of watchdog interrupt signal and reset signal. Setting WTE (WDTCR [7]) enables the watchdog timer and the WDT counter starts counting up. When the counter reaches the selected time-out interval, Watchdog timer interrupt flag WTIF will be set immediately to request a WDT interrupt if the watchdog timer interrupt enable bit WTIE is set, in the meanwhile, a specified delay time (1024 * TWDT) follows the time-out event. User must set WTR (WDTCR [0]) (Watchdog timer reset) high to reset the 18-bit WDT counter to avoid chip from Watchdog timer reset before the delay time expires. WTR bit is cleared automatically by hardware after WDT counter is reset. There are eight time-out intervals with specific delay time which are selected by Watchdog timer interval select bits WTIS (WDTCR [10:8]). If the WDT counter has not been cleared after the specific delay time expires, the watchdog timer will set Watchdog Timer Reset Flag (WTRF) high and reset chip. This reset will last 63 WDT clocks (TRST) then chip restarts executing program from reset vector (0x0000_0000). WTRF will not be cleared by Watchdog reset. User may poll WTRF by software to recognize the reset source. WDT also provides wake-up function. When chip is powered down and the Watchdog Timer Wake-up Function Enable bit (WDTR[4]) is set, if the WDT counter reaches the specific time interval defined by WTIS (WDTCR [10:8]) , the chip is waken up from power down state. First example, if WTIS is set as 000, the specific time interval for chip to wake up from power down state is 24 * TWDT. When power down command is set by software, then, chip enters power down state. After 24 * TWDT time is elapsed, chip is waken up from power down state. Second example, if WTIS (WDTCR [10:8]) is set as 111, the specific time interval for chip to wake up from power down state is 218 * TWDT. If power down command is set by software, then, chip enters power down state. After 218 * TWDT time is elapsed, chip is waken up from power down state. Notice if WTRE (WDTCR [1]) is set to 1, after chip is waken up, software should clear the Watchdog Timer counter by setting WTR(WDTCR [0]) to 1 as soon as possible. Otherwise, if the Watchdog Timer counter is not cleared by setting WTR (WDTCR [0]) to 1 before time starting from waking up to software clearing Watchdog Timer counter is over 1024 * TWDT , the chip is reset by Watchdog Timer. - 42 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet WTIS Timeout Interval Selection Interrupt Period WTR Timeout startingInterval (WDT_CLK=10 kHz) TINT TTIS MIN. TWTR ~ Max. TWTR 000 24 * TWDT 1024 * TWDT 1.6 ms ~ 104 ms 001 26 * TWDT 1024 * TWDT 6.4 ms ~ 108.8 ms 1024 * TWDT 25.6 ms ~ 128 ms 010 8 2 * TWDT 10 011 2 * TWDT 1024 * TWDT 102.4 ms ~ 204.8 ms 100 212 * TWDT 1024 * TWDT 409.6 ms ~ 512 ms 101 214 * TWDT 1024 * TWDT 1.6384 s ~ 1.7408 s 110 216 * TWDT 1024 * TWDT 6.5536 s ~ 6.656 s 1024 * TWDT 26.2144 s ~ 26.3168 s 111 18 2 * TWDT Table 5-5 Watchdog Timeout Interval Selection TWDT INT RST TTIS TINT 1024 * TWDT TRST Minimum TWTR 63 * TWDT Maximum TWTR TWDT : Watchdog Engine Clock Time Period TTIS : Watchdog Timeout Interval Selection Period TINT : Watchdog Interrupt Period TRST : Watchdog Reset Period TWTR : Watchdog Timeout Interval Period Figure 5-10 Timing of Interrupt and Reset Signal - 43 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.10.2 Features z 18-bit free running counter to avoid chip from Watchdog timer reset before the delay time expires. z Selectable time-out interval (2^4 ~ 2^18) and the time out interval is 104 ms ~ 26.3168 s (if WDT_CLK = 10 kHz). z Reset period = (1 / 10 kHz) * 63, if WDT_CLK = 10 kHz. - 44 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.11 UART Interface Controller (UART) NuMicro™ NUC130/NUC140 provides up to three channels of Universal Asynchronous Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1~2 perform Normal Speed UART, besides, only UART0 and UART1 support flow control function. 5.11.1 Overview The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the CPU. The UART controller also supports IrDA SIR Function, LIN master/slave mode function and RS-485 mode functions. Each UART channel supports seven types of interrupts including transmitter FIFO empty interrupt (INT_THRE), receiver threshold level reaching interrupt (INT_RDA), line status interrupt (parity error or framing error or break interrupt) (INT_RLS), receiver buffer time out interrupt (INT_TOUT), MODEM/Wake-up status interrupt (INT_MODEM), Buffer error interrupt (INT_BUF_ERR) and LIN receiver break field detected interrupt (INT_LIN_RX_BREAK). Interrupts of UART0 and UART2 share the interrupt number 12 (vector number is 28); Interrupt number 13 (vector number is 29) only supports UART1 interrupt. Refer to Nested Vectored Interrupt Controller chapter for System Interrupt Map. The UART0 is built-in with a 64-byte transmitter FIFO (TX_FIFO) and a 64-byte receiver FIFO (RX_FIFO) that reduces the number of interrupts presented to the CPU and the UART1~2 are equipped 16-byte transmitter FIFO (TX_FIFO) and 16-byte receiver FIFO (RX_FIFO). The CPU can read the status of the UART at any time during the operation. The reported status information includes the type and condition of the transfer operations being performed by the UART, as well as 4 error conditions (parity error, framing error, break interrupt and buffer error) probably occur while receiving data. The UART includes a programmable baud rate generator that is capable of dividing clock input by divisors to produce the serial clock that transmitter and receiver need. The baud rate equation is Baud Rate = UART_CLK / M * [BRD + 2], where M and BRD are defined in Baud Rate Divider Register (UA_BAUD). Table 5-6 lists the equations in the various conditions and Table 5-7 list the UART baud rate setting table. Mode DIV_X_EN DIV_X_ONE Divider X BRD Baud rate equation 0 0 0 B A UART_CLK / [16 * (A+2)] 1 1 0 B A UART_CLK / [(B+1) * (A+2)] , B must >= 8 2 1 1 Don’t care A UART_CLK / (A+2), A must >=3 Table 5-6 UART Baud Rate Equation System clock = internal 22.1184 MHz high speed oscillator Mode0 Baud rate Mode1 Mode2 Parameter Register Parameter Register Parameter Register 921600 x x A=0,B=11 0x2B00_0000 A=22 0x3000_0016 460800 A=1 0x0000_0001 A=1,B=15 A=2,B=11 0x2F00_0001 0x2B00_0002 A=46 0x3000_002E - 45 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet System clock = internal 22.1184 MHz high speed oscillator Mode0 Baud rate Mode1 Mode2 Parameter Register Parameter Register Parameter Register 230400 A=4 0x0000_0004 A=4,B=15 A=6,B=11 0x2F00_0004 0x2B00_0006 A=94 0x3000_005E 115200 A=10 0x0000_000A A=10,B=15 0x2F00_000A A=14,B=11 0x2B00_000E A=190 0x3000_00BE 57600 A=22 0x0000_0016 A=22,B=15 0x2F00_0016 A=30,B=11 0x2B00_001E A=382 0x3000_017E 38400 A=34 A=62,B=8 0x2800_003E 0x0000_0022 A=46,B=11 0x2B00_002E A=34,B=15 0x2F00_0022 A=574 0x3000_023E 19200 A=70 A=126,B=8 0x2800_007E 0x0000_0046 A=94,B=11 0x2B00_005E A=70,B=15 0x2F00_0046 A=1150 0x3000_047E 9600 A=142 A=254,B=8 0x2800_00FE 0x0000_008E A=190,B=11 0x2B00_00BE A=142,B=15 0x2F00_008E A=2302 0x3000_08FE 4800 A=286 A=510,B=8 0x2800_01FE 0x0000_011E A=382,B=11 0x2B00_017E A=286,B=15 0x2F00_011E A=4606 0x3000_11FE Table 5-7 UART Baud Rate Setting Table The UART0 and UART1 controllers support auto-flow control function that uses two low-level signals, /CTS (clear-to-send) and /RTS (request-to-send), to control the flow of data transfer between the UART and external devices (ex: Modem). When auto-flow is enabled, the UART is not allowed to receive data until the UART asserts /RTS to external device. When the number of bytes in the RX FIFO equals the value of RTS_TRI_LEV (UA_FCR [19:16]), the /RTS is deasserted. The UART sends data out when UART controller detects /CTS is asserted from external device. If a valid asserted /CTS is not detected the UART controller will not send data out. The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (User must set IrDA_EN (UA_FUN_SEL [1]) to enable IrDA function). The SIR specification defines a short-range infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit. The maximum data rate is 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA SIR Protocol encoder/decoder. The IrDA SIR protocol is half-duplex only. So it cannot transmit and receive data at the same time. The IrDA SIR physical layer specifies a minimum 10ms transfer delay between transmission and reception. This delay feature must be implemented by software. The alternate function of UART controllers is LIN (Local Interconnect Network) function. The LIN mode is selected by setting the UA_FUN_SEL[1:0] to ’01’. In LIN mode, one start bit and 8-bit data format with 1-bit stop bit are required in accordance with the LIN standard. For NuMicro™ NUC100 Series, another alternate function of UART controllers is RS-485 9-bit mode function, and direction control provided by RTS pin or can program GPIO (PB.2 for RTS0 and PB.6 for RTS1) to implement the function by software. The RS-485 mode is selected by setting the UA_FUN_SEL register to select RS-485 function. The RS-485 driver control is implemented using the RTS control signal from an asynchronous serial port to enable the RS-485 driver. In RS-485 mode, many characteristics of the RX and TX are same as UART. - 46 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.11.2 Features z Full duplex, asynchronous communications z Separate receive / transmit 64/16/16 bytes (UART0/UART1/UART2) entry FIFO for data payloads z Support hardware auto flow control/flow control function (CTS, RTS) and programmable RTS flow control trigger level (UART0 and UART1 support) z Programmable receiver buffer trigger level z Support programmable baud-rate generator for each channel individually z Support CTS wake-up function (UART0 and UART1 support) z Support 7-bit receiver buffer time out detection function z UART0/UART1 can be served by the DMA controller z Programmable transmitting data delay time between the last stop and the next start bit by setting UA_TOR [DLY] register z Support break error, frame error, parity error and receive / transmit buffer overflow detect function z Fully programmable serial-interface characteristics z „ Programmable number of data bit, 5-, 6-, 7-, 8-bit character „ Programmable parity bit, even, odd, no parity or stick parity bit generation and detection „ Programmable stop bit, 1, 1.5, or 2 stop bit generation Support IrDA SIR function mode „ z z Support for 3-/16-bit duration for normal mode Support LIN function mode „ Support LIN master/slave mode „ Support programmable break generation function for transmitter „ Support break detect function for receiver Support RS-485 function mode. „ Support RS-485 9-bit mode „ Support hardware or software direct enable control provided by RTS pin - 47 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.12 Controller Area Network (CAN) 5.12.1 Overview The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and Module Interface (Refer Error! Reference source not found.). The CAN Core performs communication according to the CAN protocol version 2.0 part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to the physical layer, additional transceiver hardware is required. For communication on a CAN network, individual Message Objects are configured. The Message Objects and Identifier Masks for acceptance filtering of received messages are stored in the Message RAM. All functions concerning the handling of messages are implemented in the Message Handler. These functions include acceptance filtering, the transfer of messages between the CAN Core and the Message RAM, and the handling of transmission requests as well as the generation of the module interrupt. The register set of the C_CAN can be accessed directly by the software through the module interface. These registers are used to control/configure the CAN Core and the Message Handler and to access the Message RAM. 5.12.2 Features z Supports CAN protocol version 2.0 part A and B. z Bit rates up to 1 MBit/s. z 32 Message Objects. z Each Message Object has its own identifier mask. z Programmable FIFO mode (concatenation of Message Objects). z Maskable interrupt. z Disabled Automatic Re-transmission mode for Time Triggered CAN applications. z Programmable loop-back mode for self-test operation. z 16-bit module interfaces to the AMBA APB bus. z Support wake-up function - 48 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.13 PS/2 Device Controller (PS2D) 5.13.1 Overview PS/2 device controller provides basic timing control for PS/2 communication. All communication between the device and the host is managed through the CLK and DATA pins. Unlike PS/2 keyboard or mouse device controller, the received/transmit code needs to be translated as meaningful code by firmware. The device controller generates the CLK signal after receiving a request to send, but host has ultimate control over communication. DATA sent from the host to the device is read on the rising edge and DATA sent from device to the host is change after rising edge. A 16 bytes FIFO is used to reduce CPU intervention. S/W can select 1 to 16 bytes for a continuous transmission. 5.13.2 Features z Host communication inhibit and request to send detection z Reception frame error detection z Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention z Double buffer for data reception z S/W override bus - 49 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.14 I2S Controller (I2S) 5.14.1 Overview The I2S controller consists of IIS protocol to interface with external audio CODEC. Two 8 word deep FIFO for read path and write path respectively and is capable of handling 8 ~ 32 bit word sizes. DMA controller handles the data movement between FIFO and memory. 5.14.2 Features z I2S can operate as either master or slave z Capable of handling 8-, 16-, 24- and 32-bit word sizes z Mono and stereo audio data supported z I2S and MSB justified data format supported z Two 8 word FIFO data buffers are provided, one for transmit and one for receive z Generates interrupt requests when buffer levels cross a programmable boundary z Two DMA requests, one for transmit and one for receive - 50 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.15 Analog-to-Digital Converter (ADC) 5.15.1 Overview NuMicro™ NUC100 Series contains one 12-bit successive approximation analog-to-digital converters (SAR A/D converter) with 8 input channels. The A/D converter supports three operation modes: single, single-cycle scan and continuous scan mode. The A/D converters can be started by software and external STADC pin. 5.15.2 Features z Analog input voltage range: 0~VREF z 12-bit resolution and 10-bit accuracy is guaranteed z Up to 8 single-end analog input channels or 4 differential analog input channels z Maximum ADC clock frequency is 16 MHz z Up to 700K SPS conversion rate z Three operating modes „ Single mode: A/D conversion is performed one time on a specified channel „ Single-cycle scan mode: A/D conversion is performed one cycle on all specified channels with the sequence from the lowest numbered channel to the highest numbered channel „ Continuous scan mode: A/D converter continuously performs Single-cycle scan mode until software stops A/D conversion z An A/D conversion can be started by „ Software write 1 to ADST bit „ External pin STADC z Conversion results are held in data registers for each channel with valid and overrun indicators z Conversion result can be compared with specify value and user can select whether to generate an interrupt when conversion result is equal to the compare register setting z Channel 7 supports 3 input sources: external analog voltage, internal bandgap voltage, and internal temperature sensor output z Support Self-calibration to minimize conversion error - 51 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.16 Analog Comparator (CMP) 5.16.1 Overview NuMicro™ NUC100 Series contains two comparators. The comparators can be used in a number of different configurations. The comparator output is a logical one when positive input greater than negative input, otherwise the output is a zero. Each comparator can be configured to cause an interrupt when the comparator output value changes. The block diagram is shown in Error! Reference source not found.. 5.16.2 Features z Analog input voltage range: 0~5.0 V z Hysteresis function supported z Two analog comparators with optional internal reference voltage input at negative end z One interrupt vector for both comparators - 52 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.17 PDMA Controller (PDMA) 5.17.1 Overview NuMicro™ NUC130/NUC140 contains a peripheral direct memory access (PDMA) controller that transfers data to and from memory or transfer data to and from APB devices. The PDMA has nine channels of DMA (Peripheral-to-Memory or Memory-to-Peripheral or Memory-to-Memory). For each PDMA channel (PDMA CH0~CH8), there is one word buffer as transfer buffer between the Peripherals APB devices and Memory. Software can stop the PDMA operation by disable PDMA [PDMACEN]. The CPU can recognize the completion of a PDMA operation by software polling or when it receives an internal PDMA interrupt. The PDMA controller can increase source or destination address or fixed them as well. Notice: The partial of NuMicro™ NUC130/NUC140 only has 1 PDMA channel (channel 0). 5.17.2 Features z Support nine DMA channels. Each channel can support a unidirectional transfer z AMBA AHB master/slave interface compatible, for data transfer and register read/write z Support source and destination address increased mode or fixed mode z Hardware channel priority. DMA channel 0 has the highest priority and channel 8 has the lowest priority - 53 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 5.18 External Bus Interface (EBI) 5.18.1 Overview The NuMicro™ NUC130/NUC140 LQFP-64 and LQFP-100 package equips an external bus interface (EBI) for external device used. To save the connections between external device and this chip, EBI support address bus and data bus multiplex mode. And, address latch enable (ALE) signal supported differentiate the address and data cycle. 5.18.2 Features External Bus Interface has the following functions: z External devices with max. 64K-byte size (8-bit data width)/128K-byte (16-bit data width) supported z Variable external bus base clock (MCLK) supported z 8-bit or 16-bit data width supported z Variable data access time (tACC), address latch enable time (tALE) and address hold time (tAHD) supported z Address bus and data bus multiplex mode supported to save the address pins z Configurable idle cycle supported for different access condition: Write command finish (W2X), Read-to-Read (R2R) - 54 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 6 6.1 FLASH MEMORY CONTROLLER (FMC) Overview NuMicro™ NUC100 Series equips with 128/64/32K bytes on chip embedded Flash for application program memory (APROM) that can be updated through ISP procedure. In System Programming (ISP) function enables user to update program memory when chip is soldered on PCB. After chip power on, Cortex-M0 CPU fetches code from APROM or LDROM decided by boot select (CBS) in Config0. By the way, NuMicro™ NUC100 Series also provides additional DATA Flash for user, to store some application dependent data before chip power off. For 128K bytes APROM device, the data flash is shared with original 128K program memory and its start address is configurable and defined by user application request in Config1. For 64K/32K bytes APROM device, the data flash is fixed at 4K. 6.2 Features z Run up to 50 MHz with zero wait state for continuous address read access z 128/64/32KB application program memory (APROM) z 4KB in system programming (ISP) loader program memory (LDROM) z Configurable or fixed 4KB data flash with 512 bytes page erase unit z Programmable data flash start address for 128K APROM device z In System Program (ISP) to update on chip Flash - 55 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 7 7.1 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings PARAMETER SYMBOL MIN. MAX UNIT VDD−VSS -0.3 +7.0 V VIN VSS-0.3 VDD+0.3 V 1/tCLCL 4 24 MHz TA -40 +85 °C TST -55 +150 °C - 120 mA Maximum Current out of VSS 120 mA Maximum Current sunk by a I/O pin 35 mA Maximum Current sourced by a I/O pin 35 mA Maximum Current sunk by total I/O pins 100 mA Maximum Current sourced by total I/O pins 100 mA DC Power Supply Input Voltage Oscillator Frequency Operating Temperature Storage Temperature Maximum Current into VDD Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device. - 56 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet 7.2 DC Electrical Characteristics 7.2.1 NuMicro™ NUC130/NUC140 DC Electrical Characteristics (VDD-VSS=3.3 V, TA = 25°C, FOSC = 50 MHz unless otherwise specified.) SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. Operation voltage Power Ground VDD VSS AVSS 2.5 MAX. UNIT 5.5 V -0.3 LDO Output Voltage VLDO -10% Analog Operating Voltage AVDD Analog Reference Voltage Vref IDD1 TYP. VDD =2.5 V ~ 5.5 V up to 50 MHz V 2.5 +10% V 0 VDD V 0 AVDD V 51 VDD > 2.7 V VDD = 5.5 V@50 MHz, mA enable all IP and PLL, XTAL=12 MHz VDD = 5.5 V@50 MHz, Operating Current IDD2 25 IDD3 48 Normal Run Mode @ 50 MHz mA disable all IP and enable PLL, XTAL=12 MHz VDD = 3 V@50 MHz, mA enable all IP and PLL, XTAL=12 MHz VDD = 3 V@50 MHz, IDD4 23 IDD5 19 Operating Current Normal Run Mode @ 12 MHz mA disable all IP and enable PLL, XTAL=12 MHz VDD = 5.5 V@12 MHz, mA enable all IP and disable PLL, XTAL=12 MHz VDD = 5.5 V@12 MHz, IDD6 7 IDD7 17 - 57 - mA disable all IP and disable PLL, XTAL=12 MHz VDD = 3 V@12 MHz, mA enable all IP and disable PLL, XTAL=12 MHz Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. Operating Current TYP. Operating Current 6 VDD = 3 V@12 MHz, mA disable all IP and disable PLL, XTAL=12 MHz IDD9 11 VDD = 5 V@4 MHz, mA enable all IP and disable PLL, XTAL=4 MHz IDD10 3 VDD = 5 V@4 MHz, mA disable all IP and disable PLL, XTAL=4 MHz IDD11 10 VDD = 3 V@4 MHz, mA enable all IP and disable PLL, XTAL=4 MHz IDD12 2.5 VDD = 3 V@4 MHz, mA disable all IP and disable PLL, XTAL=4 MHz IIDLE1 35 VDD= 5.5 V@50 MHz, mA enable all IP and PLL, XTAL=12 MHz IIDLE2 15 VDD=5.5 V@50 MHz, mA disable all IP and enable PLL, XTAL=12 MHz IIDLE3 33 VDD = 3 V@50 MHz, mA enable all IP and PLL, XTAL=12 MHz IIDLE4 13 VDD = 3 V@50 MHz, mA disable all IP and enable PLL, XTAL=12 MHz IIDLE5 10 VDD = 5.5 V@12 MHz, mA enable all IP and disable PLL, XTAL=12 MHz IIDLE6 4.5 VDD = 5.5 V@12 MHz, mA disable all IP and disable PLL, XTAL=12 MHz IIDLE7 9 VDD = 3 V@12 MHz, mA enable all IP and disable PLL, XTAL=12 MHz Idle Mode @ 50 MHz Operating Current Idle Mode UNIT IDD8 Normal Run Mode @ 4 MHz MAX. @ 12 MHz - 58 - Publication Release Date: Jan. 2, 2012 Revision V3.02 NuMicro™ NUC130 Data Sheet SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. Operating Current TYP. MAX. IIDLE8 3.5 VDD = 3 V@12 MHz, mA disable all IP and disable PLL, XTAL=12 MHz IIDLE9 4 VDD = 5 V@4 MHz, mA enable all IP and disable PLL, XTAL=4 MHz IIDLE10 2.5 VDD = 5 V@4 MHz, mA disable all IP and disable PLL, XTAL=4 MHz IIDLE11 3.5 VDD = 3 V@4 MHz, mA enable all IP and disable PLL, XTAL=4 MHz IIDLE12 1.5 VDD = 3 V@4 MHz, mA disable all IP and disable PLL, XTAL=4 MHz IPWD1 12 μA VDD = 5.5 V, RTC OFF, No load @ Disable BOV function IPWD2 9 μA VDD = 3.3 V, RTC OFF, No load @ Disable BOV function IPWD3 μA VDD = 5.5 V, RTC run , No load @ Disable BOV function IPWD4 μA VDD = 3.3 V, RTC run , No load @ Disable BOV function Idle Mode @ 4 MHz Standby Current Power down Mode UNIT Input Current PA, PB, PC, PD, PE (Quasi-bidirectional mode) IIN1 Input Current at /RESET[1] IIN2 Input Leakage Current PA, PB, PC, PD, PE -50 -60 μA VDD = 5.5 V, VIN = 0 V or VIN=VDD -55 -45 -30 μA VDD = 3.3 V, VIN = 0.45 V ILK -2 - +2 μA VDD = 5.5 V, 0