SDSDQAF3-032G-MK

microSD3.0 UHS-I microSD3.0 UHS-I Specification NOTE: INFORMATION IN THIS PRODUCT SPECIFICATION IS SUBJECT TO CHANGE AT ANYTIME WITHOUT NOTICE, ALL PRODUCT SPECIFICATIONS ARE PROVIDED FOR REFERENCE ONLY.TO ANY INTELLECTUAL, PROPERTY RIGHTS IN MK Founder CO., LTD. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED. Revision History: Rev. Date Changes Remark 1.0 2017/12/16 Basic spec and architecture Preliminary MK Founder Technology Corporation Confidential and Proprietary -1- www.mkfounder.com Rev. 1.0 microSD3.0 UHS-I SPEC CONTENTS 1. Overview ................................................................................................ 1 1.1 Product Description ............................................................................ 1 1.2 Features Summary ............................................................................. 1 2. Pin Assignment ...................................................................................... 2 3. Product List ............................................................................................ 3 4. Current Consumption ............................................................................. 4 5. Reliability and Durability ........................................................................ 4 6. SD Card Registers .................................................................................. 4 6.1 Card Identification Register (CID) ......................................................... 4 6.2 Card Specific Data Register (CSD) ........................................................ 5 7. Bus Operation Conditions ....................................................................... 6 7.1 For 3.3V Signaling .............................................................................. 6 7.1.1 Threshold Level for High Voltage Range .............................................. 6 7.1.2 Peak Voltage and Leakage Current ..................................................... 6 7.1.3 Bus Signal Line Load ........................................................................ 6 7.1.4 Bus Signal Levels ............................................................................ 7 7.1.5 Bus Timing(Default)......................................................................... 7 7.1.6 Bus Timing(High-Speed Mode) .......................................................... 9 7.2 For 1.8V Signaling .............................................................................10 7.2.1 Threshold Level for High Voltage Range .............................................10 7.2.2 Peak Voltage and Leakage Current ....................................................10 7.2.3 Bus Timing Specification in SDR12, SDR25, SDR50 and SDR104 Modes . 10 7.2.3.1 Clock Timing ...............................................................................10 7.2.3.2 Card Input Timing .......................................................................11 7.2.3.3 Card Output Timing .....................................................................11 7.2.3.3.1 Output Timing of Fixed Data Window (SDR12, SDR25 and SDR50) ... 11 7.2.3.3.2 Output Timing of Variable Window (SDR104) ................................12 8. Physical Dimension .............................................................................. 12 MK Founder Technology Corporation Confidential and Proprietary -2- www.mkfounder.com Rev. 1.0 microSD3.0 UHS-I SPEC 1. Overview 1.1 Product Description The microSD3.0 Cards are fully compatible with Physical Layer Specification, Version 3.0 (this specification is available from the SDA), support Ultra High Speed(UHS), provides high write/read speed and high IOPS, It was designed to meet the security, high capacity, high performance and environmental requirements inherent in next generation consumer electronic devices. The SD card system is a new mass-storage system based on innovations in semiconductor technology. It has been developed to provide an inexpensive, mechanically robust storage medium in card form for multimedia consumer applications. SD card allows the design of inexpensive players and drivers without moving parts. A low power consumption and a wide supply voltage range favors consumer electronic devices. Ultra High Speed (UHS) Card It provides up to 104MB/s* performance. UHS cards are backward compatible on non-UHS hosts. *Based on internal testing; performance may vary depending upon host device. 1 megabyte (MB) =1,000,000bytes. 1.2 Features Summary -Capacity: 4GB/8GB/16GB/32GB/64GB -Complies to SD specifications version 3.0 -Voltage operating: 2.7~3.6V. -Targeted for portable and stationary applications -Greater Performance Choices -Bus Speed Mode: DS-Default Speed mode: 3.3V signaling, frequency up to 25MHz, up to 12.5MB/sec HS-High Speed mode: 3.3V signaling, frequency up to 50MHz, up to 25MB/sec SDR12-1.8V signaling, frequency up to 25MHz, up to 12.5MB/sec SDR25-1.8V signaling, frequency up to 50MHz, up to 25MB/sec SDR50-1.8V signaling, frequency up to 100MHz, up to 50MB/sec SDR104-1.8V signaling, frequency up to 208MHz, up to 104MB/sec DDR50-1.8V signaling, frequency up to 50MHz, sampled on both clock edges, up to 50MB/s -Switch function command supports Bus Speed Mode, Command System, Drive Strength, and future functions. -password protection (CMD42-LOCK_UNLOCK) -Sophisticated system for error recovery including a powerful ECC -Global Wear Leveling -Power management for low power operation -Add TF card adapter can be used in SD card socket -4- Rev. 1.0 microSD3.0 UHS-I SPEC 2. Pin Assignment SD Mode Pin SPI Mode No. Name Type 1 Dat2 I/O/PP 2 CD/DAT3 I/O/PP 3 CMD PP Command/Response 4 VDD S 5 CLK 6 Description Data Line [Bit 2] Card Detect / Name Type RSV Description Reserved CS I Chip Select DI I Data In Supply voltage VDD S Supply voltage I Clock SCLK I Clock VSS S Supply voltage ground VSS S Supply voltage ground 7 DAT0 I/O/PP Data Line [Bit 0] DO O/PP 8 DAT1 I/O/PP Data Line [Bit 1] RSV Data Line [Bit 3] Data Out Reserved S: power supply; I: input; O: output; PP: I/O using push-pull drivers Table 1: Pin Assignment -5- Rev. 1.0 microSD3.0 UHS-I SPEC 3. Product List Part Number Capacity Actual Speed Class UHS-I Size (Note1) (Note1) Type SDSDQAB-004G-MK 4GB 3.62GB C10,U1,V10 SDR104 SDHC SDSDQAB-008G-MK 8GB 7.68GB C10,U1,V10 SDR104 SDHC SDSDQAB-016G-MK 16GB 14.75GB C10,U1,V10,A1 SDR104 SDHC SDSDQAF3-032G-MK 32GB 29.12GB C10,U1,V10,A1 SDR104 SDHC SDSDQAF3-064G-MK 64GB 58.24GB C10,U1,V10,A1 SDR104 SDHC Table 2：Product List Note1：*Measurement based on VTE3100 Test Metrix device, SW 3.2A software or up version. Test scripts: SD_Card(Spec3.0_High&Extended-Capacity_UHS-I and Non-UHS-I)_Compliance [rev31R].vte SDR104@SDR104-208MHz. SD_Card (Spec2.0-3.0 High&Extended-Capacity_UHS-I) Performance-Speed (Multiple Block Sequential) [rev31M] - SDR104-With Background Data.vte] *Maximum speed differs from the bus I/F speed. It varies depending upon the card performance. The average speed that a device writes to an SD memory card may vary depending upon the device and the operation it is performing. Normal and high-speed cards can also be used with UHS-I host devices, but the high performance enabled by a UHS-I host device can only be achieved with a UHS- I memory card. -6- Rev. 1.0 microSD3.0 UHS-I SPEC 4. Current Consumption Standby current: 500uA（Maximum value） Standby current: 250uA（average value） Operating current: 250mA（Maximum value） Operating current: 150mA（average value） *Test condition: Realtek5308 card reader (Voltage 3.3V), Fluke289C multi-meter. 5. Reliability and Durability Temperature Moisture and corrosion Operation: - 25°C/85°C Storage: -25°C/85°C Operation: 25°C/95% rel. humidity Storage: 40°C/93% rel. hum./500h Salt Water Spray: 3% NaCl/35C; 24h acc. MIL STD Method 1009 Durability 10,000 insertion/removal cycles; Bending 10[N] Center 200[mm/minute] 60[sec] Torque 0.10Nm,+/-2.5 deg.max. Drop test 1.5m free fall Electrostatic IEC 61000-4-2 contact discharge: +/- 2[kV] and +/- 4[kV] 150[pF],330[Ohm] air discharge: up to +/- 15[kV] 150[pF], 330[Ohm] Discharge (ESD) Table 3: Reliability and Durability 6. SD Card Registers 6.1 Card Identification Register (CID) The Card Identification (CID) register is 128 bit wide. It contains the card identification information used during the card identification phase. Every individual flash card shall have a unique identification number. The structure of the CID register is defined in the following table. CID Bit Width Name Field [127:120] 8 Manufacture ID MID [119:104] 16 OEM/Application ID OID [103:64] 40 Product Name PNM [63:56] 8 Product Revision PRV [55:24] 32 Product Serial Number PSN [23:20] 4 Reserved --- [19:8] 12 Manufacturing Date MDT [7:1] 7 CRC7 check sum CRC [0] 1 Not used,always”1 --- Table 4: SD Card CID Table - All contents in the CID table are programmable; Manufacturers can update the CID data through utility. - Manufacturers should license MID and OID field form the SD Card Association(SDA) -7- Rev. 1.0 microSD3.0 UHS-I SPEC 6.2 Card Specific Data Register (CSD) The Card-Specific Data register provides information regarding access to the card contents. The CSD defines the data format, error correction type, maximum data access time, whether the DSR register can be used, etc. The programmable part of the register (entries marked by W or E, see below) can be changed by CMD27. The CSD Table Version 2.0(as shown below) is applied to SDHC and SDXC Cards. Note that bits [15:0] are programmable by the host side. Refer to the SD specification for detailed information CSD Bit Width Name Field Value [127:126] 2 CSD structure CSD_STRUCTURE 01b [125:120] 6 Reserved --- --- [119:112] 8 Data read access-time 1 (TAAC) 0E h [111:104] 8 (NSAC) 00 h Data read access-time2 in CLK cycles(NSA*100) V2.0(>2G B Card) --- [103:96] 8 Max data transfer rate (TRAN_SPEED) 32 5A 0B 2B [95:84] 12 Card command classes CCC 5B5 h [83:80] 4 Max. read data block length (READ_BL_LEN) 9h [79] 1 Partial block read allowed (READ_BL_PARTIAL) 0 [78] 1 Write block misalignment (WRITE_BLK_MISALIGN) 0 [77] 1 Read block misalignment (READ_BLK_MISALIGN) 0 [76] 1 DSR implemented DSR_IMP x [75:70] 6 Reserve --- --- [69:48] 22 Device size C_SIZE xxxxxxh [47] 1 Reserved --- 0 [46] 1 Erase single block enable (ERASE_BLK_EN) 1 [45:39] 7 Erase sector size (SECTOR_SIZE) 7F h [38:32] 7 Write protect group size C_SIZE 0b [31] 1 Write protect group enable --- 0 [30:29] 2 Reserved (ERASE_BLK_EN) 0b [28:26] 3 Write speed factor (SECTOR_SIZE) 010 b [25:22] 4 Max. write data block length (WP_GRP_SIZE) 9h [21] 1 Partial block write allowed (WP_GRP_ENABLE) 0 [20:16] 5 Reserved --- --- [15] 1 File format group (FILE_FORMAT_GRP) 0 [14] 1 Copy flag COPY x [13] 1 Permanent write protection PERM_WRITE_PROTECT x [12] 1 Temporary write protection TMP_WRITE_PROTECT x [11:10] 2 File format (FILE_FORMAT) 00 b [9:8] 2 Reserved --- 00 b [7:1] 7 CRC CRC --- [0] 1 Not used,always’1’ --- 1 -8- Note h h h h 512 Byte Rev. 1.0 microSD3.0 UHS-I SPEC Table 5: CSD (Version 2.0) Table 7. Bus Operation Conditions 7.1 For 3.3V Signaling 7.1.1 Threshold Level for High Voltage Range Parameter Symbol Min Max Supply Voltage VDD 2.7 3.6 Output High Voltage VOH 0.75* VDD Output Low Voltage VOL Input High Voltage VIH Input Low Voltage VIL Unit Remark V V IOH=2mA VDD min 0.125* VDD V IOL=2mA VDD min 0.625* VDD Vss+0.3 V Vss-0.3 0.25* VDD V 250 ms Power Up Time From 0V to VDD min Table 6: Threshold Level for High Voltage 7.1.2 Peak Voltage and Leakage Current Parameter Symbol Peak voltage on all lines Min Max Unit -0.3 VDD+0.3 V -10 10 uA -10 10 uA Remark All Inputs Input Leakage Current All Outputs Output Leakage Current Table 7: Peak Voltage and Leakage Current 7.1.3 Bus Signal Line Load Parameter Symbol Min Max Unit Remark Pull-up resistance RCMD 10 100 KΏ To prevent bus floating 40 pF 1 card CHOST+CBUS shall RDAT Total bus capacitance for CL each signal line Card capacitance for each not exceed 30pF CCARD 10 pF 16 nH 90 KΏ 5 uF signal pin Maximum signal inductance Pull-up resistance inside card(pin1) Capacity Connected to Power Line RDAT3 10 CC May be used for card detection To prevent inrush current Table 8: Bus Operating Conditions - Signal Line's Load -9- Rev. 1.0 microSD3.0 UHS-I SPEC 7.1.4 Bus Signal Levels As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage. Figure 1: Bus Signal Levels To meet the requirements of the JEDEC specification JESD8-1A and JESD8-7, the card input and output voltages shall be within the specified ranges shown in Table 6-2 for any VDD of the allowed voltage range: 7.1.5 Bus Timing(Default) Figure 2: Card input Timing (Default Speed Card) - 10 - Rev. 1.0 microSD3.0 UHS-I SPEC Figure 3: Card Output Timing (Default Speed Mode) (1) 0 Hz means to stop the clock.The given minimum frequency range is for cases were continues Parameter Symb ol Min. Max Unit Remark Clock CLK （All values are referred to min（VIH）and max（VIL）） Clock frequency data transfer Mode fpp 0 25 MHz CCARD ≤ 10pF (1 card) Clock frequency Identification Mode fOD 0(1)/100 400 KHz CCARD ≤ 10pF (1 card) Clock low time tWL 10 ns CCARD ≤ 10pF (1 card) Clock high time tWH 10 ns CCARD ≤ 10pF (1 card) Clock rise time tTLH 10 ns CCARD ≤ 10pF (1 card) Clock fall time tTHL 10 ns CCARD ≤ 10pF (1 card) Inputs CMD, DAT (referenced to CLK) Input set-up time tISU 5 ns CCARD ≤ 10pF (1 card) Input hold time tIH 5 ns CCARD ≤ 10pF (1 card) tODLY 0 14 ns CL ≤ 40pF (1 card) tOH 0 50 ns CL ≤ 40pF (1 card) Outputs CMD, DAT (referenced to CLK) Output Delay time during Data Transfer Mode Output Hold time clock is required (refer to Chapter 4.4-Clock Control) Table 9: Bus Timing-Parameters Values (Default Speed) - 11 - Rev. 1.0 microSD3.0 UHS-I SPEC 7.1.6 Bus Timing (High-Speed Mode) Figure 4:Card Input Timing(High Speed Card) Figure 5: Card Output Timing(High Speed Mode) Parameter Symbol Min. Max Unit Remark MHz CCARD ≤ 10pF (1 card) Clock CLK （All values are referred to min（VIH）and max（VIL）） Clock frequency data transfer Mode fpp 0 50 Clock low time tWL 7 ns CCARD ≤ 10pF (1 card) Clock high time tWH 7 ns CCARD ≤ 10pF (1 card) Clock rise time tTLH 3 ns CCARD ≤ 10pF (1 card) Clock fall time tTHL 3 ns CCARD ≤ 10pF (1 card) Inputs CMD, DAT (referenced to CLK) Input set-up time tISU 6 ns CCARD ≤ 10pF (1 card) Input hold time tTH 2 ns CCARD ≤ 10pF (1 card) Outputs CMD, DAT (referenced to CLK) - 12 - Rev. 1.0 microSD3.0 UHS-I SPEC Output Delay time during Data 14 tODLY Transfer Mode Output Hold time 2.5 tOH Total System capacitance for each CL line1p 40 ns CL ≤ 40pF (1 card) ns CL ≥ 15pF (1 card) pF 1 card (1) In order to satisty sever timing , host shall drive only one card. Table 10: Bus Timing – Parameters Values (High Speed) 7.2 For 1.8V Signaling 7.2.1 Threshold Level for High Voltage Range Parameter Symbol Min Max Unit Remark Supply Voltage VDD 2.7 3.6 V Regulator Voltage VDDIO 1.7 1.95 V Generated by VDD Output High Voltage VOH 1.4 V IOH=2mA VDD min Output Low Voltage VOL 0.45 V IOL=2mA VDD min Input High Voltage VIH 1.27 2.0 V Input Low Voltage VIL Vss-0.3 0.58 V Table 11: Threshold Level for High Voltage 7.2.2 Peak Voltage and Leakage Current Parameter Symbol Input Leakage Current Min -2 Max 2 Unit uA Remark DAT3 pull-up is disconnected Table 12: Peak Voltage and Leakage Current 7.2.3 Bus Timing Specification in SDR12, SDR25, SDR50 and SDR104 Modes 7.2.3.1 Clock Timing Figure 6: Clock Signal Timing Symbol tCLK Min Max Unit 4.8 - ns Remark 208MHz (Max.), Between rising edge, VCT=0.975V tCR, tCF < 2.00ns (max.) at 208MHz, CCARD=10pF tCR, tCF - 0.2* tCLK ns tCR, tCF < 2.00ns (max.) at 100MHz, CCARD=10pF The absolute maximum value of tCR, tCF is 10ns regardless of clock frequency. Clock Duty 30 70 % Table 13: Clock Signal Timing - 13 - Rev. 1.0 microSD3.0 UHS-I SPEC 7.2.3.2 Card Input Timing Figure 7: Card Input Timing Symbol Min Max Unit SDR104 mode tIS 1.40 - ns CCARD = 10pF, VCT = 0.975V tIH 0.80 ns CCARD = 5pF, VCT = 0.975V Symbol Min Max Unit tIS 3.00 - ns CCARD = 10pF, VCT = 0.975V tIH 0.80 - ns CCARD = 5pF, VCT = 0.975V SDR12, SDR25 and SDR50 modes Table 14: SDR50 and SDR104 Input Timing 7.2.3.3 Card Output Timing 7.2.3.3.1 Output Timing of Fixed Data Window (SDR12, SDR25 and SDR50) Figure 8: Output Timing of Fixed Data Window Symbol Min Max Unit tODLY - 7.5 ns 14 ns - ns tODLY tOH 1.5 Remark tCLK ≥10.0ns, CL=30pF, using driver Type B, for SDR50. tCLK ≥20.0ns, CL=40pF, using driver Type B, for SDR25 and SDR12. Hold time at the tODLY (min.). CL=15pF Table 15: Output Timing of Fixed Data Window - 14 - Rev. 1.0 microSD3.0 UHS-I SPEC 7.2.3.3.2 Output Timing of Variable Window (SDR104) Figure 9: Output Timing of Variable Data Window Symbol Min Max Unit tOP - 2 UI △tOP -350 +1550 ps tODW 0.60 - UI Remark Card Output Phase Delay variation due to temperature change after tuning tODW = 2.88ns at 208MHz Table 16: Output Timing of Variable Data Window 8. Physical Dimension Type Measurement Length 15mm +/- 0.1mm(B) Width 11mm +/- 0.1mm(A) Thickness 1.0mm+/-0.1mm(C) 0.7mm+/-0.1mm(C1) Weight 0.33 gram Max Physical Dimension Specifications (Unit in mm) - 15 - Rev. 1.0 microSD3.0 UHS-I SPEC Mechanical form factor as follows: (Unit in mm) Figure 10: Dimension Drawing - 16 -