RV1106 Datasheet
Rev 1.1
Rockchip
RV1106
Datasheet
Revision History
Date
2022-04-27
2022-04-06
Revision
1.1
1.0
Description
Update MSL information and package thermal characteristics
Initial released
Copyright 2022 ©Rockchip Electronics Co., Ltd.
1
RV1106 Datasheet
Rev 1.1
Table of Content
Table of Content ...................................................................................................... 2
Figure Index ........................................................................................................... 3
Table Index............................................................................................................. 4
Warranty Disclaimer ................................................................................................. 5
Chapter 1 Introduction ................................................................................... 6
1.1 Overview ............................................................................................... 6
1.2 Features ................................................................................................ 6
1.3 Block Diagram ...................................................................................... 14
Chapter 2 Package Information ...................................................................... 15
2.1 Order Information ................................................................................. 15
2.2 Top Marking ......................................................................................... 15
2.3 Package Dimension ............................................................................... 15
2.4 Pin Number List .................................................................................... 17
Chapter 3 Electrical Specification .................................................................... 19
3.1 Absolute Ratings ................................................................................... 19
3.2 Recommended Operating Condition ......................................................... 19
3.3 DC Characteristics ................................................................................. 20
3.4 Electrical Characteristics for General IO .................................................... 20
3.5 Electrical Characteristics for PLL .............................................................. 21
3.6 Electrical Characteristics for USB2.0 Interface ........................................... 21
3.7 Electrical Characteristics for MIPI CSI interface .......................................... 22
3.8 Electrical Characteristics for Audio CODEC interface ................................... 22
3.9 Electrical Characteristics for SARADC ....................................................... 23
3.10 Electrical Characteristics for TSADC ........................................................ 23
Chapter 4 Thermal Management ..................................................................... 24
4.1 Overview ............................................................................................. 24
4.2 Package Thermal Characteristics ............................................................. 24
Copyright 2022 ©Rockchip Electronics Co., Ltd.
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RV1106 Datasheet
Rev 1.1
Figure Index
Fig.1-1
Fig.2-1
Fig.2-2
Fig.2-3
Block Diagram ...........................................................................................14
Package definition ......................................................................................15
Package Top View ......................................................................................15
Package Bottom View .................................................................................16
Copyright 2022 ©Rockchip Electronics Co., Ltd.
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RV1106 Datasheet
Rev 1.1
Table Index
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
2-1 Pin Number Order Information ................................................................... 17
3-1 Absolute ratings....................................................................................... 19
3-2 Recommended operating condition ............................................................. 19
3-3 DC Characteristics.................................................................................... 20
3-4 Electrical Characteristics for Digital General IO ............................................. 20
3-5 Electrical Characteristics for INT PLL ........................................................... 21
3-6 Electrical Characteristics for FRAC PLL ......................................................... 21
3-7 Electrical Characteristics for USB2.0 Interface .............................................. 21
3-8 HS Receiver AC specifications (for MIPI mode) ............................................. 22
3-9 LP Receiver AC specifications (for MIPI mode) .............................................. 22
3-10 HS Receiver AC specifications (for LVDS mode) .......................................... 22
3-11 Electrical Characteristics for Audio CODEC ................................................. 22
3-12 Electrical Characteristics for SARADC ........................................................ 23
3-13 Electrical Characteristics for TSADC .......................................................... 23
4-1 Thermal Resistance Characteristics ............................................................. 24
Copyright 2022 ©Rockchip Electronics Co., Ltd.
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RV1106 Datasheet
Rev 1.1
Warranty Disclaimer
Rockchip Electronics Co., Ltd makes no warranty, representation or guarantee (expressed, implied, statutory, or otherwise)
by or with respect to anything in this document, and shall not be liable for any implied warranties of non-infringement,
merchantability or fitness for a particular purpose or for any indirect, special or consequential damages.
Information furnished is believed to be accurate and reliable. However, Rockchip Electronics Co., Ltd assumes no
responsibility for the consequences of use of such information or for any infringement of patents or other rights of third
parties that may result from its use.
Rockchip Electronics Co., Ltd’s products are not designed, intended, or authorized for using as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Rockchip Electronics Co., Ltd’s product could create a situation where personal injury or
death may occur, should buyer purchase or use Rockchip Electronics Co., Ltd’s products for any such unintended or
unauthorized application, buyers shall indemnify and hold Rockchip Electronics Co., Ltd and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees
arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended
or unauthorized use, even if such claim alleges that Rockchip Electronics Co., Ltd was negligent regarding the design or
manufacture of the part.
Copyright and Patent Right
Information in this document is provided solely to enable system and software implementers to use Rockchip Electronics Co.,
Ltd ’s products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Rockchip Electronics Co., Ltd does not convey any license under its patent rights nor the
rights of others.
All copyright and patent rights referenced in this document belong to their respective owners
and shall be subject to corresponding copyright and patent licensing requirements.
Trademarks
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Confidentiality
The information contained herein (including any attachments) is confidential. The recipient hereby acknowledges the
confidentiality of this document, and except for the specific purpose, this document shall not be disclosed to any third party.
Reverse engineering or disassembly is prohibited.
ROCKCHIP ELECTRONICS CO.,LTD. RESERVES THE RIGHT TO MAKE CHANGES IN ITS PRODUCTS OR PRODUCT
SPECIFICATIONS WITH THE INTENT TO IMPROVE FUNCTION OR DESIGN AT ANY TIME AND WITHOUT NOTICE
AND IS NOT REQUIRED TO UNDATE THIS DOCUMENTATION TO REFLECT SUCH CHANGES.
Copyright © 2022 Rockchip Electronics Co., Ltd.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or
by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Rockchip
Electronics Co., Ltd.
Copyright 2022 ©Rockchip Electronics Co., Ltd.
5
RV1106 Datasheet
Rev 1.1
Chapter 1 Introduction
1.1 Overview
RV1106 is a highly integrated vision processor SoC for IPC, especially for AI related
application.
It is based on single-core ARM Cortex-A7 32-bit core which integrates NEON and FPU.
There is a 32KB I-cache and 32KB D-cache and 128KB unified L2 cache.
The build-in NPU supports INT4/INT8/INT16 hybrid operation and computing power is up to
0.5TOPs. In addition, with its strong compatibility, network models based on a series of
frameworks such as TensorFlow/MXNet/PyTorch/Caffe can be easily converted.
RV1106 introduces a new generation totally hardware-based maximum 5-Megapixel ISP
(image signal processor). It implements a lot of algorithm accelerators, such as HDR, 3A,
LSC, 3DNR, 2DNR, sharpening, dehaze, gamma correction and so on. Cooperating with two
MIPI CSI (or LVDS) and one DVP (BT.601/BT.656/BT.1120) interface, users can build a
system that receives video data from 3 camera sensors simultaneous.
The video encoder embedded in RV1106 supports H.265/H.264 encoding. It also supports
multi-stream encoding. With the help of this feature, the video from camera can be
encoded with higher resolution and stored in local memory and transferred another lower
resolution video to cloud storage at the same time. To accelerate video processing, an
intelligent video engine with 22 calculation units is also embedded.
RV1106 has a build-in 16-bit DRAM DDR3L capable of sustaining demanding memory
bandwidths. It also integrated build-in RTC, POR, audio codec and MAC PHY.
1.2 Features
The features listed below which may or may not be present in actual product, may be
subject to the third-party licensing requirements. Please contact Rockchip for actual
product feature configurations and licensing requirements.
1.2.1 Application Processor
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Single core ARM Cortex-A7
Full implementation of the ARM architecture v7-A instruction set, ARM Neon Advanced
SIMD
Separately Integrated Neon and FPU
32KB L1 I-Cache and 32KB L1 D-Cache
Unified 128KB L2 Cache for Cortex-A7
TrustZone technology support
One isolated voltage domain to support DVFS
1.2.2 Memory Organization
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Internal on-chip memory
◼ BootRom
◆ Support system boot from the following device:
➢ SPI interface
➢ eMMC interface
➢ SD/MMC interface
◆ Support system code download by the following interface:
➢ USB interface
➢ UART interface
◼ 256KB Share Memory
◼ 8KB PMU SRAM
◼ RV1106G2 SIP 1Gb DDR3L
External off-chip memory
◼ eMMC Interface
◆ Fully compliant with JEDEC eMMC 4.51 specification
◆ Support HS200, but not support CMD Queue
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RV1106 Datasheet
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Rev 1.1
◆ Support three data bus width: 1bit, 4bits or 8bits
SD/MMC Interface
◆ Compatible with SD3.0, MMC ver4.51
◆ Data bus width is 4bits
Flexible Serial Flash Interface (FSPI)
◆ Support transfer data from/to serial flash device
◆ Support 1bit, 2bits or 4bits data bus width
1.2.3 System Component
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MCU
◼ MCU in VD_CORE integrate 16KB Cache
◼ Integrated Programmable Interrupt Controller, all IRQ lines connected to GIC
for CPU also connect to MCU
◼ Integrated Debug Controller with JTAG interface
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CRU (clock & reset unit)
◼ Support total 4 PLLs to generate all clocks
◼ One oscillator with 24MHz clock input
◼ Support clock gating control for individual components
◼ Support global soft-reset control for whole chip, also individual soft-reset for each
component
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PMU (power management unit)
◼ Multiple configurable work modes to save power by different frequency or
automatic clock gating control or power domain on/off control
◼ Lots of wakeup sources in different mode
◼ Support 3 separate voltage domains，VDD_ARM,VDD_LOGIC,VDD_PMU.
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Timer
◼ Support
◼ Support
◼ Support
◼ Support
2 secure timers with 64bits counter and interrupt-based operation
6 non-secure timers with 64bits counter and interrupt-based operation
two operation modes: free-running and user-defined count for each timer
timer work state checkable
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PWM
◼ Support 12 on-chip PWMs (PWM0~PWM11) with interrupt-based operation
◼ Programmable pre-scaled operation to bus clock and then further scaled
◼ Embedded 32-bit timer/counter facility
◼ Support capture mode
◼ Support continuous mode or one-shot mode
◼ Provides reference mode and output various duty-cycle waveform
◼ Optimized for IR application for PWM3, PWM7, PWM11
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Watchdog
◼ 32-bit watchdog counter
◼ Counter counts down from a preset value to 0 to indicate the occurrence of a
timeout
◼ WDT can perform two types of operations when timeout occurs:
◆ Generate a system reset
◆ First generate an interrupt and if this is not cleared by the service routine by
the time a second timeout occurs then generate a system reset
◼ One Watchdog for non-secure application
◼ One Watchdog for secure application
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Interrupt Controller
◼ Support 121 SPI interrupt sources input from different components inside RV1106
◼ Support 16 software-triggered interrupts
◼ Input interrupt level is fixed, high-level sensitive or rising edge sensitive
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RV1106 Datasheet
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Rev 1.1
Support different interrupt priority for each interrupt source, and they are always
software-programmable
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DMAC
◼ Micro-code programming-based DMA
◼ Linked list DMA function is supported to complete scatter-gather transfer
◼ Support data transfer types including memory-to-memory, memory-to-peripherals,
peripherals-to-memory
◼ Totally three embedded DMA controllers for peripheral system
◼ Each DMAC features:
◆ Support 8 channels
◆ 32 hardware requests from peripherals
◆ 2 interrupt output
◆ Support TrustZone technology and programmable secure state for each DMA
channel
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Secure System
◼ Embedded one cipher engines
◆ Support Link List Item (LLI) DMA transfer
◆ Support SHA-1, SHA-256/224, MD5 with hardware padding
◆ Support HMAC of SHA-1, SHA-256, MD5 with hardware padding
◆ Support AES-128, AES-192, AES-256 encrypt and decrypt cipher
◆ Support DES and TDES cipher
◆ Support AES ECB/CBC/OFB/CFB/CTR/CTS/XTS/GCM/CBC-MAC/CMAC mode
◆ Support DES/TDES ECB/CBC/OFB/CFB mode
◆ Support up to 4096 bits PKA mathematical operations for RSA/ECC/SM2
◼ Support generating random numbers, one secure only engine, another one security
configurable
◼ Support secure OTP
◼ Support secure debug
◼ Support secure OS
◼ Except CPU, the other masters in the SoC can also support security and nonsecurity mode by software-programmable
◼ Some slave components in SoC can only be addressed by security master and the
other slave components can be addressed by security master or non-security
master by software-programmable
◼ System SRAM (share memory), part of space is addressed only in security mode
◼ External DDR space can be divided into 16 parts, each part can be softwareprogrammable to be enabled by each master
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Mailbox
◼ One Mailbox in SoC to service CPU and MCU communication
◼ Support four mailbox elements, each element includes one data word, one
command word register and one flag bit that can represent one interrupt
◼ Provide 32 lock registers for software to use to indicate whether mailbox is
occupied
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Decompression
◼ Support for decompressing GZIP files
◼ Support for decompressing data in DEFLATE format
◼ Support for decompressing data in ZLIB format
◼ Support the limit size function of the decompressed data to prevent the memory
from being maliciously destroyed during the decompression process
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Real Time Clock (RTC)
◼ Provides year, month, day, weekday, hours, minutes, and seconds based on a
32.768 kHz crystal oscillator
◼ Support compensation for the second and hour count
Copyright 2022 ©Rockchip Electronics Co., Ltd.
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RV1106 Datasheet
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Rev 1.1
BCD representation of time, calendar and alarm
12- or 24-hour clock with AM and PM in 12-hour mode
Interrupts are separately software maskable
◆ Alarm interrupt
◆ Periodic interrupt
◆ Chip power off interrupt
◆ Battery power atypical interrupt
1.2.4 Video CODEC
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Video Encoder
◼ H.265/HEVC Main Profile, level 5.0
◼ H.264/AVC High Profile, level 5.0
◼ Support multi-channel encoding with performance up to 5-megapixel@30fps
◼ JPEG baseline, up to 4-megapixel @60fps in standalone mode, resolution up to
8192 x 8192
◼ Bitrate up to 60Mbps
◼ Six bit rate control modes (CBR, VBR, FIXQP, AVBR, QPMAP, and CVBR)
◼ Support YUV420 and YUV400 format input
◼ Intelligent encoding mode
◼ 8-area OSD
◼ YUV/RGB video source with crop, rotation and mirror
◼ Ultra-low delay encoding
1.2.5 Neural Process Unit
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Neural network acceleration engine with processing performance up to 0.5 TOPS
Support integer 4, integer 8 and integer 16 operation
Support creating simple custom operators
Support deep learning frameworks: TensorFlow, Caffe, Tflite, Pytorch, Onnx NN, etc.
1.2.6 Rockchip Intelligent Video Engine (RKIVE)
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GMM
◼ Support 1 to 5 gaussian model
BGM (base on codebook)
◼ Support 3 codebook model
Canny
◼ Staging buffer stride require 64 pixel align
◼ Support 3X3 and 5x5 template coefficient
CCL
◼ Support max to 254 connected regions
◼ Support 4-connected and 8-connected region
Stcorner
◼ Support max to 500 corner sort output
LK
◼ Support max to 500 corner input
◼ Support 1~4 optical flow layers
Integral
◼ Require all the buffer base is 16bytes align
LBP
◼ Support simple and absolute value comparison mode
Filter
◼ Support 3X3 and 5x5 mode
Sobel
◼ Support 3X3 and 5x5 mode
Morph
◼ Support eroding and dilating mode
Denoise Filter
◼ Support minimum/median/maximum 3 types filter
DMA
Copyright 2022 ©Rockchip Electronics Co., Ltd.
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RV1106 Datasheet
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Rev 1.1
◼ Support direct copy mode
◼ Support interval copy mode
CSC
◼ Support rgb2yuv, yuv2rgb, rgb2hsv, yuv2hsv
◼ Support 601 and 709 format, full and limit range
Hist/eqhist
◼ Support hist only, eqhist only, hist + eqhist 3 types mode
Logic OP
◼ Support logic and, logic or, logic xor, add, sub, absolute difference
Mag and Ang
◼ Calculation of the image gradient magnitude and direction
Morph
◼ Support eroding and dilating mode
NCC
◼ Calculation of the image normalized cross-correlation
Cast
◼ Data linear transformation
Sad
◼ Support sad size is 4x4, 8x8 and 16x16
Threshold
◼ Convert grayscale into a binary image
Map
◼ Support 8bit to 8bit and 8bit to 16bit map operation
1.2.7 Graphics Engine
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2D Graphics Engine
◼ Input data:
◆ ARGB/RGB888/RGB565/RGB4444/RGB5551
◆ YUV420/YUV422/YVYU422/YVYU420/YUV422SP10bit/YUV420SP10bit
◼ Output data:
◆ ARGB/RGB888/RGB565/RGB4444/RGB5551
◆ YUV420/YUV422/YUV400/Y4/YVYU422/YVYU420
◼ Pixel Format conversion, BT.601/BT.709
◼ Dither operation
◼ Max resolution: 8192x8192 source, 4096x4096 destination
◼ Scaling
◆ Down-scaling: Average filter
◆ Up-scaling: Bi-cubic filter(source>2048 would use Bi-linear)
◆ Arbitrary non-integer scaling ratio, from 1/16 to 16
◼ Rotation
◆ 0, 90, 180, 270-degree rotation
◆ x-mirror, y-mirror
◆ Mirroring and rotation co-operation
◼ BitBLT
◆ Block transfer
◆ Color palette/Color fill, support with alpha
◆ Transparency mode (color keying/stencil test, specified value/value range)
◆ Two source BitBLT
◆ A+B=B only BitBLT, A support rotate & scale when B fixed
◆ A+B=C second source (B) has same attribute with (C) plus rotation function
◼ Alpha Blending
◆ Comprehensive per-pixel alpha(color/alpha channel separately)
◆ Fading
◆ Support SRC1(R2Y)+SRC0(YUV) -> DST(YUV)
◆ Support DST Full CSC convert for YUV2YUV
◼ OSD Automatic Inversion
◆ Supports OSD sources in ARGB8888/ARGB1555/ARGB444/ARGB2BPP format
◆ Support SRC0 and OSD overlay
Copyright 2022 ©Rockchip Electronics Co., Ltd.
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RV1106 Datasheet
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Rev 1.1
Support square mosaic patterns to cover rectangular mosaic areas
1.2.8 Video Input Interface
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MIPI Interface
◼ Two MIPI CSI DPHY
◆ Each MIPI DPHY V1.2, 2lanes, 1.5Gbps per lane
◆ Support to combine 2 DPHY together to one 4lanes
DVP interface
◼ One 8/10/12/16-bit standard DVP interface, up to 100MHz input data
◼ Support BT.601/BT.656 and BT.1120 VI interface
◼ Support the polarity of pixel_clk, hsync, vsync configurable
1.2.9 Image Signal Processor
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Video Capture (VICAP)
◼ Support BT601 YCbCr 422 8bit input, RAW 8/10/12bit input
◼ Support BT656 YCbCr 422 8bit progressive/interlace input
◼ Support BT1120 YCbCr 422 16bit progressive/interlace input, single/dual-edge
sampling
◼ Support YUYV sequence configurable
◼ Support the polarity of hsync and vsync configurable
◼ Support receiving two interfaces of MIPI CSI /LVDS, up to four IDs for each
interface
◼ Support five CSI data formats: RAW8/10/12/14, YUV422
◼ Support three modes of MIPI CSI HDR: virtual channel mode, identification code
mode, line counter mode
◼ Support four LVDS data formats: RAW8/10/12, YUV422
◼ Support reducing frame rate
◼ Support window cropping
◼ Support RAW data through to ISP
◼ Support 8/16/32 times down-sampling for RAW data
◼ Support virtual stride when write to DDR
◼ Support NV16/NV12/YUV400/YUYV output format for YUV data
◼ Support compact/non-compact output format for RAW data
Maximum input: 3072x1728 (5M) @30fps
Minimum input: 256x256
3A: Include Auto Enhance (AE)/Histogram, Auto Focus (AF), and Auto White Balance
(AWB) statistics output
EXPANDER: Sensor expander
BLC: Black Level Correction
DPCC: Static/Dynamic Defect Pixel Cluster Correction
PDAF: Phase Detection Auto Focus
LSC: Lens Shading Correction
Bayer-2DNR: Spatial Bayer-raw Noise Reduction
Bayer-3DNR: Temporal Bayer-raw Noise Reduction
CAC: Chromatic Aberration Correction
HDR-MGE: 2-Frame Merge into High-Dynamic Range
HDR-DRC: HDR Dynamic Range Compression, Tone mapping
GIC: Green Imbalance Correction
DeBayer: Advanced Adaptive Demosaic
CCM/CSM: Color Correction Matrix, RGB2YUV, etc.
Gamma: Gamma out correction
Dehaze/Enhance: Automatic Dehaze and effect enhancement
3DLUT: 3D-LUT Color Palette for Customer
LDCH: Lens Distortion Correction only in the Horizontal direction
YUV-2DNR: Spatial YUV Noise Reduction
Sharp: Image sharpening and boundary filtering
CMSK: Privacy cover and mask
Gain: Image local gain
Copyright 2022 ©Rockchip Electronics Co., Ltd.
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RV1106 Datasheet
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Rev 1.1
Multi-sensor reuse ISP, 4 sensors for maximum
Bus interface: 32bit AHB configuration, 128bit AXI R/W
Low power, auto-gating for each block
MI R/W burst group to improve memory utilization
MI 3+2 path output, MP stepless scaling, SP/BP scaling under 1080p, MPDS/SPDS fixed
1/16 downscaling
1.2.10 Display interface
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Parallel RGB LCD Interface: 18-bit (RGB666), 16-bit (RGB565)
Serial RGB LCD Interface
MCU LCD Interface
Max output resolution: 1280x720 for RGB/BT656/BT1120
1.2.11 Video Output Processor
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Display process
◼ Background layer
◆ programmable 18-bit color
◼ Win1 layer
◆ RGB888, ARGB888, RGB565
◆ Support virtual display
◆ 256 level alpha blending (pre-multiplied alpha support)
◆ Transparency color key
◆ RGB2YCbCr (BT601/BT709)
Others
◼ Support RGB or YUV domain overlay
◼ BCSH (Brightness, Contrast, Saturation, Hue adjustment)
◼ BCSH: YCbCr2RGB (rec601-mpeg/ rec601-jpeg/rec709)
◼ BCSH: RGB2YCbCr (BT601/BT709)
◼ Support dither down allegro RGB888to666 RGB888to565 & dither down frc
(configurable) RGB888to666
◼ Blank and black display
◼ Standby mode
◼ Support all layers reg_done separately
1.2.12 Audio Interface
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I2S0 with 8 channels
◼ Up to 8 channels TX and 8 channels RX path
◼ Audio resolution from 16bits to 32bits
◼ Sample rate up to 192KHz
◼ Provides master and slave work mode, software configurable
◼ Support 3 I2S formats (normal, left-justified, right-justified)
◼ Support 4 PCM formats (early, late1, late2, late3)
Audio Codec
◼ Support two 24-bits ADC channels with 90dB SNR for stereo recording from
microphone
◼ Support one 24-bits DAC channels with 90dB SNR for stereo playback
◼ Support differential and single-ended microphone or line input
◼ Sampling rate of 8KHz/12KHz/16KHz/24KHz/32KHz/44.1kHz/48KHz/96KHz
1.2.13 Connectivity
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SDIO interface
◼ Compatible with SDIO3.0 protocol
◼ 4-bit data bus widths
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MAC 10/100M Ethernet controller and embedded PHY
◼ Support one Ethernet controllers
◼ Support 10/100-Mbps data transfer rates with the RMII interfaces
Copyright 2022 ©Rockchip Electronics Co., Ltd.
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RV1106 Datasheet
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Rev 1.1
Support both full-duplex and half-duplex operation
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USB 2.0
◼ Compatible with USB 2.0 specification
◼ Support one USB 2.0 Host/Device
◼ Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
◼ Support Enhanced Host Controller Interface Specification (EHCI), Revision 1.0
◼ Support Open Host Controller Interface Specification (OHCI), Revision 1.0a
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SPI interface
◼ Support 2 SPI Controllers (SPI0-SPI1)
◼ Support two chip-select output
◼ Support serial-master and serial-slave mode, software-configurable
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I2C Master controller
◼ Support 5 I2C Master(I2C0-I2C4)
◼ Support 7bits and 10bits address mode
◼ Software programmable clock frequency
◼ Data on the I2C-bus can be transferred at rates of up to 100k bits/s in the
Standard-mode, up to 400k bits/s in the Fast-mode
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UART interface
◼ Support 6 UART interfaces (UART0-UART5)
◼ Embedded two 64-byte FIFO for TX and RX operation respectively
◼ Support 5bit, 6bit, 7bit, 8bit serial data transmit or receive
◼ Standard asynchronous communication bits such as start, stop and parity
◼ Support different input clock for UART operation to get up to 4Mbps baud rate
◼ Support auto flow control mode for all UART
1.2.14 Others
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Multiple groups of GPIO
◼ All of GPIOs can be used to generate interrupt
◼ Support level trigger and edge trigger interrupt
◼ Support configurable polarity of level trigger interrupt
◼ Support configurable rising edge, falling edge and both edge trigger interrupt
◼ Support configurable pull direction (a weak pull-up and a weak pull-down)
◼ Support configurable drive strength
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Temperature Sensor (TS-ADC)
◼ Support User-Defined Mode and Automatic Mode
◼ In User-Defined Mode, start_of_conversion can be controlled completely by
software, and also can be generated by hardware.
◼ In Automatic Mode, the temperature of alarm (high/low temperature) interrupt can
be configurable
◼ In Automatic Mode, the temperature of system reset can be configurable
◼ -40~125°C temperature range and 1°C temperature resolution
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Successive approximation ADC (SARADC)
◼ 10-bit resolution
◼ Up to 1MS/s sampling rate
◼ 2 single-ended input channels
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OTP
◼ Support 8K bits Size, 7K bits for secure application
◼ Support Program/Read/Idle mode
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Package Type
◼ RoHS QFN128 (body: 12.3mm x 12.3mm pitch 0.35mm)
Copyright 2022 ©Rockchip Electronics Co., Ltd.
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RV1106 Datasheet
Rev 1.1
1.3 Block Diagram
The following diagram shows the basic block diagram.
Fig.1-1 Block Diagram
Copyright 2022 ©Rockchip Electronics Co., Ltd.
14
RV1106 Datasheet
Rev 1.1
Chapter 2 Package Information
2.1 Order Information
Orderable
Device
RoHS
status
Package
Package Q’ty
Device Feature
RV1106G2
RoHS
QFN128
1520 pcs by tray
Cortex A7 + MCU + 1Gb DDR3L
2.2 Top Marking
Rockchip : Brand Name
RVXXXX : Chip Name
ABC
: Subcontractor Code
XXXXXXX : Die Lot NO #
DEFG
: Date Code
NXXXXXX FXX : Sub-lot info in
OSAT
The first pin
2.3 Package Dimension
Fig.2-1 Package definition
Fig.2-2 Package Top View
Copyright 2022 ©Rockchip Electronics Co., Ltd.
15
RV1106 Datasheet
Rev 1.1
Fig.2-3 Package Bottom View
Fig.2-4 Package Side View
Copyright 2022 ©Rockchip Electronics Co., Ltd.
16
RV1106 Datasheet
Rev 1.1
Fig.2-5 Package Dimension
2.4 MSL Information
Moisture sensitivity Level ：MSL3
2.5 Pin Number List
Table 2-1 Pin Number Order Information
Pin Name
MIPI_AVDD1V8/GPIO7_VCC1V8
VI_CIF_CLKO_M0/MIPI_CLK0_OUT/GPIO3_C4_d
VI_CIF_VSYNC_M0/GPIO3_C5_d
VI_CIF_D10/PWM7_IR_M2/MIPI_CLK1_OUT/GPIO3_C6_d
VI_CIF_D11/UART5_TX_M2/I2C4_SCL_M2/GPIO3_C7_d
VI_CIF_D13/UART5_RTS_M2/I2C3_SCL_M2/GPIO3_D1_d
VI_CIF_D12/UART5_RX_M2/I2C4_SDA_M2/GPIO3_D0_d
1
2
3
4
5
6
7
VI_CIF_D14/UART5_CTS_M2/I2C3_SDA_M2/GPIO3_D2_d
8
VI_CIF_D15/PWM1_M2/GPIO3_D3_d
DVDD_1
SDMMC0_DET/GPIO3_A1_u
SDMMC0_D1/UART2_TX_M0/PWM9_M0/GPIO3_A2_u
GPIO4_VCC
9
10
11
12
13
SDMMC0_D0/UART2_RX_M0/PWM8_M0/GPIO3_A3_u
14
SDMMC0_CLK/UART5_RTS_M0/I2C0_SCL_M2/JTAG_LPMCU_TC
K_M1/PWM10_M0/GPIO3_A4_d
SDMMC0_CMD/UART5_CTS_M0/I2C0_SDA_M2/JTAG_LPMCU_T
MS_M1/PWM11_IR_M0/GPIO3_A5_u
SDMMC0_D3/UART5_TX_M0/JTAG_CPU_TMS_M0/JTAG_HPMCU
_TMS_M1/GPIO3_A6_u
SDMMC0_D2/UART5_RX_M0/JTAG_CPU_TCK_M0/JTAG_HPMCU
_TCK_M1/GPIO3_A7_u
Pin
Pin Name
I2C1_SDA_M0/UART1_CTS_M0/PWM6_M0/GPIO0_A6_d
nPOR
PMU_DVDD0V9
OSC_XIN
OSC_XOUT
OSC_AVDD1V8/PLL_AVDD1V8
OSC_PLL_DVDD
UART3_TX_M0/I2C2_SCL_M0/PWM7_IR_M0/GPIO1_A0_
d
UART3_RX_M0/I2C2_SDA_M0/PWM4_M0/GPIO1_A1_d
PWM0_M0/CPU_AVS/VI_CIF_D0_M1/GPIO1_A2_d
UART1_TX_M0/I2C0_SCL_M0/GPIO1_A3_d
UART1_RX_M0/I2C0_SDA_M0/GPIO1_A4_d
UART4_RX_M0/PWM3_IR_M1/GPIO1_B0_d
UART4_TX_M0/PWM7_IR_M1/SPI1_CS1_M0/VI_CIF_D1
_M1/GPIO1_B1_d
JTAG_CPU_TCK_M1/UART2_TX_M1/JTAG_HPMCU_TCK_
M0/JTAG_LPMCU_TCK_M0/GPIO1_B2_d
JTAG_CPU_TMS_M1/UART2_RX_M1/JTAG_HPMCU_TMS_
M0/JTAG_LPMCU_TMS_M0/GPIO1_B3_u
Pin
65
66
67
68
69
70
71
17
GPIO1_VCC3V3
81
18
DVDD_5
82
15
16
RTC_AVDD3V3
19
RTC_XOUT
20
RTC_XIN
21
SARADC_IN1/PWM1_M1/GPI4_C1_z
22
SARADC_IN0/GPI4_C0_z
23
SARADC_USB_AVDD1V8
24
USB_VBUSDET
25
USB_DM
26
Copyright 2022 ©Rockchip Electronics Co., Ltd.
VO_LCDC_D1/VI_CIF_D8_M1/PWM10_M1/UART4_RTS_
M1/GPIO1_C6_d
VO_LCDC_D0/VI_CIF_D9_M1/PWM11_IR_M1/UART4_CT
S_M1/GPIO1_C7_d
VO_LCDC_CLK/VI_CIF_CLKO_M1/I2C3_SCL_M1/UART5_
TX_M1/PWM11_IR_M2/AUD_DSM_N/GPIO1_D3_d
VO_LCDC_VSYNC/VI_CIF_VSYNC_M1/I2C3_SDA_M1/UA
RT5_RX_M1/SPI0_CS1_M0/PWM0_M1/AUD_DSM_P/GPI
O1_D2_d
VO_LCDC_HSYNC/VI_CIF_HREF_M1/PWM10_M2/UART5
_CTS_M1/UART3_RX_M1/GPIO1_D1_d
GPIO6_VCC
VO_LCDC_DEN/VI_CIF_CLKI_M1/PWM3_IR_M2/UART5_
RTS_M1/UART3_TX_M1/GPIO1_D0_d
VO_LCDC_D2/VI_CIF_D7_M1/PWM9_M1/UART4_TX_M1/
SDMMC1_D2_M1/GPIO1_C5_d
72
73
74
75
76
77
78
79
80
83
84
85
86
87
88
89
90
17
RV1106 Datasheet
Pin Name
Rev 1.1
USB_DP
27
USB_AVDD3V3
28
CODEC_LINEOUT
29
CODEC_VCM
30
CODEC_AVDD1V8
31
CODEC_MICBIAS
CODEC_MIC0N
CODEC_MIC0P
CODEC_MIC1N
CODEC_MIC1P
CODEC_AVSS
EMMC_D5/SPI1_CLK_M0/UART1_RX_M2/I2C2_SCL_M1/GPIO4
_A7_u
EMMC_D3/FSPI_D3/GPIO4_A6_u
EMMC_D4/SPI1_CS0_M0/UART1_TX_M2/I2C2_SDA_M1/GPIO4
_A5_u
32
33
34
35
36
37
Pin Name
VO_LCDC_D3/VI_CIF_D6_M1/PWM8_M1/UART4_RX_M1
/SDMMC1_D3_M1/GPIO1_C4_d
VO_LCDC_D4/VI_CIF_D5_M1/PWM6_M2/I2C4_SDA_M1/
SDMMC1_CMD_M1/SPI0_MISO_M0/GPIO1_C3_d
VO_LCDC_D5/VI_CIF_D4_M1/PWM5_M2/I2C4_SCL_M1/
SDMMC1_CLK_M1/SPI0_MOSI_M0/GPIO1_C2_d
VO_LCDC_D6/VI_CIF_D3_M1/PWM4_M2/SPI0_CLK_M0/
SDMMC1_D0_M1/GPIO1_C1_d
VO_LCDC_D7/VI_CIF_D2_M1/PWM2_M2/SPI0_CS0_M0/
SDMMC1_D1_M1/GPIO1_C0_d
OTP_AVDD1V8/ETH_AVDD1V8/TSADC_AVDD1V8
ETH_PHY_RXN
ETH_PHY_RXP
ETH_PHY_TXN
ETH_PHY_TXP
ETH_AVDD3V3
38
ETH_EXTR
102
39
103
EMMC_D0/FSPI_D0/GPIO4_A4_u
41
EMMC_D1/FSPI_D1/GPIO4_A3_u
42
GPIO3_VCC
43
EMMC_D2/FSPI_D2/GPIO4_A2_u
EMMC_D6/SPI1_MOSI_M0/UART0_TX_M2/I2C0_SCL_M1/GPIO
4_A1_u
EMMC_D7/SPI1_MISO_M0/UART0_RX_M2/I2C0_SDA_M1/GPIO
4_A0_u
44
EMMC_CMD/FSPI_CS0/GPIO4_B0_u
47
EMMC_CLK/FSPI_CLK/GPIO4_B1_d
48
DDR_VDDQ_1
49
DDR_VDDQ_2
50
DVDD_2
DRAM_ZQ
51
52
DDR_PLL_AVDD1V8
53
DVDD_3
54
DVDD_4
55
DDR_VDDQ_3
56
TVSS
57
UART0_RX_M0/CLK_32K/CLK_REFOUT/RTC_CLKO/GPIO0_A0_z
58
UART0_TX_M0/PWM2_M0/GPIO0_A1_d
59
PWM3_IR_M0/GPIO0_A2_d
60
PMU_VCC3V3
61
PMIC_PWR_CTRL_M1/GPIO0_A3_u
62
PMIC_PWR_CTRL_M0/PWM1_M0/GPIO0_A4_d
63
I2C1_SCL_M0/UART1_RTS_M0/PWM5_M0/GPIO0_A5_d
64
DVDD_6
UART0_TX_M1/I2C1_SDA_M1/VO_LCDC_D17/PWM6_M1
/GPIO2_B1_d
UART0_TX_M1/I2C1_SDA_M1/VO_LCDC_D17/PWM6_M1
/GPIO2_B1_d
UART0_CTS_M1/I2S0_SDO1_SDI3/VO_LCDC_D15/PWM
4_M1/I2C3_SDA_M0/PRELIGHT_TRIG_OUT/GPIO2_A7_d
UART0_RTS_M1/I2S0_SDO2_SDI2/VO_LCDC_D14/PWM
2_M1/I2C3_SCL_M0/FLASH_TRIG_OUT/GPIO2_A6_d
GPIO5_VCC
SDMMC1_D1_M0/I2S0_SCLK/VO_LCDC_D8/UART1_CTS
_M1/I2C4_SDA_M0/GPIO2_A0_d
SDMMC1_D1_M0/I2S0_SCLK/VO_LCDC_D8/UART1_CTS
_M1/I2C4_SDA_M0/GPIO2_A0_d
SDMMC1_CLK_M0/I2S0_MCLK/VO_LCDC_D10/GPIO2_A
2_d
SDMMC1_CMD_M0/I2S0_SDO3_SDI1/VO_LCDC_D11/GP
IO2_A3_d
SDMMC1_D3_M0/I2S0_SDO0/VO_LCDC_D12/UART1_TX
_M1/GPIO2_A4_d
SDMMC1_D2_M0/I2S0_SDI0/VO_LCDC_D13/UART1_RX
_M1/GPIO2_A5_d
CPU_DVDD
DVDD_7
VI_CIF_D0_M0/MIPI_CSI_RX_D3N/LVDS_RX_D3N/GPIO
3_B0_d
VI_CIF_D1_M0/MIPI_CSI_RX_D3P/LVDS_RX_D3P/GPIO3
_B1_d
VI_CIF_D2_M0/MIPI_CSI_RX_CK1N/LVDS_RX_CK1N/GP
IO3_B2_d
VI_CIF_D3_M0/MIPI_CSI_RX_CK1P/LVDS_RX_CK1P/GPI
O3_B3_d
VI_CIF_D4_M0/MIPI_CSI_RX_D2N/LVDS_RX_D2N/GPIO
3_B4_d
VI_CIF_D5_M0/MIPI_CSI_RX_D2P/LVDS_RX_D2P/GPIO3
_B5_d
VI_CIF_D6_M0/MIPI_CSI_RX_D1N/LVDS_RX_D1N/GPIO
3_B6_d
VI_CIF_D7_M0/MIPI_CSI_RX_D1P/LVDS_RX_D1P/GPIO3
_B7_d
VI_CIF_D8_M0/MIPI_CSI_RX_CK0N/LVDS_RX_CK0N/GP
IO3_C0_d
VI_CIF_D9_M0/MIPI_CSI_RX_CK0P/LVDS_RX_CK0P/GPI
O3_C1_d
VI_CIF_CLKI_M0/MIPI_CSI_RX_D0N/LVDS_RX_D0N/GPI
O3_C2_d
VI_CIF_HREF_M0/MIPI_CSI_RX_D0P/LVDS_RX_D0P/GPI
O3_C3_d
VSS
Copyright 2022 ©Rockchip Electronics Co., Ltd.
Pin
40
45
46
Pin
91
92
93
94
95
96
97
98
99
100
101
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
E-PAD
18
RV1106 Datasheet
Rev 1.1
Chapter 3 Electrical Specification
3.1 Absolute Ratings
The below table provides the absolute ratings.
Absolute maximum or minimum ratings specify the values beyond which the device may be
damaged permanently. Long-term exposure to absolute maximum ratings conditions may
affect device reliability.
Table 3-1 Absolute ratings
Parameters
Related Power Group
Min
Supply voltage for CPU
Max
Unit
CPU_DVDD
0
TBD
V
Supply voltage for LOGIC
DVDD_i(i=1~7)
0
0.99
V
Supply voltage for PMU
PMU_DVDD0V9
0
0.99
V
Supply voltage for RTC
RTC_AVDD3V3
0
3.6
V
DVDD_i(i=1~7)
PMU_DVDD0V9
OSC_PLL_DVDD
0
0.99
V
GPIOi_VCC(i=3~6, 1.8V/3.3V mode)
0
3.63
V
0
1.98
V
0
3.63
V
0.9V supply voltage
1.8V/3.3V supply voltage
1.8V supply voltage
3.3V supply voltage
Supply voltage for DDR IO
OSC_AVDD1V8/PLL_AVDD1V8
MIPI_AVDD1V8/GPIO7_VCC1V8
SARADC_USB_AVDD1V8
DDR_PLL_AVDD1V8
OTP_AVDD1V8/ETH_AVDD1V8/TSADC_AVDD1V8
CODEC_AVDD1V8
GPIO1_VCC3V3
PMU_VCC3V3
RTC_AVDD3V3
USB_AVDD3V3
ETH_AVDD3V3
VDDIO_DDR_i（i=1~3）
Storage Temperature
Max Conjunction Temperature
0
TBD
V
Tstg
NA
NA
℃
Tj
NA
NA
℃
3.2 Recommended Operating Condition
Following table describes the recommended operating condition.
Table 3-2 Recommended operating condition
Parameters
Symbol
Min
Typ
Max
Unit
CPU_DVDD
TBD
0.90
TBD
V
Voltage for LOGIC
DVDD_i(i=1~7)
0.81
0.90
TBD
V
Voltage for PMU
PMU_DVDD0V9
0.81
0.90
TBD
V
Voltage for CPU
Voltage for RTC
RTC_AVDD3V3
1.6
3.3
3.6
V
Voltage for PLL Analog (1.8V)
OSC_AVDD1V8/PLL_AVDD1V8
1.62
1.8
TBD
V
Voltage for GPIO (1.8V/3.3V)
GPIOi_VCC(i=3~6)
1.62
3.0
1.8
3.3
1.98
3.465
V
Voltage for GPIO (1.8V only)
MIPI_AVDD1V8/GPIO7_VCC1V8
1.62
1.8
1.98
V
Voltage for GPIO (3.3V only)
GPIO1_VCC3V3
PMU_VCC3V3
3.0
3.3
3.465
V
SARADC_USB_AVDD1V8
1.62
1.8
1.98
V
USB_AVDD3V3
3.0
3.3
3.6
V
OTP_AVDD1V8/ETH_AVDD1V8/TSADC_AVDD1V8
1.62
1.8
1.98
V
ETH_AVDD3V3
2.97
3.3
3.63
V
CODEC_AVDD1V8
1.62
1.8
1.98
V
Voltage for MIPI Analog
MIPI_AVDD1V8/GPIO7_VCC1V8
1.62
1.8
1.98
V
Voltage for DDR PHY PLL
DDR_PLL_AVDD1V8
TBD
1.8
TBD
V
TA
0
NA
80
℃
Voltage for USB/SARADC
Analog (1.8V)
Voltage for USB Analog
(3.3V)
Voltage for OTP/MAC Analog
(1.8V)
Voltage for MAC Analog
(3.3V)
Voltage for CODEC Analog
Ambient Operating
Temperature
Copyright 2022 ©Rockchip Electronics Co., Ltd.
19
RV1106 Datasheet
Rev 1.1
3.3 DC Characteristics
Table 3-3 DC Characteristics
Parameters
Digital GPIO
@3.3V
Digital GPIO
@1.8V
Symbol
MIPI_LVDS
Combo IO@
MIPI HS
receiver mode
MIPI_LVDS
Combo IO@
MIPI LP receiver
mode
MIPI_LVDS
Combo IO@
1.8V TTL RX
mode
Typ
Max
Unit
Input Low Voltage
Vil
-0.3
NA
0.8
V
Input High Voltage
Vih
2.0
NA
VDDO+0.3
V
Output Low Voltage
Vol
-0.3
NA
0.4
V
Output High Voltage
Voh
2.4
NA
VDDO+0.3
V
Pullup Resistor
Rpu
16
25
43
Kohm
Pulldown Resistor
Rpd
16
25
43
Kohm
0.35*VDDO
V
VDDO+0.3
V
Input Low Voltage
Vil
-0.3
NA
Input High Voltage
Vih
0.65*VDDO
NA
Output Low Voltage
Vol
-0.3
NA
0.4
V
Output High Voltage
Voh
1.4
NA
VDDO+0.3
V
43
Kohm
43
Kohm
Pullup Resistor
Rpu
16
25
Pulldown Resistor
Rpd
16
25
Parameters
MIPI_LVDS
Combo
IO@LVDS HS
receiver mode
Min
Symbol
Min
Typ
Max
Unit
Common-mod voltage HS receive mode
VCMRX(DC)
0.8
NA
1.32
V
Differential input high threshold
VIDTH
NA
NA
70
mV
Differential input low threshold
VIDTL
-70
NA
NA
mV
Single-ended input high voltage
VIHHS
NA
NA
1.5
V
Single-ended input low voltage
VILHS
-40
NA
NA
mV
Differential input impedance
ZID
80
100
125
ohm
Common-mod voltage HS receive mode
VCMRX(DC)
70
NA
300
mV
Differential input high threshold
VIDTH
NA
NA
70
mV
Differential input low threshold
VIDTL
-70
NA
NA
mV
Single-ended input high voltage
VIHHS
NA
NA
460
mV
Single-ended input low voltage
VILHS
-40
NA
NA
mV
Single-ended threshold for HS
termination enable
VTERM-EN
NA
NA
450
mV
Differential input impedance
ZID
80
100
125
ohm
Logic 1 input voltage
VIH
880
NA
NA
mV
Logic 0 input voltage, not in ULP State
VIL
NA
NA
550
mV
Logic 0 input voltage, ULP State
VIL-ULPS
NA
NA
300
mV
Input hysteresis
VHYST
25
NA
NA
mV
Logic 1 input voltage
VIH
1.2
NA
1.58
V
Logic 0 input voltage, not in ULP State
VIL
NA
NA
0.6
V
VHYST
25
NA
NA
mV
Input hysteresis
3.4 Electrical Characteristics for General IO
Table 3-4 Electrical Characteristics for Digital General IO
Parameters
Symbol
Input leakage current
Tri-state output leakage
current
Ii
Ioz
Digital GPIO
@3.3V
High level input current
Copyright 2022 ©Rockchip Electronics Co., Ltd.
Iih
Test condition
Min
Typ
Max
Unit
Vin = 3.3V or 0V
NA
NA
10
uA
Vout = 3.3V or 0V
NA
NA
10
uA
Vin = 3.3V, pulldown
disabled
NA
NA
10
uA
Vin = 3.3V, pulldown
enabled
NA
NA
10
uA
20
RV1106 Datasheet
Rev 1.1
Parameters
Symbol
Low level input current
Iil
Input leakage current
Ii
Tri-state output leakage
current
Digital GPIO
@1.8V
Ioz
High level input current
Min
Typ
Max
Unit
NA
NA
10
uA
NA
NA
10
uA
Vin = 1.8V or 0V
NA
NA
10
uA
Vout = 1.8V or 0V
NA
NA
10
uA
NA
NA
10
uA
NA
NA
10
uA
NA
NA
10
uA
NA
NA
10
uA
Vin = 1.8V, pulldown
disabled
Vin = 1.8V, pulldown
enabled
Vin = 0V, pullup
disabled
Vin = 0V, pullup
enabled
Iih
Low level input current
Test condition
Vin = 0V, pullup
disabled
Vin = 0V, pullup
enabled
Iil
Note: VDDO and DVDD are both IO power Supply
3.5 Electrical Characteristics for PLL
Table 3-5 Electrical Characteristics for INT PLL
Parameters
Symbol
Test condition
Min
Typ
Max
Unit
Input clock
frequency(Frac)
Fin
Fin = FREF @1.8V/0.99V
10
NA
800
MHz
VCO operating range
Fvco
475
NA
1900
MHz
Output clock
frequency
Fout
9
NA
1900
MHz
Lock time
Tlt
NA
1000
1500
Input
clock
cycles
Fvco = Fref * FBDIV
@3.3V/0.99V
Fout = Fvco/POSTDIV
@3.3V/0.99V
@ 3.3V/0.99V,
FREF=24M,REFDIV=1
Table 3-6 Electrical Characteristics for FRAC PLL
Parameters
Symbol
Test condition
Min
Typ
Max
Unit
Fin
Fin = FREF @1.8V/0.99V
1
NA
1200
MHz
950
NA
3800
MHz
NA
3800
MHz
500
Input
clock
cycles
Input clock
frequency(Frac)
VCO operating range
Fvco
Output clock
frequency
Fout
Lock time
Tlt
Fvco = Fref * FBDIV
@3.3V/0.99V
Fout = Fvco/POSTDIV
@3.3V/0.99V
19
@ 3.3V/0.99V,
FREF=24M,REFDIV=1
NA
250
Notes:
①
②
③
REFDIV is the input divider value;
FBDIV is the feedback divider value;
POSTDIV is the output divider value
3.6 Electrical Characteristics for USB2.0 Interface
Table 3-7 Electrical Characteristics for USB2.0 Interface
Parameters
Symbol
Test condition
Min
Typ
Max
Unit
40.5
45
49.5
ohms
40.5
45
49.5
Transmitter
Output resistance
ROUT
Output Capacitance
COUT
Output Common Mode Voltage
VM
Differential output signal high
VOH
Classic mode (Vout = 0 or
3.3V)
HS mode (Vout = 0 to
800mV)
seen from D+ or DClassic (LS/FS) mode
pF
1.45
1.65
1.85
V
0.2
0.225
V
Classic (LS/FS); Io=0mA
2.97
3.3
3.63
V
Classic (LS/FS); Io=6mA
2.2
2.7
NA
V
360
400
440
mV
-0.33
0
0.33
V
Classic (LS/FS); Io=6mA
NA
0.3
0.8
V
HS mode; Io=0mA
-40
0
40
mV
Classic (LS/FS); Io=0mA
VOL
3
0.175
HS mode
HS mode; Io=0mA
Differential output signal low
ohms
Copyright 2022 ©Rockchip Electronics Co., Ltd.
21
RV1106 Datasheet
Rev 1.1
Parameters
Symbol
Test condition
Min
Typ
Max
Unit
Classic mode
NA
+-250
NA
mV
HS mode
NA
+-25
NA
mV
Classic mode
HS mode (differential and
squelch comparator)
HS mode (disconnect
comparator)
0.8
1.65
2.5
V
0.1
0.2
0.3
V
0.5
0.6
0.7
V
Input capacitance (seen at D+ or
D-)
NA
NA
3
pF
Squelch threshold
100
NA
150
mV
Disconnect threshold
570
600
664
mV
Receiver
Receiver sensitivity
RSENS
Receiver common mode
RCM
3.7 Electrical Characteristics for MIPI CSI interface
Table 3-8 HS Receiver AC specifications (for MIPI mode)
Parameters
Common-mode interference
beyond 450 MHz
Common-mode interference
50MHz – 450MHz
Common-mode termination
Symbol
Min
Typ
Max
Unit
ΔVCMRX(HF)
NA
NA
100
mV
ΔVCMRX(LF)
-50
NA
50
mV
CCM
NA
NA
60
pF
Table 3-9 LP Receiver AC specifications (for MIPI mode)
Parameters
Symbol
Min
Typ
Max
Unit
Input pulse rejection
eSPIKE
NA
NA
300
V.ps
Minimum pulse width response
TMIN-RX
20
NA
NA
ns
Peak interference amplitude
VINT
NA
NA
200
mv
Interference frequency
fINT
450
NA
NA
MHz
Table 3-10 HS Receiver AC specifications (for LVDS mode)
Parameters
Common-mode interference
beyond 450 MHz
Common-mode interference
50MHz – 450MHz
Common-mode termination
Symbol
Min
Typ
Max
Unit
ΔVCMRX(HF)
NA
NA
100
mV
ΔVCMRX(LF)
-50
NA
50
mV
CCM
NA
NA
50
pF
3.8 Electrical Characteristics for Audio CODEC interface
Table 3-11 Electrical Characteristics for Audio CODEC
Test conditions: AVDD = 1.8V, DVDD = 0.8V, TA = 25°C, 1KHz Sine Input, Fs = 48KHz
Parameters
Analog Supply
Test
condition
Operating Condition
Symbol
Min
Typ
Max
Units
AVDD
1.62
1.8
1.98
V
VMICB
0.8*AVDD
NA
0.975*AVDD
V
IMICB
NA
NA
3
mA
0
NA
20
dB
Microphone Bias
Bias Voltage
Bias Current
Microphone Gain Boost PGA
Programmable Gain
GBST
Gain Step Size
Input Resistance
RIN
Input Capacitance
CIN
NA
20
NA
dB
GBST=0dB
NA
44
NA
KΩ
GBST=20dB
NA
8
NA
KΩ
NA
10
NA
pF
-9
NA
37.5
dB
NA
1.5
NA
dB
ALC PGA
Programmable Gain
GALC
Gain Step Size
Copyright 2022 ©Rockchip Electronics Co., Ltd.
22
RV1106 Datasheet
Rev 1.1
Parameters
Test
condition
Symbol
Min
Typ
Max
Units
NA
92
NA
dB
NA
-80
NA
dB
NA
80
NA
dB
NA
80
NA
dB
0.1
0.125
0.125
-39
NA
6
dB
NA
1.5
NA
dB
NA
93
NA
dB
NA
-84
NA
dB
NA
55
NA
dB
NA
0.01
NA
mA
NA
2.5
NA
mA
NA
2.5
NA
mA
ADC
Signal to Noise Ratio
SNR
Total Harmonic Distortion
THD
Aweighted
-3dBFS
input
Channel Separation
Power Supply Rejection
1KHz
PSRR
Digital Filter Pass Band Ripple
DAC Line Output
Programmable Gain
GDRV
Gain Step Size
Signal to Noise Ratio
SNR
Total Harmonic Distortion
THD
Power Supply Rejection
Aweighted
-3dBFS
output
600Ω load
1KHz
PSRR
Power Consumption
Standby
Mono Recording
Quiescent
output
Mono Playback
3.9 Electrical Characteristics for SARADC
Table 3-12 Electrical Characteristics for SARADC
Parameters
Symbol
Test condition
Resolution
Min
Typ
Max
Unit
NA
10
NA
bit
Effective Number of Bit
ENOB
NA
9
NA
bit
Differential Non-Linearity
DNL
-1
NA
+1
LSB
Integral Non-Linearity
INL
-2
NA
+2
LSB
Reference voltage
VREFP
NA
1.8
NA
V
Input Capacitance
CIN
NA
8
NA
pF
Sampling Rate
fS
NA
NA
1
MS/s
Spurious Free Dynamic Range
SFDR
NA
61
NA
dB
Signal to Noise and Harmonic Ratio
SNDR
NA
56
NA
dB
fS=1MS/s fOUT=1.17KHz
3.10 Electrical Characteristics for TSADC
Table 3-13 Electrical Characteristics for TSADC
Parameters
Symbol
Test condition
Min
Typ
Max
Unit
Accuracy from -40℃ to 125℃
TJACC
NA
NA
±3
℃
Sensing Temperature Range
TRANGE
-40
NA
125
℃
Resolution
TLSB
NA
0.6
NA
℃
Copyright 2022 ©Rockchip Electronics Co., Ltd.
23
RV1106 Datasheet
Rev 1.1
Chapter 4 Thermal Management
4.1 Overview
For reliability and operability concerns, the absolute maximum junction temperature has to
be below 125℃.
4.2 Package Thermal Characteristics
Table 4-1 provides the thermal resistance characteristics for the package used on the SoC.
The resulting simulation data for reference only, please prevail in kind test.
Table 4-1 Thermal Resistance Characteristics
Parameter
Symbol
Typical
Unit
Junction-to-ambient thermal resistance
𝜽𝑱𝑨
27.3
(℃/𝑾)
Junction-to-board thermal resistance
𝜽𝑱𝑩
12.5
(℃/𝑾)
Junction-to-case thermal resistance
𝜽𝑱𝑪
8.4
(℃/𝑾)
Note: The JEDEC 2S2P PCB is 4 layers, 114.3mm*76.2mm.
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