Application Note: AN_ SY8388A
High Efficiency Fast Response, 8A, 24V Input
Synchronous Step Down Regulator
General Description
Features
SY8388A develops a high efficiency synchronous stepdown DC/DC regulator capable of delivering 8A
current over a wide input voltage range of 4V to 24V.
Ordering Information
SY8388 □(□□)□
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Package type
QFN2.5×2.5-16
Note
--
LCD-TV/Net-TV/3DTV
Set Top Box
Notebook
High Power AP
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Ordering Number
SY8388ARHC
Applications
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Temperature Code
Package Code
Optional Spec Code
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Internal 20mΩ power and 10mΩ synchronous rectifier
switches provide excellent efficiency over a range of
applications, especially for low output voltages and low
duty cycles. SY8388A also integrates a bypass switch
which allows the IC to be powered by external DC
source. Cycle-by-cycle current limit, input under
voltage lock-out, internal soft-start, output under
voltage protection and over voltage protection and
thermal shutdown provide safe operation in all
operating conditions. The SY8388A is available in a
compact QFN2.5×2.5-16 package.
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Silergy’s proprietary Instant-PWM™ fast-response,
constant-on-time (COT) PWM control method supports
high input/output voltage ratios (low duty cycles), and
fast transient response while maintaining a near
constant operating frequency over line, load and output
voltage ranges. This control method provides stable
operation without complex compensation and even
with low ESR ceramic capacitors.
Low RDS(ON) for Internal Switches (Top/Bottom):
20/10 mΩ
Wide Input Voltage Range: 4~24V
Integrated Bypass Switch: 1.5Ω
Instant PWM Architecture to Achieve Fast
Transient Responses
Internal Soft-Start Limits the Inrush Current
Pseudo-Constant Frequency: 600kHz
Adjustable Output Voltage Application
8A Output Current Capability
±1% Internal Reference Voltage
PFM/FCCM Selectable Light Load Operation Mode
Power Good Indicator
Output Discharge Function
Cycle-by-cycle Valley and Peak Current Limit
Protection
Programmable Valley Current Limit Threshold
by ILMT Pin
Hic-cup Mode Output Under Voltage Protection
Auto-recovery Mode Output Over Voltage
Protection
Auto-recovery Mode Over Temperature Protection
Input UVLO
RoHS Compliant and Halogen Free
Compact Package: QFN2.5×2.5-16
ON/OFF
PG
GND
BS
MODE
LX
Sil
High/Low
IN
High/Floating/Low
3.3V External Voltage
(opt.)
EN
Efficiency vs. Output Current
100
95
CBS=0.1µF
L1=1.5µH
VOUT=3.3V
COUT=22µF×3
RFF=1kΩ
SY8388A
CFF=220pF
ILMT
FB
BYP
VCC
R1=100kΩ
90
85
80
75
VIN=5V, VOUT=3.3V
VIN=12V, VOUT=3.3V
VIN=19V, VOUT=3.3V
VIN=24V, VOUT=3.3V
70
R2=22.1kΩ
CVCC=2.2µF
CBYP=1.0µF
(VBYP=3.3V, PFM, L=1.5μH/PCMB104T-1R5MS)
PG (Open Drain Output)
Efficiency (%)
CIN=10µF CIN=0.1µF
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VIN=4~24V
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Typical Applications
65
60
0.001
0.01
0.1
1
8
Output Current (A)
Figure1. Schematic Diagram
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
Figure2. Efficiency vs. Output Current
Silergy Corp. Confidential- Prepared for Customer Use Only
1
All Rights Reserved.
SY8388A
3
IN
4
LX
GND
VCC
Exposed
Pad
(GND)
12
BYP
11
FB
10
ILMT
9
5
6
7
8
(QFN2.5×2.5-16)
EN
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IN
13
MODE
2
14
PG
IN
15
GND
1
16
LX
BS
LX
Pinout (top view)
Top Mark: B3xyz, (Device code: B3, x=year code, y=week code, z= lot number code)
IN
2, 3, 4
LX
GND
5, 15, 16
6, 14, EP
PG
7
MODE
8
EN
9
ILMT
FB
10
11
BYP
12
VCC
13
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BS
Pin Description
Boot-strap pin. Supply high side gate driver. Connect a 0.1µF ceramic capacitor
between the BS and the LX pin.
Input pin. Decouple this pin to the GND pin with at least a 10µF ceramic
capacitor. A 0.1μF input ceramic capacitor is recommended to reduce the input
noise.
Inductor pin. Connect this pin to the switching node of the inductor.
Ground pin.
Power good Indicator. Open drain output when the output voltage is within 90% to
120% of regulation point.
Operating mode selection under light load. Pull this pin low for PFM operating
and pull this pin high for FCCM operation. Do not leave this pin floating.
Enable control of the IC. Pull high to turn on the IC and pull low to turn off the
IC.
Valley current limit threshold selection pin. See Table1 to find more details.
Output feedback pin. Connect to the center point of resistor divider.
External 3.3V bypass power supply input. Decouple this pin to GND with a 1µF
ceramic capacitor. Leave this pin floating or connect this pin to the GND if it is
not used.
Internal 3.3V LDO output. Power supply for internal analog circuits and driving
circuit. Decouple this pin to GND with a 2.2µF ceramic capacitor.
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Pin Number
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Pin Name
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
Silergy Corp. Confidential- Prepared for Customer Use Only
2
All Rights Reserved.
SY8388A
Block Diagram
IN
Input
UVLO
Current Sense
PG
VCC
Bootstrap
Charge
MODE
BS
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EN
ILMT
Internal
SST
OTP
OVP
PWM
Control &
Protection
Logic
LX
Current Sense
VCC
UVP
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0.6V
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FB
IN
3.1V
BYP
GND
VCC
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3.3V LDO
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Figure3. Block Diagram
Absolute Maximum Ratings (Note 1)
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Supply Input Voltage ------------------------------------------------------------------------------------------------- -0.3V to 26V
IN-LX, LX, PG, MODE, EN Voltage------------------------------------------------------------------------ -0.3V to IN+0.3V
BS-LX, ILMT, VCC Voltage----------------------------------------------------------------------------------------- -0.3V to 4V
FB, BYP Voltage ------------------------------------------------------------------------------------------------------- -0.3V to 6V
Maximum Power Dissipation, PD,MAX @ TA = 25°C QFN2.5×2.5-16 ---------------------------------------------------- 3W
Package Thermal Resistance (Note 2)
θ JA, QFN2.5×2.5-16 ------------------------------------------------------------------------------------------- 33°C/W
θ JC, QFN2.5×2.5-16 ------------------------------------------------------------------------------------------- 5.5°C/W
Junction Temperature Range ------------------------------------------------------------------------------------- -40°C to 150°C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------------ 260°C
Storage Temperature Range -------------------------------------------------------------------------------------- -65°C to 150°C
Dynamic LX Voltage in 10ns Duration -------------------------------------------------------------------- GND-5V to IN+3V
Dynamic LX Voltage in 20ns Duration -------------------------------------------------------------------- GND-1V to IN+2V
Recommended Operating Conditions (Note 3)
Supply Input Voltage ---------------------------------------------------------------------------------------------------- 4V to 24V
Junction Temperature Range ------------------------------------------------------------------------------------- -40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------- -40°C to 85°C
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
Silergy Corp. Confidential- Prepared for Customer Use Only
3
All Rights Reserved.
SY8388A
Electrical Characteristics
Min
4
Typ
Max
24
3.9
Unit
V
V
V
140
170
µA
4
0.600
9
0.606
50
20
10
100
22
µA
V
nA
mΩ
mΩ
mA
A
A
A
A
4.8
A
0.5
0.594
-50
8
12
16
3
1.2
Sil
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
1.98
1
0.4
0.4
VIN
1
0
1
2.5
510
3.15
115
55
80
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(VIN= 12V, COUT= 66µF, TA= 25°C, IOUT= 1A unless otherwise specified)
Parameter
Symbol
Test Conditions
Input Voltage Range
VIN
Input UVLO Threshold
VIN rising
VUVLO
UVLO Hysteresis
VHYS
PFM, IOUT=0A,
Quiescent Current
IQ
VOUT=VSET×105%
Shutdown Current
ISHDN
EN=0
Feedback Reference Voltage
VREF
FB Input Current
IFB
VFB=1V
Top FET RDS(ON)
RDS(ON)1
Bottom FET RDS(ON)
RDS(ON)2
Output Discharge Current
IDIS
VOUT=5V
Top FET Current Limit
ILMT,TOP
ILMT=Low
Bottom FET Current Limit
ILMT,BOT
ILMT=Floating
ILMT=High
Bottom FET Reverse Current
ILMT,RVS
FCCM mode
Limit
VFB from 0% to100VREF
Soft-start Time
tSS
(Note 4)
EN Input Voltage High
VEN, H
EN Input Voltage Low
VEN, L
MODE Voltage for PFM Mode
VMODE,PFM
MODE Voltage for FCCM Mode VMODE,FCCM
EN/MODE Input Current
IEN/MODE
VEN/VMODE=3.3V
ILMT Input Voltage High
VILMT, H
ILMT Input Voltage Low
VILMT, L
Switching Frequency
fSW
VOUT=5V, CCM
Min ON Time
tON,MIN
VIN=VIN,MAX (Note 4)
Min OFF Time
tOFF,MIN
VCC Output Voltage
VCC
VCC adds 1mA load
Output Over Voltage Threshold
VOVP
VFB rising
Output Over Voltage Hysteresis
VOVP,HYS
Output Under Voltage Protection
VUVP
Threshold
Output UVP Delay
tUVP,DLY
(Note 4)
Power Good Threshold
VPG,F
VFB falling(not good)
Power Good Hysteresis
VPG,HYS
VFB rising (good)
tPG,R
Low to high (Note 4)
Power Good Delay
tPG,F
High to low (Note 4)
Power Good Low Voltage
VPG,LOW
VFB=0V, IPG=5mA
Bypass Switch RDS(ON)
RDS(ON),BYP
Bypass Switch Turn-on Voltage
VBYP
Bypass
Switch
Switchover
VBYP,HYS
Hysteresis
Bypass Switch OVP Threshold
VBYP,OVP
Thermal Shutdown Temperature
TOTP
TJ rising (Note 4)
Thermal Shutdown Hysteresis
TOTP,HYS
(Note 4)
600
50
150
3.3
120
5
60
200
83
7
200
30
0.4
690
3.45
125
65
V
V
V
V
μA
V
V
kHz
ns
ns
V
%VREF
%VREF
%VREF
1.5
3.1
µs
%VREF
%VREF
µs
µs
V
Ω
V
0.2
V
120
150
15
%VLDO
°C
°C
86
0.45
2.97
ms
Silergy Corp. Confidential- Prepared for Customer Use Only
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All Rights Reserved.
SY8388A
Note 1: Stresses beyond the “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability
Note 2: Package thermal resistance is measured in the natural convection at TA = 25°C on a 8.5cm×8.5cm size,
four-layer Silergy Evaluation Board with 2-oz copper.
Note 3: The device is not guaranteed to function outside its operating conditions.
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Note4：Guaranteed by design.
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
Silergy Corp. Confidential- Prepared for Customer Use Only
5
All Rights Reserved.
SY8388A
Typical Performance Characteristics
(TA=25°C, VIN=12V, VOUT=3.3V, L=1.5μH, COUT=66μF, unless otherwise noted)
Efficiency vs. Output Current
Efficiency vs. Output Current
(VBYP=3.3V, PFM, L=1.0μH/PCMB104T-1R0MT)
(VBYP=3.3V, FCCM, L=1.0μH/PCMB104T-1R0MT)
90
80
80
70
70
60
50
40
VIN=5V, VOUT=1.2V
VIN=12V, VOUT=1.2V
VIN=19V, VOUT=1.2V
VIN=24V, VOUT=1.2V
30
20
50
40
VIN=5V, VOUT=1.2V
VIN=12V, VOUT=1.2V
VIN=19V, VOUT=1.2V
VIN=24V, VOUT=1.2V
30
20
10
10
0
0.001
60
0
0.01
0.1
1
0.001
8
0.1
1
8
Output Current (A)
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Efficiency vs. Output Current
(VBYP=3.3V, PFM, L=1.0μH/PCMB104T-1R0MT)
Efficiency vs. Output Current
(VBYP=3.3V, FCCM, L=1.0μH/PCMB104T-1R0MT)
100
100
90
90
lP
70
Efficiency (%)
80
80
50
40
VIN=5V, VOUT=1.8V
VIN=12V, VOUT=1.8V
VIN=19V, VOUT=1.8V
VIN=24V, VOUT=1.8V
30
20
10
0.01
0.1
1
70
60
50
40
30
VIN=5V, VOUT=1.8V
VIN=12V, VOUT=1.8V
VIN=19V, VOUT=1.8V
VIN=24V, VOUT=1.8V
20
10
0
0.001
8
0.01
0.1
1
8
Output Current (A)
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Output Current (A)
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Efficiency (%)
0.01
dF
Output Current (A)
0
0.001
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Efficiency (%)
100
90
Efficiency (%)
100
Efficiency vs. Output Current
Efficiency vs. Output Current
(VBYP=3.3V, PFM, L=1.5μH/PCMB104T-1R5MS)
VIN=5V, VOUT=3.3V
VIN=12V, VOUT=3.3V
VIN=19V, VOUT=3.3V
VIN=24V, VOUT=3.3V
70
65
60
0.001
Efficiency (%)
85
75
80
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90
Sil
Efficiency (%)
95
80
90
yC
100
(VBYP=3.3V, FCCM, L=1.5μH/PCMB104T-1R5MS)
100
0.01
0.1
1
Output Current (A)
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
70
60
50
40
VIN=5V, VOUT=3.3V
VIN=12V, VOUT=3.3V
VIN=19V, VOUT=3.3V
VIN=24V, VOUT=3.3V
30
20
10
8
0
0.001
0.01
0.1
1
8
Output Current (A)
Silergy Corp. Confidential- Prepared for Customer Use Only
6
All Rights Reserved.
SY8388A
Efficiency vs. Output Current
Efficiency vs. Output Current
(VBYP=3.3V, PFM, L=1.5μH/PCMB104T-1R5MS)
(VBYP=3.3V, FCCM, L=1.5μH/PCMB104T-1R5MS)
100
100
90
95
80
85
80
75
VIN=7.4V, VOUT=5.0V
VIN=12V, VOUT=5.0V
VIN=19V, VOUT=5.0V
VIN=24V, VOUT=5.0V
70
65
60
0.001
0.01
0.1
1
10
0
0.001
8
IL
10A/div
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10V/div
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VLX
Startup from EN
.C
Time (4ms/div)
IL
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10V/div
Sil
VLX
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(VIN=12V, VOUT=3.3V, IOUT=8A)
5V/div
0.1
1
10A/div
Time (4ms/div)
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
8
Shutdown from VIN
(VIN=12V, VOUT=3.3V, IOUT=8A)
VIN
10V/div
VOUT
5V/div
VLX
10V/div
IL
10A/div
lP
5V/div
VOUT
0.01
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10V/div
2V/div
VIN=7.4V, VOUT=5.0V
VIN=12V, VOUT=5.0V
VIN=19V, VOUT=5.0V
VIN=24V, VOUT=5.0V
Output Current (A)
Startup from VIN
EN
40
20
(VIN=12V, VOUT=3.3V, IOUT=8A)
VOUT
60
50
30
Output Current (A)
VIN
70
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Efficiency (%)
Efficiency (%)
90
Time (4ms/div)
Shutdown from EN
(VIN=12V, VOUT=3.3V, IOUT=8A)
EN
2V/div
VOUT
5V/div
VLX
10V/div
IL
10A/div
Time (4ms/div)
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All Rights Reserved.
SY8388A
Output Short Circuit Protection
Output Short Circuit Protection
(VIN=12V, VOUT=3.3V, IOUT=0A~Short, ILMT=Low, PFM)
(VIN=12V, VOUT=3.3V, IOUT=8A~Short, ILMT=Low)
2V/div
IL
10A/div
VOUT
IL
Time (4ms/div)
Output Short Circuit Protection
Output Short Circuit Protection
lP
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Time (4ms/div)
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10A/div
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IL
(VIN=12V, VOUT=3.3V, IOUT=8A~Short, ILMT=Floating)
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(VIN=12V, VOUT=3.3V, IOUT=0A~Short, ILMT=Floating, PFM)
2V/div
10A/div
dF
Time (4ms/div)
VOUT
2V/div
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VOUT
VOUT
2V/div
IL
10A/div
Time (4ms/div)
Output Short Circuit Protection
(VIN=12V, VOUT=3.3V, IOUT=8A~Short, ILMT=High)
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Output Short Circuit Protection
(VIN=12V, VOUT=3.3V, IOUT=0A~Short, ILMT=High, PFM)
2V/div
VOUT
2V/div
Sil
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VOUT
IL
10A/div
Time (4ms/div)
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
IL
10A/div
Time (4ms/div)
Silergy Corp. Confidential- Prepared for Customer Use Only
8
All Rights Reserved.
SY8388A
Output Ripple
Output Ripple
(VIN=12V, VOUT=3.3V, IOUT=0A, PFM)
(VIN=12V, VOUT=3.3V, IOUT=0A, FCCM)
50mV/div
∆VOUT
50mV/div
VLX
10V/div
VLX
10V/div
IL
5A/div
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∆VOUT
IL
Time (2μs/div)
5A/div
dF
Time (2μs/div)
Output Ripple
50mV/div
VLX
10V/div
IL
10A/div
Output Ripple
(VIN=12V, VOUT=3.3V, IOUT=8A)
∆VOUT
50mV/div
VLX
10V/div
IL
10A/div
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∆VOUT
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(VIN=12V, VOUT=3.3V, IOUT=4A)
Load Transient
.C
Time (2μs/div)
200mV/div
Load Transient
(VIN=12V, VOUT=3.3V, IOUT=0~4A, FCCM)
ΔVOUT
200mV/div
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ΔVOUT
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(VIN=12V, VOUT=3.3V, IOUT=0~4A, PFM)
Time (2μs/div)
Sil
IL
5A/div
Time (200μs/div)
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
IL
5A/div
Time (200μs/div)
Silergy Corp. Confidential- Prepared for Customer Use Only
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All Rights Reserved.
SY8388A
Load Transient
Load Transient
(VIN=12V, VOUT=3.3V, IOUT=0.8~8A, PFM)
(VIN=12V, VOUT=3.3V, IOUT=0.8~8A, FCCM)
200mV/div
ΔVOUT
200mV/div
5A/div
IL
5A/div
IL
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ΔVOUT
Time (200μs/div)
Time (200μs/div)
dF
Switching Frequency vs. Output Voltage
(VIN=12V, IOUT=0A, FCCM)
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700
650
600
550
fSW, MIN
fSW, TYP
fSW, MAX
400
350
300
2
3
4
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Output Voltage (V)
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500
450
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Switching Frequency (kHz)
750
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
Silergy Corp. Confidential- Prepared for Customer Use Only
10
All Rights Reserved.
SY8388A
Instant-PWM Operation
Detailed Description
L1
VIN
General Features
R2
Ramp
Generator
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Minimum Duty Cycle and Maximum Duty Cycle
In the COT architecture, there is no limitation for
small duty cycle, since at very low duty cycle
operation, once the on-time is close to the minimum
on time, the switching frequency can be reduced as
needed to always ensure a proper operation.
The device can support ~75% maximum duty cycle
operation under TJ=-40℃~125℃ condition.
VRAMP
VFB
S
Q
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PWM
signal
VREF
tON
Generator
dF
Silergy’s instant-PWM control method adds several
proprietary improvements to the traditional COT
architecture. Whereas most legacy based on COT
implementations require a dedicated connection to
the output voltage terminal to calculate the tON
duration, instant-PWM control method derives this
signal internally. Another improvement optimizes
operation with low ESR ceramic output capacitors. In
many applications it is desirable to utilize very low
ESR ceramic output capacitors, but legacy COT
regulators may become unstable in these cases
because the beneficial ramp signal that results from
the inductor current flowing into the output capacitor
maybe become too small to maintain smooth
operation. For this reason, instant-PWM synthesizes
a virtual replica of this signal internally. This internal
virtual ramp and the feedback voltage are combined
and compared to the reference voltage. When the sum
is lower than the reference voltage, the tON pulse is
triggered as long as the minimum tOFF has been
satisfied and the inductor current as measured in the
low-side synchronous rectifier is lower than the
bottom FET current limit. As the t ON pulse is
triggered, the low-side synchronous rectifier turns off
and the high-side power switch turns on. Then the
inductor current ramps up linearly during the t ON
period. At the conclusion of the tON period, the highside power switch turns off, the low-side
synchronous rectifier turns on and the inductor
current ramps down linearly. This action also initiates
the minimum tOFF timer to ensure sufficient time for
stabilizing any transient conditions and settling the
feedback comparator
before the next cycle is
initiated. This minimum tOFF is relatively short so that
during high speed load transient tON can be
retriggered with minimal delay, allowing the inductor
current to ramp quickly to provide sufficient energy
to the load side.
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In a COT architecture, there is no fixed clock, so the
high-side power switch can turn on almost
immediately after a load transient and subsequent
switching pulses can be quickly initiated, ramping the
inductor current up to meet load requirements with
minimal delays. Traditional current mode or voltage
mode control methods must simultaneously monitor
the feedback voltage, current feedback and internal
ramps and compensation signals to determine when
to turn off the high-side power switch and turn on the
low-side synchronous rectifier. Considering these
small signals in a switching environment are difficult
to be noise-free after switching large currents,
making those architectures difficult to apply in noisy
environments and at low duty cycles.
R1
COUT
CIN
lP
Constant-on-time Architecture
Fundamental to any constant-on-time (COT)
architecture is the one-shot circuit or on-time
generator, which determines how long to turn on the
high-side power switch. Each on-time (tON) is a
“fixed” period internally calculated to operate the
step down regulator at the desired switching
frequency considering the input and output voltage
ration, tON = (VOUT/VIN)×(1/fSW). For example,
considering that a hypothetical converter targets 3.3V
output from a 12V input at 600kHz, the target ontime is (3.3V/12V)×(1/600kHz) = 458ns. Each tON
pulse is triggered by the feedback comparator when
the output voltage as measured at FB drops below the
target value. After one tON period, a minimum offtime (tOFF,MIN) is imposed before any further
switching is initiated, even if the output voltage is
less than the target. This approach avoids the making
any switching decisions during the noisy periods just
after switching events and while the switching node
(LX) is rapidly rising or falling.
VOUT
In order to avoid shoot-through, a dead time (tDEAD) is
generated internally between the high-side power
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
Silergy Corp. Confidential- Prepared for Customer Use Only
11
All Rights Reserved.
SY8388A
switch off and the low-side synchronous rectifier on
period or the low-side synchronous rectifier off and
the high-side power switch on period.
VUVLO less than the input UVLO hysteresis,
switching actions will again be suppressed.
If the input UVLO threshold is low for some high
input UVLO threshold requirement applications, use
EN to adjust the input UVLO by adopting two
external divided resistors.
Light Load Operation Mode Selection
PFM or FCCM light load operation is selected by
MODE pin. Pull MODE pin low for PFM operation,
and pull this pin high for FCCM operation.
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If FCCM light load operation is selected, under light
load conditions, the low-side synchronous rectifier
still turns on even when the inductor current crosses
zero. Current flow will continue until the next tON
cycle. The device always operates under continuous
conditions mode and keeps fairly constant switching
frequency over all the output current range.
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EN
RL
GND
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Enable Control
The EN input is a high-voltage capable input with
logic-compatible threshold. When EN is driven above
1V normal device operation will be enabled. When
driven < 0.4V the device will be shut down, reducing
input current to < 10µA.
It is not recommended to connect EN and IN directly.
A resistor in a range of 1kΩ to 1MΩ should be used
if EN is pulled high by IN.
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Startup and Shutdown
The SY8388A incorporates an internal soft-start
circuit to smoothly ramp the output to the desired
voltage whenever the device is enabled. Internally,
the soft-start circuit clamps the output at a low
voltage and then allows the output to rise to the
desired voltage over approximately 1.2ms, which
avoids high current flow and transients during
startup. The startup and shutdown sequence is shown
below.
VUVLO
VIN
EN
tDLY1
VCC
125µs
tDLY2
275µs
VREF
VSS(internal signal)
Input Under Voltage Lock-out (UVLO)
To prevent operation before all internal circuitry is
ready and to ensure that the power and synchronous
rectifier switches can be sufficiently enhanced, the
instant-PWM incorporates one input under-voltage
lockout protections. The device remains in a low
current state and all switching actions are inhibited
until VIN exceeds their own UVLO (rising) threshold.
At that time, if EN is enabled, the device will start-up
by initiating a soft-start ramp. If VIN falls below
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
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If PFM light load operation is selected, under light
load conditions, typically IOUT < 1/2×ΔIL, the current
through the low-side synchronous rectifier will ramp
to near zero before the next tON time. When this
occurs, the low-side synchronous rectifier turns off,
preventing recirculation current that can seriously
reduce efficiency under these light load conditions.
As load current is further reduced, and the combined
feedback and ramp signals remain much greater than
the reference voltage, the instant-PWM control loop
will not trigger another tON until needed, so the
apparent operating switching frequency will
correspondingly drop, further enhancing efficiency.
The switching frequency can be lower than audible
frequency area under deep light load or null load
conditions. Continuous conduction mode (CCM)
resumes smoothly as soon as the load current
increases sufficiently for the inductor current to
remain above zero at the time of the next tON cycle.
The device enters CCM once the load current
exceeds the critical level. After that, the switching
frequency stays fairly constant over the output
current range. The critical level of the load current is
determined with
V (1 D)
I
IOUT_CTL L OUT
2
2 fSW L1
VIN
VPG,R
VPG, F
VUVP
VFB
tSS
VOUT
tPG,R
tPG,F
PG
After the input voltage exceeds its own UVLO
(rising) threshold, VCC is turned on after EN is
Silergy Corp. Confidential- Prepared for Customer Use Only
12
All Rights Reserved.
SY8388A
enabled for one delay time tDLY1, the buck regulator
is turned on after another delay time tDLY2 after VCC
voltage is set up. When the output voltage is 90% of
the regulation point, PG becomes high-impedance
after one delay time tPG,R.
BS
CBS
0.1µF
LX
If the output is pre-biased to a certain voltage before
start-up, the device disables the switching of both the
high-side power switch and the low-side synchronous
rectifier until the voltage on the internal soft start
circuit voltage VSS exceeds the sensed output voltage
at the FB node.
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CVCC
2.2µF
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PG should be connected to VIN or another voltage
source through a resistor (e.g. 100kΩ). After the input
voltage exceeds its own UVLO (rising) threshold, the
PG MOSFET is turned on so that PG is pulled to
GND before output voltage is ready. After feedback
voltage VFB reaches VPG,R, PG is pulled high (after
one delay time typical 200µs). When VFB drops to
VPG,F, or rises to VOVP for one OVP delay time, PG is
pulled low (after one delay time typical 30µs).
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External Bootstrap Capacitor Connection
This device integrates a floating power supply for the
gate driver that operates the high-side power switch.
Proper operation requires a 0.1µF low ESR ceramic
capacitor to be connected between BS and LX. This
bootstrap capacitor provides the gate driver supply
voltage for the high-side N-channel MOSFET power
switch.
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BYP Input
The control and drive circuit can also be powered by
external 3.3V power supply. When a 3.3V external
power supply is connected to the BYP pin, the VCC
LDO is turned off and the switch between BYP and
VCC is turned on. The overall efficiency may be
improved by connecting the BYP pin to external
3.3V switching power supply. Connect a 1.0µF low
ESR ceramic capacitor from BYP pin to GND when
BYP is supplied by 3.3V external power. Leave the
BYP pin floating or connect this pin to the GND if it
is not used.
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Output Power Good Indicator
The buck power good indicator is an open drain
output controlled by a window comparator connected
to the feedback signal. If VFB is greater than VPG,R
and less than VOVP for at least the power good delay
time (low to high), PG will be high-impedance.
VCC
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Output Discharge
SY8388A discharges the output voltage when the
converter shuts down from VIN or EN, or thermal
shutdown, so that output voltage can be discharged in
a minimal time, even output load current is zero. The
discharge FET in parallel with the low-side
synchronous rectifier turns on after the low-side
synchronous rectifier turns off when shut down logic
is triggered. The output discharge current is typically
100mA when the LX voltage is 5V. Note that the
discharge FET is not active beyond these shutdown
conditions.
VCC Linear Regulator
An internal linear regulator (VCC) produces a 3.3V
supply from VIN that powers the internal gate drivers,
PWM logic, analog circuitry, and other blocks.
Connect a 2.2μF low ESR ceramic capacitor from
VCC to GND.
Fault Protection Modes
Output Current Limit
Instant-PWM incorporates a cycle-by-cycle“valley”
current limit. Inductor current is measured in the lowside synchronous rectifier when it turns on and as the
inductor current ramps down. If the current exceeds
the bottom FET current limit threshold, tON is
inhibited until the current returns back to the limit
threshold or lower.
Bottom FET current limit
IL
VFB
VREF
VLX
VFB 500µF and minimum load
current is low, set feed-forward values as RFF = 1kΩ
and CFF = 2.2nF to provide sufficient ripple to FB for
small output ripple and good transient behavior.
t ON
t ON +t OFF,MIN
Thermal Design Considerations
Maximum power dissipation depends on the thermal
resistance of the IC package, the PCB layout, the
surrounding airflow, and the difference between the
junction and ambient temperatures. The maximum
power dissipation may be calculated by:
PD,MAX = (TJ,MAX− TA) / θJA
Where, TJ,MAX is the maximum junction temperature,
TA is the ambient temperature, and θJA is the junction
to ambient thermal resistance.
Given this, the capacitive undershoot may be
calculated by
2
L1 IOUT
2 COUT (VIN,MIN D MAX VOUT )
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VUNDERSHOOT,CAP
Consider a 4A load increase using the ceramic
capacitor case when VIN = 12V.At VOUT = 3.3V, the
result is tON = 458ns, tOFF,MIN = 150ns, DMAX = 458 /
(458 + 150) = 0.753 and
VUNDERSHOOT,CAP
1.5H (4A) 2
31.7mV
2 66F (12V 0.753 3.3V)
To comply with the recommended operating conditions,
the maximum junction temperature is 125℃. The
junction to ambient thermal resistance θJA is layout
dependent. For the QFN2.5×2.5-16 package the
thermal resistance θJA is 33℃/W when measured on a
standard Silergy four-layer thermal test board. These
standard thermal test layouts have a very large area
with long 2-oz. copper traces connected to each IC
pin and very large, unbroken 1-oz. internal power and
ground planes.
Using the POS capacitor case, the above result is
VOVERSHOOT,CAP
2
L1 IOUT
2 COUT VOUT
Consider a 4A load decrease using the ceramic
capacitor case above. At VOUT = 3.3V the result is
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VOVERSHOOT,CAP
1.5H (4A)2
55.1mV
2 66F 3.3V
Using the POS capacitor case, the above result is
VOVERSHOOT,CAP
1.5H (4A)2
24.2mV
2 150F 3.3V
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Combine the ESR and capacitive undershoot and
overshoot to calculate the total overshoot and
undershoot for a given application.
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Load Transient Considerations:
The SY8388A adopts the instant PWM architecture
to achieve good stability and fast transient responses.
In applications with high step load current, adding an
RC feed-forward compensation network RFF and CFF
may further speed up the load transient responses.
RFF = 1kΩ and CFF = 220pF have been shown to
perform well in most applications. Increase CFF will
speed up the load transient response if there is no
stability issue.
L1
LX
RFF
(opt.)
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Capacitive overshoot (load decreasing) is a function
of the output capacitance, the inductor value and the
output voltage.
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1.5H (4A) 2
13.95mV
2 150F (12V 0.753 3.3V)
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VUNDERSHOOT,CAP
Meeting the performance of the standard thermal test
board in a typical tiny evaluation board area requires
wide copper traces well-connected to the IC's
backside pads leading to exposed copper areas on the
component side of the board as well as good thermal
via from the exposed pad connecting to a wide
middle-layer ground plane and, perhaps, to an
exposed copper area on the board's solder side.
The maximum power dissipation at T A=25℃ may be
calculated by the following formula:
PD,MAX = (125℃ − 25℃) / (33℃/W) = 3W
The maximum power dissipation depends on
operating ambient temperature for fixed T J,MAX and
thermal resistance θJA. Use the derating curve in
figure below to calculate the effect of rising ambient
temperature on the maximum power dissipation.
VOUT
R1
COUT
FB
CFF
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
R2
Silergy Corp. Confidential- Prepared for Customer Use Only
17
All Rights Reserved.
SY8388A
Avoid routing the feedback line near LX, BS or other
high frequency signal as it is noise sensitive. Make
the feedback sampling point Kelvin connect with
COUT rather than the inductor output terminal.
3
2.5
2
LX Connection: Keep LX area small to prevent
excessive EMI, while providing wide copper traces to
minimize parasitic resistance and inductance. Wide
LX copper trace between pin 5 and pin 15, 16 should
be adopted to improve efficiency.
1.5
1
0.5
0
0
25
50
75
100
Ambient Temperature (
125
)
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Maximum Power Dissipation (W)
Maximum Power Derating Curve
3.5
BS Capacitor: Place the BS capacitor on the same
layer as the device, keep the BS voltage path (BS, LX
and CBS) as short as possible.
Layout Design
Follow these PCB layout guidelines for optimal
performance and thermal dissipation.
Control Signals: It is not recommended to connect
control signals and IN directly. A resistor in a range
of 1kΩ to 1MΩ should be used if they are pulled high
by IN.
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VCC Capacitor: Place the VCC capacitor close to
VCC using short, direct copper trace to one nearest
device GND pin (pin 14).
GND Vias: Place adequate number of vias on the
GND layer around the device for better thermal
performance. The exposed GND pad should be
connected by a larger copper area than its size, place
four GND vias on it for heat dissipation.
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BYP Capacitor: Place the BYP capacitor close to
BYP using short, direct copper trace to one nearest
device GND pin (pin 14) if bypass function is used.
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Feedback Network: Place the feedback components
(R1, R2, RFF and CFF) as close to FB pin as possible.
PCB Board: A four-layer layout with 2-oz copper is
strongly recommended to achieve better thermal
performance. The top layer and bottom layer should
place power IN and GND copper plane as wide as
possible. Middle1 layer should place all GND layer
for conducting heat and shielding middle2 layer
signal line from top layer crosstalk. Place signal lines
on middle2 layer instead of the other layers, so that
the other layers’ GND plane not be cut apart by these
signal lines.
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Output Capacitors: Guarantee the COUT negative
sides are connected with GND pin by wide copper
traces instead of vias, in order to achieve better
accuracy and stability of output voltage.
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Input Capacitors: Place the input capacitor very
near IN and GND, minimizing the loop formed by
these connections. And the input capacitor should be
connected to the IN and GND by wide copper plane.
A 0.1μF input ceramic capacitor is recommended to
reduce the input noise.
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
Silergy Corp. Confidential- Prepared for Customer Use Only
18
All Rights Reserved.
SY8388A
L
IN Vias
VIN
CBS
CIN
CIN
IN
BS
3
2
1
4
LX
8
GND
13
7
LX
14
Exposed Pad
(GND)
15
6
16
5
PG
IN
IN
LX
GND
MODE
VCC
COUT
FB
BYP
EN
ILMT
12
9
10
11
GND Vias
CVCC
R2
CBYP
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CIN
COUT
COUT
R1
Feedback line
GND
VOUT
CFF
RFF
VBYP
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Middle1 Layer
(GND Layer, not shown)
Top Layer
dF
GND
Middle2 Layer
Exposed GND Vias Detail
0.5mm
0.35mm
Exposed Pad
(GND)
Bottom Layer
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Figure4. PCB Layout Suggestion
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
Silergy Corp. Confidential- Prepared for Customer Use Only
19
All Rights Reserved.
SY8388A
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QFN2.5×2.5-16 Package Outline Drawing
Bottom view
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Top view
Sil
Side view
layout
Recommended PCB
(Reference only)
Notes:
All dimension in millimeter and exclude mold flash & metal burr.
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
Silergy Corp. Confidential- Prepared for Customer Use Only
20
All Rights Reserved.
SY8388A
Taping & Reel Specification
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1. QFN2.5×2.5 taping orientation
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2. Carrier Tape & Reel specification for packages
Tape width
(mm)
QFN2.5×2.5
8
Reel size
(Inch)
Trailer
length(mm)
Leader length
(mm)
Qty per
reel
4
7"
400
160
3000
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3. Others: NA
Pocket
pitch(mm)
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Package
types
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Reel
Size
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
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All Rights Reserved.
SY8388A
Revision History
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The revision history provided is for informational purpose only and is believed to be accurate, however, not
warranted. Please make sure that you have the latest revision.
Date
Revision
Change
Jan.22, 2021
Revision 0.9A
1. Add (IN-LX) voltage in Absolute Maximum Ratings;
2. Add “A 0.1μF input ceramic capacitor is recommended to reduce the input
noise.” in the pin description and the layout design;
3. Update in Table1 (page14):
----Change “Pull ILMT to GNG by 0~20kΩ” to “Pull ILMT to GND by
≤10kΩ Resistor” (ILMT=Low);
---- Change “Pull ILMT to VCC by 0~150kΩ” to “Pull ILMT to VCC by
≤10kΩ Resistor” (ILMT=High).
Revision 0.9A
Fixed an error in the calculation formula of DMAX (tON is 458ns) (page17)
Jul.24, 2020
Revision 0.9
Initial Release
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Sep.21, 2020
AN_SY8388A Rev. 0.9B
© 2020 Silergy Corp.
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22
All Rights Reserved.
SY8388A
IMPORTANT NOTICE
1. Right to make changes. Silergy and its subsidiaries (hereafter Silergy) reserve the right to change any information
published in this document, including but not limited to circuitry, specification and/or product design, manufacturing or
descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the
publication hereof. Buyers should obtain the latest relevant information before placing orders and should verify that such
information is current and complete. All semiconductor products are sold subject to Silergy’s standard terms and conditions of
sale.
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2. Applications. Application examples that are described herein for any of these products are for illustrative purposes only.
Silergy makes no representation or warranty that such applications will be suitable for the specified use without further testing or
modification. Buyers are responsible for the design and operation of their applications and products using Silergy products.
Silergy or its subsidiaries assume no liability for any application assistance or designs of customer products. It is customer’s sole
responsibility to determine whether the Silergy product is suitable and fit for the customer’s applications and products planned.
To minimize the risks associated with customer’s products and applications, customer should provide adequate design and
operating safeguards. Customer represents and agrees that it has all the necessary expertise to create and implement safeguards
which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures
that might cause harm and take appropriate remedial actions. Silergy assumes no liability related to any default, damage, costs or
problem in the customer’s applications or products, or the application or use by customer’s third-party buyers. Customer will
fully indemnify Silergy, its subsidiaries, and their representatives against any damages arising out of the use of any Silergy
components in safety-critical applications. It is also buyers’ sole responsibility to warrant and guarantee that any intellectual
property rights of a third party are not infringed upon when integrating Silergy products into any application. Silergy assumes no
responsibility for any said applications or for any use of any circuitry other than circuitry entirely embodied in a Silergy product.
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3. Limited warranty and liability. Information furnished by Silergy in this document is believed to be accurate and reliable.
However, Silergy makes no representation or warranty, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such information. In no event shall Silergy be liable for
any indirect, incidental, punitive, special or consequential damages, including but not limited to lost profits, lost savings, business
interruption, costs related to the removal or replacement of any products or rework charges, whether or not such damages are
based on tort or negligence, warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer
might incur for any reason whatsoever, Silergy’ aggregate and cumulative liability towards customer for the products described
herein shall be limited in accordance with the Standard Terms and Conditions of Sale of Silergy.
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4. Suitability for use. Customer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory
and safety-related requirements concerning its products, and any use of Silergy components in its applications, notwithstanding
any applications-related information or support that may be provided by Silergy. Silergy products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where
failure or malfunction of an Silergy product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. Silergy assumes no liability for inclusion and/or use of Silergy products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own risk.
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5. Terms and conditions of commercial sale. Silergy products are sold subject to the standard terms and conditions of
commercial sale, as published at http://www.silergy.com/stdterms, unless otherwise agreed in a valid written individual
agreement specifically agreed to in writing by an authorized officer of Silergy. In case an individual agreement is concluded only
the terms and conditions of the respective agreement shall apply. Silergy hereby expressly objects to and denies the application
of any customer’s general terms and conditions with regard to the purchase of Silergy products by the customer.
Sil
erg
6. No offer to sell or license. Nothing in this document may be interpreted or construed as an offer to sell products that is
open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or
intellectual property rights. Silergy makes no representation or warranty that any license, either express or implied, is granted
under any patent right, copyright, mask work right, or other intellectual property right. Information published by Silergy
regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from Silergy under the patents or other intellectual property of Silergy.
For more information, please visit: www.silergy.com
© 2020 Silergy Corp.
AN_SY8388A Rev. 0.9B
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