ISD4004-08MEYIR

ISD4004 ISD ChipCorder® ISD4004 Series Datasheet The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of Audio Product Line based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com Jun 28, 2021 Page 1 of 34 Rev1.5 ISD4004 TABLE OF CONTENTS Table of contents......................................................................................................... 2 1. GENERAL DESCRIPTION .................................................................................... 3 2. FEATURES............................................................................................................ 3 3. BLOCK DIAGRAM ................................................................................................. 4 4. PIN CONFIGURATION .......................................................................................... 5 5. PIN DESCRIPTION ............................................................................................... 6 6. FUNCTIONAL DESCRIPTION ............................................................................ 10 6.1. Detailed Description ................................................................................... 10 6.2. Serial Peripheral Interface (SPI) Description .............................................. 11 6.2.1 OPCODES .............................................................................................. 12 6.2.2 SPI Diagrams .......................................................................................... 13 6.2.3 SPI Control and Output Registers ........................................................... 14 7. TIMING DIAGRAMS ............................................................................................ 16 8. ABSOLUTE MAXIMUM RATINGS ...................................................................... 18 8.1. Operating Conditions ................................................................................. 19 9. ELECTRICAL CHARACTERISTICS .................................................................... 20 9.1. Parameters For Packaged Parts ................................................................ 20 9.2. Parameters For Die .................................................................................... 23 9.3. SPI AC Parameters .................................................................................... 24 10. TYPICAL APPLICATION CIRCUIT...................................................................... 25 11. PACKAGING AND DIE INFORMATION .............................................................. 28 11.1. 28-Lead 300-Mil Plastic Small Outline IC (SOIC) ....................................... 28 11.2. 28-Lead 600-Mil Plastic Dual Inline Package (PDIP) ................................. 29 11.3. Die Information ........................................................................................... 30 12. ORDERING INFORMATION ............................................................................... 32 13. REVISION HISTORY ........................................................................................... 33 Important Notice ........................................................................................................ 34 Jun 28, 2021 Page 2 of 34 Rev1.5 ISD4004 1. GENERAL DESCRIPTION The ISD4004 ChipCorder® series provides high-quality, 3-volt, single-chip record/playback solutions for 8- to 16-minute messaging applications ideally for cellular phones and other portable products. The CMOS-based devices include an on-chip oscillator, anti-aliasing filter, smoothing filter, AutoMute® feature, audio amplifier, and high density multilevel Flash memory array. The ISD4004 series is designed to be used in a microprocessor- or microcontroller-based system. Address and control are accomplished through a Serial Peripheral Interface (SPI) or Microwire Serial Interface to minimize pin count. Recordings are stored into the on-chip Flash memory cells, providing zero-power message storage. This unique single-chip solution utilizes Nuvoton’s patented multilevel storage technology. Voice and audio signals are directly stored onto memory array in their natural form, providing high-quality voice reproduction. 2. FEATURES • • • • • • • • • • • • • • • • • Single-chip voice record/playback solution Single 3 volt supply Low-power consumption  Operating current: - ICC_Play = 15 mA (typical) - ICC_Rec = 25 mA (typical)  Standby current: - ICC_Standby = 1 µA (typical) Duration: 8, 10, 12, and 16 minutes High-quality, natural voice/audio reproduction AutoMute feature provides background noise attenuation No algorithm development required Microcontroller SPI or Microwire™ Serial Interface Fully addressable to handle multiple messages Non-volatile message storage 100K record cycles (typical) 100-year message retention (typical) On-chip oscillator Power-down feature to reduce power consumption Available in die, PDIP and SOIC Packaged type: Lead-Free Temperature: - Commercial (die): 0°C to +50°C - Commercial (packaged units): 0°C to +70°C - Industrial (packaged units): -40°C to +85°C Jun 28, 2021 Page 3 of 34 Rev1.5 ISD4004 3. BLOCK DIAGRAM Timing Internal Clock XCLK Sampling Clock ANA IN- Amp 5-Pole Active Antialiasing Filter Analog Transceivers 3,840K Cell Nonvolatile Multilevel Storage Array Decoders ANA IN+ 5-Pole Active Smoothing Filter AutoMuteTM Feature Amp Power Conditioning VCCA Jun 28, 2021 VSSA VSSA VSSA VSSD VCCD AUDOUT Device Control SCLK SS MOSI MISO Page 4 of 34 INT RAC AM CAP Rev1.5 ISD4004 4. PIN CONFIGURATION SS 1 28 MOSI 2 27 VCCD MISO 3 26 XCLK VSSD 4 25 INT NC 5 24 RAC NC 6 23 VSSA NC 7 22 NC NC 8 21 NC ISD4004 SCLK NC 9 20 NC NC 10 19 NC VSSA 11 18 VCCA VSSA 12 17 ANA IN+ AUD OUT 13 16 ANA IN- AM CAP 14 15 NC SOIC / PDIP Jun 28, 2021 Page 5 of 34 Rev1.5 ISD4004 5. PIN DESCRIPTION PIN NAME PIN # FUNCTION SOIC / PDIP 1 Slave Select: This input, when LOW, will select the ISD4004 device. MOSI 2 Master Out Slave IN: This is the serial input to the ISD4004 device when it is configured as slave. The master microcontroller places data on the MOSI line one half-cycle before the rising edge of SCLK for clocking into the device. MISO 3 Master In Slave Out: This is the serial output of the ISD4004 device. This output goes into a high-impedance state if the device is not selected. VSSA / VSSD 11, 12, 23 / 4 Ground: The ISD4004 series utilizes separate analog and digital ground busses. The analog ground (VSSA) pins should be tied together as close as possible and connected through a low-impedance path to power supply ground. The digital ground (VSSD) pin should be connected through a separate low-impedance path to power supply ground. These ground paths should be large enough to ensure that the impedance between the VSSA pins and the VSSD pin is less than 3 Ω. The backside of the die is connected to VSS through the substrate. For chip-on-board design, the die attach area must be connected to VSS or left floating. NC 5-10, 15, 1922 Not connected AUD OUT [1] 13 Audio Output: This pin provides an audio output of the stored data and is recommended be AC coupled. It is capable of driving a 5 KΩ impedance REXT. AM CAP 14 AutoMute™ Feature: The AutoMute feature only applies for playback operation and helps to minimize noise (with 6 dB of attenuation) when there is no signal (i.e. during periods of silence). A 1 µF capacitor to ground is recommended to connect to the AM CAP pin. This capacitor becomes a part of an internal peak detector which senses the signal amplitude. This peak level is compared to an internally set threshold to determine the AutoMute trip point. For large signals, the AutoMute attenuation is set to 0 dB automatically but 6 dB of attenuation occurs for silence. The 1 µF capacitor also affects the rate at which the AutoMute feature changes with the signal amplitude (or the attack time). The AutoMute feature can be disabled by connecting the AM CAP pin directly to VCCA.. SS [1] The AUD OUT pin is always at 1.2 volts when the device is powered up. When in playback, the output buffer connected to this pin can drive a load as small as 5 KΩ. When in record, a built-in resistor connects AUD OUT to the internal 1.2-volt analog ground supply. This resistor is approximately 850 KΩ, but will vary somewhat according to the sample rate of the device. This relatively high impedance allows this pin to be connected to an audio bus without loading it down. Jun 28, 2021 Page 6 of 34 Rev1.5 ISD4004 PIN NAME PIN # FUNCTION SOIC / PDIP ANA IN- 16 Inverting Analog Input: This pin transfers the signal into the device during recording via differential-input mode. In this differential-input mode, a 16 mVp-p maximum input signal should be capacitively coupled to ANA IN- for optimal signal quality, as shown in Figure 1: ANA IN Modes. This capacitor value should be equal to that used on ANA IN+ pin. The input impedance at ANA IN- is normally 56 KΩ. In the single-ended mode, ANA IN- should be capacitively coupled to VSSA through a capacitor equal to that used on the ANA IN+ pin. ANA IN+ 17 Non-Inverting Analog Input: This pin is the non-inverting analog input that transfers the signal to the device for recording. The analog input amplifier can be driven single ended or differentially. In the single-ended input mode, a 32 mVp-p (peak-to-peak) maximum signal should be capacitively connected to this pin for optimal signal quality. The external capacitor associated with ANA IN+ together with the 3 KΩ input impedance are selected to give cutoff at the low frequency end of the voice passband. In the differential-input mode, the maximum input signal at ANA IN+ should be 16 mVp-p capacitively coupled for optimal signal quality. The circuit connections for the two modes are shown in Figure 1. VCCA / VCCD 18 / 27 Supply Voltage: To minimize noises, the analog and digital circuits in the ISD4004 devices use separate power busses. These +3V busses are brought out to separate pins and should be tied together as close to the supply as possible. In addition, these supplies should be decoupled as close to the package as possible. RAC 24 Row Address Clock: This is an open drain output that provides the signal of a ROW with a 200 ms period for 8 KHz sampling frequency. (This represents a single row of memory.) This signal stays HIGH for 175 ms and stays LOW for 25 ms when it reaches the end of a row. The RAC pin stays HIGH for 109.37 µsec and stays LOW for 15.63 µsec in Message Cueing mode (see Message Cueing section for detailed description). Refer to the AC Parameters table for RAC timing information at other sample rates. When a record command is first initiated, the RAC pin remains HIGH for an extra TRACL period. This is due to the need of loading the internal sample and hold circuits in the device. This pin can be used for message management techniques. A pull-up resistor is required to connect this pin to other device. INT 25 Interrupt: This is an open drain output pin. This pin goes LOW and stays LOW when an Overflow (OVF) or End of Message (EOM) marker is detected. Each operation that ends with an EOM or OVF will generate an interrupt. The interrupt will be cleared the next time an SPI cycle is initiated. The interrupt status can also be read by an RINT instruction. A pull-up resistor is required to connect this pin to other device. Overflow Flag (OVF) – The Overflow flag indicates that the end of memory has been reached during a record or playback operation. End of Message (EOM) – The End of Message flag is set only during playback operation when an EOM is found. There are eight EOM flag position options per row. Jun 28, 2021 Page 7 of 34 Rev1.5 ISD4004 PIN NAME PIN # FUNCTION SOIC / PDIP XCLK 26 External Clock Input: The ISD4004 series is configured at the factory with an internal sampling clock frequency centered to ±1 percent of specification. The frequency is then maintained to a variation of ±2.25 percent over the entire commercial temperature and operating voltage ranges. The internal clock has a –6/+4 percent tolerance over the industrial temperature and voltage ranges. A regulated power supply is recommended for industrial temperature range parts. If greater precision is required, the device can be clocked through the XCLK pin as follows: Part Number Sample Rate Required Clock ISD4004-08M 8.0 kHz 1024 kHz ISD4004-10M 6.4 kHz 819.2 kHz ISD4004-12M 5.3 kHz 682.7 kHz ISD4004-16M 4.0 kHz 512 kHz These recommended clock rates should not be varied because the antialiasing and smoothing filters are fixed. Otherwise, aliasing problems can occur if the sample rate differs from the one recommended. The duty cycle on the input clock is not critical, as the clock is immediately divided by two. If the XCLK is not used, this input must be connected to ground. SCLK Jun 28, 2021 28 Serial Clock: This is the input clock to the ISD4004 device. It is generated by the master device (typically microcontoller) and is used to synchronize the data transfer in and out of the device through the MOSI and MISO lines, respectively. Data is latched into the ISD4004 on the rising edge of SCLK and shifted out of the device on the falling edge of SCLK. Page 8 of 34 Rev1.5 ISD4004 Internal to the device 53KΩ 0.1 µ F Signal 3KΩ ANA IN+ 32m Vp-p To Filter + 0.1 µ F 3KΩ ANA IN- 53KΩ 1.2V Single-Ended Input Mode Internal to the device 53KΩ 0.1 µ F 3KΩ ANA IN+ Input Signal 16m Vp-p - Input Signal 16m Vp-p 180° + To Filter 0.1 µ F 3KΩ ANA IN- 53KΩ 1.2V Differential Input Mode FIGURE 1: ISD4004 SERIES ANA IN MODES TRAC (200 ms) RAC 25 ms TRACL FIGURE 2: RAC TIMING WAVEFORM DURING NORMAL OPERATION (example of 8KHz sampling rate) Jun 28, 2021 Page 9 of 34 Rev1.5 ISD4004 6. FUNCTIONAL DESCRIPTION 6.1. DETAILED DESCRIPTION Audio Quality The Nuvoton’s ISD4004 ChipCorder® series is offered at 8.0, 6.4, 5.3 and 4.0 kHz sampling frequencies, allowing the user a choice of speech quality options. Increasing the sampling frequency will produce better sound quality, but affects duration. Please refer to Table 1: Product Summary for details. Analog speech samples are stored directly into on-chip non-volatile memory without the digitization and compression associated with other solutions. Direct analog storage provides higher quality reproduction of voice, music, tones, and sound effects than other solid-state solutions. Duration The ISD4004 Series is a single-chip solution with 8-, 10-, 12-, and 16-minute duration. TABLE 1: PRODUCT SUMMARY OF ISD4004 SERIES Part Number Duration (Minutes) Sample Rate (kHz) Typical Filter Pass Band (kHz) * ISD4004-08M 8 8.0 3.4 ISD4004-10M 10 6.4 2.7 ISD4004-12M 12 5.3 2.3 ISD4004-16M 16 4.0 1.7 * This is the –3dB point. This parameter is not checked during production testing and may vary due to process variations and other factors. Therefore, the customer should not rely upon this value for testing purposes. Flash Storage The ISD4004 series utilizes on-chip Flash memory, providing zero-power message storage. The message is retained for up to 100 years typically without power. In addition, the device can be rerecorded typically over 100,000 times. Memory Architecture The ISD4004 series contains a total of 3,840K Flash memory cells, which is organized as 2,400 rows of 1,600 cells each. The address bits (A0-A15) are used to access various rows for multiple messages of different durations. Jun 28, 2021 Page 10 of 34 Rev1.5 ISD4004 Microcontroller Interface A four-wire (SCLK, MOSI, MISO & SS ) SPI interface is provided for controlling and addressing functions. The ISD4004 is configured to operate as a peripheral slave device, with a microcontrollerbased SPI bus interface. Read and write operations are controlled through this SPI interface. An interrupt signal ( INT ) and internal read only Status Register are provided for handshake purposes. Programming The ISD4004 series is also ideal for playback-only applications, where single- or multiple-messages playback is controlled through the SPI port. Once the desired message configuration is created, duplicates can easily be generated via a programmer. 6.2. SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION The ISD4004 series operates via SPI serial interface with the following protocol. First, the data transfer protocol assumes that the microcontroller’s SPI shift registers are clocked on the falling edge of the SCLK. However, for the ISD4004, the protocols are as follows: 1. All serial data transfers begin with the falling edge of SS pin. 2. SS is held LOW during all serial communications and held HIGH between instructions. 3. Data is clocked in on the rising edge of the SCLK signal and clocked out on the falling edge of the SCLK signal, with LSB first. 4. Playback and record operations are initiated when the device is enabled by asserting the SS pin LOW, shifting in an opcode and an address data to the ISD4004 device (refer to the Opcode Summary in the following page). 5. The opcodes contain and . 6. Each operation that ends with an EOM or Overflow will generate an interrupt. The Interrupt will be cleared the next time a SPI cycle is initiated. 7. As Interrupt data is shifted out of the MISO pin, while address and control data are simultaneously shifted into the MOSI pin. Care should be taken such that the data shifted in is compatible with current system operation. Because it is possible to read an interrupt data and start a new operation within the same SPI cycle. 8. An operation begins with the RUN bit set and ends with the RUN bit reset. 9. All operations begin after the rising edge of SS . Jun 28, 2021 Page 11 of 34 Rev1.5 ISD4004 6.2.1 OPCODES The available Opcodes are summarized as follows: TABLE 2: OPCODE SUMMARY Instructions OpCodes Address (16 bits) POWERUP SETPLAY PLAY SETREC REC SETMC Descriptions Control bits (8 bits) XXX C0 C1 C2 C3 C4 XXX 0 0 1 0 0 Power-Up: Device will be ready for an operation after TPUD. XXX 0 0 1 1 1 Initiates playback from address . XXX 0 1 1 1 1 Playback from the current address (until EOM or OVF). XXX 0 0 1 0 1 Initiates a record operation from address . XXX 0 1 1 0 1 Records from current address until OVF is reached or Stop command is sent. XXX 1 0 1 1 1 Initiates Message Cueing (MC) from address . [ 1] XXX 1 1 1 1 1 Performs a Message Cueing from current location. Proceeds to the end of message (EOM) or enters OVF condition if no more messages are present. STOP XXX 0 1 1 X 0 Stops the current operation. STOPPWRDN XXX X 1 0 X 0 Stops the current operation and enters into standby (powerdown) mode. RINT [ 2] XXX 0 1 X 0 Read Interrupt status bits: Overflow and EOM. MC 1 Notes: C0 = Message cueing C1 = Ignore address bit C2 = Master power control C3 = Record or playback operation C4 = Enable or disable an operation [1] Message Cueing can be selected only at the beginning of a playback operation. [2] As the Interrupt data is shifted out of the ISD4004, control and address data are being shifted in. Care should be taken such that the data shifted in is compatible with current system operation. It is possible to read interrupt data and start a new operation at the same time. See Figures 5 - 8 for references. Jun 28, 2021 Page 12 of 34 Rev1.5 ISD4004 6.2.2 SPI Diagrams LSB A15 A0 X X X C Input Shift Register (Loaded to Row Counter only if IAB = 0) MISO MOSI A0-A15 Select Logic Row Counter LSB C 4 0 P0-P15 Output Shift Register OVF EOM P0 ... P15 FIGURE 3: SPI INTERFACE SIMPLIFIED BLOCK DIAGRAM The following diagram describes the SPI port and the control bits associated with it. LSB A0 MSB A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 x x x C0 C1 C2 C3 C4 0 0 0 MOSI Message Cueing (MC) Ignore Address Bit (IAB) Power Up (PU) Play/Record (P/R) RUN LSB MISO OVF MSB EOM P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 0 0 0 Notes: 1. For MOSI, LSB is the 1st bit shifted into the ISD4004. 2. For MISO, LSB is the 1st bit shifted out from the ISD4004. FIGURE 4: SPI PORT Jun 28, 2021 Page 13 of 34 Rev1.5 ISD4004 6.2.3 SPI Control and Output Registers The SPI control register provides control of individual function such as play, record, message cueing, power-up, power-down, start, stop and ignore address pointer operations. TABLE 3: SPI CONTROL REGISTERS Control Bit C0 Control Register Bit MC = = C1 C2 1 0 Message Cueing function Enable Message Cueing Disable Message Cueing 1 0 Ignore Address bit Ignore input address register (A0-A15) Use the input address register (A0-A15) 1 0 Power Up Power-Up Power-Down 1 0 Playback or Record Play Record 1 0 Enable or Disable an operation Start Stop IAB [1] = = PU = = Device Function P/ R C3 C4 = = RUN = = Address Bits A0-A15 Input address register TABLE 4: SPI OUTPUT REGISTERS Output Bits Description OVF Overflow EOM End-of-Message P0-P15 Output of the row pointer register [1] When IAB (Ignore Address Bit) is set to 0, a playback or record operation starts from address (A0-A15). For consecutive playback or record, IAB should be changed to a 1 before the end of that row (see RAC timing). Otherwise the ISD4004 will repeat the operation from the same row address. For memory management, the Row Address Clock (RAC) signal and IAB can be used to move around the memory segments. Jun 28, 2021 Page 14 of 34 Rev1.5 ISD4004 Message Cueing Message cueing (MC) allows the user to skip through messages, without knowing the actual physical location of the messages. It will stop when an EOM marker is reached. Then, the internal address counter will point to the next message. Also, it will enter into OVF condition when it reaches the end of memory. In this mode, the messages are skipped 1,600 times faster than the normal playback mode. Power-Up Sequence The ISD4004 will be ready for an operation after power-up command is sent and followed by the TPUD timing (25 ms for 8 KHz sampling rate). Refer to the AC timing table for other TPUD values with respect to different sampling rates. The following sequences are recommended for optimized Record and Playback operations. Record Mode 1. Send POWERUP command. 2. Wait TPUD (power-up delay). 3. Send POWERUP command. 4. Wait 2 x TPUD (power-up delay). 5. a). Send SETREC command with address xx, or b). Send REC command (recording from current location). 6. Send STOP command to stop recording. 7. Wait TSTOP/PAUSE. For 3 & 4), please refer to Apps Brief 39A: recorded pop elimination in the ISD4000 series. For 5.a), the device will start recording at address xx and will generate an interrupt when an overflow (end of memory array) is reached, if no STOP command is sent before that. Then, it will automatic stop recording operation. Playback Mode 1. Send POWERUP command 2. Wait TPUD (power-up delay) 3. a). Send SETPLAY command with address xx, or b). Send PLAY command (playback from current location). 4. a). Send STOP command to halt the playback operation, or b). Wait for playback operation to stop automatically, when an EOM or OVF is reached. 5. Wait TSTOP/PAUSE. For 3.a), the device will start playback at address xx and it will generate an interrupt when an EOM or OVF is reached. It will then stop playback operation. Jun 28, 2021 Page 15 of 34 Rev1.5 ISD4004 7. TIMING DIAGRAMS TSSH SS TSSmin TSCKhi TSSS SCLK TDIS TDIH TSCKlow MOSI TPD (TRISTATE) MISO TPD TDF LSB FIGURE 5: TIMING DIAGRAM SS SCLK LSB A8 MOSI A9 A10 C0 C1 C2 C3 C4 LSB MISO OVF EOM P0 P1 P2 P3 P4 P5 FIGURE 6: 8-BIT COMMAND FORMAT Jun 28, 2021 Page 16 of 34 Rev1.5 ISD4004 SS BYTE 1 BYTE 2 BYTE 3 SCLK LSB MOSI A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 X X C0 C1 C2 C3 C4 X LSB MISO OVFEOM P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 X X X X X X ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ MISO Data ≈ ≈ ≈ ≈ ≈ ≈ ≈ Play/Record Stop ≈ ≈ ≈ MOSI ≈ ≈ SCLK ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ SS ≈ ≈ FIGURE 7: 16-BIT COMMAND FORMAT Data TSTOP/PAUSE ANA IN ≈ (Rec) TSTOP/PAUSE ≈ (Play) ANA OUT FIGURE 8: PLAYBACK/RECORD AND STOP CYCLE Jun 28, 2021 Page 17 of 34 Rev1.5 ISD4004 8. ABSOLUTE MAXIMUM RATINGS TABLE 5: ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS) CONDITIONS VALUES Junction temperature 150°C Storage temperature range -65°C to +150°C Voltage applied to any pin (VSS –0.3V) to (VCC +0.3V) Voltage applied to any pin (Input current limited to ±20mA) (VSS –1.0V) to (VCC +1.0V) Voltage applied to MOSI, SCLK, and SS pins (VSS –1.0V) to 5.5V (Input current limited to ±20mA) Lead temperature (soldering – 10 seconds) 300°C VCC – VSS -0.3V to +7.0V TABLE 6: ABSOLUTE MAXIMUM RATINGS (DIE) CONDITIONS VALUES Junction temperature 150°C Storage temperature range -65°C to +150°C Voltage applied to any pad (VSS –0.3V) to (VCC +0.3V) Voltage applied to any pad (Input current limited to ±20 mA) (VSS –1.0V) to (VCC +1.0V) Voltage applied to MOSI, SCLK, and SS pins (VSS –1.0V) to 5.5V (Input current limited to ±20mA) VCC – VSS -0.3V to +7.0V Note: Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability and performance. Functional operation is not implied at these conditions. Jun 28, 2021 Page 18 of 34 Rev1.5 ISD4004 8.1. OPERATING CONDITIONS TABLE 7: OPERATING CONDITIONS (PACKAGED PARTS) CONDITIONS VALUES Commercial operating temperature range (Case temperature) 0°C to +70°C Industrial operating temperature (Case temperature) -40°C to +85°C Supply voltage (VCC) [1] +2.7V to +3.3V Ground voltage (VSS) [2] 0V TABLE 8: OPERATING CONDITIONS (DIE) CONDITIONS Commercial operating temperature range Supply voltage (VCC) [1] [2] 0°C to +50°C +2.7V to +3.3V Ground voltage (VSS) [2] [1] VALUES 0V VCC = VCCA = VCCD VSS = VSSA = VSSD Jun 28, 2021 Page 19 of 34 Rev1.5 ISD4004 9. ELECTRICAL CHARACTERISTICS 9.1. PARAMETERS FOR PACKAGED PARTS TABLE 9: DC PARAMETERS PARAMETERS SYMBOLS MIN[2] TYP[1] MAX[2] UNITS VCC x 0.2 V CONDITIONS Input Low Voltage VIL Input High Voltage VIH Output Low Voltage VOL 0.4 V IOL = 10 µA RAC, INT Output Low Voltage VOL1 0.4 V IOL = 1 mA Output High Voltage VOH V IOH = -10 µA Operating Current - Playback - Record ICC Standby Current ISB Input Leakage Current IIL MISO Tri-State Current IHZ Output Load Impedance REXT ANA IN+ Input Resistance RANA IN+ 2.2 3.0 3.8 KΩ ANA IN- Input Resistance RANA IN- 40 56 71 KΩ ANA IN+ or ANA IN- to AUD OUT Gain AARP VCC x 0.8 V VCC - 0.4 15 25 30 40 mA mA REXT = ∞ [3] REXT = ∞ [3] 1 10 µA [3] [4] ±1 µA 10 µA 1 KΩ 5 23 dB 32 mVpp 1 KHz sinewave input [5] Notes: [1] Typical values @ TA = 25°C and VCC = 3.0V. [2] All Min/Max limits are guaranteed by Nuvoton via electronical testing or characterization. Not all specifications are 100 percent tested. [3] VCCA and VCCD connected together. [4] SS = VCCA = VCCD, XCLK = MOSI = VSSA = VSSA and all other pins floating. [5] Measured with AutoMute feature disabled. Jun 28, 2021 Page 20 of 34 Rev1.5 ISD4004 TABLE 10: AC PARAMETERS (Packaged Parts) CHARACTERISTIC Sampling Frequency ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M Filter Pass Band ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M Record Duration ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M Playback Duration ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M Power-Up Delay ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M Stop or Pause in Record or Play ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M RAC Clock Period ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M RAC Clock Low Time ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M RAC Clock Period in Message Cueing Mode ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M RAC Clock Low Time in Message Cueing Mode ISD4004-08M ISD4004-10M ISD4004-12M ISD4004-16M Total Harmonic Distortion ANA IN Input Voltage Jun 28, 2021 MIN[2] SYMBOLS FS FCF TREC TPLAY TPUD TSTOP or TPAUSE TRAC TRACL TYP[1] MAX[2] UNITS CONDITIONS 8.0 6.4 5.3 4.0 KHz KHz KHz KHz [5] 3.4 2.7 2.3 1.7 KHz KHz KHz KHz 3 dB Roll-Off Point[3][7] 8 10 12 16 min min min min [6] 8 10 12 16 min min min min [6] 25 31.25 37.5 50 msec msec msec msec 50 62.5 75 100 msec msec msec msec 200 250 300 400 msec msec msec msec 25 31.25 37.5 50 msec msec msec msec 125 156.3 187.5 250 µsec µsec µsec µsec 15.63 19.53 23.44 31.25 1 2 µsec µsec µsec µsec % 32 mV [5] [5] [5] [6] [6] [6] [6] [6] [6] [10] [10] [10] [10] TRACM TRACML THD VIN Page 21 of 34 32 mVpp 1 KHz sinewave input [11] Peak-to-Peak [4] [8] [9] Rev1.5 ISD4004 Notes: [1] Typical values @ TA = 25°C, VCC = 3.0V and timing measurement at 50% of Vcc level. [2] All Min/Max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all specifications are 100 percent tested. [3] Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions) [4] Single-ended input mode. In the differential input mode, VIN maximum for ANA IN+ and ANA IN- is 16 mVp-p. [5] Sampling Frequency can vary as much as ±2.25 percent over the commercial temperature and voltage ranges, and –6/+4 percent over the industrial temperature and voltage ranges. For greater stability, an external clock can be utilized (see Pin Descriptions) [6] Playback and Record Duration can vary as much as ±2.25 percent over the commercial temperature and voltage ranges, and –6/+4 percent over the industrial temperature and voltage ranges. For greater stability, an external clock can be utilized (see Pin Descriptions) [7] Filter specification applies to the antialiasing filter and the smoothing filter. Therefore, from input to output, expect a 6 dB drop by nature of passing through both filters. [8] The typical output voltage will be approximately 450 mVp-p with VIN at 32 mVp-p. [9] For optimal signal quality, this maximum limit is recommended. [10] When a record command is sent, T RAC = TRAC + TRACL on the first row address. [11] Measured with AutoMute feature disabled. Jun 28, 2021 Page 22 of 34 Rev1.5 ISD4004 9.2. PARAMETERS FOR DIE TABLE 11: DC PARAMETERS PARAMETERS [6] SYMBOLS MIN[2] TYP[1] MAX[2] UNITS VCC x 0.2 V CONDITIONS Input Low Voltage VIL Input High Voltage VIH Output Low Voltage VOL 0.4 V IOL = 10 µA RAC, INT Output Low Voltage VOL1 0.4 V IOL = 1 mA Output High Voltage VOH V IOH = -10 µA Operating Current -Playback -Record ICC Standby Current VCC x 0.8 V VCC - 0.4 15 25 30 40 mA mA REXT = ∞ [3] REXT = ∞ [3] ISB 1 10 µA [3] [4] Total Harmonic Distortion THD 1 2 % ANA IN+ or ANA IN- to AUD OUT Gain AARP 23 32 mVpp 1 KHz sinewave input [5] 32 mVpp 1 KHz sinewave input [5] dB Notes: [1] [2] [3] Typical values @ TA = 25°C and VCC = 3.0V. Sampling Frequency can vary as much as ±2.25 percent over the commercial temperature and voltage ranges. All Min/Max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all specifications are 100 percent tested. VCCA and VCCD connected together. [4] SS = VCCA = VCCD, XCLK = MOSI = VSSA = VSSA and all other pins floating. [5] Measured with AutoMute feature disabled. The test coverage for die is limited to room temperature testing. The test conditions may differ from that of packaged parts. [6] Jun 28, 2021 Page 23 of 34 Rev1.5 ISD4004 9.3. SPI AC PARAMETERS TABLE 12: AC PARAMETERS[1] PARAMETER SYMBOL MIN TSSS 500 nsec TSSH 500 nsec Data in Setup Time TDIS 200 nsec Data in Hold Time TDIH 200 nsec SS Setup Time SS Hold Time Output Delay Output Delay to HighZ [2] TYP MAX UNITS TPD 500 nsec TDF 500 nsec TSSmin 1 µsec SCLK High Time TSCKhi 400 nsec SCLK Low Time TSCKlow 400 nsec CLK Frequency F0 SS HIGH 1,000 CONDITIONS KHz Notes: [1] Typical values @ TA = 25°C, VCC = 3.0V and timing measurement at 50% of Vcc level. [2] Tri-state test condition. VCC 6.32KΩ MISO 10.91KΩ 50pF (Includes scope and fixture capacitance) Jun 28, 2021 Page 24 of 34 Rev1.5 ISD4004 10. TYPICAL APPLICATION CIRCUIT These application examples are for illustration purposes only. Nuvoton makes no representation or warranty that such application will be suitable for production. Make sure all bypass capacitors are as close as possible to the package. C9 15-30 pF C8 15-25 pF R7 10 K Ω OCS1 38 OCS2 1 RESET 2 IRQ 37 35 PD1/TD0 30 PD2/MISO 31 PD3/MOSI 32 PD4/SCK 33 PD5/SS 34 PC0 28 TCMP 68HC705C8P R6 47 K Ω R5 47 K Ω 29 TCAP VCC VCC PD0/RDI 3 MISO 2 MOSI 27 26 PC3 25 PC4 24 PC5 23 PC6 22 PC7 21 24 RAC PB0 12 25 INT PB1 13 PA0 PB2 10 PA1 PB3 15 9 PA2 PB4 16 8 PA3 PB5 17 7 PA4 PB6 18 6 PA5 PB7 19 5 PA6 4 PA7 C1 22 µ F VCCA 18 VSSA 23 PC1 14 C2 0.1 µF 28 SCLK 1 SS PC2 11 VCC U1 VCCD 27 VSSD 4 U2 39 C11 0.1 µF 16 ANA IN- C3 0.1 µF VSSA 12 VSSA 11 13 AUD OUT C4 1 µF 3 ISD4004 C10 0.1 µ F J1 2 4 17 ANA IN+ LINE OUT 5 R2 1M 1 R1 10K AM CAP 14 R3 100 26 XCLK R4 100K POT 1 C5 1µ F 3 2 U3 PDIP / SOIC C6 1µ F 13 -IN 14 +IN GAIN-OUT 11 V01 10 V02 5 BYPASS 6 7 HP-IN1 HP-IN2 3 HPSENSE 2 SHUTDOWN PD7 3 2 4 15 VDD 12 GND GND GND GND GND 1 4 8 9 16 5 J4 EXT SPEAKER 1 C7 .1µ F LM4860M FIGURE 9: APPLICATION EXAMPLE USING SPI Jun 28, 2021 Page 25 of 34 Rev1.5 ISD4004 VCC U2 23 24 GND RESET VCC COP 820C 6 VCC R7 3.3 K Ω C10 82 pF U1 3 MISO VCCD 27 21 2 MOSI VSSD 4 20 28 SCLK D0 19 1 G3 28 G2 27 VCCA 18 G1 26 VSSA 23 INT 25 VSSA 12 D3 22 D2 D1 SI 3 SK 2 G7 4 SO 1 L7 18 L6 17 L5 16 5 CLI L4 15 7 10 L3 14 8 11 L2 13 9 12 L1 12 10 13 L0 C9 0.1 µ F 16 C2 0.1 µF C1 22µ F SS ANA IN- VSSA 11 AUD OUT 13 C3 0.1 µF C4 1 µF 3 C8 0.1 µF 17 ANA IN+ 24 RAC 25 VCC VCC 11 R6 4.7 K Ω 4 LINE OUT 5 1 R2 1M R1 10K AM CAP 1 C5 1µ F INT C6 1µ F PDIP / SOIC R4 100K POT R3 100 14 26 XCLK R5 4.7 K Ω J1 2 ISD4004 3 2 U3 13 -IN 14 +IN GAIN-OUT 11 V01 10 V02 5 BYPASS 6 7 HP-IN1 HP-IN2 3 HPSENSE 2 SHUTDOWN 3 2 4 15 VDD 12 GND GND GND GND GND 1 4 8 9 16 5 J4 EXT SPEAKER 1 C7 .1µ F LM4860M FIGURE 10: APPLICATION EXAMPLE USING MICROWIRE Jun 28, 2021 Page 26 of 34 Rev1.5 ISD4004 VCC U1 U2 8 VSS 19 VSS MISO VCCD 27 2 MOSI VSSD 4 RC4 15 RC5 16 28 RC3 14 1 RC4 1 3 7 C1 22µ F SS MCLR RB0 C2 0.1 µF SCLK VCCA 18 VSSA 23 21 C3 0.1 µF VSSA 12 C9 0.1 µ F VCC VSSA 16 ANA IN- C8 0.1 µF VDD R7 3.3 K Ω RC0 9 11 17 ANA IN+ 24 RAC 25 11 C4 1 µF 13 3 4 VCC R1 10K AM CAP 1 C5 1µ F INT 26 XCLK R5 4.7 K Ω C6 1µ F PDIP / SOIC R4 100K POT R3 100 14 C10 R6 4.7 K Ω LINE OUT 5 1 R2 1M OSC1 VCC J1 2 ISD4004 PIC16C62A 20 AUD OUT 3 2 U3 13 -IN 14 +IN GAIN-OUT 11 V01 10 V02 5 BYPASS 6 7 HP-IN1 HP-IN2 3 HPSENSE 2 SHUTDOWN 3 2 4 15 VDD 12 GND GND GND GND GND 1 4 8 9 16 5 J4 EXT SPEAKER 1 C7 .1µ F LM4860M FIGURE 11: APPLICATION EXAMPLE USING SPI PORT ON MICROCONTROLLER Jun 28, 2021 Page 27 of 34 Rev1.5 ISD4004 11. PACKAGING AND DIE INFORMATION 11.1. 28-LEAD 300-MIL PLASTIC SMALL OUTLINE IC (SOIC) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A G C B D E H F INCHES MILLIMETERS Min Nom Max Min Nom Max A 0.701 0.706 0.711 17.81 17.93 18.06 B 0.097 0.101 0.104 2.46 2.56 2.64 C 0.292 0.296 0.299 7.42 7.52 7.59 D 0.005 0.009 0.0115 0.127 0.22 0.29 E 0.014 0.016 0.019 0.35 0.41 0.48 F 0.050 1.27 G 0.400 0.406 0.410 10.16 10.31 10.41 H 0.024 0.032 0.040 0.61 0.81 1.02 Note: Lead coplanarity to be within 0.004 inches. Jun 28, 2021 Page 28 of 34 Rev1.5 ISD4004 28-LEAD 600-MIL PLASTIC DUAL INLINE PACKAGE (PDIP) 11.2. INCHES A MILLIMETERS Min Nom Max Min Nom Max 1.445 1.450 1.455 36.70 36.83 36.96 B1 0.150 B2 0.065 C1 0.600 C2 0.530 0.070 0.540 D 3.81 0.075 1.65 0.625 15.24 0.550 13.46 1.78 15.88 13.72 0.19 D1 0.015 E 0.125 F 0.015 G 0.055 H 1.91 13.97 4.83 0.38 0.135 3.18 0.018 0.022 0.38 0.46 0.56 0.060 0.065 1.40 1.52 1.62 0.100 3.43 2.54 J 0.008 0.010 0.012 0.20 0.25 0.30 S 0.070 0.075 0.080 1.78 1.91 2.03 q 0° 15° 0° Jun 28, 2021 Page 29 of 34 15° Rev1.5 ISD4004 11.3. DIE INFORMATION ISD4004 Series o Die Dimensions (with scribe line) [1] X: 166.6 ± 1 mils V Y: 385.0 ± 1 mils VSSD MOSI MISO SCLK VCCD INT VCCD XCLK SS RAC VSSA SSD o Die Thickness [2] 11.5 ± 0.5 mils o Pad Opening Single pad: 90 x 90 microns Double pad: 180 x 90 microns ≈ VSSA[3] VSSA VSSA[3] ISD4004 ≈ [3] AUD OUT ANA IN- VCCA [3] AM CAP ANA IN+ VCCA Notes: [1] The backside of die is internally connected to VSS. It MUST NOT be connected to any other potential or damage may occur. [2] Die thickness is subject to change, please contact Nuvoton as this thickness may change in the future. [3] Double bond is recommended if treated as one pad. Jun 28, 2021 Page 30 of 34 Rev1.5 ISD4004 ISD4004 SERIES PAD COORDINATIONS (with respect to die center) Pad Pad Description X Axis (µm) Y Axis (µm) VSSA Analog Ground 1885.2 4623.7 RAC Row Address Clock 1483.8 4623.7 INT Interrupt 794.8 4623.7 XCLK External Clock Input 564.8 4623.7 VCCD Digital Power Supply 387.9 4623.7 VCCD Digital Power Supply 169.5 4623.7 SCLK Slave Clock -14.7 4623.7 Slave Select -198.1 4623.7 MOSI Master Out Slave In -1063.7 4623.7 MISO Master In Slave Out -1325.6 4623.7 VSSD Digital Ground -1665.3 4623.7 SS VSSD Digital Ground -1836.9 4623.7 VSSA [1] Analog Ground -1943.1 -4622.4 VSSA [1] Analog Ground -1853.1 -4622.4 VSSA Analog Ground -1599.9 -4622.4 AUD OUT Audio Output 281.9 -4622.4 AM CAP AutoMute 577.3 -4622.4 ANA IN- Inverting Analog Input 1449.3 -4622.4 ANA IN+ Noninverting Analog Input 1603.5 -4622.4 VCCA [1] Analog Power Supply 1853.7 -4622.4 VCCA [1] Analog Power Supply 1943.7 -4622.4 Note: [1] Jun 28, 2021 Double bond recommended if treated as one pad. Page 31 of 34 Rev1.5 ISD4004 12. ORDERING INFORMATION Jun 28, 2021 Page 32 of 34 Rev1.5 ISD4004 13. REVISION HISTORY VERSION DATE DESCRIPTION 1.0 Feb, 2004 Reformat the document. Add note for typical filter pass band. Add memory architecture description. Revise RAC timing parameter for MC. Revise AutoMute: playback only. Revise SPI, opcodes sections, record & playback steps. Rename TRACLO to TRACL. Revise AARP parameter. Revise DC & AC parameters tables for die. Revise die: (x,y) coordinates. 1.1 Apr, 2005 Add lead-free parts. Revise the Ordering information. Revise disclaim section. 1.2 Oct, 2005 Revise Packaging information. 1.3 Oct 31, 2008 Remove the leaded package option Remove the extended temperature option Update the external clock description Revise Ordering Information section Change to Nuvoton logo Revise MISO description 1.4 May 21, 2020 Update Document Format Remove TSOP Package 1.5 Jun 28, 2021 Update Ordering Information Jun 28, 2021 Page 33 of 34 Rev1.5 ISD4004 Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. Jun 28, 2021 Page 34 of 34 Rev1.5