TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Features
◼
◼
Applications
Input Voltage Range:
◼
Wireless Communication: CPU, ASIC, FPGA, CPLD, DSP
◆
Without BIAS: 1.4 V to 6.5 V
◼
High-Performance Analog: ADC, DAC, LVDS, VCO
◆
With BIAS: 1.1 V to 6.5V
◼
Noise-Sensitive Imaging: CMOS Sensors, Video ASICs
Output Voltage Options:
Description
◆
Fixed Output Voltage: 0.8 V to 3.95 V
◆
Adjustable Output Voltage: 0.8 V to 5.2 V
The TPL920 series products are 2-A high-current, 6-μVRMS low-
±1% Output Accuracy Over Line, Load Regulation, and
noise, high-PSRR, high-accuracy linear regulators with typically
Operating Temperature Range With BIAS
110-mV ultra-low dropout voltage at 2-A load condition. The
◼
2A Maximum Output Current
TPL920 series products support both fixed output voltage
◼
Low Dropout Voltage: 110 mV typ at 2 A
ranges from 0.8 V to 3.95 V and adjustable output voltage
◼
High PSRR:
ranges from 0.8 V to 5.2 V with external resistor divider.
◼
◆
70dB at 1kHz
◆
40dB at 1MHz
Ultra-low noise, high PSRR, and high output current capability
◼
6 μVRMS Output Voltage Noise
makes the TPL920 series products ideal power supply for noise-
◼
Excellent Transient Response
sensitive applications, such as high-speed communication
◼
Enable and Adjustable Soft-Start Control
facilities, test and measurement devices, or high-definition
◼
Open-Drain Power-Good (PG) Output
imaging equipment. Accurate output voltage tolerance, output
◼
Stable with a 22 μF or Larger Ceramic Output Capacitor
voltage remote sensing, excellent transient response, and
◼
Thermal Shutdown and Over-Current Protection
adjustable soft-start control ensures the TPL920 series products
◼
Operating Junction Temperature: –40°C to +125°C
optimal power supply for the large-scale processors or digital
◼
Package Options:
loads, such as ASIC, FPGA, CPLD and DSP.
◆
5×5 QFN-20
The TPL920 series products provide 5×5 QFN-20 package with
guaranteed operating junction temperature range (T J) from –
40°C to +125°C.
Typical Application Schematic
CIN
COUT
VIN
Digital I/O
or VIN
Optiona l
VBIAS
IN
PG
EN
OUT
TPL920
VOUT
SNS
BIAS
CBIAS
FB
NR/SS
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1 / 17
GND
50mV
100 mV
200 mV
400 mV
800 mV
1.6V
CNR /SS
GND
Rev.A.0
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Product Family Table
Part Number
Output Voltage
Orderable Number
Package
TPL920
Adjustable (0.8 V ~ 5.2 V)
TPL920ADJ-QF7R
5×5 QFN-20
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2 / 17
Transport Media,
Quantity
3,000
MSL
MSL3
Marking
information
L920A
Rev.A.0
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Table of Contents
Features ........................................................................................................................................................................... 1
Applications ..................................................................................................................................................................... 1
Description....................................................................................................................................................................... 1
Typical Application Schematic ...................................................................................................................................... 1
Product Family Table ...................................................................................................................................................... 2
Table of Contents ............................................................................................................................................................ 3
Revision History .............................................................................................................................................................. 4
Pin Configuration and Functions .................................................................................................................................. 5
Specifications .................................................................................................................................................................. 6
Absolute Maximum Ratings .......................................................................................................................................................... 6
ESD Ratings ................................................................................................................................................................................. 6
Recommended Operating Conditions ........................................................................................................................................... 6
Thermal Information ...................................................................................................................................................................... 6
Electrical Characteristics ............................................................................................................................................................... 7
Typical Performance Characteristics............................................................................................................................................. 9
Detailed Description ..................................................................................................................................................... 11
Overview ..................................................................................................................................................................................... 11
Functional Block Diagram ........................................................................................................................................................... 11
Feature Description ..................................................................................................................................................................... 11
Application and Implementation.................................................................................................................................. 15
Application Information................................................................................................................................................................ 15
Typical Application ...................................................................................................................................................................... 15
Layout Requirements .................................................................................................................................................................. 16
Package Outline Dimensions ....................................................................................................................................... 17
5×5 QFN-20 ................................................................................................................................................................................ 17
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3 / 17
Rev.A.0
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Revision History
Date
Revision
2019/04/30
Rev.Pre
Preliminary Version
2020/05/08
Rev.A.0
Initial Release
www.3peakic.com.cn
Notes
4 / 17
Rev.A.0
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Pin Configuration and Functions
TPL920 Series
QFN-20 Package
OUT
1
SNS
2
OUT
OUT
GND
IN
IN
Top View
20
19
18
17
16
Exposed
PAD
15
IN
14
EN
13
NR/SS
BIAS
50mV
5
11
1.6V
6
7
8
9
10
800 mV
12
400 mV
4
GND
PG
200 mV
3
100 mV
FB
Pin Functions
NAME
50mV, 100mV, 200mV,
400mV, 800mV, 1.6V
PIN NUMBER
TYPE
DESCRIPTION
Fixed output voltage setting pins. Connecting these pins to ground increases the
5, 6, 7, 9, 10, 11
I
output voltage. Multiple pins may be simultaneously connected to GND to select the
desired output voltage. Leave these pins open when use external resistor divider.
BIAS
12
I
EN
14
I
BIAS voltage input pin. A 10-µF capacitor or larger must be connected between this
pin and ground. BIAS must be left open or tied to ground when not used.
Regulator enable pin. Drive EN high to turn on the regulator; drive EN low to turn off
the regulator. For automatic startup, connect EN to IN directly.
Output voltage feedback pin. Connect to an external resistor divider to adjust the
FB
3
I
output voltage. A 10-nF feed-forward capacitor from FB to OUT (as close as possible
to FB pin) is recommended to maximize regulator ac performance.
GND
8, 18
–
IN
15, 16, 17
I
NR/SS
13
I
OUT
1, 19, 20
O
PG
4
O
Ground reference pin. Connect GND pin to PCB ground plane directly.
Input voltage pin. A 10-μF or larger ceramic capacitor from IN to ground (as close as
possible to IN pin) is required to reduce the jitter from previous-stage power supply.
Noise-reduction and soft-start pin. A 10-nF or larger capacitor from NR/SS to GND
(as close as possible to NR/SS pin) is recommended to maximize ac performance.
Regulated output voltage pin. A 22-μF or larger ceramic capacitor from OUT to ground
(as close as possible to OUT pin) is required to ensure regulator stability.
Open-drain power-good output pin. Leave PG pin open when not used.
Output voltage sense input pin. Connect this pin to the load side of the output trace
SNS
2
I
only when using fixed output voltage. Leave this pin open when using external
resistor divider.
(1) Exposed PAD must be connected to a large-area ground plane to maximum the thermal performance.
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5 / 17
Rev.A.0
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Specifications
Absolute Maximum Ratings
MIN
MAX
UNIT
IN, BIAS, EN, PG
–0.3
7
V
OUT, SNS
–0.3
VIN + 0.3
V
NR/SS, FB
–0.3
3.6
V
50mV, 100mV, 200mV, 400mV, 800mV, 1.6V
–0.3
VOUT + 0.3
V
TJ
Junction Temperature Range
–40
150
°C
TSTG
Storage Temperature Range
–65
150
°C
TL
Lead Temperature (Soldering 10 sec)
260
°C
(1) Stresses beyond the Absolute Maximum Ratings may permanently damage the device.
(2) All voltage values are with respect to GND.
ESD Ratings
Condition
Minimum Level
Unit
HBM
Human Body Model ESD
ANSI/ESDA/JEDEC JS-001
±4000
V
CDM
Charged Device Model ESD
ANSI/ESDA/JEDEC JS-002
±1500
V
Recommended Operating Conditions
MIN
TYP
MAX
UNIT
IN
Input voltage
1.1
6.5
V
BIAS
BIAS voltage
3
6.5
V
EN
Enable voltage
0
6.5
V
OUT
Output voltage
0.8
5.2
V
CIN
Input capacitor
10
µF
COUT
Output capacitor
22
µF
CFF
Feed-forward capacitor
10
nF
CNR/SS
NR/SS capacitor
10
nF
RPG
Power-good pull-up resistor
R1
High-side resistor of the resistor divider
R2
Low-side resistor of the resistor divider
TJ
Junction Temperature Range
10
100
kΩ
12.1
–40
kΩ
160
kΩ
125
°C
Thermal Information
PACKAGE
θJA
θJC,bottom
UNIT
5×5 QFN-20
54.5
11.15
°C/W
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6 / 17
Rev.A.0
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Electrical Characteristics
TJ = –40°C to +125°C (typical value at TJ = +25°C), VIN = VOUT(NOM) + 0.4 V or 1.4 V, whichever is greater; VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
CIN = 10 µF, COUT = 47 µF, CNR/SS = 0 nF, CFF = open, OUT connect to 50 Ω to ground, PG connected to 100 kΩ to OUT, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.1
6.5
V
3
6.5
V
1.0
V
Supply Input Voltage and Current
VIN
Input supply voltage range
VBIAS
Bias supply voltage range
VIN = 1.1 V
Input supply UVLO with BIAS
VIN rising with VBIAS = 3 V
Hysteresis
VBIAS = 3 V
60
Input supply UVLO without BIAS
VIN rising
1.3
UVLOIN1
UVLOIN2
UVLOBIAS
IGND
0.75
Hysteresis
mV
1.4
V
200
mV
Bias supply UVLO
VBIAS rising, VIN = 1.1 V
2.7
Hysteresis
VIN = 1.1 V
180
VIN = 6.5 V, IOUT = 5 mA
17
30
mA
VIN = 1.4 V, IOUT = 2 A
12
25
mA
6
20
mA
10
25
µA
3.5
10
mA
GND pin current
VIN = 1.1 V, VBIAS = 3 V, VOUT(NOM) = 0.8 V, IOUT =
2A
ISD
Shutdown current
IBIAS
BIAS pin current
VIN = 6.5 V, VEN = 0.5 V, PG = open
VIN = 1.1 V, VBIAS = 6.5 V, VOUT(NOM) = 0.8 V, IOUT
=2A
2.95
V
mV
Enable and Power Good
VIH(EN)
EN pin high-level input voltage
Device enable
1.1
6.5
V
VIL(EN)
EN pin low-level input voltage
Device disable
0
0.4
V
IEN
EN pin current
VIN = 6.5 V, VEN = 0 V to 6.5 V
–0.2
0.2
µA
PG pin threshold
VOUT falling
82%
93%
× VOUT
VPG
Hysteresis
88%
2%
× VOUT
VOL(PG)
PG pin low-level output voltage
VOUT < VPG, source 1 mA to PG pin
0.4
V
IPG
PG pin leakage current
VOUT > VPG, apply 6.5 V at PG pin
2
µA
0.8 + 1%
V
100
nA
Regulated Output Voltage and Current
VFB
Feedback voltage
IFB
FB pin leakage current
VNR/SS
NR/SS pin voltage
INR/SS
NR/SS pin charging current
Output voltage range
VOUT
Accuracy
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0.8 – 1%
VIN = 6.5 V, stress VFB = 0.8V
0.8
–100
0.8
VIN = 6.5 V, VNR/SS = GND
4
7.2
V
9
µA
Fixed
0.8
3.95
V
Adjustable (resistor tolerances are not included)
0.8
5.2
V
–1%
1%
VOUT = 0.8 V to 5.2 V, IOUT = 5 mA to 2 A (resistor
tolerances are not included)
7 / 17
Rev.A.0
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Electrical Characteristics (continued)
TJ = –40°C to +125°C (typical value at TJ = +25°C), VIN = VOUT(NOM) + 0.4 V or 1.4 V, whichever is greater; VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
CIN = 10 µF, COUT = 47 µF, CNR/SS = 0 nF, CFF = open, OUT connect to 50 Ω to ground, PG connected to 100 k Ω to OUT, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Regulated Output Voltage and Current
Line regulation
ΔVOUT
Load regulation
Dropout voltage without BIAS
VDO
Dropout voltage with BIAS
VIN = 1.4 V to 6.5 V, IOUT = 5 mA
0.03
mV/V
VIN = 1.1 V, VBIAS = 3 V to 6.5 V, IOUT = 5 mA to 2 A
0.7
mV/A
IOUT = 5 mA to 2 A
0.8
mV/A
VIN = 1.4 V, IOUT = 1 A, VFB = 0.8 V – 3%
55
130
mV
VIN = 1.4 V, IOUT = 2 A, VFB = 0.8 V – 3%
110
260
mV
VIN = 5.4 V, IOUT = 2 A, VFB = 0.8 V – 3%
120
280
mV
VIN = 5.6 V, IOUT = 2 A, VFB = 0.8 V – 3%
120
280
mV
VIN = 1.1 V, VBIAS = 5 V, IOUT = 1 A, VFB = 0.8 V – 3%
55
130
mV
VIN = 1.1 V, VBIAS = 5 V, IOUT = 2 A, VFB = 0.8 V – 3%
110
260
mV
3.4
4.2
A
ILIM
Output current limit
VOUT forced at 0.9 × VOUT(NOM), VIN = VOUT(NOM) + 0.4 V
ISC
Short-circuit current limit
RLOAD ≤ 20 mΩ
2.1
0.9
A
f = 1 kHz, VBIAS = 3 V
70
dB
IOUT = 2 A, CNR/SS = 100 nF,
f = 1 MHz, VBIAS = 3 V
40
dB
CFF = 10 nF, COUT = 22 μF
f = 1 kHz
70
dB
f = 1 MHz
40
dB
6
μVRMS
8
μVRMS
11
μVRMS
160
°C
20
°C
PSRR and Noise
PSRR
Power supply ripple rejection
BW = 10 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.8 V,
VBIAS = 5 V, IOUT = 2 A, CNR/SS = 100 nF, CFF = 10 nF,
COUT = 47 μF || 10μF || 10μF
BW = 10 Hz to 100 kHz,
VN
Output noise voltage
VOUT = 5 V, IOUT = 2 A, CNR/SS = 100 nF, CFF = 100 nF,
COUT = 47 μF || 10μF || 10μF
BW = 10 Hz to 100 kHz,
VOUT = 5 V, IOUT = 2 A, CNR/SS = 100 nF, CFF = 10 nF,
COUT = 47 μF || 10μF || 10μF
Temperature Range
TSD
TJ
Thermal shutdown threshold
Temperature increasing
Hysteresis
Operating junction temperature
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–40
8 / 17
125
Rev.A.0
°C
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Typical Performance Characteristics
TA = +25°C, VIN = VOUT(NOM) + 0.4 V or 1.4 V, whichever is greater; VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, CIN = 10 µF, COUT = 47 µF, CNR/SS = 0 nF,
CFF = open, OUT connect to 50 Ω to ground, PG connected to 100 k Ω to OUT, unless otherwise noted.
120
140
IOUT = 0.1 A
IOUT = 0.1 A
100
IOUT = 1 A
IOUT = 2 A
PSRR(dB)
PSRR(dB)
80
60
120
IOUT = 1 A
100
IOUT = 2 A
80
60
40
40
20
20
0
0
10
100
1K
10K
100K
1M
10M
10
100
1K
Frequency(Hz)
10K
100K
1M
VIN = 1.1 V, VBIAS = 3 V, VOUT = 0.8 V,
VIN = 5.5 V, VBIAS = 3 V, VOUT = 5.2 V,
COUT = 47µF // 10µF // 10µF, CNR/SS =100nF, CFF = open
COUT = 47µF // 10µF // 10µF, CNR/SS =100nF, CFF = open
Figure 1 PSRR vs. Frequency and IOUT
Figure 2 PSRR vs. Frequency and IOUT
120
IOUT = 2 A
80
VOUT = 0.8 V
VOUT = 5.2 V
100
IOUT = 1 A
PSRR(dB)
PSRR(dB)
120
IOUT = 0.1 A
100
60
80
60
40
40
20
20
0
0
10
100
1K
10K
100K
1M
10M
10
100
1K
Frequency(Hz)
10K
100K
1M
10M
Frequency(Hz)
VIN = 5.5 V, VBIAS = open, VOUT = 5.2 V,
VIN = VIN = VOUT(NOM) + 0.3 V, VBIAS = 3V,
COUT = 47µF // 10µF // 10µF, CNR/SS =100nF, CFF = open
COUT = 47µF // 10µF // 10µF, CNR/SS =100nF, CFF = open
Figure 3 PSRR vs. Frequency and IOUT
Figure 4 PSRR vs. Frequency and VOUT
150
150
−40°C
−40°C
25°C
25°C
Dropout Voltage (mV)
Dropout Voltage (mV)
10M
Frequency(Hz)
85°C
100
50
85°C
100
50
0
0
0
0.5
1
1.5
2
0
Load Current (A)
VIN = 1.1 V
0.5
1
1.5
Load Current (A)
VIN = 5.5 V
Figure 5 Dropout Voltage vs. IOUT
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Figure 6 Dropout Voltage vs. IOUT
9 / 17
Rev.A.0
2
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Typical Performance Characteristics (continued)
TA = +25°C, VIN = VOUT(NOM) + 0.4 V or 1.4 V, whichever is greater; VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, CIN = 10 µF, COUT = 47 µF, CNR/SS = 0 nF,
1
1
0.8
0.8
Enable Threshold (V)
Enable Threshold (V)
CFF = open, OUT connect to 50 Ω to ground, PG connected to 100 k Ω to OUT, unless otherwise noted.
0.6
0.4
VIH(EN)
0.2
VIL(EN)
0
0.6
0.4
VIH(EN)
VIL(EN)
0.2
0
-40 -25 -10 5
20 35 50 65 80 95 110 125
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
Ambient Temperature (°C)
Supply Voltage (V)
VIN = 1.4 V, VBIAS = open, VOUT = 0.8 V, IOUT = 1 mA
VBIAS = open, VOUT = 0.8 V, IOUT = 1 mA
Figure 7 Enable Threshold vs Temperature
Figure 8 Enable Threshold vs Input Voltage
1.5
UVLOIN2 Threshold (V)
UVLOIN1 Threshold (V)
1
0.8
0.6
0.4
VIN,rising
0.2
VIN,falling
0
1
0.5
VIN,rising
VIN,falling
0
-40 -25 -10 5
20 35 50 65 80 95 110 125
-40 -25 -10 5
Ambient Temperature (°C)
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
VBIAS = 3 V, VOUT = 0.8 V, IOUT = 1 mA
VBIAS = open, VOUT = 0.8 V, IOUT = 1 mA
Figure 9 UVLOIN1 vs. Temperature
Figure 10 UVLOIN2 vs. Temperature
0.820
0.820
25°C
0.810
Output Voltage (V)
Output Voltage (V)
–40°C
85°C
125°C
0.800
0.790
0.780
–40°C
25°C
0.810
85°C
125°C
0.800
0.790
0.780
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
0
Supply Voltage (V)
VBIAS = 3 V, VOUT = 0.8 V, IOUT = 5 mA
1
1.5
Load Current (A)
VIN = 1.1 V, VBIAS = 3 V, VOUT = 0.8 V
Figure 11 Line Regulation
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0.5
Figure 12 Load Regulation
10 / 17
Rev.A.0
2
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Detailed Description
Overview
The TPL920 series products are 2-A high-current, 6-μVRMS low-noise, high-PSRR, high-accuracy linear regulators with typically 110mV ultra-low dropout voltage at 2-A load condition. The TPL920 series products support both fixed output voltage ranges from 0.8 V
to 3.95 V and adjustable output voltage ranges from 0.8 V to 5.2 V with external resistor divider.
Ultra-low noise, high PSRR, and high output current capability makes the TPL920 series products ideal power supply for noisesensitive applications, such as high-speed communication facilities, test and measurement devices, or high-definition imaging
equipment. Accurate output voltage tolerance, output voltage remote sensing, excellent transient response, and adjustable soft-start
control ensures the TPL920 series products optimal power supply for the large-scale processors or digital loads, such as ASIC, FPGA,
CPLD and DSP.
Functional Block Diagram
IN
OUT
Charge
Pump
BIAS
Curren t
Control
Acti ve
Discha rge
PSRR
Control
Regula tor
Control
Thermal
Control
UVLO
Control
SNS
Device
Ena ble
Control
2R
EA
EN
Thermal
Shu tdo wn
+
–
FB
R
VREF
2R
4R
INR /SS
16R
NR/SS
PG
8R
32R
1.6V
800 mV
400 mV
200 mV
100 mV
50mV
Power Goo d
Control
GND
Figure 13 Functional Block Diagram
Feature Description
Enable (EN)
The TPL920 series provide a device enable pin (EN) to enable or disable the device. Connect this pin to the GPIO of an external
digital logic control circuit to control the device. When the V EN voltage falls below VIL(EN), the LDO device turns off, and when the VEN
ramps above VIH(EN), the LDO device turns on.
Under-Voltage Lockout (UVLO)
The TPL920 series use an under-voltage lockout circuit to keep the output shut off until the internal circuitry operates properly.
Voltage Regulation
The TPL920 series provide two options to set the output voltage: fixed output voltage by the programming pins or adjustable the
output voltage by external resistors.
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11 / 17
Rev.A.0
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
•
Fixed Output Voltage Setting
The TPL920 series integrate resistor divider internally to set the fixed output voltage. The fixed output voltage can be set
from 0.8V to 3.95V by connecting the output voltage setting pins (pin 5 to pin 11) to ground or left them open. Use Equation
1 to calculate the output voltage.
VOUT = VNR/SS + VPin _ Settings
(1)
Table 1 provides a full list of different output voltage target and the corresponding pin settings.
Table 1 Fixed Output Voltage Setting
VOUT (V)
50mV
100mV
200mV
400mV
800mV
1.6V
VOUT (V)
50mV
100mV
200mV
400mV
800mV
1.6V
Pin
5
6
7
9
10
11
Pin
5
6
7
9
10
11
0.80
Open
Open
Open
Open
Open
Open
2.40
Open
Open
Open
Open
Open
GND
0.85
GND
Open
Open
Open
Open
Open
2.45
GND
Open
Open
Open
Open
GND
0.90
Open
GND
Open
Open
Open
Open
2.50
Open
GND
Open
Open
Open
GND
0.95
GND
GND
Open
Open
Open
Open
2.55
GND
GND
Open
Open
Open
GND
1.00
Open
Open
GND
Open
Open
Open
2.60
Open
Open
GND
Open
Open
GND
1.05
GND
Open
GND
Open
Open
Open
2.65
GND
Open
GND
Open
Open
GND
1.10
Open
GND
GND
Open
Open
Open
2.70
Open
GND
GND
Open
Open
GND
1.15
GND
GND
GND
Open
Open
Open
2.75
GND
GND
GND
Open
Open
GND
1.20
Open
Open
Open
GND
Open
Open
2.80
Open
Open
Open
GND
Open
GND
1.25
GND
Open
Open
GND
Open
Open
2.85
GND
Open
Open
GND
Open
GND
1.30
Open
GND
Open
GND
Open
Open
2.90
Open
GND
Open
GND
Open
GND
1.35
GND
GND
Open
GND
Open
Open
2.95
GND
GND
Open
GND
Open
GND
1.40
Open
Open
GND
GND
Open
Open
3.00
Open
Open
GND
GND
Open
GND
1.45
GND
Open
GND
GND
Open
Open
3.05
GND
Open
GND
GND
Open
GND
1.50
Open
GND
GND
GND
Open
Open
3.10
Open
GND
GND
GND
Open
GND
1.55
GND
GND
GND
GND
Open
Open
3.15
GND
GND
GND
GND
Open
GND
1.60
Open
Open
Open
Open
GND
Open
3.20
Open
Open
Open
Open
GND
GND
1.65
GND
Open
Open
Open
GND
Open
3.25
GND
Open
Open
Open
GND
GND
1.70
Open
GND
Open
Open
GND
Open
3.30
Open
GND
Open
Open
GND
GND
1.75
GND
GND
Open
Open
GND
Open
3.35
GND
GND
Open
Open
GND
GND
1.80
Open
Open
GND
Open
GND
Open
3.40
Open
Open
GND
Open
GND
GND
1.85
GND
Open
GND
Open
GND
Open
3.45
GND
Open
GND
Open
GND
GND
1.90
Open
GND
GND
Open
GND
Open
3.50
Open
GND
GND
Open
GND
GND
1.95
GND
GND
GND
Open
GND
Open
3.55
GND
GND
GND
Open
GND
GND
2.00
Open
Open
Open
GND
GND
Open
3.60
Open
Open
Open
GND
GND
GND
2.05
GND
Open
Open
GND
GND
Open
3.65
GND
Open
Open
GND
GND
GND
2.10
Open
GND
Open
GND
GND
Open
3.70
Open
GND
Open
GND
GND
GND
2.15
GND
GND
Open
GND
GND
Open
3.75
GND
GND
Open
GND
GND
GND
2.20
Open
Open
GND
GND
GND
Open
3.80
Open
Open
GND
GND
GND
GND
2.25
GND
Open
GND
GND
GND
Open
3.85
GND
Open
GND
GND
GND
GND
2.30
Open
GND
GND
GND
GND
Open
3.90
Open
GND
GND
GND
GND
GND
2.35
GND
GND
GND
GND
GND
Open
3.95
GND
GND
GND
GND
GND
GND
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12 / 17
Rev.A.0
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
•
Adjustable Output Voltage Setting
The TPL920 series also provide an adjustable output voltage option. Using external resistors divider, the output voltage of
TPL920 series is determined by the value of the resistor R1 and R2 in Figure 14. Use Equation 2 to calculate the output
voltage.
R1
VOUT = VFB 1 +
R2
(2)
Where the feedback voltage VFB is 0.8 V.
Table 2 provides a list of recommended resistor combinations to achieve the common output voltage values.
Table 2 External Resistor Combinations
Target Output Voltage (V)
External Resistors Divider
Calculated Output Voltage (V)
R1 (kΩ)
R2 (kΩ)
0.80
0
Open
0.800
0.81
2
160
0.810
0.82
4.02
160
0.820
0.83
6.04
160
0.830
0.84
8.06
160
0.840
0.85
10
160
0.850
0.86
12
160
0.860
0.87
12.4
143
0.869
0.88
12.4
124
0.880
0.89
12
107
0.890
0.90
12.4
100
0.899
0.95
12.4
66.5
0.949
1.00
12.4
49.9
0.999
1.10
12.4
33.2
1.099
1.20
12.4
24.9
1.198
1.50
12.4
14.3
1.494
1.80
12.4
10
1.792
1.90
12.1
8.87
1.891
2.50
12.4
5.9
2.481
2.85
12.1
4.75
2.838
3.00
12.1
4.42
2.990
3.30
11.8
3.74
3.324
3.60
12.1
3.48
3.582
4.50
11.8
2.55
4.502
5.00
12.4
2.37
4.986
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13 / 17
Rev.A.0
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Programmable Soft Start
The TPL930 series integrate a programmable soft-start function to control the output voltage ramp-up slew rate and start-up time. By
selecting the external capacitor at the NR/SS pin (CNR/SS), the output start-up time can be can calculated with Equation 3.
t Start −up = 1.25
VNR/SS CNR/SS
INR/SS
(3)
Where:
•
the typical value of VNR/SS is 0.8V
•
the typical value of INR/SS is 7.2uA
•
CNR/SS is the external capacitor at the NR/SS pin
Charge Pump Noise
The TPL920 series integrate a charge pump to improve the PSRR and transient response under low input voltage conditions and it
generates a minimal amount of noise at the frequency around 15 MHz. It is recommended to use 10-nF to 100-nF bypass capacitors
close to the load a ferrite bead between the LDO output and the load input capacitors forms a pi-filter to reduce the high-frequency
noise level.
Power Good (PG)
The TPL920 series integrate an open-drain output power good indicator. Connect PG pin to a pull-up voltage through a resistor from
10 kΩ to 100 kΩ if power good function is used, or left PG pin open if it is not used.
After regulator startup, the PG pin keeps low impendence until the output voltage reached the power good threshold VPG,TH. When
output voltage is higher than VPG,TH , the PG pin turns to high output impedance, and PG is pulled up to high voltage level to indicate
the output voltage is ready.
Output Active Discharge
The TPL920 series integrate an output discharge path from OUT to GND. When the device is disabled, either EN or VIN is lower than
turn-on threshold, the output will actively discharge the output voltage through an internal resistor of several hundred ohms.
Do not rely on this active discharge circuit for discharging large output capacitors when the input voltage falls below the output voltage.
Reverse current flow through internal power MOSFET can permanently damage the device, and external current protection is
essential at this condition.
Over-Current Protection and Short-to-Ground Protection
The TPL920 series integrate an internal current limit that helps to protect the device during fault conditions.
•
When the output is pulled down below the target output voltage, over-current protection starts to work and limit the output
current to a typical value of 3.4 A.
•
When the output is shorted to ground directly, short-to-ground protection starts to work and limit the output current to ISC.
Under the over-current conditions, the internal junction temperature ramps up quickly. When the junction temperature is high enough,
it will cause the over temperature protection.
Over-Temperature Protection
The recommended operating junction temperature range is –40°C to 125°C. When the junction temperature is between 125°C and
the thermal shutdown (TSD) threshold, the regulator can still work well, but will reduce the device lifetime for long-term using.
The over-temperature protection works when the junction temperature exceeds the thermal shutdown (TSD) threshold, which turns
off the regulator immediately. Until when the device cools down and the junction temperature falls below the thermal shutdown
threshold minus thermal shutdown hysteresis, the regulator turns on again.
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14 / 17
Rev.A.0
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Application and Implementation
NOTE
Information in the following applications sections is not part of the 3PEAK’s component specification and 3PEAK does
not warrant its accuracy or completeness. 3PEAK’s customers are responsible for determining suitability of
components for their purposes. Customers should validate and test their design implementation to confirm system
functionality.
Application Information
The TPL920 series products are 2-A high-current, 6-μVRMS low-noise, high-PSRR, high-accuracy linear regulators with typically 110mV ultra-low dropout voltage at 2-A load condition. The following application schematic shows a typical usage of the TPL920 series.
Typical Application
Adjustable Output Operation
Figure 14 shows a typical application schematic of the TPL920 series with adjustable output operation. Refer to section Adjustable
Output Voltage Setting to set the output voltage.
CIN
COUT
VIN
Digital I/O
or VIN
Optiona l
VBIAS
IN
PG
EN
OUT
TPL920
VOUT
SNS
BIAS
CBIAS
FB
NR/SS
100 mV
GND
50mV
200 mV
800 mV
400 mV
1.6V
CNR /SS
GND
Figure 14 Adjustable Output Operation
Fixed Output Operation
Figure 15 shows a typical application schematic of the TPL920 series with fixed output operation. Refer to section Fixed Output
Voltage Setting to set the output voltage. In this example, output voltage is set to 1.8 V (VNR/SS +0.8 V + 0.2 V).
CIN
COUT
VIN
Digital I/O
or VIN
IN
PG
EN
OUT
TPL920
VBIAS
VOUT
SNS
BIAS
CBIAS
FB
NR/SS
GND
50mV
100 mV
200 mV
400 mV
800 mV
1.6V
CNR /SS
Figure 15 Fixed 1.8V Output Voltage Operation
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15 / 17
Rev.A.0
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Input Capacitor and Output Capacitor
The TPL920 series is designed to be stable with low equivalent series resistance (ESR) ceramic capacitors at the input, output, and
noise-reduction pin (NR/SS). It is recommended to use ceramic capacitors with X7R-, X5R-, and COG-rated dielectric materials to
get good capacitive stability across temperature.
3PEAK recommends adding a 10 μF or greater capacitor with a 0.1 μF bypass capacitor in parallel at IN pin to keep the input voltage
stable. The voltage rating of the capacitors must be greater than the maximum input voltage.
To ensure loop stability, the TPL920 series requires an output capacitor with a minimum effective capacitance value of 10 μF. 3PEAK
recommends selecting a X7R-type 22-μF ceramic capacitor with low ESR over temperature.
Both input capacitors and output capacitors must be placed as close to the device pins as possible.
Power Dissipation
During normal operation, LDO junction temperature should not exceed 125°C. Using below equations to calculate the power
dissipation and estimate the junction temperature.
The power dissipation can be calculated using Equation 4.
PD = ( VIN − VOUT ) IOUT + VIN IGND
(4)
The junction temperature can be estimated using Equation 5. θJA is the junction-to-ambient thermal resistance.
TJ = TA + PD JA
(5)
Layout Requirements
•
Both input capacitors and output capacitors must be placed as close to the device pins as possible, and vias between
capacitors and device power pins must be avoid.
•
It is recommended to bypass the input pin to ground with a 0.1 μF bypass capacitor. The loop area formed by the bypass
capacitor connection, IN pin and the GND pin of the system must be as small as possible.
•
It is recommended to use wide trace lengths or thick copper weight to minimize I×R drop and heat dissipation.
www.3peakic.com.cn
16 / 17
Rev.A.0
TPL920 Series
2-A Output, High-PSRR, Low-Noise LDO Regulator
Package Outline Dimensions
5×5 QFN-20
Symbol
A
A1
A3
D
E
D1
E1
k
b
e
L
⚫
Dimensions In Millimeters
Min.
Max.
0.700
0.800
0.000
0.050
0.203REF.
4.900
5.100
4.900
5.100
3.000
3.200
3.000
3.200
0.400REF.
0.250
0.350
0.650BSC.
0.450
0.650
Dimensions In Inches
Min.
Max.
0.028
0.031
0.000
0.002
0.008REF.
0.193
0.201
0.193
0.201
0.118
0.126
0.118
0.126
0.016REF.
0.010
0.014
0.016BSC.
0.018
0.026
3PEAK and the 3PEAK logo are registered trademarks of 3PEAK INCORPORATED. All
other trademarks are the property of their respective owners.
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17 / 17
Rev.A.0
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