TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Features
Description
◼
Input Voltage Range: 2.2 V to 6.5 V
The TPL910 series products are 1-A high-current, 24-μVRMS
◼
Output Voltage Options:
low-noise, high-PSRR, high-accuracy linear regulators with only
◼
◆
Fixed Output Voltage: 0.8 V to 5 V
500-mV maximum ultra-low dropout voltage at 1-A load current.
◆
Adjustable Output Voltage: 0.8 V to 5.2 V
The TPL910 series products support both fixed output voltage
3% Accuracy over Line Regulation, Load Regulation, and
ranges from 0.8 V to 5 V and adjustable output voltage ranges
Operating Temperature Range
from 0.8 V to 5.2 V with external resistor divider.
◼
1 A Maximum Output Current
◼
Low Dropout Voltage: 500 mV Maximum at 1 A
Ultra-low noise, high PSRR, and high output current capability
◼
High PSRR:
makes the TPL910 series products ideal power supply for noise-
◆
65 dB at 1 kHz
sensitive applications, such as high-speed communication
◆
50 dB at 100 kHz
facilities, test and measurement devices, or high-definition
◼
24 μVRMS Output Voltage Noise (100 Hz to 100kHz)
imaging equipment. Accurate output voltage tolerance, output
◼
Excellent Transient Response
remote sensing, excellent transient response, and adjustable
◼
Stable with a 10 μF or Larger Ceramic Output Capacitor
soft-start control ensures the TPL910 series products optimal
◼
Thermal Shutdown and Over-Current Protection
power supply for the large-scale processors or digital loads,
◼
Operating Junction Temperature: –40°C to +125°C
such as ASIC, FPGA, CPLD and DSP.
◼
Package: 3×3 DFN-8
The TPL910 series products provide 3×3 DFN-8 package with
Applications
guaranteed operating junction temperature range (T J) from –
◼
Wireless Communication: CPU, ASIC, FPGA, CPLD, DSP
◼
High-Performance Analog: ADC, DAC, LVDS, VCO
◼
Noise-Sensitive Imaging: CMOS Sensors, Video ASICs
40°C to +125°C.
Typical Application Schematic
CIN
VIN
VIN
Digital I/O
or VIN
EN
VOUT
VOUT
R1
TPL910
CFF
COUT
FB
R2
NR
CNR
www.3peakic.com.cn
GND
1 / 17
Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Product Family Table
Part Number
Output Voltage
Orderable Number
Package
TPL910
Adjustable (0.8 V ~ 5.2 V)
TPL910ADJ-DF6R
3×3 DFN-8
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2 / 17
Transport Media,
Quantity
4,000
MSL
MSL3
Marking
information
L910A
Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Table of Contents
Features ........................................................................................................................................................................... 1
Applications ..................................................................................................................................................................... 1
Description....................................................................................................................................................................... 1
Typical Application Schematic ...................................................................................................................................... 1
Product Family Table ...................................................................................................................................................... 2
Table of Contents ............................................................................................................................................................ 3
Revision History .............................................................................................................................................................. 4
Pin Configuration and Functions .................................................................................................................................. 5
Specifications .................................................................................................................................................................. 6
Absolute Maximum Ratings .......................................................................................................................................................... 6
ESD Ratings ................................................................................................................................................................................. 6
Recommended Operating Conditions ........................................................................................................................................... 6
Thermal Information ...................................................................................................................................................................... 6
Electrical Characteristics ............................................................................................................................................................... 7
Typical Performance Characteristics............................................................................................................................................. 9
Detailed Description ..................................................................................................................................................... 11
Overview ..................................................................................................................................................................................... 11
Functional Block Diagram ........................................................................................................................................................... 11
Feature Description ..................................................................................................................................................................... 11
Application and Implementation.................................................................................................................................. 14
Application Information................................................................................................................................................................ 14
Typical Application ...................................................................................................................................................................... 14
Layout Requirements .................................................................................................................................................................. 15
Package Outline Dimensions ....................................................................................................................................... 16
3×3 DFN-8 .................................................................................................................................................................................. 17
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3 / 17
Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Revision History
Date
Revision
Notes
2019/04/30
Rev.Pre
Preliminary Version
2020/05/08
Rev.A.0
Initial Release
1. Update the top view figure of DFN-8 Package in Page 5
2021/06/07
Rev.A.1
2. Add Tape and Reel Information in Page 16
3. Change Package Outline Dimensions, 3×3 DFN-8, in Page 17
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4 / 17
Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Pin Configuration and Functions
TPL910 Series
DFN-8 Package
Top View
OUT
1
OUT
2
8
IN
7
IN
Exposed
PAD
FB
3
6
NR
GND
4
5
EN
Pin Functions
NAME
PIN NUMBER
TYPE
EN
5
I
DESCRIPTION
Regulator enable pin. Drive EN high to turn on the regulator; drive EN low to turn off
the regulator. For automatic startup, connect EN to IN directly.
Output voltage feedback pin. Connect to an external resistor divider to adjust the
FB
3
I
output voltage. A 10-nF feed-forward capacitor from FB to OUT (as close as possible
to FB pin) is recommended to maximize regulator ac performance.
GND
4
–
IN
7, 8
I
NR
6
I
OUT
1, 2
O
Ground reference pin. Connect GND pin to PCB ground plane directly.
Input voltage pin. A 10-μF or larger ceramic capacitor from IN to ground (as close as
possible to IN pin) is required to reduce the jitter from previous-stage power supply.
Noise-reduction and soft-start pin. A 10-nF or larger capacitor from NR/SS to GND
(as close as possible to NR/SS pin) is recommended to maximize ac performance.
Regulated output voltage pin. A 10-μF or larger ceramic capacitor from OUT to ground
(as close as possible to OUT pin) is required to ensure regulator stability.
(1) Exposed PAD must be connected to a large-area ground plane to maximum the thermal performance.
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Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Specifications
Absolute Maximum Ratings
MIN
MAX
UNIT
IN, EN
–0.3
7
V
OUT
–0.3
VIN + 0.3
V
FB, NR
–0.3
3.6
V
TJ
Junction Temperature Range
–40
150
°C
TSTG
Storage Temperature Range
–65
150
°C
TL
Lead Temperature (Soldering 10 sec)
260
°C
(1) Stresses beyond the Absolute Maximum Ratings may permanently damage the device.
(2) All voltage values are with respect to GND.
ESD Ratings
Condition
Minimum Level
Unit
HBM
Human Body Model ESD
ANSI/ESDA/JEDEC JS-001
±4000
V
CDM
Charged Device Model ESD
ANSI/ESDA/JEDEC JS-002
±1500
V
Recommended Operating Conditions
MIN
TYP
MAX
UNIT
2.2
6.5
V
IN
Input voltage
EN
Enable voltage
0
6.5
V
OUT
Output voltage
0.8
5.2
V
OUT
Output current
0
1
A
CIN
Input capacitor
10
µF
COUT
Output capacitor
10
µF
CFF
Feed-forward capacitor
10
nF
CNR
NR capacitor
10
nF
PD
Power dissipation
1000
mW
TJ
Junction Temperature Range
–40
125
°C
Thermal Information
PACKAGE
θJA
θJC,bottom
UNIT
3×3 DFN-8
69.3
8.16
°C/W
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Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Electrical Characteristics
TJ = –40°C to +125°C (typical value at TJ = +25°C), VIN = VOUT(NOM) + 0.5 V or 2.2 V, whichever is greater; VEN = 2.2 V, IOUT = 1 mA, CIN = 10 µF, COUT
= 47 µF, CNR = 10 nF, CFF = open, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6.5
V
2.1
V
Supply Input Voltage and Current
VIN
UVLO
Input supply voltage range (1)
Input supply UVLO
2.2
VIN rising, RL = 1 kΩ
1.3
Hysteresis
200
IGND
GND pin current
ISD
Shutdown current
mV
VIN = 6.5 V, IOUT = 1 mA
15
30
mA
VIN = 6.5 V, IOUT = 1 A
15
30
mA
VIN = 6.5 V, VEN = Low
10
25
µA
Device Enable
VIH(EN)
EN pin high-level input voltage
Device enable
1.2
6.5
V
VIL(EN)
EN pin low-level input voltage
Device disable
0
0.4
V
IEN
EN pin current
VIN = 6.5 V, VEN = 0 V to 6.5 V
0.1
1
µA
0.8
0.81
V
0.1
1
µA
Regulated Output Voltage and Current
VFB
Feedback voltage
IFB
FB pin leakage current
VNR
NR/SS pin voltage
INR
NR/SS pin charging current
0.79
VIN = 6.5 V, stress VFB = 0.8V
0.8
VIN = 6.5 V, VNR = GND
VIN = VOUT(NOM) + 0.5 V or 2.5 V to 6 V, VOUT = 0.8 V
VOUT
Output accuracy
(2)
to 5.2 V, IOUT = 100 mA to 500 mA
VIN = VOUT(NOM) + 0.5 V or 2.2 V to 6.5 V, VOUT = 0.8
V to 5.2 V, IOUT = 100 mA to 1 A
ΔVOUT
Line regulation
Load regulation
7.2
2%
–3%
3%
VIN = VOUT(NOM) + 0.5 V or 2.2 V to 6.5 V, IOUT = 100
mA
IOUT = 100 mA to 1 A
mV/V
0.07
mV/A
VIN = VOUT(NOM) + 0.5 V or 2.2 V to 6.5 V, IOUT = 750
mA, VFB = GND or VSNS = GND
VIN = VOUT(NOM) + 0.5 V or 2.2 V to 6.5 V, IOUT = 1 A,
VFB = GND or VSNS = GND
ILIM
Output current limit
tSTR
Start-up time
VOUT forced at 0.9 × VOUT(NOM), VIN ≥ 3.3 V
VOUT(NOM) = 3.3 V, VOUT = 0% to 90% VOUT(NOM), RL =
3.3 kΩ, COUT = 10 μF, CNR = 100 nF
1.1.
µA
0.03
mA, VFB = GND or VSNS = GND
Dropout voltage (1)
9
–2%
VIN = VOUT(NOM) + 0.5 V or 2.2 V to 6.5 V, IOUT = 500
VDO
V
250
mV
350
mV
500
mV
1.4
A
13
ms
(1) Minimum VIN = VOUT(NOM) + VDO or 2.2 V, whichever is greater.
(2) Resistor tolerance is not included. Output accuracy is not tested at this condition: VOUT = 0.8 V, 4.5V ≤ VIN ≤ 6.5 V, and 750 mA ≤ IOUT ≤ 1 A, because
the power dissipation is out of package limitation.
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Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Electrical Characteristics (continued)
TJ = –40°C to +125°C (typical value at TJ = +25°C), VIN = VOUT(NOM) + 0.5 V or 2.2 V, whichever is greater; VEN = 2.2 V, IOUT = 1 mA, CIN = 10 µF, COUT
= 47 µF, CNR = 10 nF, CFF = open, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PSRR and Noise
PSRR
VN
Power supply ripple rejection
Output noise voltage
VIN = 5.5 V, VOUT = 5.2 V,
IOUT = 1 A
f = 1 kHz
65
dB
f = 100 kHz
50
dB
f = 1 MHz
30
dB
24
μVRMS
160
°C
20
°C
BW = 100 Hz to 100 kHz, VIN = 5.5 V, VOUT = 5.2 V,
IOUT = 1 A, CNR = 100 nF, CFF = 10 nF
Temperature Range
TSD
TJ
Thermal shutdown threshold
Temperature increasing
Hysteresis
Operating junction temperature
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–40
8 / 17
125
Rev.A.1
°C
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Typical Performance Characteristics
VIN = VOUT(NOM) + 0.5 V or 2.2 V, whichever is greater; VEN = 2.2 V, CIN = 10 µF, COUT = 47 µF, CNR = 10 nF, CFF = open, unless otherwise noted.
0.820
0.810
–40°C
25°C
–40°C
25°C
85°C
125°C
85°C
125°C
Output Voltage (V)
Output Voltage (V)
0.820
0.800
0.790
0.780
0.810
0.800
0.790
0.780
0
0.2
0.4
0.6
0.8
1
0
0.01
Load Current (A)
VOUT = 0.8 V
Figure 2 Load Regulation at Light Load
0.820
250
–40°C
25°C
85°C
0.810
−40°C
Dropout Voltage (mV)
Output Voltage (V)
0.03
VOUT = 0.8 V
Figure 1 Load Regulation
125°C
0.800
0.790
0.780
200
25°C
85°C
150
125°C
100
50
0
2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2 6.6
0
0.2
0.4
Supply Voltage (V)
0.6
0.8
1
Load Current (A)
VOUT = 0.8 V, IOUT = 5 mA
VOUT = 1.5 V
Figure 3 Line Regulation
Figure 4 Dropout Voltage vs. Load Current
1
Enable Threshold (V)
200
Dropout Voltage (mV)
0.02
Load Current (A)
150
100
50
0
0.8
0.6
0.4
VIH(EN)
0.2
VIL(EN)
0
2.2 2.6
3
3.4 3.8 4.2 4.6
5
5.4 5.8 6.2 6.6
Supply Voltage (V)
5
20
35
50
65
80
95 110 125
Ambient Temperature (°C)
Figure 5 Dropout Voltage vs. Supply Voltage
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-40 -25 -10
Figure 6 Enable Threshold vs. Temperature
9 / 17
Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Typical Performance Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V or 2.2 V, whichever is greater; VEN = 2.2 V, CIN = 10 µF, COUT = 47 µF, CNR = 10 nF, CFF = open, unless otherwise noted.
1
120
0.8
100
PSRR(dB)
Enable Threshold (V)
IOUT = 0.1 A
0.6
0.4
VIH(EN)
IOUT = 1 A
80
60
40
VIL(EN)
0.2
20
0
2.2 2.6
3
3.4 3.8 4.2 4.6
5
5.4 5.8 6.2 6.6
0
10
Supply Voltage (V)
100
1K
10K
100K
1M
10M
Frequency(Hz)
VIN = 5.5 V, VOUT = 5.2 V, COUT = 47µF // 10µF // 10µF, CNR/SS =100nF,
CFF = open
Figure 7 Enable Threshold vs. Supply Voltage
VIN = 2.2V to 6.5V, VOUT = 0.8V
Figure 8 PSRR
IOUT = 0.1A to 1A, VOUT = 0.8V
Figure 9 Line Transient
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Figure 10 Load Transient
10 / 17
Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Detailed Description
Overview
The TPL910 series products are 1-A high-current, 24-μVRMS low-noise, high-PSRR, high-accuracy linear regulators with only 500-mV
maximum ultra-low dropout voltage at 1-A load current. The TPL910 series products support both fixed output voltage ranges from
0.8 V to 5 V and adjustable output voltage ranges from 0.8 V to 5.2 V with external resistor divider.
Ultra-low noise, high PSRR, and high output current capability makes the TPL910 series products ideal power supply for noisesensitive applications, such as high-speed communication facilities, test and measurement devices, or high-definition imaging
equipment. Accurate output voltage tolerance, output remote sensing, excellent transient response, and adjustable soft-start control
ensures the TPL910 series products optimal power supply for the large-scale processors or digital loads, such as ASIC, FPGA, CPLD
and DSP.
Functional Block Diagram
IN
OUT
UVLO
Control
Curren t
Control
PSRR
Control
Regula tor
Control
Acti ve
Discha rge
Thermal
Control
EN
Ena ble
Control
+
EA
–
FB
VREF
INR /SS
GND
NR
Figure 11 Functional Block Diagram
Feature Description
Enable (EN)
The TPL910 series provide a device enable pin (EN) to enable or disable the device. Connect this pin to the GPIO of an external
digital logic control circuit to control the device. When the V EN voltage falls below VIL(EN), the LDO device turns off, and when the VEN
ramps above VIH(EN), the LDO device turns on.
Under-Voltage Lockout (IN and UVLO)
The TPL910 series use an under-voltage lockout circuit to keep the output shut off until the internal circuitry operates properly.
Voltage Regulation (OUT and FB)
The TPL910 series provide adjustable output voltage option. Using external resistors divider, the output voltage of TPL910 series is
determined by the value of the resistor R1 and R2 in Figure 12. Use Equation 1 to calculate the output voltage.
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Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
R1
VOUT = VFB 1 +
R2
(1)
Where the feedback voltage VFB is 0.8 V.
Table 1 provides a list of recommended resistor combinations to achieve the common output voltage values.
Table 1 External Resistor Combinations
Target Output Voltage (V)
External Resistors Divider
Calculated Output Voltage (V)
R1 (kΩ)
R2 (kΩ)
0.80
0
Open
0.800
0.81
2
160
0.810
0.82
4.02
160
0.820
0.83
6.04
160
0.830
0.84
8.06
160
0.840
0.85
10
160
0.850
0.86
12
160
0.860
0.87
12.4
143
0.869
0.88
12.4
124
0.880
0.89
12
107
0.890
0.90
12.4
100
0.899
0.95
12.4
66.5
0.949
1.00
12.4
49.9
0.999
1.10
12.4
33.2
1.099
1.20
12.4
24.9
1.198
1.50
12.4
14.3
1.494
1.80
12.4
10
1.792
1.90
12.1
8.87
1.891
2.50
12.4
5.9
2.481
2.85
12.1
4.75
2.838
3.00
12.1
4.42
2.990
3.30
11.8
3.74
3.324
3.60
12.1
3.48
3.582
4.50
11.8
2.55
4.502
5.00
12.4
2.37
4.986
Output Active Discharge
The TPL910 series integrate an output discharge path from OUT to GND. When the device is disabled, either EN or VIN is lower than
turn-on threshold, the output will actively discharge the output voltage through an internal resistor of several hundred ohms.
Do not rely on this active discharge circuit for discharging large output capacitors when the input voltage falls below the output voltage.
Reverse current flow through internal power MOSFET can permanently damage the device, and external current protection is
essential at this condition.
Over-Current Protection
The TPL910 series integrate an internal current limit that helps to protect the device during fault conditions. When the output is pulled
down below the target output voltage, over-current protection starts to work and limit the output current to a typical value of 1.4 A.
Under the over-current conditions, the internal junction temperature ramps up quickly. When the junction temperature is high enough,
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12 / 17
Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
it will cause the over temperature protection.
Over-Temperature Protection
The recommended operating junction temperature range is –40°C to 125°C. When the junction temperature is between 125°C and
the thermal shutdown (TSD) threshold, the regulator can still work well, but will reduce the device lifetime for long-term using.
The over-temperature protection works when the junction temperature exceeds the thermal shutdown (TSD) threshold, which turns
off the regulator immediately. Until when the device cools down and the junction temperature falls below the thermal shutdown
threshold minus thermal shutdown hysteresis, the regulator turns on again.
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Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Application and Implementation
NOTE
Information in the following applications sections is not part of the 3PEAK’s component specification and 3PEAK does
not warrant its accuracy or completeness. 3PEAK’s customers are responsible for determining suitability of
components for their purposes. Customers should validate and test their design implementation to confirm system
functionality.
Application Information
The TPL910 series products are 1-A high-current, 24-μVRMS low-noise, high-PSRR, high-accuracy linear regulators with only 500-mV
maximum ultra-low dropout voltage. The following application schematic shows a typical usage of the TPL910 series.
Typical Application
Adjustable Output Operation
Figure 12 shows the typical application schematic of the TPL910 series.
CIN
VIN
VIN
Digital I/O
or VIN
EN
VOUT
VOUT
R1
TPL910
CFF
COUT
FB
R2
NR
GND
CNR
Figure 12 Adjustable Output Operation
Input Capacitor and Output Capacitor
The TPL910 series is designed to be stable with low equivalent series resistance (ESR) ceramic capacitors at the input, output, and
noise-reduction pin (NR/SS). It is recommended to use ceramic capacitors with X7R-, X5R-, and COG-rated dielectric materials to
get good capacitive stability across temperature.
3PEAK recommends adding a 10 μF or greater capacitor with a 0.1 μF bypass capacitor in parallel at IN pin to keep the input voltage
stable. The voltage rating of the capacitors must be greater than the maximum input voltage.
To ensure loop stability, the TPL910 series requires an output capacitor with a minimum effective capacitance value of 3.3 μF. 3PEAK
recommends selecting a X7R-type 10-μF ceramic capacitor with low ESR over temperature.
Both input capacitors and output capacitors must be placed as close to the device pins as possible.
Power Dissipation
During normal operation, LDO junction temperature should not exceed 125°C. Using below equations to calculate the power
dissipation and estimate the junction temperature.
The power dissipation can be calculated using Equation 2.
PD = ( VIN − VOUT ) IOUT + VIN IGND
(2)
The junction temperature can be estimated using Equation 3. θJA is the junction-to-ambient thermal resistance.
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Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
TJ = TA + PD JA
(3)
Layout Requirements
•
Both input capacitors and output capacitors must be placed as close to the device pins as possible, and vias between
capacitors and device power pins must be avoid.
•
It is recommended to bypass the input pin to ground with a 0.1 μF bypass capacitor. The loop area formed by the bypass
capacitor connection, IN pin and the GND pin of the system must be as small as possible.
•
It is recommended to use wide trace lengths or thick copper weight to minimize I×R drop and heat dissipation.
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15 / 17
Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Tape and Reel Information
Order Number
Package
TPL910ADJ-DF6R
3×3 DFN-8
www.3peakic.com.cn
D1
W1
A0
B0
K0
P0
W0
Pin1
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
(mm)
Quadrant
330.0
17.6
3.4
3.4
1.1
8.0
12.0
Q2
16 / 17
Rev.A.1
TPL910 Series
1-A Output, High-PSRR, Low-Noise LDO Regulator
Package Outline Dimensions
3×3 DFN-8
Top View
Side View
/
Bottom View
3PEAK and the 3PEAK logo are registered trademarks of 3PEAK INCORPORATED. All
other trademarks are the property of their respective owners.
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17 / 17
Rev.A.1
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