SIG7792/7793
4-Channel 16/24-bit Sigma-Delta ADC with PGA and Reference
FEATURES
DESCRIPTION
Programmable Gain: 1/2/4/8/16/32/64/128
Data Rates: 4.17SPS to 890SPS
RMS Noise:
20nV at 4.17SPS (Gain=128)
63nV at 16.7SPS (Gain=128)
21.0 noise-free bits at 4.17SPS (Gain=1)
Offset Drift: 5nV/°C (Gain=128)
Gain Drift: 1ppm/°C
1.17V/2.5V Internal Reference with 4ppm/°C Drift
Integral Non-Linearity: 2ppm
4 Differential Inputs
Internal or External Clock
Simultaneous 50Hz/60Hz Rejection
Reference Detect
Programmable Current Sources
On-chip Bias Voltage Generator
Burnout Current Sources
Power Supply
AVDD: 2.7V to 5.25V
DVDD: 2.7V to 5.25V
Current: 470uA
Package: 16-lead TSSOP
The SIG7792/7793 are low noise, low drift, and high-resolution
16/24-bit analog-to-digital converter (ADC) with integrated
programmable gain amplifier (PGA) and low drift on-chip voltage
reference that offers high-accuracy measurement solutions for
bridge sensors, thermocouples, and resistance temperature
devices (RTD).
The device contains a low noise PGA with gains selected from
1, 2, 4, 8 16, 32, 64, and 128, a delta-sigma (Δ-Σ) modulator,
and digital filter. A low drift 1.17V or 2.5V reference is integrated
on chip and two matched excitation current sources (IEXCs) are
provided for accurate RTD measurement. The output data rate
from the device can be configured from 4.17SPS up to 890SPS.
50Hz/60Hz simultaneous rejection option is also provided.
Burnout current sources are provided at the analog inputs for
sensor connection diagnosis.
Offset and gain calibration registers are provided with calibration
command or direct register write to calibrate the ADC errors or
overall system errors. SPI-compatible interface is used for
device configuration.
The on-chip oscillator or an external clock can be used as the
clock source to the device.
The SIG7792/7793 are available in 16-lead TSSOP packages
and are fully specified over the -40°C to +125°C temperature
range.
APPLICATIONS
Weigh Scales
Strain Gauges
Temperature Measurement
Industrial Process Control
Pressure Sensors
Function Block Diagram
AVDD
REFIN1+/AIN3+
TSSOP-16
DVDD
REFIN1-/AIN3-
VBIAS
INTREF
SCLK
1
16
DIN
CLK
2
15
DOUT/DRDYn
CSn
3
14
DVDD
IOUT1/AIN4-
4
13
AVDD
AIN1+
5
12
GND
AIN1-
6
11
IOUT2/AIN4+
AIN2+
7
10
REF-/AIN3-
AIN2-
8
9
REF+/AIN3+
REF MUX
REFERENCE
DETECT
Gain=1,2,4,8,
16,32,64,128
AIN1+
AIN1AIN2+
MUX
AIN2-
PGA
BUF
ΔΣ ADC
Digital
Filter
Serial
Interface
And
Control
Logic
CSn
DIN
DOUT/DRDYn
SCLK
AIN4+/I2
AIN4-/I1
SIG7792/SIG7793
TEMP
Sensor
SIG7792: 16-BIT
SIG7793: 24-BIT
Internal
Oscillator
CLK
GND
May 2022
SIG7792/7793
TSSOP-16
Signal Micro Incorporated
http://www.signal-micro.cn
SIG7792/7793
PIN CONFIGURATION and DESCRIPTIONS
TOP VIEW (Not To Scale)
PIN
NO.
NAME
1
SCLK
2
CLK
SCLK
1
16
DIN
CLK
2
15
DOUT/DRDYn
CSn
3
14
DVDD
IOUT1/AIN4-
4
13
AVDD
AIN1+
5
12
GND
AIN1-
6
11
IOUT2/AIN4+
AIN2+
7
10
REF-/AIN3-
AIN2-
8
9
REF+/AIN3+
SIG7792/7793
TSSOP-16
FUNCTION
DESCRIPTION
Serial data clock.
Master clock input or internal clock output depending on MODE Register
bits CLK[1:0].
Serial chip select. Active low.
3
CSn
Digital Input
Digital
Input/Output
Digital Input
4
5
IOUT1/AIN4AIN1+
Analog Input
Analog Input
Internal excitation current output 1/Analog negative input channel 4.
Analog positive input channel 1.
6
7
AIN1AIN2+
Analog Input
Analog Input
Analog negative input channel 1.
Analog positive input channel 2.
8
9
AIN2REF+/AIN3+
Analog Input
Analog Input
Analog negative input channel 2.
Positive reference input/Analog positive input channel 3.
10
11
REF-/AIN3IOUT2/AIN4+
Analog Input
Analog Input
Negative reference input/Analog negative input channel 3.
Internal excitation current output 2/Analog positive input channel 4.
12
GND
Analog
13
AVDD
Analog
14
15
DVDD
DOUT/DRDYn
Digital
Digital Output
16
DIN
Digital Input
May 2022
Ground reference point.
Positive analog power supply. 2.7V to 5.25V relative to GND. AVDD is
independent of DVDD.
Digital power supply, 2.7V to 5.25V. DVDD is independent of AVDD.
Serial data output and data ready indicator.
Serial data input.
Signal Micro Incorporated
http://www.signal-micro.cn
2
SIG7792/7793
PACKAGE/ORDERING INFORMATION
MODEL
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE
RANGE
ORDERING NUMBER
PACKING OPTION
SIG7792
TSSOP-16
-40°C to +125°C
SIG7792-ITSP16-RL
Reel, 5000
SIG7793
TSSOP-16
-40°C to +125°C
SIG7793-ITSP16-RL
Reel, 5000
SPECIFICATIONS
Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted.(1)
AVDD to GND
Voltage
Current
Temperature
MIN
MAX
UNIT
–0.3
6.5
V
DVDD to GND
–0.3
6.5
V
Analog input
–0.3
VAVDD + 0.3
V
Digital input
–0.3
VDVDD + 0.3
V
Input current
–10
10
mA
Junction (TJ)
–50
150
°C
Storage (Tstg)
-60
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD Ratings
SYMBOL
PARAMTER
CONDITION
VALUE
UNIT
HBM
Human-body Model
CDM
Charged-device model
ANSI/ESDA/JEDEC JS-001
±6000
V
JEDEC EIA/JS-002-2022
±2000
V
This integrated circuit can be damaged by ESD. Signal Micro recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from
subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications.
May 2022
Signal Micro Incorporated
http://www.signal-micro.cn
3
SIG7792/7793
Electrical Characteristics
Minimum/Maximum specifications apply from -40˚C to +125˚C. Typical specifications are at +25˚C. All specification are at
VAVDD=5V, VDVDD=3.3V, VGND =0V, VREF=2.5V, fCLK=1.024MHz, data rate=16.7SPS, and PGA Gain=1, unless otherwise noted.
PARAMETER
TEST CONDITION
OR NOTES
MIN(1)
TYP
MAX(1)
UNITS
V
ANALOG INPUTS
Differential Input Voltage
VIN = VINP – VINN
–VREF/Gain
+VREF/Gain
Absolute Input Voltage
Buffer Off
Buffer On
– 0.05
+ 0.2
Common Mode Input Range
Buffer On
0.2 + |VINMAX|·Gain/2
VAVDD + 0.05
VAVDD – 0.2
VAVDD – 0.2 –
|VINMAX|·Gain/2
Absolute Input Current
Buffer off
Buffer On
±10
±1
V
V
nA
nA
SYSTEM PERFORMANCE
PGA Gain
Resolution
16
Buffer Off
±10
ppm
±2
ppm
Chop Off
±400/Gain
μV
Chop On
Gain Error(2)
All PGA gains
Gain Drift vs. Temperature
All PGA gains
fIN = 50/60Hz, ±2%,
data rate=16.7SPS
fIN = 50Hz,
data rate = 470SPS
AVDD
Power Supply Rejection (PSRR)
SPS
Buffer On
All PGA gains
Common Mode Rejection
(CMRR)
Bits
890
See Noise Table
Offset Drift vs. Temperature
Normal Mode Rejection (NMRR)
Bits
4.17
Noise
Offset Error
V/V
24
SIG7792
Data Rate
Integral Nonlinearity (INL)
1/2/4/8/16/32/64/128
SIG7793
DVDD
EXTERNAL REFERENCE INPUTs
Differential Reference Voltage
VREF = VREFP – VREFN
(VREF)
Absolute Negative Reference
Voltage (VREFN)
Absolute Positive Reference
Voltage (VREFP)
Average Voltage Input Current
±1
μV
±400/Gain ± 2
nV/°C
-0.05
±0.005
0.05
%
-3
±1
+3
ppm/°C
See Table 17
dB
100
120
dB
85
105
dB
90
110
dB
0.5
2.5
VAVDD + 0.1
V
– 0.05
VREFP – 0.5
V
VREFN + 0.5
VAVDD + 0.05
V
±1
uA
INTERNAL VOLTAGE REFERENCE
Reference Voltage
1.17/2.5
V
Initial Accuracy(2)
-0.05%
±0.005%
+0.05%
Temperature Drift
-20
±4
+20
ppm/°C
EXCITATION CURRENT SOURCES (IEXC1 and IEXC2)
Output Current
Compliance Voltage(2)
Accuracy
Current Mismatch
IEXC1=IEXC2
May 2022
10/50/100/210/250/500/1000
uA
IEXC = 50uA
-2%
±1%
+2%
IEXC = 10uA
-3.0%
±0.60%
+3.0%
IEXC = 50uA
-1.5%
±0.25%
+1.5%
Signal Micro Incorporated
http://www.signal-micro.cn
V
4
SIG7792/7793
IEXC = 100uA
-1.2%
±0.20%
+1.2%
IEXC = 210uA, 250uA
-1.0%
±0.18%
+1.0%
IEXC = 500uA
-0.8%
±0.12%
+0.8%
IEXC = 1000uA
-0.6%
±0.1%
+0.6%
Temperature Drift
-90
±20
+90
ppm/°C
Temperature Drift Mismatch
-30
±5
+30
ppm/°C
Burnout Current Sources
Current Setting
500
nA
ADC CLOCK
External Clock
Internal Oscillator
Frequency Range
0.5
Duty Cycle
40%
Nominal Frequency
1.024
1.1
60%
1.024
Accuracy
–3%
High-level Output Voltage (VOH)
IOH = 4mA
0.8·VDVDD
Low-level Output Voltage (VOL)
IOL = –4mA
MHz
MHz
±0.5%
3%
DIGITAL INPUT/OUTPUT
High-level Input Voltage (VIH)
0.7·VDVDD
Low-level Input Voltage (VIL)
0
Input Hysteresis
V
0.2·VDVDD
V
VDVDD
V
0.3·VDVDD
V
±10
μA
0.5
Input Leakage
V
POWER SUPPLY
AVDD Voltage (VAVDD)
2.7
5.25
V
DVDD Voltage (VDVDD)
2.7
5.25
V
AVDD Current (IAVDD)
DVDD Current (IDVDD)
Total Power Dissipation
Buffer Off
150
200
uA
Buffer On
350
450
uA
200
μA
Sleep Mode
1
Active Mode
120
Sleep Mode
20
μA
μA
Buffer Off
1.15
mW
Buffer On
2.15
mW
Sleep Mode
0.10
mW
TEMPERATURE RANGE
Specified temperature range
–40
125
°C
Operating temperature range
–50
125
°C
Storage temperature range
–60
150
°C
(1) Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
(2) MIN and MAX values listed for gain error are for +25˚C room temperature only.
May 2022
Signal Micro Incorporated
http://www.signal-micro.cn
5
SIG7792/7793
Timing Requirements: Serial Interface
Over the operating ambient temperature range and DVDD = 2.7V to 5.25V, unless otherwise noted.
t7
CSn
t6
t1
t5
B7
DOUT
B6
B4
B5
B3
B2
B1
B0
t2
t8
t3
SCLK
t4
t9
t10
DIN
B7
B6
B5
B4
B3
B2
B0
B1
Figure 1. Serial Interface Timing Requirements
SYMBOL
t1
t2
t3
t4
DESCRIPTION
CSn falling edge to DOUT/DRDYn driven: propagation delay(1)
SCLK falling edge to valid DOUT/DRDYn: propagation delay(1)
SCLK low pulse width
MIN
SCLK high pulse width
100
SCLK period
MAX
50
50
100
200
UNIT
ns
ns
ns
ns
106
ns
40
ns
t5
CSn rising edge to DOUT high impedance: propagation delay
t6
Last SCLK rising edge to CSn rising edge: delay time
50
ns
t7
CSn high pulse width
50
ns
50
ns
time(2)
t8
CSn falling edge to first SCLK falling edge: setup
t9
Valid DIN to SCLK rising edge: setup time
50
ns
t10
Valid DIN to SCLK rising edge: hold time
25
ns
(1) DOUT load = 20pF || 100k Ω to GND.
(2) CSn can be tied low.
May 2022
Signal Micro Incorporated
http://www.signal-micro.cn
6
SIG7792/7793
NOISE PERFORMANCE
The noise performance of the ADC is affected by PGA gain, data rate, and digital filter setting. The following tables
show the rms noise and peak-to-peak noise for different data rate with chop enabled. The effective number of bits
(ENOB) and noise-free bits are also listed according to Equation (1) and Equation (2):
ENOB= log 2 (2×VREF ⁄Gain⁄VRMS )
(1)
Noise Free Bits= log 2 �2×VREF ⁄Gain⁄Vp-p �
(2)
The noise data listed in the table are typical and are generated from continuous ADC readings with differential input
voltage of 0 V. With chop disabled, the noise increases by 30%.
External Reference
Table 1. ADC Noise in µVRMS (µVPP) at TA = 25°C, VAVDD = 5 V, VREF = 2.5 V, Chop Enabled
FS[3:0]
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Data Rate
(SPS)
4.17
6.25
8.33
10
12.5
16.7
16.7
19.6
33.2
39
50
62
123
242
470
890
PGA GAIN
1
0.510(2.10)
0.658(2.72)
0.806(3.33)
0.931(3.84)
1.14(4.71)
1.61(6.66)
1.56(6.56)
1.87(9.24)
2.55(13.7)
2.39(10.4)
2.70(15.2)
3.65(15.8)
5.48(29.5)
8.90(67.9)
22.7(127)
236(1360)
2
0.326(1.46)
0.420(1.89)
0.515(2.31)
0.595(2.67)
0.728(3.27)
1.03(4.62)
1.00(4.32)
1.06(6.26)
1.36(6.56)
1.75(7.60)
2.11(10.4)
2.20(12.1)
3.28(19.1)
4.82(30.2)
11.7(87.5)
112(746)
4
0.170(0.872)
0.220(1.13)
0.269(1.38)
0.311(1.59)
0.380(1.95)
0.538(2.76)
0.522(2.46)
0.732(2.98)
0.764(4.47)
0.863(3.80)
1.06(4.69)
1.27(5.81)
1.49(8.12)
2.37(14.3)
5.98(37.9)
58.5(395)
8
0.084(0.412)
0.109(0.532)
0.133(0.652)
0.154(0.753)
0.188(0.922)
0.266(1.30)
0.245(1.16)
0.334(1.34)
0.412(2.20)
0.468(2.35)
0.664(3.32)
0.729(4.17)
0.905(4.69)
1.48(7.49)
3.14(19.0)
28.2(266)
16
0.057(0.236)
0.073(0.304)
0.090(0.373)
0.103(0.430)
0.127(0.527)
0.179(0.745)
0.177(0.838)
0.193(1.04)
0.242(1.27)
0.268(1.38)
0.354(1.70)
0.473(1.99)
0.564(3.73)
0.721(3.93)
1.55(8.68)
13.6(103)
32
0.036(0.165)
0.047(0.213)
0.057(0.261)
0.066(0.301)
0.081(0.368)
0.114(0.521)
0.111(0.587)
0.133(0.522)
0.208(1.04)
0.204(0.903)
0.265(1.14)
0.243(1.09)
0.355(1.97)
0.488(3.10)
0.943(5.62)
7.42(49.5)
64
0.027(0.115)
0.035(0.148)
0.043(0.182)
0.049(0.210)
0.060(0.257)
0.085(0.363)
0.081(0.372)
0.091(0.405)
0.108(0.536)
0.116(0.563)
0.157(0.722)
0.191(1.02)
0.261(1.36)
0.358(1.95)
0.583(3.86)
3.60(24.7)
128
0.020(0.095)
0.026(0.122)
0.032(0.150)
0.036(0.173)
0.045(0.212)
0.063(0.300)
0.063(0.291)
0.072(0.321)
0.093(0.449)
0.096(0.403)
0.120(0.538)
0.168(0.687)
0.195(1.18)
0.287(1.59)
0.421(2.55)
1.86(12.8)
Table 2. ADC ENOB (Noise Free Bits) at TA = 25°C, VAVDD = 5 V, VREF = 2.5 V, Chop Enabled
FS[3:0]
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
May 2022
Data Rate
(SPS)
4.17
6.25
8.33
10
12.5
16.7
16.7
19.6
33.2
39
50
62
123
242
470
890
1
23.2(21.0)
22.8(20.6)
22.5(20.4)
22.3(20.1)
22.0(19.9)
21.5(19.4)
21.6(19.4)
21.2(19.2)
21.1(18.8)
20.9(18.8)
20.4(18.1)
20.5(18.4)
19.8(17.3)
19.3(16.5)
17.7(15.0)
14.4(11.5)
2
22.9(20.7)
22.5(20.3)
22.2(20.0)
22.0(19.8)
21.7(19.5)
21.2(19.0)
21.3(19.1)
21.2(18.6)
20.8(18.5)
20.4(18.3)
20.2(17.9)
20.1(17.7)
19.5(17.0)
19.0(16.3)
17.7(14.8)
14.4(11.7)
4
22.8(20.5)
22.4(20.1)
22.1(19.8)
21.9(19.6)
21.6(19.3)
21.1(18.8)
21.2(19.0)
20.7(18.7)
20.6(18.1)
20.5(18.3)
20.2(18.0)
19.9(17.7)
19.7(17.2)
19.0(16.4)
17.7(15.0)
14.4(11.6)
PGA GAIN
8
16
22.8(20.5)
22.4(20.3)
22.5(20.2)
22.0(20.0)
22.2(19.9)
21.7(19.7)
22.0(19.7)
21.5(19.5)
21.7(19.4)
21.2(19.2)
21.2(18.9)
20.7(18.7)
21.3(19.0)
20.8(18.5)
20.8(18.8)
20.6(18.2)
20.5(18.1)
20.3(17.9)
20.3(18.0)
20.2(17.8)
19.8(17.5)
19.8(17.5)
19.7(17.2)
19.3(17.3)
19.4(17.0)
19.1(16.4)
18.7(16.3)
18.7(16.3)
17.6(15.0)
17.6(15.1)
14.4(11.2)
14.5(11.6)
Signal Micro Incorporated
http://www.signal-micro.cn
32
22.0(19.9)
21.7(19.5)
21.4(19.2)
21.2(19.0)
20.9(18.7)
20.4(18.2)
20.4(18.0)
20.2(18.2)
19.5(17.2)
19.5(17.4)
19.2(17.1)
19.3(17.1)
18.7(16.3)
18.3(15.6)
17.3(14.8)
14.4(11.6)
64
21.5(19.4)
21.1(19.0)
20.8(18.7)
20.6(18.5)
20.3(18.2)
19.8(17.7)
19.9(17.7)
19.7(17.6)
19.5(17.2)
19.4(17.1)
18.9(16.7)
18.6(16.2)
18.2(15.8)
17.7(15.3)
17.0(14.3)
14.4(11.6)
128
20.9(18.7)
20.5(18.3)
20.2(18.0)
20.0(17.8)
19.7(17.5)
19.2(17.0)
19.2(17.0)
19.0(16.9)
18.7(16.4)
18.6(16.6)
18.3(16.1)
17.8(15.8)
17.6(15.0)
17.1(14.6)
16.5(13.9)
14.4(11.6)
7
SIG7792/7793
Internal Reference
Table 3. ADC Noise in µVRMS (µVPP) at TA = 25°C, VAVDD = 5 V, Internal 1.17V Reference, Chop Enabled
FS[3:0]
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Data Rate
(SPS)
4.17
6.25
8.33
10
12.5
16.7
16.7
19.6
33.2
39
50
62
123
242
470
890
PGA GAIN
1
1.05(4.23)
1.36(5.47)
1.66(6.70)
1.92(7.73)
2.35(9.47)
3.33(13.4)
3.01(13.5)
2.90(12.1)
3.94(16.9)
4.24(18.8)
5.62(23.7)
4.98(28.0)
7.95(42.7)
11.8(69.2)
18.9(125)
111(735)
2
0.484(2.18)
0.625(2.81)
0.766(3.44)
0.884(3.98)
1.08(4.87)
1.53(6.89)
1.48(6.87)
1.59(7.60)
2.12(9.28)
2.31(9.83)
2.77(11.9)
2.95(13.3)
5.12(26.1)
6.21(32.5)
10.2(63.4)
55.1(390)
4
0.250(1.13)
0.323(1.46)
0.396(1.79)
0.457(2.06)
0.560(2.53)
0.792(3.58)
0.752(3.56)
0.847(4.18)
1.19(5.26)
1.40(7.29)
1.60(8.19)
1.42(7.67)
2.55(12.0)
3.22(17.8)
5.13(31.9)
25.7(163)
8
0.117(0.546)
0.151(0.705)
0.185(0.863)
0.213(0.997)
0.261(1.22)
0.369(1.73)
0.394(1.69)
0.420(1.90)
0.560(2.48)
0.678(2.91)
0.814(3.85)
0.987(4.64)
1.09(5.46)
1.63(8.39)
2.69(14.9)
13.0(78.7)
16
0.079(0.328)
0.102(0.423)
0.125(0.519)
0.144(0.599)
0.176(0.733)
0.249(1.04)
0.246(1.09)
0.303(1.20)
0.367(1.63)
0.361(1.56)
0.440(2.22)
0.468(2.00)
0.777(4.44)
1.02(5.99)
1.43(8.47)
6.74(50.9)
32
0.042(0.190)
0.054(0.245)
0.067(0.301)
0.077(0.347)
0.094(0.425)
0.133(0.601)
0.129(0.591)
0.156(0.658)
0.175(0.752)
0.200(0.859)
0.308(1.61)
0.309(1.72)
0.420(2.36)
0.596(4.33)
0.929(5.30)
3.49(20.7)
64
0.025(0.113)
0.032(0.145)
0.039(0.178)
0.045(0.206)
0.055(0.252)
0.078(0.356)
0.078(0.353)
0.091(0.431)
0.122(0.540)
0.141(0.671)
0.174(0.891)
0.192(0.989)
0.292(1.56)
0.426(2.20)
0.565(3.20)
1.71(10.5)
128
0.022(0.099)
0.028(0.127)
0.034(0.156)
0.039(0.180)
0.048(0.221)
0.068(0.312)
0.067(0.305)
0.078(0.372)
0.091(0.369)
0.113(0.535)
0.147(0.659)
0.146(0.745)
0.181(1.11)
0.293(1.75)
0.389(2.31)
0.979(6.28)
Table 4. ADC ENOB (Noise Free Bits) at TA = 25°C, VAVDD = 5 V, Internal 1.17V Reference, Chop Enabled
FS[3:0]
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
May 2022
Data Rate
(SPS)
4.17
6.25
8.33
10
12.5
16.7
16.7
19.6
33.2
39
50
62
123
242
470
890
1
21.1(19.1)
20.7(18.7)
20.4(18.4)
20.2(18.2)
19.9(17.9)
19.4(17.4)
19.6(17.4)
19.6(17.6)
19.2(17.1)
19.1(16.9)
18.7(16.6)
18.8(16.3)
18.2(15.7)
17.6(15.0)
16.9(14.2)
14.4(11.6)
2
21.2(19.0)
20.8(18.7)
20.5(18.4)
20.3(18.2)
20.0(17.9)
19.5(17.4)
19.6(17.4)
19.5(17.2)
19.1(16.9)
19.0(16.9)
18.7(16.6)
18.6(16.4)
17.8(15.5)
17.5(15.1)
16.8(14.2)
14.4(11.5)
4
21.2(19.0)
20.8(18.6)
20.5(18.3)
20.3(18.1)
20.0(17.8)
19.5(17.3)
19.6(17.3)
19.4(17.1)
18.9(16.8)
18.7(16.3)
18.5(16.1)
18.6(16.2)
17.8(15.6)
17.5(15.0)
16.8(14.2)
14.5(11.8)
PGA GAIN
8
16
21.3(19.0)
20.8(18.8)
20.9(18.7)
20.5(18.4)
20.6(18.4)
20.2(18.1)
20.4(18.2)
20.0(17.9)
20.1(17.9)
19.7(17.6)
19.6(17.4)
19.2(17.1)
19.5(17.4)
19.2(17.0)
19.4(17.2)
18.9(16.9)
19.0(16.9)
18.6(16.5)
18.7(16.6)
18.6(16.5)
18.5(16.2)
18.3(16.0)
18.2(15.9)
18.3(16.2)
18.0(15.7)
17.5(15.0)
17.5(15.1)
17.1(14.6)
16.7(14.3)
16.6(14.1)
14.5(11.9)
14.4(11.5)
Signal Micro Incorporated
http://www.signal-micro.cn
32
20.7(18.6)
20.4(18.2)
20.1(17.9)
19.9(17.7)
19.6(17.4)
19.1(16.9)
19.1(16.9)
18.8(16.8)
18.7(16.6)
18.5(16.4)
17.9(15.5)
17.9(15.4)
17.4(14.9)
16.9(14.0)
16.3(13.8)
14.4(11.8)
64
20.5(18.3)
20.1(17.9)
19.8(17.6)
19.6(17.4)
19.3(17.1)
18.8(16.6)
18.8(16.7)
18.6(16.4)
18.2(16.0)
18.0(15.7)
17.7(15.3)
17.5(15.2)
16.9(14.5)
16.4(14.0)
16.0(13.5)
14.4(11.8)
128
19.7(17.5)
19.3(17.1)
19.0(16.8)
18.8(16.6)
18.5(16.3)
18.0(15.8)
18.1(15.9)
17.8(15.6)
17.6(15.6)
17.3(15.1)
16.9(14.8)
16.9(14.6)
16.6(14.0)
15.9(13.4)
15.5(12.9)
14.2(11.5)
8
SIG7792/7793
ON-CHIP REGISTER MAPS
There are total eight registers inside the device which is 8-bit, 16-bit, or 24-bit wide. These registers are used to
configure and control the ADC to the desired mode of operation. These registers can be accessed through the SPIcompatible serial interface by using register read and write commands. At power-on or reset, the registers default to
their initial settings, as shown in the Reset Value column of Table 5.
Table 5. SIG7793/SIG7792 register map
ADDR.
NAME
DIR.
RESET
VALUE
BIT 7
3’b000
STATUS
R
80
DRDYn
3’b001
MODE
R/W
000A
3’b010
CONFIG
R/W
0710
3’b011
DATA
R
000000
/(0000) (1)
3’b100
3’b101
ID
IO
R
R/W
XA/(XB)(1)
00
3’b110
OFFSET
R/W
800000
/(8000)(1)
BIT 6
ERR
MD[2:0]
CLK[1:0]
VBIAS[1:0]
REFSEL[1:0]
x
IEXCEN[2]
x
0
BIT 5
BIT 4
BIT 3
NOREF
BIT 2
0
24-bit
IEXC_PAIR
0
0
0
CHOPn
BURN
FORMAT
0
REFDET
BUF
0
DATA[23:16] (SIG7793 only)
DATA[15:8]
DATA[7:0]
x
x
1
0
0
0
IEXCDIR[1:0]
OFFSET[23:16] (SIG7793 only)
BIT 1
CHD[2:0]
0
FS[3:0]
PGA[2:0]
CH[2:0]
1
BIT 0
FAST_ST
1/0
IEXCEN[1:0]
OFFSET[15:8]
OFFSET[7:0]
GAIN[23:16] (SIG7793 only)
3’b111
GAIN
R/W
555555
/(5555)(1)
GAIN[15:8]
GAIN[7:0]
(1) The values in bracket are the default reset value for SIG7792.
STATUS Register
Table 6. STATUS Register (Address = 3’b000)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
DRDYn
ERR
NOREF
0
24-bit
BIT 2
BIT 1
BIT 0
CHD[2:0]
Power-On/Reset Value = 0x80(SIG7792)/ 0x88(SIG7793)
Bits
Bit Name
Access
Reset
Description
7
DRDYn
R
1’b1
ADC Ready Bit: This bit is cleared when new data is written to the
ADC data register. It is set automatically after the ADC data register is
read. In addition to this bit, DOUT/DRDYn pin can also be used as an
alternative to monitor the update of new ADC data.
6
ERR
R
1’b0
ADC Error Bit. This bit is written at the same time as new data
update. Error sources include input overrange, input underrange, or
lower than expected reference voltage.
5
NOREF
R
1’b0
No External Reference Bit: The function of this bit is only enabled by
setting the REFDET bit in the CONFIG Register to 1. While the
REFDET bit is 1 and the selected reference voltage is below a
specified threshold, which is about 0.4V, this bit is set and conversion
results are clamped to all 1s.
4
RESERVED
R
1’b0
Reserved
3
24-bit
R
1’b0(7792)
1’b1(7793)
24-Bit Device Indicator. This bit indicates whether this device is 16bit (SIG7792) or 24-bit (SIG7793).
CHD[2:0]
R
3’b000
Data Channel Number: These bits indicate the corresponding
channel to the ADC data in data register (see Table 9).
2:0
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SIG7792/7793
MODE Register
Table 7. MODE Register (Address = 3’b001)
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
IEXC_PAIR
0
0
FAST_ST
0
CHOPn
MD[2:0]
CLK[1:0]
FS[3:0]
Power-On/Reset Value = 0x000A
Bits
Bit Name
Access
Reset
Description
15:13
MD[2:0]
R/W
3’b000
Mode Select Bits: These bits select the operating mode of the device.
000: Continuous conversion mode. (default)
001: Single conversion mode. ADC first wakeup if in idle or sleep
mode; resets the filter to perform one conversion; and enters sleep
mode. The conversion result remains in the data register with
DOUT/DRDYn as low.
010: Idle mode. The digital filter is in reset state with ADC free running.
011: Sleep mode. Most of circuitry is turned off to save the power.
100: Internal zero-scale calibration.
101: Internal full-scale calibration.
110: System zero-scale calibration.
111: System full-scale calibration.
For each above calibration mode, DOUT/DRDYn goes high when the
calibration is initiated and returns low when the calibration is complete.
The ADC is automatically placed in idle mode after the calibration. The
measured offset/full-scale coefficient is placed in the offset/full-scale
register of the selected channel.
12
RESERVED
R/W
1’b0
Reserved
Always write 1’b0
11
IEXC_PAIR
R/W
1’b0
IEXC PAIR Enable Bit: Set this bit while both IEXC1 and IEXC2 are
used as a pair to improve the IEXC matching and measurement
accuracy.
0: Disabled (default)
1: Enabled
10, 9
RESERVED
R/W
2’b00
Reserved
Always write 2’b00
8
FAST_ST
R/W
1’b0
Fast Startup Bit: When FAST_ST is set, the internal bandgap stays
on during sleep mode for fast startup if internal reference is selected or
excitation current sources are used.
7:6
CLK[1:0]
R/W
2’b10
Clock Select Bits: This bits select the clock source for SYSCLK.
00: Internal 1.024MHz clock with CLK tristated. (default)
01: Internal 1.024MHz clock with its output on CLK pin.
10: External clock applied to the CLK pin.
11: External clock applied to the CLK pin.
5
RESERVED
R/W
1’b0
Reserved
Always write 1’b0
4
CHOPn
R/W
1’b0
Chop Disable Bit: When chop is enabled with bit clear to logic 0, the
offset and offset drift of the ADC are dramatically improved with
settling time doubled. All output data are fully settled data. For default
data rate settling of 16.7SPS, the conversion time is 60ms for all
output data with chop disabled. If chop is enabled, the conversion time
is 120ms for the first data and 60ms thereafter.
3:0
FS[3:0]
R/W
4’b1010
Data Rate Configuration: Selects the ADC data rate.
0000: 890SPS
0001: 470SPS
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SIG7792/7793
0010: 242SPS
0011: 123SPS
0100: 62SPS
0101: 50SPS
0110: 39SPS
0111: 33.2SPS
1000: 19.6SPS
1001: 16.7SPS
1010: 16.7SPS (default)
1011: 12.5SPS
1100: 10SPS
1101: 8.33SPS
1110: 6.25SPS
1111: 4.17SPS
CONFIG Register
Table 8. CONFIG Register (Address = 3’b010)
BIT 15
BIT 14
BIT 7
BIT 13
BIT 6
BIT 12
BIT 11
BIT10
BIT 2
BIT 9
BIT 8
BIT 1
BIT 0
BIT 5
BIT 4
BIT 3
VBIAS[1:0]
BURN
FORMAT
0
PGA[2:0]
REFSEL[1:0]
REFDET
BUF
0
CH[2:0]
Power-On/Reset Value = 0x0710
Bits
Bit Name
Access
Reset
Description
15:14
VBIAS[1:0]
R/W
2’b00
Bias Voltage Generator Enable Bits: The negative terminal of the
analog inputs can be biased at the level of middle analog supply
AVDD/2.
00: Bias voltage generator disabled
01: Bias voltage connected to AIN110: Bias voltage connected to AIN211: Bias voltage connected to AIN3-
13
BURN
R/W
1’b0
Burnout Enable Bit: When this bit is enabled, a pair of 500nA current
sources are applied to analog inputs to source positive input and sink
negative input.
12
FORMAT
R/W
1’b0
Data Format Bit: This bit sets the ADC data format.
0: Bipolar mode (default)
1: Unipolar mode
11
RESERVED
R/W
1’b0
Reserved
Always write 1’b0
10:8
PGA[2:0]
R/W
3’b111
PGA Gain Configuration: Selects the PGA gain. If PGA gain is set to
other than 1, the BUF bit setting is ignored with buffer always enabled.
000: Gain=1
001: Gain=2
010: Gain=4
011: Gain=8
100: Gain=16
101: Gain=32
110: Gain=64
111: Gain=128 (default)
7:6
REFSEL[1:0]
R/W
2’b00
Reference Select Bits: Select the reference source for the ADC.
00: REF+, REF- (default)
01: Reserved
10: 1.17V internal reference
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11
SIG7792/7793
11: 2.5V internal reference
5
REFDET
R/W
1’b0
Reference Detection Enable Bit: When this bit is enabled, the
NOREF bit in the STATUS register indicates when the reference input
voltage is less than specified threshold, which is about 0.4V.
4
BUF
R/W
1’b1
Buffer Enable Bit: When this bit is set, analog input is buffered.
Otherwise the input buffer is bypassed. The buffer can only be
disabled when the gin equals 1 or 2. For higher gains, the buffer is
automatically enabled.
3
RESERVED
R/W
1’b0
Reserved
Always write 1’b0
CH[2:0]
R/W
3’b000
Channel Select Bits: This bits select which channels are enabled for
ADC conversion (see Table 9). When ADC finishes the conversion and
places the data into data register with corresponding channel
information in STATUS register.
2:0
Table 9. Channel Selection
CHD[2:0]
(1)
(2)
Positive Input AIN+
Negative Input AIN-
Status Register Bits
CHD[2:0]
Calibration Register Pair
000
AIN1+
AIN1000
0
001
AIN2+
AIN2001
1
010
AIN3+
AIN3010
2
011
AIN1AIN1011
0
100
AIN4+
AIN4100
3
101
Reserved
101
110
Temperature Sensor(1)
110
Default Reset Values
111
AVDD Monitor(2)
111
Default Reset Values
For temperature sensor measurement, PGA gain is internally forced to 1 with buffer on and internal 1.17V reference is used disregarding user
register configuration.
For AVDD monitor measurement, the AVDD is internally attenuated by 6, PGA gain is forced to 1 with buffer on and internal 1.17V reference is
used disregarding user register configuration.
DATA Register
This register is 16 bits wide for SIG7792 and 24 bits wide for SIG7793.
Table 10. DATA Register (Address = 3’b011)
BIT 23
BIT 22
BIT 21
BIT 20
BIT 19
BIT18
BIT 17
BIT 16
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DATA[23]
DATA[22]
DATA[21]
DATA[20]
DATA[19]
DATA[18]
DATA[17]
DATA[16]
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
Power-On/Reset Value = 0x0000(SIG7792)/0x000000(SIG7793)
Bits
Bit Name
Access
Reset
Description
23:0
DATA[23:0]
R
0x000000
Data Bits: The 16-bit word for SIG7792 or 24-bit word for SIG7793 is
signed number in 2’s complement format. See Data Format section
for more information.
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SIG7792/7793
ID Register
Table 11. ID Register (Address = 3’b100)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
x
x
x
x
1
0
1
0/1
Power-On/Reset Value = 0xXA(SIG7792)/0xXB(SIG7793)
Bits
Bit Name
Access
Reset
Description
7:0
ID
R
8’bxxxx101x
ID Bits: Read only.
IO Register
Table 12. IO Register (Address = 3’b101)
BIT 7
BIT 6
BIT 5
BIT 4
IEXCEN[2]
0
0
0
BIT 3
BIT 2
IEXCDIR[1:0]
BIT 1
BIT 0
IEXCEN[1:0]
Power-On/Reset Value = 0x00
Bits
Bit Name
Access
Reset
Description
7
IEXCEN[2]
R/W
1’b0
IEXC Current Bit: This bit works together with IEXCEN[1:0] to select
the value of the excitation current sources applied to the analog input
pins.
6, 5, 4
RESERVED
R/W
3’b000
Reserved
Always write 3’b000
3:2
IEXCDIR[1:0]
R/W
2’b00
Direction of Current Sources Select Bits:
00: Current source IEXC1 connected to Pin IOUT1, Current source
IEXC2 connected to Pin IOUT2.
01: Current source IEXC1 connected to Pin IOUT2, Current source
IEXC2 connected to Pin IOUT1.
10: Both current source IEXC1 and IEXC2 connected to Pin IOUT1.
11: Both current source IEXC1 and IEXC2 connected to Pin IOUT2.
1:0
IEXCEN[1:0]
R/W
2’b00
IEXC Current Bits: Combined with IEXCEN[2], these three bits select
the value of the excitation current sources applied to the analog input
pins.
000: Off (default)
001: 10µA
010: 210µA
011: 1000µA
100: 50µA
101: 100µA
110: 250µA
111: 500µA
May 2022
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SIG7792/7793
OFFSET Register
The device has four OFFSET registers, each channel has a dedicated OFFSET register (see Table 9). This register
is 16 bits wide for SIG7792 and 24 bits wide for SIG7793. OFFSET register read is allowed anytime, but writing to
OFFSET register is only allowed while the device is in idle or sleep mode.
Table 13. OFFSET Register (Address = 3’b110)
BIT 23
BIT 22
BIT 21
BIT 20
BIT 19
BIT18
BIT 17
BIT 16
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OFFSET[23]
OFFSET[22]
OFFSET[21]
OFFSET[20]
OFFSET[19]
OFFSET[18]
OFFSET[17]
OFFSET[16]
OFFSET[15]
OFFSET[14]
OFFSET[13]
OFFSET[12]
OFFSET[11]
OFFSET[10]
OFFSET[9]
OFFSET[8]
OFFSET[7]
OFFSET[6]
OFFSET[5]
OFFSET[4]
OFFSET[3]
OFFSET[2]
OFFSET[1]
OFFSET[0]
Power-On/Reset Value = 0x8000(SIG7792)/0x800000(SIG7793)
Bits
Bit Name
Access
Reset
Description
23:0
OFFSET[23:0]
R/W
0x800000
Offset Calibration Bits: The 24-bit word is signed number in offset
binary format. See Calibration section for more information.
GAIN Register
The device has four GAIN registers, each channel has a dedicated GAIN register (see Table 9). This register is 16
bits wide for SIG7792 and 24 bits wide for SIG7793. GAIN register read is allowed anytime, but writing to GAIN register
is only allowed while the device is in idle or sleep mode.
Table 14. GAIN Register (Address = 3’b111)
BIT 23
BIT 22
BIT 21
BIT 20
BIT 19
BIT18
BIT 17
BIT 16
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
GAIN[23]
GAIN[22]
GAIN[21]
GAIN[20]
GAIN[19]
GAIN[18]
GAIN[17]
GAIN[16]
GAIN[15]
GAIN[14]
GAIN[13]
GAIN[12]
GAIN[11]
GAIN[10]
GAIN[9]
GAIN[8]
GAIN[7]
GAIN[6]
GAIN[5]
GAIN[4]
GAIN[3]
GAIN[2]
GAIN[1]
GAIN[0]
Power-On/Reset Value = 0x5555(SIG7792)/0x555555(SIG7793)
Bits
Bit Name
Access
Reset
Description
23:0
GAIN[23:0]
R/W
0x555555
Gain Calibration Bits: The 24-bit word is unsigned positive number
in binary format. See Calibration section for more information.
May 2022
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14
SIG7792/7793
REVISION HISTORY
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please contact to make sure you have the latest revision.
DATE
REVISION
May 20, 2022
CHANGE
Initial release.
DISCLAIMER
Signal Micro reserves the right to make any change in circuit design, specification or other related things if necessary
without notice at any time.
All trademarks and registered trademarks are the property of their respective owners.
May 2022
Signal Micro Incorporated
http://www.signal-micro.cn
15
SIG7792/7793
PACKAGE OUTLINE DIMENSIONS
0.30
0.19
0.65
16
0.10
M
9
0.15 NOM
4.50
4.30
6.60
6.20
0.25
0o-8o
0.75
0.50
8
1
5.10
4.90
1.10 MAX
0.15
0.05
0.10
Seating Plane
A. Compliant to JEDEC STARDARDS MO-153-AD.
B. All linear dimensions are in millimeters.
C. This drawing is subject to change without notice.
May 2022
Signal Micro Incorporated
http://www.signal-micro.cn
16
工商网监
湘ICP备2023018690号
