SIG5532B-ITSP20-RL

SIG5532B/34B SIG5532B/34B: 1.875 to 3840SPS, 32-bit Sigma-Delta ADC with PGA and Reference FEATURES DESCRIPTION Programmable Gain: 1/2/4/8/16/32/64 Selectable Data Rates: 1.875 to 3840SPS RMS Noise: 11nV at 7.5SPS (Gain=64) 22.8 Noise-Free Bits at 7.5SPS (Gain=1) Offset Drift: 5nV/°C (Gain=64) Gain Drift: 1ppm/°C 2.5V Internal Reference with 5ppm/°C Drift Integral Non-Linearity: 3ppm Internal or External Clock Automatic Channel Sequencer Burnout Current Sources Low-Side Power Switch Parity Check Power Supply AVDD: 4.75V to 5.25V or ±2.5V DVDD: 2.7V to 5.25V Current: 6.0mA Package: 20/24-lead TSSOP The SIG5532B/34B is a low noise, low drift, and highresolution 32-bit analog-to-digital converter (ADC) with integrated programmable gain amplifier (PGA) that offers high-accuracy measurement solutions for bridge sensors, thermocouples, and resistance temperature devices (RTD). The device contains a low noise PGA with gains selected from 1, 2, 4, 8 16, 32, and 64, a delta-sigma (Δ-Σ) modulator, and a programmable SINC3/SINC1 digital filter. A low drift 2.5V reference is integrated on chip for accurate measurement. The output data rate from the device can be configured to 1.875, 3.75, 7.5, 15, 30, 60, 120, 240, 480, 960, 1920, and 3840SPS. This device provides channel sequencer feature to measure the differential inputs automatically. Burnout current sources are provided at the analog inputs for sensor connection diagnosis. Offset and gain calibration registers are provided with calibration command or direct register write to calibrate the ADC errors or overall system errors. SPI-compatible interface is used for device configuration and parity check is provided for data integrity. The on-chip oscillator, an external clock, or an external crystal can be used as the clock source to the device. APPLICATIONS The device can operate with bipolar ±2.375V to ±2.625V analog power supplies, or with a single 4.75V to 5.25V analog power supply. Weigh Scales Strain Gauges Pressure Sensors Temperature Measurement Industrial Process Control The SIG5532B is available in 20-lead TSSOP package and the SIG5534B is available in 24-lead TSSOP package. These devices are fully specified over the -40°C to +125°C temperature range. Function Block Diagram AVDD VREF+ VREF- INTREF MUX Gain=1,2,4,8, 16,32,64 BUF DVDD REFERENCE DETECT AIN1+ AIN1AIN2+ MUX AIN2AIN3+ AIN3- PGA ΔΣ ADC Digital Filter Serial Interface And Control Logic CSn DIN DOUT/DRDYn SCLK A1 AIN4+ AIN4SIG5534B Only TEMP Sensor A0/PDSW AVSS May 2022 SIG5534B/SIG5532B SIG5534B: 4-channel SIG5532B: 2-channel Internal Oscillator C1 C2 Signal Micro Incorporated http://www.signal-micro.cn Clock Circuitry DGND OSC2 OSC1 SIG5532B/34B PIN CONFIGURATION and DESCRIPTIONS TOP VIEW (Not To Scale) AIN1+ 1 24 AIN2+ AIN1- 2 23 AIN2- AIN1+ 1 20 AIN2+ AIN1- 2 19 AIN2- AIN4+ 3 22 AIN3+ C1 3 18 VREF+ AIN4- 4 21 AIN3- 17 VREF- C1 5 20 VREF+ 16 DGND C2 6 19 VREF- 18 DGND C2 4 AVDD 5 AVSS 6 15 DVDD AVDD 7 A0/PDSW 7 14 CSn AVSS 8 17 DVDD A1 8 13 DIN A0/PDSW 9 16 CSn OSC2 9 12 DOUT/DRDYn A1 10 15 DIN OSC1 10 11 SCLK OSC2 11 14 DOUT/DRDYn OSC1 12 13 SCLK SIG5532B TSSOP-20 PIN SIG5534B TSSOP-24 NAME FUNCTION DESCRIPTION AIN1+ AIN1- Analog Input Analog Input Positive analog input channel 1. Negative analog input channel 1. - AIN4+ AIN4- Analog Input Analog Input 5 3 C1 Analog Output 6 4 C2 Analog Output 7 5 AVDD Analog 8 6 AVSS Analog Positive analog input channel 4. Negative analog input channel 4. Amplifier analog output. Connect a COG cap with size 4.7~22nF between C1 and C2. Amplifier analog output. Connect a COG cap with size 4.7~22nF between C1 and C2. Positive analog power supply. 4.75V to 5.25V relative to AVSS. Negative analog power supply. 9 10 7 8 A0/PDSW A1 Analog logic output or bridge power down switch. Analog logic output. 11 9 OSC2 12 10 OSC1 Analog Output Analog Output Digital Input/Output Digital Input 13 14 11 12 SCLK DOUT/DRDYn Digital Input Digital Output Serial data clock. Serial data output and data ready indicator. 15 16 13 14 DIN CSn Digital Input Digital Input 17 15 DVDD Digital 18 16 DGND Digital 19 20 17 18 REFREF+ Analog Input Analog Input Negative reference input. Positive reference input. 21 22 - AIN3AIN3+ Analog Input Analog Input Negative analog input channel 3. Positive analog input channel 3. 23 24 19 20 AIN2AIN2+ Analog Input Analog Input Negative analog input channel 2. Positive analog input channel 2. SIG5534B 1 2 SIG5532B 1 2 3 4 May 2022 Master clock input or Crystal Connection. Crystal Connection. Serial data input. Serial chip select. Active low. Digital power supply, 2.7V to 5.25V. DVDD is independent of AVDD. Digital ground reference point. Signal Micro Incorporated http://www.signal-micro.cn 2 SIG5532B/34B PACKAGE/ORDERING INFORMATION MODEL PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE ORDERING NUMBER PACKING OPTION SIG5532B TSSOP-20 -40°C to +125°C SIG5532B-ITSP20-RL Reel, 4500 SIG5534B TSSOP-24 -40°C to +125°C SIG5534B-ITSP24-RL Reel, 3000 SPECIFICATIONS Absolute Maximum Ratings Over operating free-air temperature range, unless otherwise noted.(1) AVDD to AVSS Voltage Current Temperature MIN MAX UNIT –0.3 6.5 V AVSS to DGND –3 0.3 V DVDD to DGND –0.3 6.5 V Analog input VAVSS – 0.3 VAVDD + 0.3 V Digital input VDGND – 0.3 VDVDD + 0.3 V Input current –10 10 mA Junction (TJ) –50 150 °C Storage (Tstg) -60 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD Ratings SYMBOL PARAMTER CONDITION VALUE UNIT HBM Human-body Model ANSI/ESDA/JEDEC JS-001 ±4000 V CDM Charged-device model JEDEC EIA/JS-002-2022 ±2000 V This integrated circuit can be damaged by ESD. Signal Micro recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. May 2022 Signal Micro Incorporated http://www.signal-micro.cn 3 SIG5532B/34B Electrical Characteristics Minimum/Maximum specifications apply from -40˚C to +125˚C. Typical specifications are at +25˚C. All specification are at VAVDD=5V, VAVSS=0V, VDVDD=3.3V, VREF=2.5V, fCLK=4.9152MHz, data rate=60SPS, and PGA Gain=1, unless otherwise noted. TEST CONDITION OR NOTES PARAMETER MIN(1) TYP MAX(1) UNITS V ANALOG INPUTS Differential Input Voltage VIN = VINP – VINN –VREF/(2xGain) +VREF/(2xGain) Absolute Input Voltage PGA bypass PGA enabled Common Mode Input Range PGA enabled VAVSS – 0.05 VAVSS + 0.5 VAVSS + 0.5 + |VINMAX|·Gain/2 VAVDD + 0.05 VAVDD – 0.5 VAVDD – 0.5 – |VINMAX|·Gain/2 Absolute Input Current PGA bypass PGA enabled ±20 ±2 V V nA nA SYSTEM PERFORMANCE PGA Gain 1/2/4/8/16/32/64 V/V Resolution 32 Bits Data Rate 1.875 Noise 3840 SPS See Noise Table Integral Nonlinearity (INL) ±3 ppm Offset Error All PGA gains ±200/Gain μV Offset Drift vs. Temperature All PGA gains ±200/Gain ± 3 nV/°C Gain Error All PGA gains ±0.01 % Gain Drift vs. Temperature Common Mode Rejection (CMRR) All PGA gains fIN=50/60Hz, data rate=960SPS AVDD, AVSS -5 ±1 100 120 75 90 dB DVDD 80 120 dB (2) Power Supply Rejection (PSRR) EXTERNALREFERENCE INPUT Differential Reference Voltage VREF = VREFP – VREFN (VREF) Absolute Negative Reference Voltage (VREFN) Absolute Positive Reference Voltage (VREFP) Average Voltage Input Current 5 ppm/°C dB 0.5 VAVDD – VAVSS + 0.1 V VAVSS – 0.05 VREFP – 0.5 V VREFN + 0.5 VAVDD + 0.05 V 500 nA INTERNAL VOLTAGE REFERENCE Reference Voltage 2.5 Initial Accuracy TA = 25˚C -0.1% Voltage Temperature Drift TA = -40˚C to 125˚C Power Supply Rejection V ±0.01% +0.1% 5 20 ppm/°C 90 dB 1 μA Burnout Current Sources Current Setting ADC CLOCK External Clock Internal Oscillator Frequency Range Duty Cycle 1 4.9152 40% Nominal Frequency 5 4.9152 Accuracy –3% High-level Output Voltage (VOH) IOH = 4mA 0.8·VDVDD Low-level Output Voltage (VOL) IOL = –4mA MHz 60% ±0.5% MHz 3% DIGITAL INPUT/OUTPUT High-level Input Voltage (VIH) 0.7·VDVDD Low-level Input Voltage (VIL) VDGND Input Hysteresis May 2022 V 0.5 Signal Micro Incorporated http://www.signal-micro.cn 0.2·VDVDD V VDVDD V 0.3·VDVDD V V 4 SIG5532B/34B Input Leakage ±10 μA POWER SUPPLY AVSS Voltage (VAVSS) –2.625 0 V AVDD Voltage (VAVDD) VAVSS + 4.75 VAVSS + 5.25 V DVDD Voltage (VDVDD) 2.7 5.25 V AVDD, AVSS Current (IAVDD) DVDD Current (IDVDD) Total Power Dissipation PGA Bypass 3.3 4.0 mA PGA Enabled 5.6 7.0 mA 0.6 mA μA Sleep Mode 1 Active Mode 0.4 Sleep Mode 40 μA PGA Bypass 18.0 mW PGA Enabled 30.0 mW Sleep Mode 0.15 mW TEMPERATURE RANGE Specified temperature range –40 105 °C Operating temperature range –50 125 °C Storage temperature range –60 150 °C (1) Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. (2) Power supply rejection is specified DC change in voltage. May 2022 Signal Micro Incorporated http://www.signal-micro.cn 5 SIG5532B/34B Timing Requirements: Serial Interface Over the operating ambient temperature range and DVDD = 2.7V to 5.25V, unless otherwise noted. t7 CSn t1 t5 B7 DOUT B6 B5 B4 B3 B2 B1 B0 t2 t8 t6 t3 SCLK t4 t9 t10 DIN B7 B6 B5 B4 B3 B2 B1 B0 Figure 1. Serial Interface Timing Requirements SYMBOL t1 t2 t3 t4 DESCRIPTION CSn falling edge to valid DOUT/DRDYn: propagation delay(1) SCLK falling edge to valid DOUT/DRDYn: propagation delay(1) SCLK high pulse width MIN MAX 20 20 50 UNIT ns ns ns SCLK low pulse width 50 ns SCLK period 100 106 ns 20 ns t5 CSn rising edge to DOUT high impedance: propagation delay t6 Last SCLK falling edge to CSn rising edge: delay time 20 ns t7 CSn high pulse width 50 ns 50 ns time(2) t8 CSn falling edge to first SCLK rising edge: setup t9 Valid DIN to SCLK rising edge: setup time 20 ns t10 Valid DIN to SCLK rising edge: hold time 20 ns (1) DOUT load = 20pF || 100k Ω to DGND. (2) CSn can be tied low. May 2022 Signal Micro Incorporated http://www.signal-micro.cn 6 SIG5532B/34B NOISE PERFORMANCE The noise performance of the ADC is affected by PGA gain, data rate, and digital filter setting. The following tables show the rms noise and peak-to-peak noise for SINC3 and SINC1 filters. The effective number of bits (ENOB) and noise-free bits are also listed according to Equation (1) and Equation (2): ENOB= log 2 (2×VREF ⁄Gain⁄VRMS ) (1) Noise Free Bits= log 2 �2×VREF ⁄Gain⁄Vp-p � (2) The noise data listed in the table are typical and are generated from continuous ADC readings with differential input voltage of 0 V. Table 1. ADC Noise in µVRMS (µVPP) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 2.5 V, SINC3 Filter Data Rate (SPS) 1 2 4 PGA GAIN 8 16 32 64 1.875 3.75 7.5 15 30 60 120 240 480 960 1920 3840 0.050(0.315) 0.070(0.446) 0.099(0.630) 0.141(0.891) 0.199(1.26) 0.281(1.78) 0.398(2.52) 0.562(3.56) 0.795(5.04) 1.12(7.13) 1.58(11.0) 2.27(16.5) 0.027(0.171) 0.039(0.242) 0.055(0.343) 0.078(0.484) 0.110(0.685) 0.155(0.969) 0.219(1.37) 0.310(1.94) 0.439(2.74) 0.620(3.87) 0.854(5.80) 1.24(9.39) 0.016(0.109) 0.023(0.154) 0.033(0.217) 0.046(0.307) 0.065(0.434) 0.092(0.614) 0.131(0.869) 0.185(1.23) 0.262(1.74) 0.370(2.46) 0.508(3.33) 0.748(5.92) 0.011(0.065) 0.015(0.091) 0.021(0.129) 0.030(0.182) 0.042(0.258) 0.060(0.365) 0.084(0.516) 0.119(0.730) 0.169(1.03) 0.239(1.46) 0.351(2.42) 0.491(3.64) 0.008(0.051) 0.011(0.072) 0.015(0.102) 0.022(0.144) 0.030(0.204) 0.043(0.288) 0.061(0.407) 0.086(0.576) 0.122(0.814) 0.172(1.15) 0.255(1.78) 0.360(2.91) 0.006(0.040) 0.009(0.057) 0.012(0.080) 0.017(0.113) 0.025(0.160) 0.035(0.226) 0.049(0.320) 0.069(0.453) 0.098(0.640) 0.139(0.905) 0.203(1.41) 0.280(1.78) 0.005(0.035) 0.008(0.049) 0.011(0.070) 0.015(0.099) 0.021(0.140) 0.030(0.197) 0.042(0.279) 0.060(0.395) 0.085(0.559) 0.120(0.790) 0.171(1.15) 0.243(1.85) Table 2. ADC ENOB (Noise Free Bits) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 5 V, SINC3 Filter Data Rate (SPS) 1 2 4 PGA GAIN 8 16 32 64 1.875 3.75 7.5 15 30 60 120 240 480 960 1920 3840 26.3(23.8) 25.8(23.3) 25.3(22.8) 24.8(22.3) 24.3(21.8) 23.8(21.3) 23.3(20.8) 22.8(20.3) 22.3(19.8) 21.8(19.3) 21.4(18.6) 21.0(18.2) 26.2(23.7) 25.7(23.2) 25.2(22.7) 24.7(22.2) 24.2(21.7) 23.7(21.2) 23.2(20.7) 22.7(20.2) 22.2(19.7) 21.7(19.2) 21.4(18.5) 20.9(17.9) 26.1(23.4) 25.6(22.9) 25.1(22.4) 24.6(21.9) 24.1(21.4) 23.6(20.9) 23.1(20.4) 22.6(19.9) 22.1(19.4) 21.6(18.9) 21.1(18.3) 20.6(17.7) 25.8(23.1) 25.3(22.6) 24.8(22.1) 24.3(21.6) 23.8(21.1) 23.3(20.6) 22.8(20.1) 22.3(19.6) 21.8(19.1) 21.3(18.6) 20.7(18.0) 20.3(17.5) 25.2(22.6) 24.7(22.1) 24.2(21.6) 23.7(21.1) 23.2(20.6) 22.7(20.1) 22.2(19.6) 21.7(19.1) 21.2(18.6) 20.7(18.1) 20.2(17.4) 19.7(16.8) 24.6(21.9) 24.1(21.4) 23.6(20.9) 23.1(20.4) 22.6(19.9) 22.1(19.4) 21.6(18.9) 21.1(18.4) 20.6(17.9) 20.1(17.4) 19.5(16.6) 19.1(16.3) 23.8(21.2) 23.3(20.7) 22.8(20.2) 22.3(19.7) 21.8(19.2) 21.3(18.7) 20.8(18.2) 20.3(17.7) 19.8(17.2) 19.3(16.7) 18.8(16.0) 18.3(15.5) May 2022 Signal Micro Incorporated http://www.signal-micro.cn 7 SIG5532B/34B Table 3. ADC Noise in µVRMS (µVPP) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 2.5 V, SINC1 Filter Data Rate (SPS) 1 2 4 PGA GAIN 8 16 32 64 1.875 3.75 7.5 15 30 60 120 240 480 960 1920 3840 0.068(0.474) 0.096(0.670) 0.136(0.948) 0.192(1.34) 0.271(1.90) 0.384(2.68) 0.543(3.79) 0.768(5.36) 1.09(7.58) 1.54(10.7) 2.04(14.2) 2.82(19.5) 0.036(0.228) 0.051(0.323) 0.072(0.457) 0.101(0.646) 0.143(0.913) 0.203(1.29) 0.287(1.83) 0.405(2.58) 0.573(3.65) 0.810(5.17) 1.18(8.12) 1.57(11.7) 0.022(0.149) 0.031(0.211) 0.044(0.299) 0.063(0.423) 0.089(0.598) 0.126(0.845) 0.178(1.20) 0.251(1.69) 0.355(2.39) 0.502(3.38) 0.689(4.83) 0.935(6.97) 0.015(0.097) 0.021(0.137) 0.029(0.194) 0.041(0.274) 0.058(0.387) 0.082(0.548) 0.117(0.774) 0.165(1.10) 0.233(1.55) 0.330(2.19) 0.606(4.35) 0.612(4.23) 0.010(0.068) 0.015(0.096) 0.021(0.136) 0.029(0.192) 0.041(0.272) 0.058(0.385) 0.082(0.544) 0.117(0.769) 0.165(1.09) 0.233(1.54) 0.319(2.14) 0.443(3.00) 0.008(0.050) 0.012(0.071) 0.016(0.100) 0.023(0.141) 0.033(0.200) 0.046(0.282) 0.066(0.399) 0.093(0.564) 0.131(0.798) 0.186(1.13) 0.251(1.70) 0.345(2.25) 0.007(0.049) 0.010(0.069) 0.014(0.097) 0.020(0.137) 0.029(0.194) 0.041(0.275) 0.058(0.389) 0.082(0.550) 0.116(0.777) 0.163(1.10) 0.224(1.61) 0.304(2.18) Table 4. ADC ENOB (Noise Free Bits) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 5 V, SINC1 Filter Data Rate (SPS) 1 2 4 PGA GAIN 8 16 32 64 1.875 3.75 7.5 15 30 60 120 240 480 960 1920 3840 26.0(23.2) 25.5(22.7) 25.0(22.2) 24.5(21.7) 24.0(21.2) 23.5(20.7) 23.0(20.2) 22.5(19.7) 22.0(19.2) 21.5(18.7) 21.1(18.3) 20.6(17.9) 25.9(23.4) 25.4(22.9) 24.9(22.4) 24.4(21.9) 23.9(21.4) 23.4(20.9) 22.9(20.4) 22.4(19.9) 21.9(19.4) 21.4(18.9) 21.0(18.4) 20.5(17.6) 25.7(22.9) 25.2(22.4) 24.7(21.9) 24.2(21.4) 23.7(20.9) 23.2(20.4) 22.7(19.9) 22.2(19.4) 21.7(18.9) 21.2(18.4) 20.7(17.8) 20.3(17.5) 25.4(22.6) 24.9(22.1) 24.4(21.6) 23.9(21.1) 23.4(20.6) 22.9(20.1) 22.4(19.6) 21.9(19.1) 21.4(18.6) 20.9(18.1) 20.3(17.8) 19.9(17.1) 24.8(22.2) 24.3(21.7) 23.8(21.2) 23.3(20.7) 22.8(20.2) 22.3(19.7) 21.8(19.2) 21.3(18.7) 20.8(18.2) 20.3(17.7) 19.8(17.0) 19.4(16.7) 24.2(21.5) 23.7(21.0) 23.2(20.5) 22.7(20.0) 22.2(19.5) 21.7(19.0) 21.2(18.5) 20.7(18.0) 20.2(17.5) 19.7(17.0) 19.2(16.4) 18.8(15.8) 23.3(20.6) 22.8(20.1) 22.3(19.6) 21.8(19.1) 21.3(18.6) 20.8(18.1) 20.3(17.6) 19.8(17.1) 19.3(16.6) 18.8(16.1) 18.4(15.5) 18.0(15.1) May 2022 Signal Micro Incorporated http://www.signal-micro.cn 8 SIG5532B/34B REGISTER MAPS There are total three 24-bit registers inside the device. These registers are used to configure and control the ADC to the desired mode of operation. These registers can be accessed through the SPI-compatible serial interface by using register read and write commands. At power-on or reset, the registers default to their initial settings, as shown in the Reset Value column of Table 5. Table 5. Register map ADDR. RS[2:0] NAME RESET VALUE 3’b001 OFFSET 0x00000000 3’b010 GAIN 0x01000000 3’b011 CONF 3’b101 CSR 0x00000000 0x00000000 BIT 31 BIT 23 BIT 15 BIT 7 BIT 30 BIT 22 BIT 14 BIT 6 BIT 29 BIT 21 BIT 13 BIT 5 BIT 28 BIT 27 BIT 20 BIT 19 BIT 12 BIT 11 BIT 4 BIT 3 OFFSET[31:24] OFFSET[23:16] OFFSET[15:8] OFFSET[7:0] GAIN[23:16] GAIN[23:16] GAIN[15:8] GAIN[7:0] PSS PDW RS RV SHORT A0_PSW VRS A1 A0 OLS BUF OGS FRS FILTER TPS INTREF CHKSUM CH7 CS1] LATENCY CH6 CS[0] LOOPEN CH3 PGA[0] CH2 DR[3] DELAY[2:0] CH1 DR[2] CH0 DR[1] DR[0] FORMAT OL1 OL0 DT BCS OG[1] OG[0] CS[1] CS[0] PGA[2] PGA[1] PGA[0] DR[3] DR[2] DR[1] DR[0] FORMAT OL1 OL0 DT BCS OG[1] OG[0] CLK[1:0] CH5 CH4 PGA[2] PGA[1] BIT26 BIT18 BIT10 BIT 2 BIT 25 BIT 17 BIT 9 BIT 1 BIT 24 BIT 16 BIT 8 BIT 0 OFFSET Register The device has four OFFSET registers #1, #2, #3, and #4. Each register can be accessed by setting CS[1:0] bits in the register read and write commands. User can choose which one to use by controlling CONF bit OGS and CSR register bits OG[1:0] or OL[1:0]. Table 6. OFFSET Register (Address = 3’b001) BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OFFSET[31] OFFSET[30] OFFSET[29] OFFSET[28] OFFSET[27] OFFSET[26] OFFSET[25] OFFSET[24] OFFSET[23] OFFSET[22] OFFSET[21] OFFSET[20] OFFSET[19] OFFSET[18] OFFSET[17] OFFSET[16] OFFSET[15] OFFSET[14] OFFSET[13] OFFSET[12] OFFSET[11] OFFSET[10] OFFSET[9] OFFSET[8] OFFSET[7] OFFSET[6] OFFSET[5] OFFSET[4] OFFSET[3] OFFSET[2] OFFSET[1] OFFSET[0] Power-On/Reset value = 0x00000000 Bits Bit Name Access Reset Description 31:0 OFFSET[31:0] R/W 0x00000000 Offset Calibration Bits: The 32-bit word is signed number in 2’s complement format. See Calibration section for more information. May 2022 Signal Micro Incorporated http://www.signal-micro.cn 9 SIG5532B/34B GAIN Register The device has four GAIN registers #1, #2, #3, and #4. Each register can be accessed by setting CS[1:0] bits in the register read and write commands. User can choose which one to use by controlling CONF bit OGS and CSR register bits OG[1:0] or OL[1:0]. Table 7. GAIN Register (Address = 3’b010) BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 GAIN[31] GAIN[30] GAIN[29] GAIN[28] GAIN[27] GAIN[26] GAIN[25] GAIN[24] GAIN[23] GAIN[22] GAIN[21] GAIN[20] GAIN[19] GAIN[18] GAIN[17] GAIN[16] GAIN[15] GAIN[14] GAIN[13] GAIN[12] GAIN[11] GAIN[10] GAIN[9] GAIN[8] GAIN[7] GAIN[6] GAIN[5] GAIN[4] GAIN[3] GAIN[2] GAIN[1] GAIN[0] Power-On/Reset value = 0x01000000 Bits Bit Name Access Reset Description 31:0 GAIN[31:0] R/W 0x01000000 Gain Calibration Bits: The 32-bit word is unsigned positive number in binary format. See Calibration section for more information. Configuration Register (CONF) Table 8. CONF Register (Address = 3’b011) BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PSS PDW RS RV SHORT A0_PSW VRS A1 A0 OLS BUF OGS FRS FILTER TPS INTREF CHKSUM LATENCY CH7 CH6 CLK[1:0] CH5 LOOPEN CH4 CH3 DELAY[2:0] CH2 CH1 CH0 Power-On/Reset value = 0x00000000 Bits Bit Name Access Reset Description 31 PSS R/W 1’b0 Power Save Select: 0: Standby Mode (default) 1: Sleep Mode 30 PDW R/W 1’b0 Power Down Mode: 0: Normal Mode (default) 1: Power Down Mode 29 RS R/W 1’b0 Reset System: 0: Normal Operation (default) 1: Activate a Reset cycle. 28 RV R 1’bx Reset Indicator: Read only. Bit is cleared to logic zero after the CONF register is read. 0: Normal Operation (default) 1: System was reset. 27 SHORT R/W 1’b0 Input Short: 0: Normal Input (default) 1: Analog Inputs are disconnected from the pins and shorted May 2022 Signal Micro Incorporated http://www.signal-micro.cn 10 SIG5532B/34B internally to mid-supply (VAVDD+VAVSS)/2. 26 A0_PSW R/W 1’b0 Bridge Power-down Switch Function: When this bit is set to 1, the output latch bit A0 or OL0 is served as the switch control bit. The switch is closed to short pin A0 to DVSS with low on-resistor of typical 3 Ohms if the output latch bit is set to 1. The switch is open if the output latch bit is cleared. The switch remains active in standby mode and is forced to open in sleep mode. 0: Disabled (default) 1: Enabled 25 VRS R/W 1’b0 Voltage Reference Select: The input full-scale range is [-VREF/(2xgain), VREF/(2xgain)] with VRS=0, and is [-VREF/gain, VREF/gain] with VRS=1. 0: 2.5V