SIG7796-ITSP16-RL

SIG7796/7797 2-Channel 16/24-bit Sigma-Delta ADC for Bridge Sensors FEATURES DESCRIPTION Programmable Gain: 128 Data Rates: 4.17SPS to 890SPS RMS Noise: 20nV at 4.17SPS (Gain=128) 63nV at 16.7SPS (Gain=128) Offset Drift: 5nV/°C (Gain=128) Gain Drift: 1ppm/°C Integral Non-Linearity: 2ppm 2 Differential Inputs Internal or External Clock Simultaneous 50Hz/60Hz Rejection Burnout Current Sources Power Supply AVDD: 2.7V to 5.25V DVDD: 2.7V to 5.25V Current: 470uA Package: 16-lead TSSOP The SIG7796/7797 are low noise, low drift, and high-resolution 16/24-bit analog-to-digital converter (ADC) with integrated programmable gain amplifier (PGA) that offers high-accuracy measurement solutions for bridge sensors. The device contains a low noise amplifier with fixed gain 128, a delta-sigma (Δ-Σ) modulator, and digital filter. The output data rate from the device can be configured from 4.17SPS up to 890SPS. 50Hz/60Hz simultaneous rejection option is also provided. Burnout current sources are provided at the analog inputs for sensor connection diagnosis. Offset and gain calibration registers are provided with calibration command or direct register write to calibrate the ADC errors or overall system errors. SPI-compatible interface is used for device configuration. The on-chip oscillator or an external clock can be used as the clock source to the device. The SIG7796/7797 are available in 16-lead TSSOP packages and are fully specified over the -40°C to +125°C temperature range. APPLICATIONS Weigh Scales Strain Gauges Industrial Process Control Pressure Sensors Function Block Diagram AVDD REF+/AIN3+ TSSOP-16 DVDD REF-/AIN3- SCLK 1 16 DIN CLK 2 15 DOUT/DRDYn CSn 3 14 DVDD NC 4 13 AVDD AIN1+ 5 12 GND AIN1- 6 11 NC AIN2+ 7 10 REF- AIN2- 8 9 REF+ REFERENCE DETECT BUF AIN2+ AIN2- 128 MUX AIN1+ AIN1- ΔΣ ADC Digital Filter SIG7796/SIG7797 TEMP Sensor May 2022 SIG7796: 16-BIT SIG7797: 24-BIT Serial Interface And Control Logic CSn DIN DOUT/DRDYn SIG7796/7797 TSSOP-16 SCLK Internal Oscillator CLK Signal Micro Incorporated http://www.signal-micro.cn SIG7796/7797 PIN CONFIGURATION and DESCRIPTIONS TOP VIEW (Not To Scale) PIN SCLK 1 16 DIN CLK 2 15 DOUT/DRDYn CSn 3 14 DVDD NC 4 13 AVDD AIN1+ 5 12 GND AIN1- 6 11 NC AIN2+ 7 10 REF- AIN2- 8 9 REF+ SIG7796/7797 TSSOP-16 FUNCTION DESCRIPTION CSn NC Digital Input Digital Input/Output Digital Input Analog Input Serial data clock. Master clock input or internal clock output depending on MODE Register bits CLK[1:0]. Serial chip select. Active low. No connect. 5 6 AIN1+ AIN1- Analog Input Analog Input Analog positive input channel 1. Analog negative input channel 1. 7 8 AIN2+ AIN2- Analog Input Analog Input Analog positive input channel 2. Analog negative input channel 2. 9 10 REF+ REF- Analog Input Analog Input Positive reference input. Negative reference input. 11 12 NC GND Analog Input Analog 13 AVDD Analog 14 DVDD Digital No connect. Ground reference point. Positive analog power supply. 2.7V to 5.25V relative to GND. AVDD is independent of DVDD. Digital power supply, 2.7V to 5.25V. DVDD is independent of AVDD. 15 16 DOUT/DRDYn DIN Digital Output Digital Input NO. NAME 1 SCLK 2 CLK 3 4 May 2022 Serial data output and data ready indicator. Serial data input. Signal Micro Incorporated http://www.signal-micro.cn 2 SIG7796/7797 PACKAGE/ORDERING INFORMATION MODEL PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE ORDERING NUMBER PACKING OPTION SIG7796 TSSOP-16 -40°C to +125°C SIG7796-ITSP16-RL Reel, 5000 SIG7797 TSSOP-16 -40°C to +125°C SIG7797-ITSP16-RL Reel, 5000 SPECIFICATIONS Absolute Maximum Ratings Over operating free-air temperature range, unless otherwise noted.(1) AVDD to GND Voltage Current Temperature MIN MAX UNIT –0.3 6.5 V DVDD to GND –0.3 6.5 V Analog input –0.3 VAVDD + 0.3 V Digital input –0.3 VDVDD + 0.3 V Input current –10 10 mA Junction (TJ) –50 150 °C Storage (Tstg) -60 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD Ratings SYMBOL PARAMTER CONDITION VALUE UNIT HBM Human-body Model ANSI/ESDA/JEDEC JS-001 ±6000 V CDM Charged-device model JEDEC EIA/JS-002-2022 ±2000 V This integrated circuit can be damaged by ESD. Signal Micro recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. May 2022 Signal Micro Incorporated http://www.signal-micro.cn 3 SIG7796/7797 Electrical Characteristics Minimum/Maximum specifications apply from -40˚C to +125˚C. Typical specifications are at +25˚C. All specification are at VAVDD=5V, VDVDD=3.3V, VGND =0V, VREF=2.5V, fCLK=1.024MHz, data rate=16.7SPS, and PGA Gain=1, unless otherwise noted. PARAMETER TEST CONDITION OR NOTES MIN(1) TYP MAX(1) UNITS +VREF/Gain VAVDD – 0.2 VAVDD – 0.2 – |VINMAX|·Gain/2 V V ANALOG INPUTS Differential Input Voltage Absolute Input Voltage VIN = VINP – VINN –VREF/Gain + 0.2 Common Mode Input Range 0.2 + |VINMAX|·Gain/2 Absolute Input Current ±1 V nA SYSTEM PERFORMANCE PGA Gain Resolution SIG7797 SIG7796 Buffer On ±2 Chop Off ±400/Gain μV Chop On ±1 μV ppm ±400/Gain ± 2 Gain Drift vs. Temperature Power Supply Rejection (PSRR) SPS See Noise Table Gain Error(2) Common Mode Rejection (CMRR) Bits 890 Offset Drift vs. Temperature Normal Mode Rejection (NMRR) Bits 4.17 Noise Offset Error V/V 24 16 Data Rate Integral Nonlinearity (INL) 128 nV/°C -0.05 ±0.005 0.05 % -3 ±1 +3 ppm/°C fIN = 50/60Hz, ±2%, data rate=16.7SPS fIN = 50Hz, data rate = 470SPS AVDD 100 85 105 dB DVDD 90 110 dB 0.5 2.5 EXTERNAL REFERENCE INPUTs Differential Reference Voltage VREF = VREFP – VREFN (VREF) Absolute Negative Reference Voltage (VREFN) Absolute Positive Reference Voltage (VREFP) Average Voltage Input Current See Table 14 dB 120 dB VAVDD + 0.1 V – 0.05 VREFP – 0.5 V VREFN + 0.5 VAVDD + 0.05 V ±1 uA 500 nA Burnout Current Sources Current Setting ADC CLOCK External Clock Internal Oscillator Frequency Range 0.5 Duty Cycle 40% Nominal Frequency 1.024 1.1 1.024 Accuracy –3% High-level Output Voltage (VOH) IOH = 4mA 0.8·VDVDD Low-level Output Voltage (VOL) IOL = –4mA MHz 60% ±0.5% MHz 3% DIGITAL INPUT/OUTPUT V 0.2·VDVDD V High-level Input Voltage (VIH) 0.7·VDVDD VDVDD V Low-level Input Voltage (VIL) 0 0.3·VDVDD V ±10 μA Input Hysteresis 0.5 Input Leakage V POWER SUPPLY AVDD Voltage (VAVDD) 2.7 5.25 V DVDD Voltage (VDVDD) 2.7 5.25 V May 2022 Signal Micro Incorporated http://www.signal-micro.cn 4 SIG7796/7797 AVDD Current (IAVDD) DVDD Current (IDVDD) Total Power Dissipation Normal Mode 350 Sleep Mode 1 Active Mode 120 Sleep Mode 20 450 uA 200 μA μA μA Normal Mode 2.15 mW Sleep Mode 0.10 mW TEMPERATURE RANGE Specified temperature range –40 125 °C Operating temperature range –50 125 °C Storage temperature range –60 150 °C (1) Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. (2) MIN and MAX values listed for gain error are for +25˚C room temperature only. May 2022 Signal Micro Incorporated http://www.signal-micro.cn 5 SIG7796/7797 Timing Requirements: Serial Interface Over the operating ambient temperature range and DVDD = 2.7V to 5.25V, unless otherwise noted. t7 CSn t6 t1 t5 B7 DOUT B6 B4 B5 B3 B2 B1 B0 t2 t8 t3 SCLK t4 t9 t10 DIN B7 B6 B5 B4 B3 B2 B0 B1 Figure 1. Serial Interface Timing Requirements SYMBOL t1 t2 t3 t4 DESCRIPTION CSn falling edge to DOUT/DRDYn driven: propagation delay(1) SCLK falling edge to valid DOUT/DRDYn: propagation delay(1) SCLK low pulse width MIN SCLK high pulse width 100 SCLK period MAX 50 50 100 200 UNIT ns ns ns ns 106 ns 40 ns t5 CSn rising edge to DOUT high impedance: propagation delay t6 Last SCLK rising edge to CSn rising edge: delay time 50 ns t7 CSn high pulse width 50 ns 50 ns time(2) t8 CSn falling edge to first SCLK falling edge: setup t9 Valid DIN to SCLK rising edge: setup time 50 ns t10 Valid DIN to SCLK rising edge: hold time 25 ns (1) DOUT load = 20pF || 100k Ω to GND. (2) CSn can be tied low. May 2022 Signal Micro Incorporated http://www.signal-micro.cn 6 SIG7796/7797 NOISE PERFORMANCE The noise performance of the ADC is affected by PGA gain, data rate, and digital filter setting. The following tables show the rms noise and peak-to-peak noise for different data rate with chop enabled. The effective number of bits (ENOB) and noise-free bits are also listed according to Equation (1) and Equation (2): ENOB= log 2 (2×VREF ⁄Gain⁄VRMS ) Noise Free Bits= log 2 �2×VREF ⁄Gain⁄Vp-p � (1) (2) The noise data listed in the table are typical and are generated from continuous ADC readings with differential input voltage of 0 V. With chop disabled, the noise increases by 30%. Table 1. ADC Noise in µVRMS (µVPP) at TA = 25°C, VAVDD = 5 V, VREF = 2.5 V, Chop Enabled FS[3:0] Data Rate (SPS) 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 4.17 6.25 8.33 10 12.5 16.7 16.7 19.6 33.2 39 50 62 123 242 470 890 PGA GAIN 128 0.020(0.095) 0.026(0.122) 0.032(0.150) 0.036(0.173) 0.045(0.212) 0.063(0.300) 0.063(0.291) 0.072(0.321) 0.093(0.449) 0.096(0.403) 0.120(0.538) 0.168(0.687) 0.195(1.18) 0.287(1.59) 0.421(2.55) 1.86(12.8) Table 2. ADC ENOB (Noise Free Bits) at TA = 25°C, VAVDD = 5 V, VREF = 2.5 V, Chop Enabled FS[3:0] 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 May 2022 Data Rate (SPS) 4.17 6.25 8.33 10 12.5 16.7 16.7 19.6 33.2 39 50 62 123 242 470 890 PGA GAIN 128 20.9(18.7) 20.5(18.3) 20.2(18.0) 20.0(17.8) 19.7(17.5) 19.2(17.0) 19.2(17.0) 19.0(16.9) 18.7(16.4) 18.6(16.6) 18.3(16.1) 17.8(15.8) 17.6(15.0) 17.1(14.6) 16.5(13.9) 14.4(11.6) Signal Micro Incorporated http://www.signal-micro.cn 7 SIG7796/7797 ON-CHIP REGISTER MAPS There are total eight registers inside the device which is 8-bit, 16-bit, or 24-bit wide. These registers are used to configure and control the ADC to the desired mode of operation. These registers can be accessed through the SPIcompatible serial interface by using register read and write commands. At power-on or reset, the registers default to their initial settings, as shown in the Reset Value column of Table 3. Table 3. SIG7797/SIG7796 register map ADDR. NAME DIR. RESET VALUE BIT 7 3’b000 STATUS R 80 DRDYn 3’b001 MODE R/W 000A 3’b010 CONFIG R/W 0710 3’b011 DATA R 000000 /(0000) (1) 3’b100 ID R XA/(XB)(1) 3’b110 OFFSET R/W 800000 /(8000)(1) BIT 6 ERR MD[2:0] CLK[1:0] 0 0 0 0 x x BIT 5 BIT 4 BIT 3 0 24-bit 0 0 0 CHOPn BURN FORMAT 0 REFDET 1 0 DATA[23:16] (SIG7797 only) DATA[15:8] DATA[7:0] x x 1 OFFSET[23:16] (SIG7797 only) BIT 2 NOREF 0 1 BIT 1 BIT 0 CHD[2:0] 0 FS[3:0] 1 CH[2:0] 0 0 1 1 1/0 OFFSET[15:8] OFFSET[7:0] 3’b111 GAIN R/W GAIN[23:16] (SIG7797 only) GAIN[15:8] 555555 /(5555)(1) GAIN[7:0] (1) The values in bracket are the default reset value for SIG7796. STATUS Register Table 4. STATUS Register (Address = 3’b000) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 DRDYn ERR NOREF 0 24-bit BIT 2 BIT 1 BIT 0 CHD[2:0] Power-On/Reset Value = 0x80(SIG7796)/ 0x88(SIG7797) Bits Bit Name Access Reset Description 7 DRDYn R 1’b1 ADC Ready Bit: This bit is cleared when new data is written to the ADC data register. It is set automatically after the ADC data register is read. In addition to this bit, DOUT/DRDYn pin can also be used as an alternative to monitor the update of new ADC data. 6 ERR R 1’b0 ADC Error Bit. This bit is written at the same time as new data update. Error sources include input overrange, input underrange, or lower than expected reference voltage. 5 NOREF R 1’b0 No External Reference Bit: The function of this bit is only enabled by setting the REFDET bit in the CONFIG Register to 1. While the REFDET bit is 1 and the selected reference voltage is below a specified threshold, which is about 0.4V, this bit is set and conversion results are clamped to all 1s. 4 RESERVED R 1’b0 Reserved 3 24-bit R 1’b0(7796) 1’b1(7797) 24-Bit Device Indicator. This bit indicates whether this device is 16bit (SIG7796) or 24-bit (SIG7797). CHD[2:0] R 3’b000 Data Channel Number: These bits indicate the corresponding channel to the ADC data in data register (see Table 7). 2:0 May 2022 Signal Micro Incorporated http://www.signal-micro.cn 8 SIG7796/7797 MODE Register Table 5. MODE Register (Address = 3’b001) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 0 0 CHOPn MD[2:0] CLK[1:0] FS[3:0] Power-On/Reset Value = 0x000A Bits Bit Name Access Reset Description 15:13 MD[2:0] R/W 3’b000 Mode Select Bits: These bits select the operating mode of the device. 000: Continuous conversion mode. (default) 001: Single conversion mode. ADC first wakeup if in idle or sleep mode; resets the filter to perform one conversion; and enters sleep mode. The conversion result remains in the data register with DOUT/DRDYn as low. 010: Idle mode. The digital filter is in reset state with ADC free running. 011: Sleep mode. Most of circuitry is turned off to save the power. 100: Internal zero-scale calibration. 101: Internal full-scale calibration. 110: System zero-scale calibration. 111: System full-scale calibration. For each above calibration mode, DOUT/DRDYn goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is automatically placed in idle mode after the calibration. The measured offset/full-scale coefficient is placed in the offset/full-scale register of the selected channel. 12:8 RESERVED R/W 5’b00000 Reserved Always write 5’b00000 CLK[1:0] R/W 2’b10 Clock Select Bits: This bits select the clock source for SYSCLK. 00: Internal 1.024MHz clock with CLK tristated. (default) 01: Internal 1.024MHz clock with its output on CLK pin. 10: External clock applied to the CLK pin. 11: External clock applied to the CLK pin. 5 RESERVED R/W 1’b0 Reserved Always write 1’b0 4 CHOPn R/W 1’b0 Chop Disable Bit: When chop is enabled with bit clear to logic 0, the offset and offset drift of the ADC are dramatically improved with settling time doubled. All output data are fully settled data. For default data rate settling of 16.7SPS, the conversion time is 60ms for all output data with chop disabled. If chop is enabled, the conversion time is 120ms for the first data and 60ms thereafter. 3:0 FS[3:0] R/W 4’b1010 Data Rate Configuration: Selects the ADC data rate. 0000: 890SPS 0001: 470SPS 0010: 242SPS 0011: 123SPS 0100: 62SPS 0101: 50SPS 0110: 39SPS 0111: 33.2SPS 1000: 19.6SPS 1001: 16.7SPS 1010: 16.7SPS (default) 1011: 12.5SPS 1100: 10SPS 7:6 May 2022 Signal Micro Incorporated http://www.signal-micro.cn 9 SIG7796/7797 1101: 8.33SPS 1110: 6.25SPS 1111: 4.17SPS CONFIG Register Table 6. CONFIG Register (Address = 3’b010) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT10 BIT 9 BIT 8 BIT 7 BIT 6 0 0 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BURN FORMAT 0 1 1 1 0 0 REFDET 1 0 CH[2:0] Power-On/Reset Value = 0x0710 Bits Bit Name Access Reset Description 15:14 RESERVED R/W 2’b00 Reserved Always write 2’b00 13 BURN R/W 1’b0 Burnout Enable Bit: When this bit is enabled, a pair of 500nA current sources are applied to analog inputs to source positive input and sink negative input. 12 FORMAT R/W 1’b0 Data Format Bit: This bit sets the ADC data format. 0: Bipolar mode (default) 1: Unipolar mode 11 RESERVED R/W 1’b0 Reserved Always write 1’b0 10:8 RESERVED R/W 3’b111 Reserved Always write 3’b111 7:6 RESERVED R/W 2’b00 Reserved Always write 2’b00 5 REFDET R/W 1’b0 Reference Detection Enable Bit: When this bit is enabled, the NOREF bit in the STATUS register indicates when the reference input voltage is less than specified threshold, which is about 0.4V. 4 RESERVED R/W 1’b1 Reserved Always write1’b1 3 RESERVED R/W 1’b0 Reserved Always write 1’b0 CH[2:0] R/W 3’b000 Channel Select Bits: This bits select which channels are enabled for ADC conversion (see Table 7). When ADC finishes the conversion and places the data into data register with corresponding channel information in STATUS register. 2:0 Table 7. Channel Selection CHD[2:0] (1) Positive Input AIN+ Negative Input AIN- Status Register Bits CHD[2:0] Calibration Register Pair 000 AIN1+ AIN1000 0 001 AIN2+ AIN2001 1 010 Reserved 010 011 AIN1AIN1011 0 100 Reserved 100 101 Reserved 101 110 Temperature Sensor(1) 110 Default Reset Values 111 AVDD Monitor(2) 111 Default Reset Values For temperature sensor measurement, PGA gain is internally forced to 1 with buffer on and internal 1.17V reference is used disregarding user register configuration. May 2022 Signal Micro Incorporated http://www.signal-micro.cn 10 SIG7796/7797 (2) For AVDD monitor measurement, the AVDD is internally attenuated by 6, PGA gain is forced to 1 with buffer on and internal 1.17V reference is used disregarding user register configuration. DATA Register This register is 16 bits wide for SIG7796 and 24 bits wide for SIG7797. Table 8. DATA Register (Address = 3’b011) BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DATA[23] DATA[22] DATA[21] DATA[20] DATA[19] DATA[18] DATA[17] DATA[16] DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] Power-On/Reset Value = 0x0000(SIG7796)/0x000000(SIG7797) Bits Bit Name Access Reset Description 23:0 DATA[23:0] R 0x000000 Data Bits: The 16-bit word for SIG7796 or 24-bit word for SIG7797 is signed number in 2’s complement format. See Data Format section for more information. May 2022 Signal Micro Incorporated http://www.signal-micro.cn 11 SIG7796/7797 ID Register Table 9. ID Register (Address = 3’b100) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 x x x x 1 0 1 0/1 Power-On/Reset Value = 0xXA(SIG7796)/0xXB(SIG7797) Bits Bit Name Access Reset Description 7:0 ID R 8’bxxxx101x ID Bits: Read only. OFFSET Register The device has four OFFSET registers, each channel has a dedicated OFFSET register (see Table 7). This register is 16 bits wide for SIG7796 and 24 bits wide for SIG7797. OFFSET register read is allowed anytime, but writing to OFFSET register is only allowed while the device is in idle or sleep mode. Table 10. OFFSET Register (Address = 3’b110) BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OFFSET[23] OFFSET[22] OFFSET[21] OFFSET[20] OFFSET[19] OFFSET[18] OFFSET[17] OFFSET[16] OFFSET[15] OFFSET[14] OFFSET[13] OFFSET[12] OFFSET[11] OFFSET[10] OFFSET[9] OFFSET[8] OFFSET[7] OFFSET[6] OFFSET[5] OFFSET[4] OFFSET[3] OFFSET[2] OFFSET[1] OFFSET[0] Power-On/Reset Value = 0x8000(SIG7796)/0x800000(SIG7797) Bits Bit Name Access Reset Description 23:0 OFFSET[23:0] R/W 0x800000 Offset Calibration Bits: The 24-bit word is signed number in offset binary format. See Calibration section for more information. GAIN Register The device has four GAIN registers, each channel has a dedicated GAIN register (see Table 7). This register is 16 bits wide for SIG7796 and 24 bits wide for SIG7797. GAIN register read is allowed anytime, but writing to GAIN register is only allowed while the device is in idle or sleep mode. Table 11. GAIN Register (Address = 3’b111) BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 GAIN[23] GAIN[22] GAIN[21] GAIN[20] GAIN[19] GAIN[18] GAIN[17] GAIN[16] GAIN[15] GAIN[14] GAIN[13] GAIN[12] GAIN[11] GAIN[10] GAIN[9] GAIN[8] GAIN[7] GAIN[6] GAIN[5] GAIN[4] GAIN[3] GAIN[2] GAIN[1] GAIN[0] Power-On/Reset Value = 0x5555(SIG7796)/0x555555(SIG7797) Bits Bit Name Access Reset Description 23:0 GAIN[23:0] R/W 0x555555 Gain Calibration Bits: The 24-bit word is unsigned positive number in binary format. See Calibration section for more information. May 2022 Signal Micro Incorporated http://www.signal-micro.cn 12 SIG7796/7797 REVISION HISTORY The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please contact to make sure you have the latest revision. DATE REVISION May 20, 2022 CHANGE Initial release. DISCLAIMER Signal Micro reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. All trademarks and registered trademarks are the property of their respective owners. May 2022 Signal Micro Incorporated http://www.signal-micro.cn 13 SIG7796/7797 PACKAGE OUTLINE DIMENSIONS 0.30 0.19 0.65 16 0.10 M 9 0.15 NOM 4.50 4.30 6.60 6.20 0.25 0o-8o 0.75 0.50 8 1 5.10 4.90 1.10 MAX 0.15 0.05 0.10 Seating Plane A. Compliant to JEDEC STARDARDS MO-153-AD. B. All linear dimensions are in millimeters. C. This drawing is subject to change without notice. May 2022 Signal Micro Incorporated http://www.signal-micro.cn 14