AESD05EB

SPSEMI ESD/AESD05EB     Electro-Static Discharge for Automobile AESD05EB Bidirectional TVS Diode SOD-523 Pin Configuration Features 50 Watts Peak Pulse Power per Line (tp=8/20μs) Protects one birectional I/O line Low clamping voltage Working voltages : 5V Low leakage current AEC-Q101 IEC Compatibility IEC61000-4-2 (ESD) ±20kV (air), ±20kV (contact) IEC61000-4-4 (EFT) 40A (5/50ηs) Applications Cell Phone Handsets and Accessories Microprocessor based equipment Personal Digital Assistants(PDA's) Notebooks,Desktops,and Servers Portable Instrumentation Peripherals Pagers Mechanical Characteristics SOD-523 Package Molding Compound Flammability Rating:L 94V-O Quantity Per Reel:5000pcs Reel Size:7 inch Lead Finish:Lead Free REV . 2018 . 05 . 30 www.spsemi.cn Page 1 of 3 SPSEMI ESD/AESD05EB     Maximum Ratings (T A =25 ℃ unless otherwise noted ) Maximum Ratings(@25 ℃ Unless Otherwise Specified) Symbol Value Units Peak Pulse Power(tp=8/20μs waveform) P PP 50 Watts Lead Soldering Temperature TL 260(10 sec.) ℃ Operating Temperature Range TJ -55~150 ℃ T STG -55~150 ℃ Parameter Storage Temperature Range Electrical Characteristics (Ta=25 ℃ unless otherwise specified) AESD05EB(Marking: 0 ) Symbol Parameter Reverse Stand-off Voltage Typ. Min. Conditions V RWM Max. Units 5 V Breakdown Voltage V BR I T =1mA Clamping Voltage VC I PP =5A,tp=8/20μs 10 V Reverse Leakage Current IR @V RWM 1 μA C I/O 0Vdc,f=1MHz Between I/O Pins and GND 15 pF Junction Capacitance 5.8 V 12 Ratings and Characteristic Curves Fig.2 Non-Repetitive Peak Pulse Power vs.Pulse Time Fig.1 Pulse Waveform 110 10 100 Percent of I PP 70 e 60 Peak Pulse Power-Ppk(KW) Waveform Parameters: tr=8μs t d =20μs 90 80 -1 50 40 t d =I PP /2 30 20 10 0 0 5 10 15 20 25 0.1 0.01 0 30 Time( μs ) REV . 2018 . 05 . 30 1 www.spsemi.cn 1 10 100 Pulse Duration-tp(μs) 1000 Page 2 of 3 SPSEMI ESD/AESD05EB     Application Information I/O Protection I/O I/O I/O I/O AESD05EB AESD05EB PCB Layout Recommendations The location and circuit board layout is critical to maximize the effectiveness of the I/O protection circuit. The following guidelines are recommended: Locate the protection devices as close as possible to the I/O connector. This allows the protection devices to absorb the energy of the transient voltage before it can be coupled into the adjacent traces on the PCB. Minimize the loop area for the high.speed data lines, power and ground lines to reduce the radiated emissions. Avoid running protection conductors in parallel with unprotected conductors Use ground planes wherever possible to reduce the parasitic capacitance and inductance of the PCB that degrades the effectiveness of a filter device. Using shared transient return paths to a common ground point. Dimensions(SOD-523) SOD-523 Millimeters A B D 2 1 C K J Inches DIM Min Max Min Max A 1.10 1.30 0.043 0.051 B 0.70 0.90 0.028 0.035 C 0.50 0.70 0.020 0.028 D 0.25 0.35 0.010 0.014 J 0.07 0.20 K 0.15 0.25 0.006 0.010 S 1.50 1.70 0.059 0.067 0.0028 0.0079 S Recommended Mounting Pad Layout 1.40 0.0547 0.40 0.0157 REV . 2018 . 05 . 30 0.40 0.0157 Dimensions in ( millimeters ) inches www.spsemi.cn Page 3 of 3