ZD24C512A-SSGMT

ZD24C512A ZD24C512A I2C-Compatible (2-wire) Serial EEPROM 512K-bit (65536×8) DATASHEET Features ⚫ Low Voltage Operation -VCC = 1.7V to 5.5V ⚫ Compatible with all I2C bidirectional data transfer protocol ⚫ Memory array: 512 Kbits (64 Kbytes) of EEPROM – Page size: 128 bytes – Additional Write lockable page ⚫ Single supply voltage and high speed: – 1 MHz ⚫ Random and sequential Read modes ⚫ Write: – Byte Write within 5 ms Page Write within 5 ms – Partial Page Writes Allowed ⚫ Write Protect Pin for Hardware Data Protection ⚫ Schmitt Trigger, Filtered Inputs for Noise Suppression ⚫ High-reliability – Endurance: 4 Million Write Cycles – Data Retention: 100 Years ⚫ Enhanced ESD/Latch-up protection – HBM 8000V ⚫ 8-lead PDIP/SOP/TSSOP/UDFN/WLCSP packages – – Description ⚫ ⚫ ⚫ The ZD24C512A provides 524288 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 65536 words of 8 bits each. The ZD24C512A offers an additional page, named the Identification Page (128 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 1 / 19 ZD24C512A Pin Configuration ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 2 / 19 ZD24C512A Pin Descriptions Block Diagram ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 3 / 19 ZD24C512A DEVICE/PAGE ADDRESSES (A2,A1 and A0): The A2,A1 and A0 pins are device address inputs that are hard wire for the ZD24C512A. Eight 512K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wireORed with any number of other open-drain or open- collector devices. SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. WRITE PROTECT (WP): The ZD24C512A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as shown in the following Table 2. WP Pin Status ZD24C512A At VCC Full(512K)Array At GND Normal Read/Write Operations Table 2 Functional Description 1. Memory Organization ZD24C512A, 512K SERIAL EEPROM: Internally organized with 512 pages of 128 bytes each, the 512K requires a 16-bit data word address for random word addressing. 2. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 3). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle.(see Figure 4). STANDBY MODE: The ZD24C512A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition. ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 4 / 19 ZD24C512A ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 5 / 19 ZD24C512A 3. Device Addressing The 512K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 5) The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The 512K EEPROM uses A2,A1 and A0 device address bits and one world address bit to allow as much as eight devices on the same bus. These 3 device address bits must be compared to their corresponding hardwired input pins. The A2,A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state. DATA SECURITY: The ZD24C512A has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC. ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 6 / 19 ZD24C512A 4. Write Operations BYTE WRITE: A write operation requires two 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 6). PAGE WRITE: The Page Write mode allows up to 128 bytes to be written in a single Write cycle. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 127 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 7). The data word address lower seven bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 128 data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. WRITE IDENTIFICATION PAGE: The Identification Page (128 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 7 / 19 ZD24C512A the following differences: Device type identifier = 1011b MSB address bits B15/B7 are don't care except for address bit B10 which must be "0". LSB address bits B6/B0 define the byte address inside the Identification page. If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck). ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue. ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 8 / 19 ZD24C512A 5. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 8). RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9) ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 9 / 19 ZD24C512A SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 10). READ IDENTIFICATION PAGE: The Identification Page (128 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. The Identification Page can be read by issuing an Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b. The MSB address bits B15/B6 are don't care, the LSB address bits B5/B0 define the byte address inside the Identification Page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the Identification Page from location 10d, the number of bytes should be less than or equal to 118, as the ID page boundary is 128 bytes) LOCK IDENTIFICATION PAGE: The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions: Device type identifier = 1011b Address bit B10 must be ‘1’; all other address bits are don't care The data byte must be equal to the binary value xxxx xx1x, where x is don't care ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 10 / ZD24C512A Electrical Characteristics Absolute Maximum Stress Ratings： ⚫ DC Supply Voltage................................................................................................................. -0.3V to +6.5V ⚫ Operating Ambient Temperature........................................................................... . -40℃ to +85℃ ⚫ ⚫ Input / Output Voltage................................................................................ GND-0.3V to VCC+0.3V Storage Temperature.......................................................................................... . -65℃ to +150℃ pulse (Human Body model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8000V ⚫ Electrostatic Comments： Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +2.0V to +5.5V (unless otherwise noted) Table3 Pin Capacitance Applicable over recommended operating range from TA = 25℃, f = 1.0 MHz, VCC = +1.7V Symbol Min Typ Max Unit Condition Input/Output Capacitance(SDA) CI/O - - 8 pF VIO=0V Input Capacitance(A0,A1,A2,SCL) CIN - - 6 pF VIN=0V Parameter ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 10 / 19 ZD24C512A Table 4 ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 11 / 19 ZD24C512A AC Electrical Characteristics Applicable over recommended operating range from TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Notes: Table5 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3 k Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall time: 50 ns Input and output timing reference voltages: 0.5 VCC The value of RL should be concerned according to the actual loading on the user's system. ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 12 / 19 ZD24C512A Bus Timing Notes: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 13 / 19 ZD24C512A Package Information PDIP Outline Dimensions ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 14 / 19 ZD24C512A SOP ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 15 / 19 ZD24C512A TSSOP ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 16 / 19 ZD24C512A UDFN ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 17 / 19 ZD24C512A WLCSP ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 18 / 19 ZD24C512A Ordering Information ZD 24C 512 A SS G M T Zetta Designator Product Family 24C = Standard I2C-compatible Serial EEPROM Shipping Carrier Option T = Tape and Reel, Standard Quantity Option B = Bulk (Tubes) Device Density Operating Voltage Device Revision M = 1.7V to 5.5V Package Device Grade G = Low-halogen, Lead(Pb)-free P = Lead (Pb) - free Package Option SS = JEDEC SOIC X = TSSOP MA = 2.0mm x 3.0mm UDFN P = PDIP ST = SOT23 C = VFBGA U = 3x3 Grid, 5-ball WLCSP U1 = 2x2 Grid, 4-ball WLCSP WU = Wafer Unsawn ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 19 / 19 ZD24C512A Revision History Doc. No. Date 05/2020 Comments Initial document release. ZettaDevice Electronics Technology Co.,Ltd www.zettadevice.com 20 / 19